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75c9abc6 | 1 | /* Native-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
28e7fd62 | 3 | Copyright (C) 2001-2013 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
19 | |
20 | #include "defs.h" | |
b9412953 DD |
21 | #include "command.h" |
22 | #include "gdbcmd.h" | |
23 | #include "gdb_assert.h" | |
d37eb719 | 24 | #include "inferior.h" |
6b753f60 | 25 | #include "mips-tdep.h" |
10d6c8cd | 26 | #include "target.h" |
28f5035f | 27 | #include "regcache.h" |
10d6c8cd | 28 | #include "linux-nat.h" |
d37eb719 | 29 | #include "mips-linux-tdep.h" |
822b6570 | 30 | #include "target-descriptions.h" |
2aa830e4 | 31 | |
dc60ece8 | 32 | #include "gdb_proc_service.h" |
3e00823e | 33 | #include "gregset.h" |
dc60ece8 | 34 | |
822b6570 | 35 | #include <sgidefs.h> |
d37eb719 | 36 | #include <sys/ptrace.h> |
9be14b81 | 37 | #include <asm/ptrace.h> |
d37eb719 | 38 | |
81adfced | 39 | #include "features/mips-linux.c" |
1faeff08 | 40 | #include "features/mips-dsp-linux.c" |
81adfced | 41 | #include "features/mips64-linux.c" |
1faeff08 | 42 | #include "features/mips64-dsp-linux.c" |
81adfced | 43 | |
dc60ece8 DJ |
44 | #ifndef PTRACE_GET_THREAD_AREA |
45 | #define PTRACE_GET_THREAD_AREA 25 | |
46 | #endif | |
47 | ||
d37eb719 DJ |
48 | /* Assume that we have PTRACE_GETREGS et al. support. If we do not, |
49 | we'll clear this and use PTRACE_PEEKUSER instead. */ | |
50 | static int have_ptrace_regsets = 1; | |
51 | ||
b9412953 DD |
52 | /* Whether or not to print the mirrored debug registers. */ |
53 | ||
54 | static int maint_show_dr; | |
55 | ||
d37eb719 DJ |
56 | /* Saved function pointers to fetch and store a single register using |
57 | PTRACE_PEEKUSER and PTRACE_POKEUSER. */ | |
58 | ||
b9412953 DD |
59 | static void (*super_fetch_registers) (struct target_ops *, |
60 | struct regcache *, int); | |
61 | static void (*super_store_registers) (struct target_ops *, | |
62 | struct regcache *, int); | |
63 | ||
460014f5 | 64 | static void (*super_close) (void); |
d37eb719 | 65 | |
dda0c97e | 66 | /* Map gdb internal register number to ptrace ``address''. |
7714d83a UW |
67 | These ``addresses'' are normally defined in <asm/ptrace.h>. |
68 | ||
69 | ptrace does not provide a way to read (or set) MIPS_PS_REGNUM, | |
70 | and there's no point in reading or setting MIPS_ZERO_REGNUM. | |
71 | We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */ | |
dda0c97e UW |
72 | |
73 | static CORE_ADDR | |
7714d83a | 74 | mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 75 | { |
7714d83a | 76 | CORE_ADDR regaddr; |
dda0c97e | 77 | |
2eb4d78b | 78 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
79 | error (_("Bogon register number %d."), regno); |
80 | ||
7714d83a | 81 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 82 | regaddr = regno; |
7714d83a UW |
83 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
84 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
85 | regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0); | |
86 | else if (regno == mips_regnum (gdbarch)->pc) | |
dda0c97e | 87 | regaddr = PC; |
7714d83a UW |
88 | else if (regno == mips_regnum (gdbarch)->cause) |
89 | regaddr = store? (CORE_ADDR) -1 : CAUSE; | |
90 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
91 | regaddr = store? (CORE_ADDR) -1 : BADVADDR; | |
92 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 93 | regaddr = MMLO; |
7714d83a | 94 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 95 | regaddr = MMHI; |
7714d83a | 96 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 97 | regaddr = FPC_CSR; |
7714d83a UW |
98 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
99 | regaddr = store? (CORE_ADDR) -1 : FPC_EIR; | |
1faeff08 MR |
100 | else if (mips_regnum (gdbarch)->dspacc != -1 |
101 | && regno >= mips_regnum (gdbarch)->dspacc | |
102 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
103 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); | |
104 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
105 | regaddr = DSP_CONTROL; | |
822b6570 DJ |
106 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
107 | regaddr = 0; | |
dda0c97e | 108 | else |
7714d83a | 109 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
110 | |
111 | return regaddr; | |
112 | } | |
113 | ||
114 | static CORE_ADDR | |
7714d83a | 115 | mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 116 | { |
7714d83a | 117 | CORE_ADDR regaddr; |
dda0c97e | 118 | |
2eb4d78b | 119 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
120 | error (_("Bogon register number %d."), regno); |
121 | ||
7714d83a | 122 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 123 | regaddr = regno; |
7714d83a UW |
124 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
125 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
2eb4d78b | 126 | regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch)); |
7714d83a | 127 | else if (regno == mips_regnum (gdbarch)->pc) |
dda0c97e | 128 | regaddr = MIPS64_PC; |
7714d83a UW |
129 | else if (regno == mips_regnum (gdbarch)->cause) |
130 | regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE; | |
131 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
132 | regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR; | |
133 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 134 | regaddr = MIPS64_MMLO; |
7714d83a | 135 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 136 | regaddr = MIPS64_MMHI; |
7714d83a | 137 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 138 | regaddr = MIPS64_FPC_CSR; |
7714d83a UW |
139 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
140 | regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR; | |
1faeff08 MR |
141 | else if (mips_regnum (gdbarch)->dspacc != -1 |
142 | && regno >= mips_regnum (gdbarch)->dspacc | |
143 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
144 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); | |
145 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
146 | regaddr = DSP_CONTROL; | |
822b6570 DJ |
147 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
148 | regaddr = 0; | |
dda0c97e | 149 | else |
7714d83a | 150 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
151 | |
152 | return regaddr; | |
153 | } | |
154 | ||
dc60ece8 DJ |
155 | /* Fetch the thread-local storage pointer for libthread_db. */ |
156 | ||
157 | ps_err_e | |
158 | ps_get_thread_area (const struct ps_prochandle *ph, | |
159 | lwpid_t lwpid, int idx, void **base) | |
160 | { | |
161 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
162 | return PS_ERR; | |
163 | ||
164 | /* IDX is the bias from the thread pointer to the beginning of the | |
165 | thread descriptor. It has to be subtracted due to implementation | |
166 | quirks in libthread_db. */ | |
167 | *base = (void *) ((char *)*base - idx); | |
168 | ||
169 | return PS_OK; | |
170 | } | |
171 | ||
3e00823e UW |
172 | /* Wrapper functions. These are only used by libthread_db. */ |
173 | ||
174 | void | |
7f7fe91e | 175 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
3e00823e | 176 | { |
2eb4d78b | 177 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 178 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp); |
3e00823e | 179 | else |
7f7fe91e | 180 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp); |
3e00823e UW |
181 | } |
182 | ||
183 | void | |
7f7fe91e UW |
184 | fill_gregset (const struct regcache *regcache, |
185 | gdb_gregset_t *gregsetp, int regno) | |
3e00823e | 186 | { |
2eb4d78b | 187 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 188 | mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno); |
3e00823e | 189 | else |
7f7fe91e | 190 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno); |
3e00823e UW |
191 | } |
192 | ||
193 | void | |
7f7fe91e | 194 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
3e00823e | 195 | { |
2eb4d78b | 196 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 197 | mips_supply_fpregset (regcache, (const mips_elf_fpregset_t *) fpregsetp); |
3e00823e | 198 | else |
025bb325 MS |
199 | mips64_supply_fpregset (regcache, |
200 | (const mips64_elf_fpregset_t *) fpregsetp); | |
3e00823e UW |
201 | } |
202 | ||
203 | void | |
7f7fe91e UW |
204 | fill_fpregset (const struct regcache *regcache, |
205 | gdb_fpregset_t *fpregsetp, int regno) | |
3e00823e | 206 | { |
2eb4d78b | 207 | if (mips_isa_regsize (get_regcache_arch (regcache)) == 4) |
7f7fe91e | 208 | mips_fill_fpregset (regcache, (mips_elf_fpregset_t *) fpregsetp, regno); |
3e00823e | 209 | else |
025bb325 MS |
210 | mips64_fill_fpregset (regcache, |
211 | (mips64_elf_fpregset_t *) fpregsetp, regno); | |
3e00823e UW |
212 | } |
213 | ||
214 | ||
d37eb719 DJ |
215 | /* Fetch REGNO (or all registers if REGNO == -1) from the target |
216 | using PTRACE_GETREGS et al. */ | |
217 | ||
218 | static void | |
1faeff08 MR |
219 | mips64_linux_regsets_fetch_registers (struct target_ops *ops, |
220 | struct regcache *regcache, int regno) | |
d37eb719 | 221 | { |
2eb4d78b | 222 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1faeff08 MR |
223 | int is_fp, is_dsp; |
224 | int have_dsp; | |
225 | int regi; | |
d37eb719 DJ |
226 | int tid; |
227 | ||
2eb4d78b UW |
228 | if (regno >= mips_regnum (gdbarch)->fp0 |
229 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 230 | is_fp = 1; |
2eb4d78b | 231 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 232 | is_fp = 1; |
2eb4d78b | 233 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
234 | is_fp = 1; |
235 | else | |
236 | is_fp = 0; | |
237 | ||
1faeff08 MR |
238 | /* DSP registers are optional and not a part of any set. */ |
239 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; | |
240 | if (!have_dsp) | |
241 | is_dsp = 0; | |
242 | else if (regno >= mips_regnum (gdbarch)->dspacc | |
243 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
244 | is_dsp = 1; | |
245 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
246 | is_dsp = 1; | |
247 | else | |
248 | is_dsp = 0; | |
249 | ||
d37eb719 DJ |
250 | tid = ptid_get_lwp (inferior_ptid); |
251 | if (tid == 0) | |
252 | tid = ptid_get_pid (inferior_ptid); | |
253 | ||
1faeff08 | 254 | if (regno == -1 || (!is_fp && !is_dsp)) |
d37eb719 DJ |
255 | { |
256 | mips64_elf_gregset_t regs; | |
257 | ||
258 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
259 | { | |
260 | if (errno == EIO) | |
261 | { | |
262 | have_ptrace_regsets = 0; | |
263 | return; | |
264 | } | |
265 | perror_with_name (_("Couldn't get registers")); | |
266 | } | |
267 | ||
56be3814 | 268 | mips64_supply_gregset (regcache, |
28f5035f | 269 | (const mips64_elf_gregset_t *) ®s); |
d37eb719 DJ |
270 | } |
271 | ||
272 | if (regno == -1 || is_fp) | |
273 | { | |
274 | mips64_elf_fpregset_t fp_regs; | |
275 | ||
276 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
277 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
278 | { | |
279 | if (errno == EIO) | |
280 | { | |
281 | have_ptrace_regsets = 0; | |
282 | return; | |
283 | } | |
284 | perror_with_name (_("Couldn't get FP registers")); | |
285 | } | |
286 | ||
56be3814 | 287 | mips64_supply_fpregset (regcache, |
28f5035f | 288 | (const mips64_elf_fpregset_t *) &fp_regs); |
d37eb719 | 289 | } |
1faeff08 MR |
290 | |
291 | if (is_dsp) | |
292 | super_fetch_registers (ops, regcache, regno); | |
293 | else if (regno == -1 && have_dsp) | |
294 | { | |
295 | for (regi = mips_regnum (gdbarch)->dspacc; | |
296 | regi < mips_regnum (gdbarch)->dspacc + 6; | |
297 | regi++) | |
298 | super_fetch_registers (ops, regcache, regi); | |
299 | super_fetch_registers (ops, regcache, mips_regnum (gdbarch)->dspctl); | |
300 | } | |
d37eb719 DJ |
301 | } |
302 | ||
303 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
304 | using PTRACE_SETREGS et al. */ | |
305 | ||
306 | static void | |
1faeff08 MR |
307 | mips64_linux_regsets_store_registers (struct target_ops *ops, |
308 | struct regcache *regcache, int regno) | |
d37eb719 | 309 | { |
2eb4d78b | 310 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1faeff08 MR |
311 | int is_fp, is_dsp; |
312 | int have_dsp; | |
313 | int regi; | |
d37eb719 DJ |
314 | int tid; |
315 | ||
2eb4d78b UW |
316 | if (regno >= mips_regnum (gdbarch)->fp0 |
317 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 318 | is_fp = 1; |
2eb4d78b | 319 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 320 | is_fp = 1; |
2eb4d78b | 321 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
322 | is_fp = 1; |
323 | else | |
324 | is_fp = 0; | |
325 | ||
1faeff08 MR |
326 | /* DSP registers are optional and not a part of any set. */ |
327 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; | |
328 | if (!have_dsp) | |
329 | is_dsp = 0; | |
6ce4c112 | 330 | else if (regno >= mips_regnum (gdbarch)->dspacc |
1faeff08 MR |
331 | && regno < mips_regnum (gdbarch)->dspacc + 6) |
332 | is_dsp = 1; | |
333 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
334 | is_dsp = 1; | |
335 | else | |
336 | is_dsp = 0; | |
337 | ||
d37eb719 DJ |
338 | tid = ptid_get_lwp (inferior_ptid); |
339 | if (tid == 0) | |
340 | tid = ptid_get_pid (inferior_ptid); | |
341 | ||
1faeff08 | 342 | if (regno == -1 || (!is_fp && !is_dsp)) |
d37eb719 DJ |
343 | { |
344 | mips64_elf_gregset_t regs; | |
345 | ||
346 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
347 | perror_with_name (_("Couldn't get registers")); | |
348 | ||
56be3814 | 349 | mips64_fill_gregset (regcache, ®s, regno); |
d37eb719 DJ |
350 | |
351 | if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
352 | perror_with_name (_("Couldn't set registers")); | |
353 | } | |
354 | ||
355 | if (regno == -1 || is_fp) | |
356 | { | |
357 | mips64_elf_fpregset_t fp_regs; | |
358 | ||
359 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
360 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
361 | perror_with_name (_("Couldn't get FP registers")); | |
362 | ||
56be3814 | 363 | mips64_fill_fpregset (regcache, &fp_regs, regno); |
d37eb719 DJ |
364 | |
365 | if (ptrace (PTRACE_SETFPREGS, tid, 0L, | |
366 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
367 | perror_with_name (_("Couldn't set FP registers")); | |
368 | } | |
1faeff08 MR |
369 | |
370 | if (is_dsp) | |
371 | super_store_registers (ops, regcache, regno); | |
372 | else if (regno == -1 && have_dsp) | |
373 | { | |
374 | for (regi = mips_regnum (gdbarch)->dspacc; | |
375 | regi < mips_regnum (gdbarch)->dspacc + 6; | |
376 | regi++) | |
377 | super_store_registers (ops, regcache, regi); | |
378 | super_store_registers (ops, regcache, mips_regnum (gdbarch)->dspctl); | |
379 | } | |
d37eb719 DJ |
380 | } |
381 | ||
382 | /* Fetch REGNO (or all registers if REGNO == -1) from the target | |
383 | using any working method. */ | |
384 | ||
385 | static void | |
28439f5e PA |
386 | mips64_linux_fetch_registers (struct target_ops *ops, |
387 | struct regcache *regcache, int regnum) | |
d37eb719 DJ |
388 | { |
389 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
390 | if (have_ptrace_regsets) | |
1faeff08 | 391 | mips64_linux_regsets_fetch_registers (ops, regcache, regnum); |
d37eb719 DJ |
392 | |
393 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
394 | back to PTRACE_PEEKUSER. */ | |
395 | if (!have_ptrace_regsets) | |
a0740d21 | 396 | super_fetch_registers (ops, regcache, regnum); |
d37eb719 DJ |
397 | } |
398 | ||
399 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
400 | using any working method. */ | |
401 | ||
402 | static void | |
28439f5e PA |
403 | mips64_linux_store_registers (struct target_ops *ops, |
404 | struct regcache *regcache, int regnum) | |
d37eb719 DJ |
405 | { |
406 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
407 | if (have_ptrace_regsets) | |
1faeff08 | 408 | mips64_linux_regsets_store_registers (ops, regcache, regnum); |
d37eb719 DJ |
409 | |
410 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
411 | back to PTRACE_PEEKUSER. */ | |
412 | if (!have_ptrace_regsets) | |
a0740d21 | 413 | super_store_registers (ops, regcache, regnum); |
d37eb719 DJ |
414 | } |
415 | ||
910122bf UW |
416 | /* Return the address in the core dump or inferior of register |
417 | REGNO. */ | |
418 | ||
419 | static CORE_ADDR | |
7714d83a | 420 | mips_linux_register_u_offset (struct gdbarch *gdbarch, int regno, int store_p) |
910122bf | 421 | { |
7714d83a UW |
422 | if (mips_abi_regsize (gdbarch) == 8) |
423 | return mips64_linux_register_addr (gdbarch, regno, store_p); | |
dda0c97e | 424 | else |
7714d83a | 425 | return mips_linux_register_addr (gdbarch, regno, store_p); |
910122bf UW |
426 | } |
427 | ||
81adfced DJ |
428 | static const struct target_desc * |
429 | mips_linux_read_description (struct target_ops *ops) | |
822b6570 | 430 | { |
1faeff08 MR |
431 | static int have_dsp = -1; |
432 | ||
433 | if (have_dsp < 0) | |
434 | { | |
435 | int tid; | |
436 | ||
437 | tid = ptid_get_lwp (inferior_ptid); | |
438 | if (tid == 0) | |
439 | tid = ptid_get_pid (inferior_ptid); | |
440 | ||
441 | ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0); | |
442 | switch (errno) | |
443 | { | |
444 | case 0: | |
445 | have_dsp = 1; | |
446 | break; | |
447 | case EIO: | |
448 | have_dsp = 0; | |
449 | break; | |
450 | default: | |
837a1b32 | 451 | perror_with_name (_("Couldn't check DSP support")); |
1faeff08 MR |
452 | break; |
453 | } | |
454 | } | |
455 | ||
81adfced DJ |
456 | /* Report that target registers are a size we know for sure |
457 | that we can get from ptrace. */ | |
458 | if (_MIPS_SIM == _ABIO32) | |
1faeff08 | 459 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; |
81adfced | 460 | else |
1faeff08 | 461 | return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux; |
822b6570 DJ |
462 | } |
463 | ||
9be14b81 YQ |
464 | #define MAX_DEBUG_REGISTER 8 |
465 | ||
466 | /* If macro PTRACE_GET_WATCH_REGS is not defined, kernel header doesn't | |
467 | have hardware watchpoint-related structures. Define them below. */ | |
468 | ||
b9412953 DD |
469 | #ifndef PTRACE_GET_WATCH_REGS |
470 | # define PTRACE_GET_WATCH_REGS 0xd0 | |
b9412953 | 471 | # define PTRACE_SET_WATCH_REGS 0xd1 |
b9412953 DD |
472 | |
473 | enum pt_watch_style { | |
474 | pt_watch_style_mips32, | |
475 | pt_watch_style_mips64 | |
476 | }; | |
477 | ||
025bb325 | 478 | /* A value of zero in a watchlo indicates that it is available. */ |
b9412953 DD |
479 | |
480 | struct mips32_watch_regs | |
481 | { | |
482 | uint32_t watchlo[MAX_DEBUG_REGISTER]; | |
025bb325 | 483 | /* Lower 16 bits of watchhi. */ |
b9412953 DD |
484 | uint16_t watchhi[MAX_DEBUG_REGISTER]; |
485 | /* Valid mask and I R W bits. | |
486 | * bit 0 -- 1 if W bit is usable. | |
487 | * bit 1 -- 1 if R bit is usable. | |
488 | * bit 2 -- 1 if I bit is usable. | |
489 | * bits 3 - 11 -- Valid watchhi mask bits. | |
490 | */ | |
491 | uint16_t watch_masks[MAX_DEBUG_REGISTER]; | |
492 | /* The number of valid watch register pairs. */ | |
493 | uint32_t num_valid; | |
494 | /* There is confusion across gcc versions about structure alignment, | |
495 | so we force 8 byte alignment for these structures so they match | |
496 | the kernel even if it was build with a different gcc version. */ | |
497 | } __attribute__ ((aligned (8))); | |
498 | ||
499 | struct mips64_watch_regs | |
500 | { | |
501 | uint64_t watchlo[MAX_DEBUG_REGISTER]; | |
502 | uint16_t watchhi[MAX_DEBUG_REGISTER]; | |
503 | uint16_t watch_masks[MAX_DEBUG_REGISTER]; | |
504 | uint32_t num_valid; | |
505 | } __attribute__ ((aligned (8))); | |
506 | ||
507 | struct pt_watch_regs | |
508 | { | |
509 | enum pt_watch_style style; | |
510 | union | |
511 | { | |
512 | struct mips32_watch_regs mips32; | |
513 | struct mips64_watch_regs mips64; | |
514 | }; | |
515 | }; | |
516 | ||
9be14b81 YQ |
517 | #endif /* !PTRACE_GET_WATCH_REGS */ |
518 | ||
519 | #define W_BIT 0 | |
520 | #define R_BIT 1 | |
521 | #define I_BIT 2 | |
522 | ||
523 | #define W_MASK (1 << W_BIT) | |
524 | #define R_MASK (1 << R_BIT) | |
525 | #define I_MASK (1 << I_BIT) | |
526 | ||
527 | #define IRW_MASK (I_MASK | R_MASK | W_MASK) | |
528 | ||
b9412953 DD |
529 | /* -1 if the kernel and/or CPU do not support watch registers. |
530 | 1 if watch_readback is valid and we can read style, num_valid | |
531 | and the masks. | |
532 | 0 if we need to read the watch_readback. */ | |
533 | ||
534 | static int watch_readback_valid; | |
535 | ||
536 | /* Cached watch register read values. */ | |
537 | ||
538 | static struct pt_watch_regs watch_readback; | |
539 | ||
540 | /* We keep list of all watchpoints we should install and calculate the | |
541 | watch register values each time the list changes. This allows for | |
542 | easy sharing of watch registers for more than one watchpoint. */ | |
543 | ||
544 | struct mips_watchpoint | |
545 | { | |
546 | CORE_ADDR addr; | |
547 | int len; | |
548 | int type; | |
549 | struct mips_watchpoint *next; | |
550 | }; | |
551 | ||
552 | static struct mips_watchpoint *current_watches; | |
553 | ||
554 | /* The current set of watch register values for writing the | |
555 | registers. */ | |
556 | ||
557 | static struct pt_watch_regs watch_mirror; | |
558 | ||
559 | /* Assuming usable watch registers, return the irw_mask. */ | |
560 | ||
561 | static uint32_t | |
562 | get_irw_mask (struct pt_watch_regs *regs, int set) | |
563 | { | |
564 | switch (regs->style) | |
565 | { | |
566 | case pt_watch_style_mips32: | |
567 | return regs->mips32.watch_masks[set] & IRW_MASK; | |
568 | case pt_watch_style_mips64: | |
569 | return regs->mips64.watch_masks[set] & IRW_MASK; | |
570 | default: | |
571 | internal_error (__FILE__, __LINE__, | |
572 | _("Unrecognized watch register style")); | |
573 | } | |
574 | } | |
575 | ||
576 | /* Assuming usable watch registers, return the reg_mask. */ | |
577 | ||
578 | static uint32_t | |
579 | get_reg_mask (struct pt_watch_regs *regs, int set) | |
580 | { | |
581 | switch (regs->style) | |
582 | { | |
583 | case pt_watch_style_mips32: | |
584 | return regs->mips32.watch_masks[set] & ~IRW_MASK; | |
585 | case pt_watch_style_mips64: | |
586 | return regs->mips64.watch_masks[set] & ~IRW_MASK; | |
587 | default: | |
588 | internal_error (__FILE__, __LINE__, | |
589 | _("Unrecognized watch register style")); | |
590 | } | |
591 | } | |
592 | ||
593 | /* Assuming usable watch registers, return the num_valid. */ | |
594 | ||
595 | static uint32_t | |
596 | get_num_valid (struct pt_watch_regs *regs) | |
597 | { | |
598 | switch (regs->style) | |
599 | { | |
600 | case pt_watch_style_mips32: | |
601 | return regs->mips32.num_valid; | |
602 | case pt_watch_style_mips64: | |
603 | return regs->mips64.num_valid; | |
604 | default: | |
605 | internal_error (__FILE__, __LINE__, | |
606 | _("Unrecognized watch register style")); | |
607 | } | |
608 | } | |
609 | ||
610 | /* Assuming usable watch registers, return the watchlo. */ | |
611 | ||
612 | static CORE_ADDR | |
613 | get_watchlo (struct pt_watch_regs *regs, int set) | |
614 | { | |
615 | switch (regs->style) | |
616 | { | |
617 | case pt_watch_style_mips32: | |
618 | return regs->mips32.watchlo[set]; | |
619 | case pt_watch_style_mips64: | |
620 | return regs->mips64.watchlo[set]; | |
621 | default: | |
622 | internal_error (__FILE__, __LINE__, | |
623 | _("Unrecognized watch register style")); | |
624 | } | |
625 | } | |
626 | ||
627 | /* Assuming usable watch registers, set a watchlo value. */ | |
628 | ||
629 | static void | |
630 | set_watchlo (struct pt_watch_regs *regs, int set, CORE_ADDR value) | |
631 | { | |
632 | switch (regs->style) | |
633 | { | |
634 | case pt_watch_style_mips32: | |
635 | /* The cast will never throw away bits as 64 bit addresses can | |
636 | never be used on a 32 bit kernel. */ | |
637 | regs->mips32.watchlo[set] = (uint32_t)value; | |
638 | break; | |
639 | case pt_watch_style_mips64: | |
640 | regs->mips64.watchlo[set] = value; | |
641 | break; | |
642 | default: | |
643 | internal_error (__FILE__, __LINE__, | |
644 | _("Unrecognized watch register style")); | |
645 | } | |
646 | } | |
647 | ||
648 | /* Assuming usable watch registers, return the watchhi. */ | |
649 | ||
650 | static uint32_t | |
651 | get_watchhi (struct pt_watch_regs *regs, int n) | |
652 | { | |
653 | switch (regs->style) | |
654 | { | |
655 | case pt_watch_style_mips32: | |
656 | return regs->mips32.watchhi[n]; | |
657 | case pt_watch_style_mips64: | |
658 | return regs->mips64.watchhi[n]; | |
659 | default: | |
660 | internal_error (__FILE__, __LINE__, | |
661 | _("Unrecognized watch register style")); | |
662 | } | |
663 | } | |
664 | ||
665 | /* Assuming usable watch registers, set a watchhi value. */ | |
666 | ||
667 | static void | |
668 | set_watchhi (struct pt_watch_regs *regs, int n, uint16_t value) | |
669 | { | |
670 | switch (regs->style) | |
671 | { | |
672 | case pt_watch_style_mips32: | |
673 | regs->mips32.watchhi[n] = value; | |
674 | break; | |
675 | case pt_watch_style_mips64: | |
676 | regs->mips64.watchhi[n] = value; | |
677 | break; | |
678 | default: | |
679 | internal_error (__FILE__, __LINE__, | |
680 | _("Unrecognized watch register style")); | |
681 | } | |
682 | } | |
683 | ||
684 | static void | |
685 | mips_show_dr (const char *func, CORE_ADDR addr, | |
686 | int len, enum target_hw_bp_type type) | |
687 | { | |
688 | int i; | |
689 | ||
690 | puts_unfiltered (func); | |
691 | if (addr || len) | |
5af949e3 | 692 | printf_unfiltered (" (addr=%s, len=%d, type=%s)", |
f5656ead | 693 | paddress (target_gdbarch (), addr), len, |
b9412953 DD |
694 | type == hw_write ? "data-write" |
695 | : (type == hw_read ? "data-read" | |
696 | : (type == hw_access ? "data-read/write" | |
697 | : (type == hw_execute ? "instruction-execute" | |
698 | : "??unknown??")))); | |
699 | puts_unfiltered (":\n"); | |
700 | ||
701 | for (i = 0; i < MAX_DEBUG_REGISTER; i++) | |
5af949e3 | 702 | printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i, |
f5656ead | 703 | paddress (target_gdbarch (), |
5af949e3 | 704 | get_watchlo (&watch_mirror, i)), |
f5656ead | 705 | paddress (target_gdbarch (), |
5af949e3 | 706 | get_watchhi (&watch_mirror, i))); |
b9412953 DD |
707 | } |
708 | ||
709 | /* Return 1 if watch registers are usable. Cached information is used | |
710 | unless force is true. */ | |
711 | ||
712 | static int | |
713 | mips_linux_read_watch_registers (int force) | |
714 | { | |
715 | int tid; | |
716 | ||
717 | if (force || watch_readback_valid == 0) | |
718 | { | |
719 | tid = ptid_get_lwp (inferior_ptid); | |
720 | if (ptrace (PTRACE_GET_WATCH_REGS, tid, &watch_readback) == -1) | |
721 | { | |
722 | watch_readback_valid = -1; | |
723 | return 0; | |
724 | } | |
725 | switch (watch_readback.style) | |
726 | { | |
727 | case pt_watch_style_mips32: | |
728 | if (watch_readback.mips32.num_valid == 0) | |
729 | { | |
730 | watch_readback_valid = -1; | |
731 | return 0; | |
732 | } | |
733 | break; | |
734 | case pt_watch_style_mips64: | |
735 | if (watch_readback.mips64.num_valid == 0) | |
736 | { | |
737 | watch_readback_valid = -1; | |
738 | return 0; | |
739 | } | |
740 | break; | |
741 | default: | |
742 | watch_readback_valid = -1; | |
743 | return 0; | |
744 | } | |
745 | /* Watch registers appear to be usable. */ | |
746 | watch_readback_valid = 1; | |
747 | } | |
748 | return (watch_readback_valid == 1) ? 1 : 0; | |
749 | } | |
750 | ||
751 | /* Convert GDB's type to an IRW mask. */ | |
752 | ||
753 | static unsigned | |
754 | type_to_irw (int type) | |
755 | { | |
756 | switch (type) | |
757 | { | |
758 | case hw_write: | |
759 | return W_MASK; | |
760 | case hw_read: | |
761 | return R_MASK; | |
762 | case hw_access: | |
763 | return (W_MASK | R_MASK); | |
764 | default: | |
765 | return 0; | |
766 | } | |
767 | } | |
768 | ||
769 | /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can | |
770 | handle the specified watch type. */ | |
771 | ||
772 | static int | |
773 | mips_linux_can_use_hw_breakpoint (int type, int cnt, int ot) | |
774 | { | |
775 | int i; | |
776 | uint32_t wanted_mask, irw_mask; | |
777 | ||
778 | if (!mips_linux_read_watch_registers (0)) | |
779 | return 0; | |
780 | ||
781 | switch (type) | |
782 | { | |
783 | case bp_hardware_watchpoint: | |
784 | wanted_mask = W_MASK; | |
785 | break; | |
786 | case bp_read_watchpoint: | |
787 | wanted_mask = R_MASK; | |
788 | break; | |
789 | case bp_access_watchpoint: | |
790 | wanted_mask = R_MASK | W_MASK; | |
791 | break; | |
792 | default: | |
793 | return 0; | |
794 | } | |
795 | ||
796 | for (i = 0; i < get_num_valid (&watch_readback) && cnt; i++) | |
797 | { | |
798 | irw_mask = get_irw_mask (&watch_readback, i); | |
799 | if ((irw_mask & wanted_mask) == wanted_mask) | |
800 | cnt--; | |
801 | } | |
802 | return (cnt == 0) ? 1 : 0; | |
803 | } | |
804 | ||
805 | /* Target to_stopped_by_watchpoint implementation. Return 1 if | |
806 | stopped by watchpoint. The watchhi R and W bits indicate the watch | |
025bb325 | 807 | register triggered. */ |
b9412953 DD |
808 | |
809 | static int | |
810 | mips_linux_stopped_by_watchpoint (void) | |
811 | { | |
812 | int n; | |
813 | int num_valid; | |
814 | ||
815 | if (!mips_linux_read_watch_registers (1)) | |
816 | return 0; | |
817 | ||
818 | num_valid = get_num_valid (&watch_readback); | |
819 | ||
820 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
821 | if (get_watchhi (&watch_readback, n) & (R_MASK | W_MASK)) | |
822 | return 1; | |
823 | ||
824 | return 0; | |
825 | } | |
826 | ||
827 | /* Target to_stopped_data_address implementation. Set the address | |
828 | where the watch triggered (if known). Return 1 if the address was | |
829 | known. */ | |
830 | ||
831 | static int | |
832 | mips_linux_stopped_data_address (struct target_ops *t, CORE_ADDR *paddr) | |
833 | { | |
834 | /* On mips we don't know the low order 3 bits of the data address, | |
835 | so we must return false. */ | |
836 | return 0; | |
837 | } | |
838 | ||
839 | /* Set any low order bits in mask that are not set. */ | |
840 | ||
841 | static CORE_ADDR | |
842 | fill_mask (CORE_ADDR mask) | |
843 | { | |
844 | CORE_ADDR f = 1; | |
845 | while (f && f < mask) | |
846 | { | |
847 | mask |= f; | |
848 | f <<= 1; | |
849 | } | |
850 | return mask; | |
851 | } | |
852 | ||
853 | /* Try to add a single watch to the specified registers. Return 1 on | |
854 | success, 0 on failure. */ | |
855 | ||
856 | static int | |
857 | try_one_watch (struct pt_watch_regs *regs, CORE_ADDR addr, | |
858 | int len, unsigned irw) | |
859 | { | |
860 | CORE_ADDR base_addr, last_byte, break_addr, segment_len; | |
861 | CORE_ADDR mask_bits, t_low, t_low_end; | |
862 | uint16_t t_hi; | |
863 | int i, free_watches; | |
864 | struct pt_watch_regs regs_copy; | |
865 | ||
866 | if (len <= 0) | |
867 | return 0; | |
868 | ||
869 | last_byte = addr + len - 1; | |
870 | mask_bits = fill_mask (addr ^ last_byte) | IRW_MASK; | |
871 | base_addr = addr & ~mask_bits; | |
872 | ||
873 | /* Check to see if it is covered by current registers. */ | |
874 | for (i = 0; i < get_num_valid (regs); i++) | |
875 | { | |
876 | t_low = get_watchlo (regs, i); | |
877 | if (t_low != 0 && irw == ((unsigned)t_low & irw)) | |
878 | { | |
879 | t_hi = get_watchhi (regs, i) | IRW_MASK; | |
880 | t_low &= ~(CORE_ADDR)t_hi; | |
881 | if (addr >= t_low && last_byte <= (t_low + t_hi)) | |
882 | return 1; | |
883 | } | |
884 | } | |
885 | /* Try to find an empty register. */ | |
886 | free_watches = 0; | |
887 | for (i = 0; i < get_num_valid (regs); i++) | |
888 | { | |
889 | t_low = get_watchlo (regs, i); | |
890 | if (t_low == 0 && irw == (get_irw_mask (regs, i) & irw)) | |
891 | { | |
892 | if (mask_bits <= (get_reg_mask (regs, i) | IRW_MASK)) | |
893 | { | |
894 | /* It fits, we'll take it. */ | |
895 | set_watchlo (regs, i, base_addr | irw); | |
896 | set_watchhi (regs, i, mask_bits & ~IRW_MASK); | |
897 | return 1; | |
898 | } | |
899 | else | |
900 | { | |
901 | /* It doesn't fit, but has the proper IRW capabilities. */ | |
902 | free_watches++; | |
903 | } | |
904 | } | |
905 | } | |
906 | if (free_watches > 1) | |
907 | { | |
908 | /* Try to split it across several registers. */ | |
909 | regs_copy = *regs; | |
910 | for (i = 0; i < get_num_valid (®s_copy); i++) | |
911 | { | |
912 | t_low = get_watchlo (®s_copy, i); | |
913 | t_hi = get_reg_mask (®s_copy, i) | IRW_MASK; | |
914 | if (t_low == 0 && irw == (t_hi & irw)) | |
915 | { | |
916 | t_low = addr & ~(CORE_ADDR)t_hi; | |
917 | break_addr = t_low + t_hi + 1; | |
918 | if (break_addr >= addr + len) | |
919 | segment_len = len; | |
920 | else | |
921 | segment_len = break_addr - addr; | |
922 | mask_bits = fill_mask (addr ^ (addr + segment_len - 1)); | |
923 | set_watchlo (®s_copy, i, (addr & ~mask_bits) | irw); | |
924 | set_watchhi (®s_copy, i, mask_bits & ~IRW_MASK); | |
925 | if (break_addr >= addr + len) | |
926 | { | |
927 | *regs = regs_copy; | |
928 | return 1; | |
929 | } | |
930 | len = addr + len - break_addr; | |
931 | addr = break_addr; | |
932 | } | |
933 | } | |
934 | } | |
935 | /* It didn't fit anywhere, we failed. */ | |
936 | return 0; | |
937 | } | |
938 | ||
939 | /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if | |
940 | the specified region can be covered by the watch registers. */ | |
941 | ||
942 | static int | |
943 | mips_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
944 | { | |
945 | struct pt_watch_regs dummy_regs; | |
946 | int i; | |
947 | ||
948 | if (!mips_linux_read_watch_registers (0)) | |
949 | return 0; | |
950 | ||
951 | dummy_regs = watch_readback; | |
952 | /* Clear them out. */ | |
953 | for (i = 0; i < get_num_valid (&dummy_regs); i++) | |
954 | set_watchlo (&dummy_regs, i, 0); | |
955 | return try_one_watch (&dummy_regs, addr, len, 0); | |
956 | } | |
957 | ||
958 | ||
959 | /* Write the mirrored watch register values for each thread. */ | |
960 | ||
961 | static int | |
962 | write_watchpoint_regs (void) | |
963 | { | |
964 | struct lwp_info *lp; | |
b9412953 DD |
965 | int tid; |
966 | ||
4c38200f | 967 | ALL_LWPS (lp) |
b9412953 | 968 | { |
4c38200f | 969 | tid = ptid_get_lwp (lp->ptid); |
b9412953 DD |
970 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1) |
971 | perror_with_name (_("Couldn't write debug register")); | |
972 | } | |
973 | return 0; | |
974 | } | |
975 | ||
976 | /* linux_nat new_thread implementation. Write the mirrored watch | |
977 | register values for the new thread. */ | |
978 | ||
979 | static void | |
7b50312a | 980 | mips_linux_new_thread (struct lwp_info *lp) |
b9412953 DD |
981 | { |
982 | int tid; | |
983 | ||
984 | if (!mips_linux_read_watch_registers (0)) | |
985 | return; | |
986 | ||
7b50312a | 987 | tid = ptid_get_lwp (lp->ptid); |
b9412953 DD |
988 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror) == -1) |
989 | perror_with_name (_("Couldn't write debug register")); | |
990 | } | |
991 | ||
992 | /* Fill in the watch registers with the currently cached watches. */ | |
993 | ||
994 | static void | |
995 | populate_regs_from_watches (struct pt_watch_regs *regs) | |
996 | { | |
997 | struct mips_watchpoint *w; | |
998 | int i; | |
999 | ||
1000 | /* Clear them out. */ | |
1001 | for (i = 0; i < get_num_valid (regs); i++) | |
1002 | { | |
1003 | set_watchlo (regs, i, 0); | |
1004 | set_watchhi (regs, i, 0); | |
1005 | } | |
1006 | ||
1007 | w = current_watches; | |
1008 | while (w) | |
1009 | { | |
1010 | i = try_one_watch (regs, w->addr, w->len, type_to_irw (w->type)); | |
1011 | /* They must all fit, because we previously calculated that they | |
1012 | would. */ | |
1013 | gdb_assert (i); | |
1014 | w = w->next; | |
1015 | } | |
1016 | } | |
1017 | ||
1018 | /* Target to_insert_watchpoint implementation. Try to insert a new | |
1019 | watch. Return zero on success. */ | |
1020 | ||
1021 | static int | |
0cf6dd15 TJB |
1022 | mips_linux_insert_watchpoint (CORE_ADDR addr, int len, int type, |
1023 | struct expression *cond) | |
b9412953 DD |
1024 | { |
1025 | struct pt_watch_regs regs; | |
1026 | struct mips_watchpoint *new_watch; | |
1027 | struct mips_watchpoint **pw; | |
1028 | ||
1029 | int i; | |
1030 | int retval; | |
1031 | ||
1032 | if (!mips_linux_read_watch_registers (0)) | |
1033 | return -1; | |
1034 | ||
1035 | if (len <= 0) | |
1036 | return -1; | |
1037 | ||
1038 | regs = watch_readback; | |
1039 | /* Add the current watches. */ | |
1040 | populate_regs_from_watches (®s); | |
1041 | ||
1042 | /* Now try to add the new watch. */ | |
1043 | if (!try_one_watch (®s, addr, len, type_to_irw (type))) | |
1044 | return -1; | |
1045 | ||
1046 | /* It fit. Stick it on the end of the list. */ | |
1047 | new_watch = (struct mips_watchpoint *) | |
1048 | xmalloc (sizeof (struct mips_watchpoint)); | |
1049 | new_watch->addr = addr; | |
1050 | new_watch->len = len; | |
1051 | new_watch->type = type; | |
1052 | new_watch->next = NULL; | |
1053 | ||
1054 | pw = ¤t_watches; | |
1055 | while (*pw != NULL) | |
1056 | pw = &(*pw)->next; | |
1057 | *pw = new_watch; | |
1058 | ||
1059 | watch_mirror = regs; | |
1060 | retval = write_watchpoint_regs (); | |
1061 | ||
1062 | if (maint_show_dr) | |
1063 | mips_show_dr ("insert_watchpoint", addr, len, type); | |
1064 | ||
1065 | return retval; | |
1066 | } | |
1067 | ||
1068 | /* Target to_remove_watchpoint implementation. Try to remove a watch. | |
1069 | Return zero on success. */ | |
1070 | ||
1071 | static int | |
0cf6dd15 TJB |
1072 | mips_linux_remove_watchpoint (CORE_ADDR addr, int len, int type, |
1073 | struct expression *cond) | |
b9412953 DD |
1074 | { |
1075 | int retval; | |
1076 | int deleted_one; | |
1077 | ||
1078 | struct mips_watchpoint **pw; | |
1079 | struct mips_watchpoint *w; | |
1080 | ||
1081 | /* Search for a known watch that matches. Then unlink and free | |
1082 | it. */ | |
1083 | deleted_one = 0; | |
1084 | pw = ¤t_watches; | |
1085 | while ((w = *pw)) | |
1086 | { | |
1087 | if (w->addr == addr && w->len == len && w->type == type) | |
1088 | { | |
1089 | *pw = w->next; | |
1090 | xfree (w); | |
1091 | deleted_one = 1; | |
1092 | break; | |
1093 | } | |
1094 | pw = &(w->next); | |
1095 | } | |
1096 | ||
1097 | if (!deleted_one) | |
1098 | return -1; /* We don't know about it, fail doing nothing. */ | |
1099 | ||
1100 | /* At this point watch_readback is known to be valid because we | |
1101 | could not have added the watch without reading it. */ | |
1102 | gdb_assert (watch_readback_valid == 1); | |
1103 | ||
1104 | watch_mirror = watch_readback; | |
1105 | populate_regs_from_watches (&watch_mirror); | |
1106 | ||
1107 | retval = write_watchpoint_regs (); | |
1108 | ||
1109 | if (maint_show_dr) | |
1110 | mips_show_dr ("remove_watchpoint", addr, len, type); | |
1111 | ||
1112 | return retval; | |
1113 | } | |
1114 | ||
1115 | /* Target to_close implementation. Free any watches and call the | |
1116 | super implementation. */ | |
1117 | ||
1118 | static void | |
460014f5 | 1119 | mips_linux_close (void) |
b9412953 DD |
1120 | { |
1121 | struct mips_watchpoint *w; | |
1122 | struct mips_watchpoint *nw; | |
1123 | ||
1124 | /* Clean out the current_watches list. */ | |
1125 | w = current_watches; | |
1126 | while (w) | |
1127 | { | |
1128 | nw = w->next; | |
1129 | xfree (w); | |
1130 | w = nw; | |
1131 | } | |
1132 | current_watches = NULL; | |
1133 | ||
1134 | if (super_close) | |
460014f5 | 1135 | super_close (); |
b9412953 DD |
1136 | } |
1137 | ||
10d6c8cd DJ |
1138 | void _initialize_mips_linux_nat (void); |
1139 | ||
1140 | void | |
1141 | _initialize_mips_linux_nat (void) | |
1142 | { | |
b9412953 DD |
1143 | struct target_ops *t; |
1144 | ||
cbe54154 PA |
1145 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, |
1146 | &maint_show_dr, _("\ | |
1147 | Set whether to show variables that mirror the mips debug registers."), _("\ | |
1148 | Show whether to show variables that mirror the mips debug registers."), _("\ | |
b9412953 DD |
1149 | Use \"on\" to enable, \"off\" to disable.\n\ |
1150 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
1151 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
1152 | triggers a breakpoint or watchpoint."), | |
cbe54154 PA |
1153 | NULL, |
1154 | NULL, | |
1155 | &maintenance_set_cmdlist, | |
1156 | &maintenance_show_cmdlist); | |
b9412953 DD |
1157 | |
1158 | t = linux_trad_target (mips_linux_register_u_offset); | |
1159 | ||
1160 | super_close = t->to_close; | |
1161 | t->to_close = mips_linux_close; | |
d37eb719 DJ |
1162 | |
1163 | super_fetch_registers = t->to_fetch_registers; | |
1164 | super_store_registers = t->to_store_registers; | |
1165 | ||
1166 | t->to_fetch_registers = mips64_linux_fetch_registers; | |
1167 | t->to_store_registers = mips64_linux_store_registers; | |
1168 | ||
b9412953 DD |
1169 | t->to_can_use_hw_breakpoint = mips_linux_can_use_hw_breakpoint; |
1170 | t->to_remove_watchpoint = mips_linux_remove_watchpoint; | |
1171 | t->to_insert_watchpoint = mips_linux_insert_watchpoint; | |
1172 | t->to_stopped_by_watchpoint = mips_linux_stopped_by_watchpoint; | |
1173 | t->to_stopped_data_address = mips_linux_stopped_data_address; | |
1174 | t->to_region_ok_for_hw_watchpoint = mips_linux_region_ok_for_hw_watchpoint; | |
1175 | ||
81adfced | 1176 | t->to_read_description = mips_linux_read_description; |
822b6570 | 1177 | |
f973ed9c | 1178 | linux_nat_add_target (t); |
b9412953 | 1179 | linux_nat_set_new_thread (t, mips_linux_new_thread); |
81adfced DJ |
1180 | |
1181 | /* Initialize the standard target descriptions. */ | |
1182 | initialize_tdesc_mips_linux (); | |
1faeff08 | 1183 | initialize_tdesc_mips_dsp_linux (); |
81adfced | 1184 | initialize_tdesc_mips64_linux (); |
1faeff08 | 1185 | initialize_tdesc_mips64_dsp_linux (); |
10d6c8cd | 1186 | } |