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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
47a35522 | 5 | Free Software Foundation, Inc. |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 14 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 15 | (at your option) any later version. |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b | 22 | You should have received a copy of the GNU General Public License |
a9762ec7 | 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
24 | |
25 | #include "defs.h" | |
26 | #include "gdb_string.h" | |
5e2e9765 | 27 | #include "gdb_assert.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
d1973055 | 42 | #include "mips-tdep.h" |
fe898f56 | 43 | #include "block.h" |
a4b8ebc8 | 44 | #include "reggroups.h" |
c906108c | 45 | #include "opcode/mips.h" |
c2d11a7d JM |
46 | #include "elf/mips.h" |
47 | #include "elf-bfd.h" | |
2475bac3 | 48 | #include "symcat.h" |
a4b8ebc8 | 49 | #include "sim-regno.h" |
a89aa300 | 50 | #include "dis-asm.h" |
edfae063 AC |
51 | #include "frame-unwind.h" |
52 | #include "frame-base.h" | |
53 | #include "trad-frame.h" | |
7d9b040b | 54 | #include "infcall.h" |
fed7ba43 | 55 | #include "floatformat.h" |
29709017 DJ |
56 | #include "remote.h" |
57 | #include "target-descriptions.h" | |
2bd0c3d7 | 58 | #include "dwarf2-frame.h" |
f8b73d13 | 59 | #include "user-regs.h" |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
24e05951 | 65 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
66 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
67 | #define ST0_FR (1 << 26) | |
68 | ||
b0069a17 AC |
69 | /* The sizes of floating point registers. */ |
70 | ||
71 | enum | |
72 | { | |
73 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
74 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
75 | }; | |
76 | ||
1a69e1e4 DJ |
77 | enum |
78 | { | |
79 | MIPS32_REGSIZE = 4, | |
80 | MIPS64_REGSIZE = 8 | |
81 | }; | |
0dadbba0 | 82 | |
2e4ebe70 DJ |
83 | static const char *mips_abi_string; |
84 | ||
85 | static const char *mips_abi_strings[] = { | |
86 | "auto", | |
87 | "n32", | |
88 | "o32", | |
28d169de | 89 | "n64", |
2e4ebe70 DJ |
90 | "o64", |
91 | "eabi32", | |
92 | "eabi64", | |
93 | NULL | |
94 | }; | |
95 | ||
f8b73d13 DJ |
96 | /* The standard register names, and all the valid aliases for them. */ |
97 | struct register_alias | |
98 | { | |
99 | const char *name; | |
100 | int regnum; | |
101 | }; | |
102 | ||
103 | /* Aliases for o32 and most other ABIs. */ | |
104 | const struct register_alias mips_o32_aliases[] = { | |
105 | { "ta0", 12 }, | |
106 | { "ta1", 13 }, | |
107 | { "ta2", 14 }, | |
108 | { "ta3", 15 } | |
109 | }; | |
110 | ||
111 | /* Aliases for n32 and n64. */ | |
112 | const struct register_alias mips_n32_n64_aliases[] = { | |
113 | { "ta0", 8 }, | |
114 | { "ta1", 9 }, | |
115 | { "ta2", 10 }, | |
116 | { "ta3", 11 } | |
117 | }; | |
118 | ||
119 | /* Aliases for ABI-independent registers. */ | |
120 | const struct register_alias mips_register_aliases[] = { | |
121 | /* The architecture manuals specify these ABI-independent names for | |
122 | the GPRs. */ | |
123 | #define R(n) { "r" #n, n } | |
124 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
125 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
126 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
127 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
128 | #undef R | |
129 | ||
130 | /* k0 and k1 are sometimes called these instead (for "kernel | |
131 | temp"). */ | |
132 | { "kt0", 26 }, | |
133 | { "kt1", 27 }, | |
134 | ||
135 | /* This is the traditional GDB name for the CP0 status register. */ | |
136 | { "sr", MIPS_PS_REGNUM }, | |
137 | ||
138 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
139 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
140 | ||
141 | /* This is the traditional GDB name for the FCSR. */ | |
142 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
143 | }; | |
144 | ||
7a292a7a | 145 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 146 | support single-precision floating-point operations. */ |
c906108c SS |
147 | |
148 | enum mips_fpu_type | |
6d82d43b AC |
149 | { |
150 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
151 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
152 | MIPS_FPU_NONE /* No floating point. */ | |
153 | }; | |
c906108c SS |
154 | |
155 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
156 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
157 | #endif | |
158 | static int mips_fpu_type_auto = 1; | |
159 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 160 | |
9ace0497 | 161 | static int mips_debug = 0; |
7a292a7a | 162 | |
29709017 DJ |
163 | /* Properties (for struct target_desc) describing the g/G packet |
164 | layout. */ | |
165 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
166 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
167 | ||
c2d11a7d JM |
168 | /* MIPS specific per-architecture information */ |
169 | struct gdbarch_tdep | |
6d82d43b AC |
170 | { |
171 | /* from the elf header */ | |
172 | int elf_flags; | |
173 | ||
174 | /* mips options */ | |
175 | enum mips_abi mips_abi; | |
176 | enum mips_abi found_abi; | |
177 | enum mips_fpu_type mips_fpu_type; | |
178 | int mips_last_arg_regnum; | |
179 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
180 | int default_mask_address_p; |
181 | /* Is the target using 64-bit raw integer registers but only | |
182 | storing a left-aligned 32-bit value in each? */ | |
183 | int mips64_transfers_32bit_regs_p; | |
184 | /* Indexes for various registers. IRIX and embedded have | |
185 | different values. This contains the "public" fields. Don't | |
186 | add any that do not need to be public. */ | |
187 | const struct mips_regnum *regnum; | |
188 | /* Register names table for the current register set. */ | |
189 | const char **mips_processor_reg_names; | |
29709017 DJ |
190 | |
191 | /* The size of register data available from the target, if known. | |
192 | This doesn't quite obsolete the manual | |
193 | mips64_transfers_32bit_regs_p, since that is documented to force | |
194 | left alignment even for big endian (very strange). */ | |
195 | int register_size_valid_p; | |
196 | int register_size; | |
6d82d43b | 197 | }; |
c2d11a7d | 198 | |
fed7ba43 JB |
199 | static int |
200 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
2244f671 | 201 | const void *from) |
fed7ba43 JB |
202 | { |
203 | return 1; | |
204 | } | |
205 | ||
206 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
207 | They are implemented as a pair of 64bit doubles where the high | |
208 | part holds the result of the operation rounded to double, and | |
209 | the low double holds the difference between the exact result and | |
210 | the rounded result. So "high" + "low" contains the result with | |
211 | added precision. Unfortunately, the floatformat structure used | |
212 | by GDB is not powerful enough to describe this format. As a temporary | |
213 | measure, we define a 128bit floatformat that only uses the high part. | |
214 | We lose a bit of precision but that's probably the best we can do | |
215 | for now with the current infrastructure. */ | |
216 | ||
217 | static const struct floatformat floatformat_n32n64_long_double_big = | |
218 | { | |
219 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
220 | floatformat_intbit_no, | |
8da61cc4 | 221 | "floatformat_n32n64_long_double_big", |
fed7ba43 JB |
222 | n32n64_floatformat_always_valid |
223 | }; | |
224 | ||
8da61cc4 DJ |
225 | static const struct floatformat *floatformats_n32n64_long[BFD_ENDIAN_UNKNOWN] = |
226 | { | |
227 | &floatformat_n32n64_long_double_big, | |
228 | &floatformat_n32n64_long_double_big | |
229 | }; | |
230 | ||
56cea623 AC |
231 | const struct mips_regnum * |
232 | mips_regnum (struct gdbarch *gdbarch) | |
233 | { | |
234 | return gdbarch_tdep (gdbarch)->regnum; | |
235 | } | |
236 | ||
237 | static int | |
238 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
239 | { | |
240 | return mips_regnum (gdbarch)->fp0 + 12; | |
241 | } | |
242 | ||
0dadbba0 | 243 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 244 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 245 | |
c2d11a7d | 246 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 247 | |
c2d11a7d | 248 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 249 | |
c2d11a7d | 250 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 251 | |
95404a3e AC |
252 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
253 | functions to test, set, or clear bit 0 of addresses. */ | |
254 | ||
255 | static CORE_ADDR | |
256 | is_mips16_addr (CORE_ADDR addr) | |
257 | { | |
258 | return ((addr) & 1); | |
259 | } | |
260 | ||
95404a3e AC |
261 | static CORE_ADDR |
262 | unmake_mips16_addr (CORE_ADDR addr) | |
263 | { | |
5b652102 | 264 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
265 | } |
266 | ||
d1973055 KB |
267 | /* Return the MIPS ABI associated with GDBARCH. */ |
268 | enum mips_abi | |
269 | mips_abi (struct gdbarch *gdbarch) | |
270 | { | |
271 | return gdbarch_tdep (gdbarch)->mips_abi; | |
272 | } | |
273 | ||
4246e332 | 274 | int |
1b13c4f6 | 275 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 276 | { |
29709017 DJ |
277 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
278 | ||
279 | /* If we know how big the registers are, use that size. */ | |
280 | if (tdep->register_size_valid_p) | |
281 | return tdep->register_size; | |
282 | ||
283 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
284 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
285 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
286 | } | |
287 | ||
480d3dd2 AC |
288 | /* Return the currently configured (or set) saved register size. */ |
289 | ||
e6bc2e8a | 290 | unsigned int |
13326b4e | 291 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 292 | { |
1a69e1e4 DJ |
293 | switch (mips_abi (gdbarch)) |
294 | { | |
295 | case MIPS_ABI_EABI32: | |
296 | case MIPS_ABI_O32: | |
297 | return 4; | |
298 | case MIPS_ABI_N32: | |
299 | case MIPS_ABI_N64: | |
300 | case MIPS_ABI_O64: | |
301 | case MIPS_ABI_EABI64: | |
302 | return 8; | |
303 | case MIPS_ABI_UNKNOWN: | |
304 | case MIPS_ABI_LAST: | |
305 | default: | |
306 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
307 | } | |
d929b26f AC |
308 | } |
309 | ||
71b8ef93 | 310 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 311 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 312 | "info" field is used for this purpose. |
5a89d8aa | 313 | |
95f1da47 | 314 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
315 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
316 | minimal symbol to mark it as a 16-bit function | |
317 | ||
f594e5e9 | 318 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 319 | |
5a89d8aa | 320 | static void |
6d82d43b AC |
321 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
322 | { | |
323 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
324 | { | |
325 | MSYMBOL_INFO (msym) = (char *) | |
326 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
327 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
328 | } | |
5a89d8aa MS |
329 | } |
330 | ||
71b8ef93 MS |
331 | static int |
332 | msymbol_is_special (struct minimal_symbol *msym) | |
333 | { | |
334 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
335 | } | |
336 | ||
88658117 AC |
337 | /* XFER a value from the big/little/left end of the register. |
338 | Depending on the size of the value it might occupy the entire | |
339 | register or just part of it. Make an allowance for this, aligning | |
340 | things accordingly. */ | |
341 | ||
342 | static void | |
343 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
870cd05e MK |
344 | enum bfd_endian endian, gdb_byte *in, |
345 | const gdb_byte *out, int buf_offset) | |
88658117 | 346 | { |
88658117 | 347 | int reg_offset = 0; |
f57d151a | 348 | gdb_assert (reg_num >= gdbarch_num_regs (current_gdbarch)); |
cb1d2653 AC |
349 | /* Need to transfer the left or right part of the register, based on |
350 | the targets byte order. */ | |
88658117 AC |
351 | switch (endian) |
352 | { | |
353 | case BFD_ENDIAN_BIG: | |
719ec221 | 354 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
355 | break; |
356 | case BFD_ENDIAN_LITTLE: | |
357 | reg_offset = 0; | |
358 | break; | |
6d82d43b | 359 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
360 | reg_offset = 0; |
361 | break; | |
362 | default: | |
e2e0b3e5 | 363 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
364 | } |
365 | if (mips_debug) | |
cb1d2653 AC |
366 | fprintf_unfiltered (gdb_stderr, |
367 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
368 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
369 | if (mips_debug && out != NULL) |
370 | { | |
371 | int i; | |
cb1d2653 | 372 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 373 | for (i = 0; i < length; i++) |
cb1d2653 | 374 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
375 | } |
376 | if (in != NULL) | |
6d82d43b AC |
377 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
378 | in + buf_offset); | |
88658117 | 379 | if (out != NULL) |
6d82d43b AC |
380 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
381 | out + buf_offset); | |
88658117 AC |
382 | if (mips_debug && in != NULL) |
383 | { | |
384 | int i; | |
cb1d2653 | 385 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 386 | for (i = 0; i < length; i++) |
cb1d2653 | 387 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
388 | } |
389 | if (mips_debug) | |
390 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
391 | } | |
392 | ||
dd824b04 DJ |
393 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
394 | compatiblity mode. A return value of 1 means that we have | |
395 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
396 | ||
397 | static int | |
9c9acae0 | 398 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 DJ |
399 | { |
400 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
401 | meaningful. */ | |
6d82d43b AC |
402 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
403 | 4) | |
dd824b04 DJ |
404 | return 0; |
405 | ||
406 | #if 0 | |
407 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
408 | in all the places we deal with FP registers. PR gdb/413. */ | |
409 | /* Otherwise check the FR bit in the status register - it controls | |
410 | the FP compatiblity mode. If it is clear we are in compatibility | |
411 | mode. */ | |
9c9acae0 | 412 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
413 | return 1; |
414 | #endif | |
361d1df0 | 415 | |
dd824b04 DJ |
416 | return 0; |
417 | } | |
418 | ||
7a292a7a | 419 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 420 | |
a14ed312 | 421 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 422 | |
a14ed312 | 423 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 424 | |
67b2c998 DJ |
425 | static struct type *mips_float_register_type (void); |
426 | static struct type *mips_double_register_type (void); | |
427 | ||
acdb74a0 AC |
428 | /* The list of available "set mips " and "show mips " commands */ |
429 | ||
430 | static struct cmd_list_element *setmipscmdlist = NULL; | |
431 | static struct cmd_list_element *showmipscmdlist = NULL; | |
432 | ||
5e2e9765 KB |
433 | /* Integer registers 0 thru 31 are handled explicitly by |
434 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 435 | are listed in the following tables. */ |
691c0433 | 436 | |
6d82d43b AC |
437 | enum |
438 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
439 | |
440 | /* Generic MIPS. */ | |
441 | ||
442 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
443 | "sr", "lo", "hi", "bad", "cause", "pc", |
444 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
445 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
446 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
447 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
448 | "fsr", "fir", "" /*"fp" */ , "", | |
449 | "", "", "", "", "", "", "", "", | |
450 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
451 | }; |
452 | ||
453 | /* Names of IDT R3041 registers. */ | |
454 | ||
455 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
456 | "sr", "lo", "hi", "bad", "cause", "pc", |
457 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
458 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
459 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
460 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
461 | "fsr", "fir", "", /*"fp" */ "", | |
462 | "", "", "bus", "ccfg", "", "", "", "", | |
463 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
464 | }; |
465 | ||
466 | /* Names of tx39 registers. */ | |
467 | ||
468 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
469 | "sr", "lo", "hi", "bad", "cause", "pc", |
470 | "", "", "", "", "", "", "", "", | |
471 | "", "", "", "", "", "", "", "", | |
472 | "", "", "", "", "", "", "", "", | |
473 | "", "", "", "", "", "", "", "", | |
474 | "", "", "", "", | |
475 | "", "", "", "", "", "", "", "", | |
476 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
477 | }; |
478 | ||
479 | /* Names of IRIX registers. */ | |
480 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
481 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
482 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
483 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
484 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
485 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
486 | }; |
487 | ||
cce74817 | 488 | |
5e2e9765 | 489 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 490 | static const char * |
5e2e9765 | 491 | mips_register_name (int regno) |
cce74817 | 492 | { |
691c0433 | 493 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
494 | /* GPR names for all ABIs other than n32/n64. */ |
495 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
496 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
497 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
498 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
499 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
500 | }; |
501 | ||
502 | /* GPR names for n32 and n64 ABIs. */ | |
503 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
504 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
505 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
506 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
507 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
508 | }; |
509 | ||
510 | enum mips_abi abi = mips_abi (current_gdbarch); | |
511 | ||
f57d151a UW |
512 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
513 | but then don't make the raw register names visible. */ | |
514 | int rawnum = regno % gdbarch_num_regs (current_gdbarch); | |
515 | if (regno < gdbarch_num_regs (current_gdbarch)) | |
a4b8ebc8 AC |
516 | return ""; |
517 | ||
5e2e9765 KB |
518 | /* The MIPS integer registers are always mapped from 0 to 31. The |
519 | names of the registers (which reflects the conventions regarding | |
520 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 521 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
522 | { |
523 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 524 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 525 | else |
a4b8ebc8 | 526 | return mips_gpr_names[rawnum]; |
5e2e9765 | 527 | } |
f8b73d13 DJ |
528 | else if (tdesc_has_registers (gdbarch_target_desc (current_gdbarch))) |
529 | return tdesc_register_name (rawnum); | |
f57d151a | 530 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (current_gdbarch)) |
691c0433 AC |
531 | { |
532 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
533 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
534 | } | |
5e2e9765 KB |
535 | else |
536 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 537 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 538 | } |
5e2e9765 | 539 | |
a4b8ebc8 | 540 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 541 | |
a4b8ebc8 AC |
542 | static int |
543 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
544 | struct reggroup *reggroup) | |
545 | { | |
546 | int vector_p; | |
547 | int float_p; | |
548 | int raw_p; | |
f57d151a UW |
549 | int rawnum = regnum % gdbarch_num_regs (current_gdbarch); |
550 | int pseudo = regnum / gdbarch_num_regs (current_gdbarch); | |
a4b8ebc8 AC |
551 | if (reggroup == all_reggroup) |
552 | return pseudo; | |
553 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
554 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
555 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
556 | (gdbarch), as not all architectures are multi-arch. */ | |
f57d151a | 557 | raw_p = rawnum < gdbarch_num_regs (current_gdbarch); |
c9f4d572 UW |
558 | if (gdbarch_register_name (current_gdbarch, regnum) == NULL |
559 | || gdbarch_register_name (current_gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
560 | return 0; |
561 | if (reggroup == float_reggroup) | |
562 | return float_p && pseudo; | |
563 | if (reggroup == vector_reggroup) | |
564 | return vector_p && pseudo; | |
565 | if (reggroup == general_reggroup) | |
566 | return (!vector_p && !float_p) && pseudo; | |
567 | /* Save the pseudo registers. Need to make certain that any code | |
568 | extracting register values from a saved register cache also uses | |
569 | pseudo registers. */ | |
570 | if (reggroup == save_reggroup) | |
571 | return raw_p && pseudo; | |
572 | /* Restore the same pseudo register. */ | |
573 | if (reggroup == restore_reggroup) | |
574 | return raw_p && pseudo; | |
6d82d43b | 575 | return 0; |
a4b8ebc8 AC |
576 | } |
577 | ||
f8b73d13 DJ |
578 | /* Return the groups that a MIPS register can be categorised into. |
579 | This version is only used if we have a target description which | |
580 | describes real registers (and their groups). */ | |
581 | ||
582 | static int | |
583 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
584 | struct reggroup *reggroup) | |
585 | { | |
586 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
587 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
588 | int ret; | |
589 | ||
590 | /* Only save, restore, and display the pseudo registers. Need to | |
591 | make certain that any code extracting register values from a | |
592 | saved register cache also uses pseudo registers. | |
593 | ||
594 | Note: saving and restoring the pseudo registers is slightly | |
595 | strange; if we have 64 bits, we should save and restore all | |
596 | 64 bits. But this is hard and has little benefit. */ | |
597 | if (!pseudo) | |
598 | return 0; | |
599 | ||
600 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
601 | if (ret != -1) | |
602 | return ret; | |
603 | ||
604 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
605 | } | |
606 | ||
a4b8ebc8 | 607 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 608 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 609 | registers. Take care of alignment and size problems. */ |
c5aa993b | 610 | |
a4b8ebc8 AC |
611 | static void |
612 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 613 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 614 | { |
f57d151a UW |
615 | int rawnum = cookednum % gdbarch_num_regs (current_gdbarch); |
616 | gdb_assert (cookednum >= gdbarch_num_regs (current_gdbarch) | |
617 | && cookednum < 2 * gdbarch_num_regs (current_gdbarch)); | |
47ebcfbe | 618 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 619 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
620 | else if (register_size (gdbarch, rawnum) > |
621 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
622 | { |
623 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
4c6b5505 | 624 | || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
625 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
626 | else | |
627 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
628 | } | |
629 | else | |
e2e0b3e5 | 630 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
631 | } |
632 | ||
633 | static void | |
6d82d43b AC |
634 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
635 | struct regcache *regcache, int cookednum, | |
47a35522 | 636 | const gdb_byte *buf) |
a4b8ebc8 | 637 | { |
f57d151a UW |
638 | int rawnum = cookednum % gdbarch_num_regs (current_gdbarch); |
639 | gdb_assert (cookednum >= gdbarch_num_regs (current_gdbarch) | |
640 | && cookednum < 2 * gdbarch_num_regs (current_gdbarch)); | |
47ebcfbe | 641 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 642 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
643 | else if (register_size (gdbarch, rawnum) > |
644 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
645 | { |
646 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
4c6b5505 | 647 | || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
648 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
649 | else | |
650 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
651 | } | |
652 | else | |
e2e0b3e5 | 653 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 654 | } |
c5aa993b | 655 | |
c906108c | 656 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 657 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
658 | |
659 | /* Heuristic_proc_start may hunt through the text section for a long | |
660 | time across a 2400 baud serial line. Allows the user to limit this | |
661 | search. */ | |
662 | ||
663 | static unsigned int heuristic_fence_post = 0; | |
664 | ||
46cd78fb | 665 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
666 | register N. NOTE: This defines the pseudo register type so need to |
667 | rebuild the architecture vector. */ | |
43e526b9 JM |
668 | |
669 | static int mips64_transfers_32bit_regs_p = 0; | |
670 | ||
719ec221 AC |
671 | static void |
672 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
673 | struct cmd_list_element *c) | |
43e526b9 | 674 | { |
719ec221 AC |
675 | struct gdbarch_info info; |
676 | gdbarch_info_init (&info); | |
677 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
678 | instead of relying on globals. Doing that would let generic code | |
679 | handle the search for this specific architecture. */ | |
680 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 681 | { |
719ec221 | 682 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 683 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 684 | } |
a4b8ebc8 AC |
685 | } |
686 | ||
47ebcfbe | 687 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 688 | |
ff2e87ac AC |
689 | static int |
690 | mips_convert_register_p (int regnum, struct type *type) | |
691 | { | |
4c6b5505 | 692 | return (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
719ec221 | 693 | && register_size (current_gdbarch, regnum) == 4 |
f57d151a UW |
694 | && (regnum % gdbarch_num_regs (current_gdbarch)) |
695 | >= mips_regnum (current_gdbarch)->fp0 | |
696 | && (regnum % gdbarch_num_regs (current_gdbarch)) | |
697 | < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 698 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
699 | } |
700 | ||
42c466d7 | 701 | static void |
ff2e87ac | 702 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 703 | struct type *type, gdb_byte *to) |
102182a9 | 704 | { |
47a35522 MK |
705 | get_frame_register (frame, regnum + 0, to + 4); |
706 | get_frame_register (frame, regnum + 1, to + 0); | |
102182a9 MS |
707 | } |
708 | ||
42c466d7 | 709 | static void |
ff2e87ac | 710 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 711 | struct type *type, const gdb_byte *from) |
102182a9 | 712 | { |
47a35522 MK |
713 | put_frame_register (frame, regnum + 0, from + 4); |
714 | put_frame_register (frame, regnum + 1, from + 0); | |
102182a9 MS |
715 | } |
716 | ||
a4b8ebc8 AC |
717 | /* Return the GDB type object for the "standard" data type of data in |
718 | register REG. */ | |
78fde5f8 KB |
719 | |
720 | static struct type * | |
a4b8ebc8 AC |
721 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
722 | { | |
f57d151a UW |
723 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (current_gdbarch)); |
724 | if ((regnum % gdbarch_num_regs (current_gdbarch)) | |
725 | >= mips_regnum (current_gdbarch)->fp0 | |
726 | && (regnum % gdbarch_num_regs (current_gdbarch)) | |
727 | < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 728 | { |
5ef80fb0 | 729 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 730 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 DJ |
731 | if (mips_isa_regsize (gdbarch) == 4) |
732 | return builtin_type_ieee_single; | |
733 | else | |
734 | return builtin_type_ieee_double; | |
a6425924 | 735 | } |
f57d151a | 736 | else if (regnum < gdbarch_num_regs (current_gdbarch)) |
d5ac5a39 AC |
737 | { |
738 | /* The raw or ISA registers. These are all sized according to | |
739 | the ISA regsize. */ | |
740 | if (mips_isa_regsize (gdbarch) == 4) | |
741 | return builtin_type_int32; | |
742 | else | |
743 | return builtin_type_int64; | |
744 | } | |
78fde5f8 | 745 | else |
d5ac5a39 AC |
746 | { |
747 | /* The cooked or ABI registers. These are sized according to | |
748 | the ABI (with a few complications). */ | |
f57d151a | 749 | if (regnum >= (gdbarch_num_regs (current_gdbarch) |
d5ac5a39 | 750 | + mips_regnum (current_gdbarch)->fp_control_status) |
f57d151a UW |
751 | && regnum <= gdbarch_num_regs (current_gdbarch) |
752 | + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
753 | /* The pseudo/cooked view of the embedded registers is always |
754 | 32-bit. The raw view is handled below. */ | |
755 | return builtin_type_int32; | |
756 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
757 | /* The target, while possibly using a 64-bit register buffer, | |
758 | is only transfering 32-bits of each integer register. | |
759 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
760 | return builtin_type_int32; | |
761 | else if (mips_abi_regsize (gdbarch) == 4) | |
762 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
763 | 32- or 64-bit). */ | |
764 | return builtin_type_int32; | |
765 | else | |
766 | /* 64-bit ABI. */ | |
767 | return builtin_type_int64; | |
768 | } | |
78fde5f8 KB |
769 | } |
770 | ||
f8b73d13 DJ |
771 | /* Return the GDB type for the pseudo register REGNUM, which is the |
772 | ABI-level view. This function is only called if there is a target | |
773 | description which includes registers, so we know precisely the | |
774 | types of hardware registers. */ | |
775 | ||
776 | static struct type * | |
777 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
778 | { | |
779 | const int num_regs = gdbarch_num_regs (gdbarch); | |
780 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
781 | int rawnum = regnum % num_regs; | |
782 | struct type *rawtype; | |
783 | ||
784 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
785 | ||
786 | /* Absent registers are still absent. */ | |
787 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
788 | if (TYPE_LENGTH (rawtype) == 0) | |
789 | return rawtype; | |
790 | ||
791 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
792 | /* Present the floating point registers however the hardware did; | |
793 | do not try to convert between FPU layouts. */ | |
794 | return rawtype; | |
795 | ||
796 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
797 | { | |
798 | /* The pseudo/cooked view of embedded registers is always | |
799 | 32-bit, even if the target transfers 64-bit values for them. | |
800 | New targets relying on XML descriptions should only transfer | |
801 | the necessary 32 bits, but older versions of GDB expected 64, | |
802 | so allow the target to provide 64 bits without interfering | |
803 | with the displayed type. */ | |
804 | return builtin_type_int32; | |
805 | } | |
806 | ||
807 | /* Use pointer types for registers if we can. For n32 we can not, | |
808 | since we do not have a 64-bit pointer type. */ | |
809 | if (mips_abi_regsize (gdbarch) == TYPE_LENGTH (builtin_type_void_data_ptr)) | |
810 | { | |
811 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
812 | return builtin_type_void_data_ptr; | |
813 | else if (rawnum == MIPS_EMBED_PC_REGNUM) | |
814 | return builtin_type_void_func_ptr; | |
815 | } | |
816 | ||
817 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
818 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
819 | return builtin_type_int32; | |
820 | ||
821 | /* For all other registers, pass through the hardware type. */ | |
822 | return rawtype; | |
823 | } | |
bcb0cc15 | 824 | |
c906108c | 825 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 826 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
827 | |
828 | static int | |
480d3dd2 | 829 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
830 | { |
831 | switch (mask_address_var) | |
832 | { | |
7f19b9a2 | 833 | case AUTO_BOOLEAN_TRUE: |
4014092b | 834 | return 1; |
7f19b9a2 | 835 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
836 | return 0; |
837 | break; | |
7f19b9a2 | 838 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 839 | return tdep->default_mask_address_p; |
4014092b | 840 | default: |
e2e0b3e5 | 841 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 842 | return -1; |
361d1df0 | 843 | } |
4014092b AC |
844 | } |
845 | ||
846 | static void | |
08546159 AC |
847 | show_mask_address (struct ui_file *file, int from_tty, |
848 | struct cmd_list_element *c, const char *value) | |
4014092b | 849 | { |
480d3dd2 | 850 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
08546159 AC |
851 | |
852 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
853 | switch (mask_address_var) |
854 | { | |
7f19b9a2 | 855 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
856 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
857 | break; | |
7f19b9a2 | 858 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
859 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
860 | break; | |
7f19b9a2 | 861 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
862 | printf_filtered |
863 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
864 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
865 | break; |
866 | default: | |
e2e0b3e5 | 867 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 868 | break; |
361d1df0 | 869 | } |
4014092b | 870 | } |
c906108c | 871 | |
c906108c SS |
872 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
873 | ||
0fe7e7c8 AC |
874 | int |
875 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
876 | { |
877 | struct minimal_symbol *sym; | |
878 | ||
879 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 880 | if (is_mips16_addr (memaddr)) |
c906108c SS |
881 | return 1; |
882 | ||
883 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
884 | the high bit of the info field. Use this to decide if the function is | |
885 | MIPS16 or normal MIPS. */ | |
886 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
887 | if (sym) | |
71b8ef93 | 888 | return msymbol_is_special (sym); |
c906108c SS |
889 | else |
890 | return 0; | |
891 | } | |
892 | ||
b2fa5097 | 893 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
894 | all registers should be sign extended for simplicity? */ |
895 | ||
896 | static CORE_ADDR | |
61a1198a | 897 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 898 | { |
61a1198a UW |
899 | ULONGEST pc; |
900 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
901 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
902 | return pc; | |
b6cb9035 AC |
903 | } |
904 | ||
58dfe9ff AC |
905 | static CORE_ADDR |
906 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
907 | { | |
edfae063 | 908 | return frame_unwind_register_signed (next_frame, |
f57d151a UW |
909 | gdbarch_num_regs (current_gdbarch) |
910 | + mips_regnum (gdbarch)->pc); | |
edfae063 AC |
911 | } |
912 | ||
30244cd8 UW |
913 | static CORE_ADDR |
914 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
915 | { | |
f57d151a UW |
916 | return frame_unwind_register_signed (next_frame, |
917 | gdbarch_num_regs (current_gdbarch) | |
918 | + MIPS_SP_REGNUM); | |
30244cd8 UW |
919 | } |
920 | ||
edfae063 AC |
921 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
922 | dummy frame. The frame ID's base needs to match the TOS value | |
923 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
924 | breakpoint. */ | |
925 | ||
926 | static struct frame_id | |
927 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
928 | { | |
f57d151a UW |
929 | return frame_id_build |
930 | (frame_unwind_register_signed (next_frame, | |
931 | gdbarch_num_regs (current_gdbarch) | |
932 | + MIPS_SP_REGNUM), | |
933 | frame_pc_unwind (next_frame)); | |
58dfe9ff AC |
934 | } |
935 | ||
b6cb9035 | 936 | static void |
61a1198a | 937 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 938 | { |
61a1198a UW |
939 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
940 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 941 | } |
c906108c | 942 | |
c906108c SS |
943 | /* Fetch and return instruction from the specified location. If the PC |
944 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
945 | ||
d37cca3d | 946 | static ULONGEST |
acdb74a0 | 947 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 948 | { |
47a35522 | 949 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
950 | int instlen; |
951 | int status; | |
952 | ||
0fe7e7c8 | 953 | if (mips_pc_is_mips16 (addr)) |
c906108c | 954 | { |
95ac2dcf | 955 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 956 | addr = unmake_mips16_addr (addr); |
c906108c SS |
957 | } |
958 | else | |
95ac2dcf | 959 | instlen = MIPS_INSN32_SIZE; |
359a9262 | 960 | status = read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
961 | if (status) |
962 | memory_error (status, addr); | |
963 | return extract_unsigned_integer (buf, instlen); | |
964 | } | |
965 | ||
c906108c | 966 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
967 | #define mips32_op(x) (x >> 26) |
968 | #define itype_op(x) (x >> 26) | |
969 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 970 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 971 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 972 | |
e135b889 DJ |
973 | #define jtype_op(x) (x >> 26) |
974 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 975 | |
e135b889 DJ |
976 | #define rtype_op(x) (x >> 26) |
977 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
978 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
979 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
980 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
981 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 982 | |
06987e64 MK |
983 | static LONGEST |
984 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 985 | { |
06987e64 | 986 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
987 | } |
988 | ||
f49e4e6d MS |
989 | /* Determine where to set a single step breakpoint while considering |
990 | branch prediction. */ | |
5a89d8aa | 991 | static CORE_ADDR |
0b1b3e42 | 992 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b JM |
993 | { |
994 | unsigned long inst; | |
995 | int op; | |
996 | inst = mips_fetch_instruction (pc); | |
e135b889 | 997 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 998 | { |
e135b889 | 999 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1000 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1001 | { |
e135b889 | 1002 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1003 | switch (op) |
1004 | { | |
e135b889 DJ |
1005 | case 0: /* BEQL */ |
1006 | goto equal_branch; | |
1007 | case 1: /* BNEL */ | |
1008 | goto neq_branch; | |
1009 | case 2: /* BLEZL */ | |
1010 | goto less_branch; | |
1011 | case 3: /* BGTZ */ | |
1012 | goto greater_branch; | |
c5aa993b JM |
1013 | default: |
1014 | pc += 4; | |
c906108c SS |
1015 | } |
1016 | } | |
e135b889 | 1017 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1018 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1019 | { |
1020 | int tf = itype_rt (inst) & 0x01; | |
1021 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 1022 | int fcrcs = |
0b1b3e42 UW |
1023 | get_frame_register_signed (frame, mips_regnum (current_gdbarch)-> |
1024 | fp_control_status); | |
e135b889 DJ |
1025 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1026 | ||
1027 | if (((cond >> cnum) & 0x01) == tf) | |
1028 | pc += mips32_relative_offset (inst) + 4; | |
1029 | else | |
1030 | pc += 8; | |
1031 | } | |
c5aa993b JM |
1032 | else |
1033 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1034 | } |
1035 | else | |
c5aa993b JM |
1036 | { /* This gets way messy */ |
1037 | ||
c906108c | 1038 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1039 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1040 | { |
c5aa993b JM |
1041 | case 0: /* SPECIAL */ |
1042 | op = rtype_funct (inst); | |
1043 | switch (op) | |
1044 | { | |
1045 | case 8: /* JR */ | |
1046 | case 9: /* JALR */ | |
6c997a34 | 1047 | /* Set PC to that address */ |
0b1b3e42 | 1048 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b JM |
1049 | break; |
1050 | default: | |
1051 | pc += 4; | |
1052 | } | |
1053 | ||
6d82d43b | 1054 | break; /* end SPECIAL */ |
c5aa993b | 1055 | case 1: /* REGIMM */ |
c906108c | 1056 | { |
e135b889 DJ |
1057 | op = itype_rt (inst); /* branch condition */ |
1058 | switch (op) | |
c906108c | 1059 | { |
c5aa993b | 1060 | case 0: /* BLTZ */ |
e135b889 DJ |
1061 | case 2: /* BLTZL */ |
1062 | case 16: /* BLTZAL */ | |
c5aa993b | 1063 | case 18: /* BLTZALL */ |
c906108c | 1064 | less_branch: |
0b1b3e42 | 1065 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1066 | pc += mips32_relative_offset (inst) + 4; |
1067 | else | |
1068 | pc += 8; /* after the delay slot */ | |
1069 | break; | |
e135b889 | 1070 | case 1: /* BGEZ */ |
c5aa993b JM |
1071 | case 3: /* BGEZL */ |
1072 | case 17: /* BGEZAL */ | |
1073 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1074 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1075 | pc += mips32_relative_offset (inst) + 4; |
1076 | else | |
1077 | pc += 8; /* after the delay slot */ | |
1078 | break; | |
e135b889 | 1079 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1080 | default: |
1081 | pc += 4; | |
c906108c SS |
1082 | } |
1083 | } | |
6d82d43b | 1084 | break; /* end REGIMM */ |
c5aa993b JM |
1085 | case 2: /* J */ |
1086 | case 3: /* JAL */ | |
1087 | { | |
1088 | unsigned long reg; | |
1089 | reg = jtype_target (inst) << 2; | |
e135b889 | 1090 | /* Upper four bits get never changed... */ |
5b652102 | 1091 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1092 | } |
c5aa993b JM |
1093 | break; |
1094 | /* FIXME case JALX : */ | |
1095 | { | |
1096 | unsigned long reg; | |
1097 | reg = jtype_target (inst) << 2; | |
5b652102 | 1098 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1099 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1100 | } | |
c5aa993b | 1101 | break; /* The new PC will be alternate mode */ |
e135b889 | 1102 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1103 | equal_branch: |
0b1b3e42 UW |
1104 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1105 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1106 | pc += mips32_relative_offset (inst) + 4; |
1107 | else | |
1108 | pc += 8; | |
1109 | break; | |
e135b889 | 1110 | case 5: /* BNE, BNEL */ |
c5aa993b | 1111 | neq_branch: |
0b1b3e42 UW |
1112 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1113 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1114 | pc += mips32_relative_offset (inst) + 4; |
1115 | else | |
1116 | pc += 8; | |
1117 | break; | |
e135b889 | 1118 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1119 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1120 | pc += mips32_relative_offset (inst) + 4; |
1121 | else | |
1122 | pc += 8; | |
1123 | break; | |
1124 | case 7: | |
e135b889 DJ |
1125 | default: |
1126 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1127 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1128 | pc += mips32_relative_offset (inst) + 4; |
1129 | else | |
1130 | pc += 8; | |
1131 | break; | |
c5aa993b JM |
1132 | } /* switch */ |
1133 | } /* else */ | |
1134 | return pc; | |
1135 | } /* mips32_next_pc */ | |
c906108c SS |
1136 | |
1137 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1138 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1139 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1140 | We dont want to set a single step instruction on the extend instruction | |
1141 | either. | |
c5aa993b | 1142 | */ |
c906108c SS |
1143 | |
1144 | /* Lots of mips16 instruction formats */ | |
1145 | /* Predicting jumps requires itype,ritype,i8type | |
1146 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1147 | */ |
c906108c SS |
1148 | enum mips16_inst_fmts |
1149 | { | |
c5aa993b JM |
1150 | itype, /* 0 immediate 5,10 */ |
1151 | ritype, /* 1 5,3,8 */ | |
1152 | rrtype, /* 2 5,3,3,5 */ | |
1153 | rritype, /* 3 5,3,3,5 */ | |
1154 | rrrtype, /* 4 5,3,3,3,2 */ | |
1155 | rriatype, /* 5 5,3,3,1,4 */ | |
1156 | shifttype, /* 6 5,3,3,3,2 */ | |
1157 | i8type, /* 7 5,3,8 */ | |
1158 | i8movtype, /* 8 5,3,3,5 */ | |
1159 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1160 | i64type, /* 10 5,3,8 */ | |
1161 | ri64type, /* 11 5,3,3,5 */ | |
1162 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1163 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1164 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1165 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1166 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1167 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1168 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1169 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1170 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1171 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1172 | }; | |
12f02c2a AC |
1173 | /* I am heaping all the fields of the formats into one structure and |
1174 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1175 | struct upk_mips16 |
6d82d43b AC |
1176 | { |
1177 | CORE_ADDR offset; | |
1178 | unsigned int regx; /* Function in i8 type */ | |
1179 | unsigned int regy; | |
1180 | }; | |
c906108c SS |
1181 | |
1182 | ||
12f02c2a AC |
1183 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1184 | for the bits which make up the immediatate extension. */ | |
c906108c | 1185 | |
12f02c2a AC |
1186 | static CORE_ADDR |
1187 | extended_offset (unsigned int extension) | |
c906108c | 1188 | { |
12f02c2a | 1189 | CORE_ADDR value; |
c5aa993b JM |
1190 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1191 | value = value << 6; | |
1192 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1193 | value = value << 5; | |
1194 | value |= extension & 0x01f; /* extract 4:0 */ | |
1195 | return value; | |
c906108c SS |
1196 | } |
1197 | ||
1198 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1199 | instruction. It won't malfunction, but why make excess remote memory |
1200 | references? If the immediate operands get sign extended or something, | |
1201 | do it after the extension is performed. */ | |
c906108c | 1202 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1203 | when the offset is to be used in relative addressing. */ |
c906108c | 1204 | |
12f02c2a | 1205 | static unsigned int |
c5aa993b | 1206 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1207 | { |
47a35522 | 1208 | gdb_byte buf[8]; |
c5aa993b JM |
1209 | pc &= 0xfffffffe; /* clear the low order bit */ |
1210 | target_read_memory (pc, buf, 2); | |
1211 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1212 | } |
1213 | ||
1214 | static void | |
c5aa993b | 1215 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1216 | unsigned int extension, |
1217 | unsigned int inst, | |
6d82d43b | 1218 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1219 | { |
12f02c2a AC |
1220 | CORE_ADDR offset; |
1221 | int regx; | |
1222 | int regy; | |
1223 | switch (insn_format) | |
c906108c | 1224 | { |
c5aa993b | 1225 | case itype: |
c906108c | 1226 | { |
12f02c2a AC |
1227 | CORE_ADDR value; |
1228 | if (extension) | |
c5aa993b JM |
1229 | { |
1230 | value = extended_offset (extension); | |
1231 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1232 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1233 | } |
1234 | else | |
c5aa993b | 1235 | { |
12f02c2a | 1236 | value = inst & 0x7ff; |
c5aa993b | 1237 | /* FIXME : Consider sign extension */ |
c906108c | 1238 | } |
12f02c2a AC |
1239 | offset = value; |
1240 | regx = -1; | |
1241 | regy = -1; | |
c906108c | 1242 | } |
c5aa993b JM |
1243 | break; |
1244 | case ritype: | |
1245 | case i8type: | |
1246 | { /* A register identifier and an offset */ | |
c906108c SS |
1247 | /* Most of the fields are the same as I type but the |
1248 | immediate value is of a different length */ | |
12f02c2a AC |
1249 | CORE_ADDR value; |
1250 | if (extension) | |
c906108c | 1251 | { |
c5aa993b JM |
1252 | value = extended_offset (extension); |
1253 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1254 | value |= inst & 0xff; /* eleven bits from instruction */ |
1255 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1256 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1257 | { | |
1258 | value &= ~0x3fff; /* remove the sign bit */ | |
1259 | value = -value; | |
c906108c SS |
1260 | } |
1261 | } | |
c5aa993b JM |
1262 | else |
1263 | { | |
12f02c2a AC |
1264 | value = inst & 0xff; /* 8 bits */ |
1265 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1266 | /* FIXME: Do sign extension , this format needs it */ |
1267 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1268 | { | |
1269 | value &= 0xef; /* remove the sign bit */ | |
1270 | value = -value; | |
1271 | } | |
c5aa993b | 1272 | } |
12f02c2a AC |
1273 | offset = value; |
1274 | regy = -1; | |
c5aa993b | 1275 | break; |
c906108c | 1276 | } |
c5aa993b | 1277 | case jalxtype: |
c906108c | 1278 | { |
c5aa993b | 1279 | unsigned long value; |
12f02c2a AC |
1280 | unsigned int nexthalf; |
1281 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1282 | value = value << 16; |
1283 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1284 | value |= nexthalf; | |
12f02c2a AC |
1285 | offset = value; |
1286 | regx = -1; | |
1287 | regy = -1; | |
c5aa993b | 1288 | break; |
c906108c SS |
1289 | } |
1290 | default: | |
e2e0b3e5 | 1291 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1292 | } |
12f02c2a AC |
1293 | upk->offset = offset; |
1294 | upk->regx = regx; | |
1295 | upk->regy = regy; | |
c906108c SS |
1296 | } |
1297 | ||
1298 | ||
c5aa993b JM |
1299 | static CORE_ADDR |
1300 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1301 | { |
5b652102 | 1302 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1303 | } |
1304 | ||
12f02c2a | 1305 | static CORE_ADDR |
0b1b3e42 | 1306 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1307 | unsigned int extension, unsigned int insn) |
c906108c | 1308 | { |
12f02c2a AC |
1309 | int op = (insn >> 11); |
1310 | switch (op) | |
c906108c | 1311 | { |
6d82d43b | 1312 | case 2: /* Branch */ |
12f02c2a AC |
1313 | { |
1314 | CORE_ADDR offset; | |
1315 | struct upk_mips16 upk; | |
1316 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1317 | offset = upk.offset; | |
1318 | if (offset & 0x800) | |
1319 | { | |
1320 | offset &= 0xeff; | |
1321 | offset = -offset; | |
1322 | } | |
1323 | pc += (offset << 1) + 2; | |
1324 | break; | |
1325 | } | |
6d82d43b | 1326 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1327 | { |
1328 | struct upk_mips16 upk; | |
1329 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1330 | pc = add_offset_16 (pc, upk.offset); | |
1331 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1332 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1333 | else | |
1334 | pc |= 0x01; | |
1335 | break; | |
1336 | } | |
6d82d43b | 1337 | case 4: /* beqz */ |
12f02c2a AC |
1338 | { |
1339 | struct upk_mips16 upk; | |
1340 | int reg; | |
1341 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1342 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1343 | if (reg == 0) |
1344 | pc += (upk.offset << 1) + 2; | |
1345 | else | |
1346 | pc += 2; | |
1347 | break; | |
1348 | } | |
6d82d43b | 1349 | case 5: /* bnez */ |
12f02c2a AC |
1350 | { |
1351 | struct upk_mips16 upk; | |
1352 | int reg; | |
1353 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1354 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1355 | if (reg != 0) |
1356 | pc += (upk.offset << 1) + 2; | |
1357 | else | |
1358 | pc += 2; | |
1359 | break; | |
1360 | } | |
6d82d43b | 1361 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1362 | { |
1363 | struct upk_mips16 upk; | |
1364 | int reg; | |
1365 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1366 | /* upk.regx contains the opcode */ | |
0b1b3e42 | 1367 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1368 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1369 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1370 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1371 | pc += (upk.offset << 1) + 2; | |
1372 | else | |
1373 | pc += 2; | |
1374 | break; | |
1375 | } | |
6d82d43b | 1376 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1377 | { |
1378 | struct upk_mips16 upk; | |
1379 | /* upk.fmt = rrtype; */ | |
1380 | op = insn & 0x1f; | |
1381 | if (op == 0) | |
c5aa993b | 1382 | { |
12f02c2a AC |
1383 | int reg; |
1384 | upk.regx = (insn >> 8) & 0x07; | |
1385 | upk.regy = (insn >> 5) & 0x07; | |
1386 | switch (upk.regy) | |
c5aa993b | 1387 | { |
12f02c2a AC |
1388 | case 0: |
1389 | reg = upk.regx; | |
1390 | break; | |
1391 | case 1: | |
1392 | reg = 31; | |
6d82d43b | 1393 | break; /* Function return instruction */ |
12f02c2a AC |
1394 | case 2: |
1395 | reg = upk.regx; | |
1396 | break; | |
1397 | default: | |
1398 | reg = 31; | |
6d82d43b | 1399 | break; /* BOGUS Guess */ |
c906108c | 1400 | } |
0b1b3e42 | 1401 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1402 | } |
12f02c2a | 1403 | else |
c5aa993b | 1404 | pc += 2; |
12f02c2a AC |
1405 | break; |
1406 | } | |
1407 | case 30: | |
1408 | /* This is an instruction extension. Fetch the real instruction | |
1409 | (which follows the extension) and decode things based on | |
1410 | that. */ | |
1411 | { | |
1412 | pc += 2; | |
0b1b3e42 | 1413 | pc = extended_mips16_next_pc (frame, pc, insn, fetch_mips_16 (pc)); |
12f02c2a AC |
1414 | break; |
1415 | } | |
1416 | default: | |
1417 | { | |
1418 | pc += 2; | |
1419 | break; | |
1420 | } | |
c906108c | 1421 | } |
c5aa993b | 1422 | return pc; |
12f02c2a | 1423 | } |
c906108c | 1424 | |
5a89d8aa | 1425 | static CORE_ADDR |
0b1b3e42 | 1426 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a AC |
1427 | { |
1428 | unsigned int insn = fetch_mips_16 (pc); | |
0b1b3e42 | 1429 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1430 | } |
1431 | ||
1432 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1433 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1434 | It works by decoding the current instruction and predicting where a |
1435 | branch will go. This isnt hard because all the data is available. | |
ce1f96de | 1436 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1437 | static CORE_ADDR |
0b1b3e42 | 1438 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1439 | { |
ce1f96de | 1440 | if (is_mips16_addr (pc)) |
0b1b3e42 | 1441 | return mips16_next_pc (frame, pc); |
c5aa993b | 1442 | else |
0b1b3e42 | 1443 | return mips32_next_pc (frame, pc); |
12f02c2a | 1444 | } |
c906108c | 1445 | |
edfae063 AC |
1446 | struct mips_frame_cache |
1447 | { | |
1448 | CORE_ADDR base; | |
1449 | struct trad_frame_saved_reg *saved_regs; | |
1450 | }; | |
1451 | ||
29639122 JB |
1452 | /* Set a register's saved stack address in temp_saved_regs. If an |
1453 | address has already been set for this register, do nothing; this | |
1454 | way we will only recognize the first save of a given register in a | |
1455 | function prologue. | |
eec63939 | 1456 | |
f57d151a UW |
1457 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1458 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1459 | Strictly speaking, only the second range is used as it is only second | |
1460 | range (the ABI instead of ISA registers) that comes into play when finding | |
1461 | saved registers in a frame. */ | |
eec63939 AC |
1462 | |
1463 | static void | |
29639122 JB |
1464 | set_reg_offset (struct mips_frame_cache *this_cache, int regnum, |
1465 | CORE_ADDR offset) | |
eec63939 | 1466 | { |
29639122 JB |
1467 | if (this_cache != NULL |
1468 | && this_cache->saved_regs[regnum].addr == -1) | |
1469 | { | |
f57d151a UW |
1470 | this_cache->saved_regs[regnum |
1471 | + 0 * gdbarch_num_regs (current_gdbarch)].addr | |
1472 | = offset; | |
1473 | this_cache->saved_regs[regnum | |
1474 | + 1 * gdbarch_num_regs (current_gdbarch)].addr | |
1475 | = offset; | |
29639122 | 1476 | } |
eec63939 AC |
1477 | } |
1478 | ||
eec63939 | 1479 | |
29639122 JB |
1480 | /* Fetch the immediate value from a MIPS16 instruction. |
1481 | If the previous instruction was an EXTEND, use it to extend | |
1482 | the upper bits of the immediate value. This is a helper function | |
1483 | for mips16_scan_prologue. */ | |
eec63939 | 1484 | |
29639122 JB |
1485 | static int |
1486 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1487 | unsigned short inst, /* current instruction */ | |
1488 | int nbits, /* number of bits in imm field */ | |
1489 | int scale, /* scale factor to be applied to imm */ | |
1490 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1491 | { |
29639122 | 1492 | int offset; |
eec63939 | 1493 | |
29639122 JB |
1494 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1495 | { | |
1496 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1497 | if (offset & 0x8000) /* check for negative extend */ | |
1498 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1499 | return offset | (inst & 0x1f); | |
1500 | } | |
eec63939 | 1501 | else |
29639122 JB |
1502 | { |
1503 | int max_imm = 1 << nbits; | |
1504 | int mask = max_imm - 1; | |
1505 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1506 | |
29639122 JB |
1507 | offset = inst & mask; |
1508 | if (is_signed && (offset & sign_bit)) | |
1509 | offset = 0 - (max_imm - offset); | |
1510 | return offset * scale; | |
1511 | } | |
1512 | } | |
eec63939 | 1513 | |
65596487 | 1514 | |
29639122 JB |
1515 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1516 | the associated FRAME_CACHE if not null. | |
1517 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1518 | |
29639122 JB |
1519 | static CORE_ADDR |
1520 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
1521 | struct frame_info *next_frame, | |
1522 | struct mips_frame_cache *this_cache) | |
1523 | { | |
1524 | CORE_ADDR cur_pc; | |
1525 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1526 | CORE_ADDR sp; | |
1527 | long frame_offset = 0; /* Size of stack frame. */ | |
1528 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1529 | int frame_reg = MIPS_SP_REGNUM; | |
1530 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1531 | unsigned inst = 0; /* current instruction */ | |
1532 | unsigned entry_inst = 0; /* the entry instruction */ | |
1533 | int reg, offset; | |
a343eb3c | 1534 | |
29639122 JB |
1535 | int extend_bytes = 0; |
1536 | int prev_extend_bytes; | |
1537 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1538 | |
29639122 JB |
1539 | /* Can be called when there's no process, and hence when there's no |
1540 | NEXT_FRAME. */ | |
1541 | if (next_frame != NULL) | |
d2ca4222 UW |
1542 | sp = frame_unwind_register_signed (next_frame, |
1543 | gdbarch_num_regs (current_gdbarch) | |
1544 | + MIPS_SP_REGNUM); | |
29639122 JB |
1545 | else |
1546 | sp = 0; | |
eec63939 | 1547 | |
29639122 JB |
1548 | if (limit_pc > start_pc + 200) |
1549 | limit_pc = start_pc + 200; | |
eec63939 | 1550 | |
95ac2dcf | 1551 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1552 | { |
1553 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1554 | the immediate offset extension from it in mips16_get_imm. */ | |
1555 | prev_inst = inst; | |
eec63939 | 1556 | |
29639122 JB |
1557 | /* Fetch and decode the instruction. */ |
1558 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1559 | |
29639122 JB |
1560 | /* Normally we ignore extend instructions. However, if it is |
1561 | not followed by a valid prologue instruction, then this | |
1562 | instruction is not part of the prologue either. We must | |
1563 | remember in this case to adjust the end_prologue_addr back | |
1564 | over the extend. */ | |
1565 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1566 | { | |
95ac2dcf | 1567 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1568 | continue; |
1569 | } | |
eec63939 | 1570 | |
29639122 JB |
1571 | prev_extend_bytes = extend_bytes; |
1572 | extend_bytes = 0; | |
eec63939 | 1573 | |
29639122 JB |
1574 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1575 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1576 | { | |
1577 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1578 | if (offset < 0) /* negative stack adjustment? */ | |
1579 | frame_offset -= offset; | |
1580 | else | |
1581 | /* Exit loop if a positive stack adjustment is found, which | |
1582 | usually means that the stack cleanup code in the function | |
1583 | epilogue is reached. */ | |
1584 | break; | |
1585 | } | |
1586 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1587 | { | |
1588 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1589 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
1590 | set_reg_offset (this_cache, reg, sp + offset); | |
1591 | } | |
1592 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1593 | { | |
1594 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1595 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1596 | set_reg_offset (this_cache, reg, sp + offset); | |
1597 | } | |
1598 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1599 | { | |
1600 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4c7d22cb | 1601 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1602 | } |
1603 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1604 | { | |
1605 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
4c7d22cb | 1606 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1607 | } |
1608 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1609 | { | |
1610 | frame_addr = sp; | |
1611 | frame_reg = 17; | |
1612 | } | |
1613 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1614 | { | |
1615 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1616 | frame_addr = sp + offset; | |
1617 | frame_reg = 17; | |
1618 | frame_adjust = offset; | |
1619 | } | |
1620 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1621 | { | |
1622 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1623 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1624 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1625 | } | |
1626 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1627 | { | |
1628 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1629 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1630 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1631 | } | |
1632 | else if ((inst & 0xf81f) == 0xe809 | |
1633 | && (inst & 0x700) != 0x700) /* entry */ | |
1634 | entry_inst = inst; /* save for later processing */ | |
1635 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ | |
95ac2dcf | 1636 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1637 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1638 | { | |
1639 | /* This instruction is part of the prologue, but we don't | |
1640 | need to do anything special to handle it. */ | |
1641 | } | |
1642 | else | |
1643 | { | |
1644 | /* This instruction is not an instruction typically found | |
1645 | in a prologue, so we must have reached the end of the | |
1646 | prologue. */ | |
1647 | if (end_prologue_addr == 0) | |
1648 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1649 | } | |
1650 | } | |
eec63939 | 1651 | |
29639122 JB |
1652 | /* The entry instruction is typically the first instruction in a function, |
1653 | and it stores registers at offsets relative to the value of the old SP | |
1654 | (before the prologue). But the value of the sp parameter to this | |
1655 | function is the new SP (after the prologue has been executed). So we | |
1656 | can't calculate those offsets until we've seen the entire prologue, | |
1657 | and can calculate what the old SP must have been. */ | |
1658 | if (entry_inst != 0) | |
1659 | { | |
1660 | int areg_count = (entry_inst >> 8) & 7; | |
1661 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1662 | |
29639122 JB |
1663 | /* The entry instruction always subtracts 32 from the SP. */ |
1664 | frame_offset += 32; | |
1665 | ||
1666 | /* Now we can calculate what the SP must have been at the | |
1667 | start of the function prologue. */ | |
1668 | sp += frame_offset; | |
1669 | ||
1670 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1671 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1672 | { | |
1673 | set_reg_offset (this_cache, reg, sp + offset); | |
1674 | offset += mips_abi_regsize (current_gdbarch); | |
1675 | } | |
1676 | ||
1677 | /* Check if the ra register was pushed on the stack. */ | |
1678 | offset = -4; | |
1679 | if (entry_inst & 0x20) | |
1680 | { | |
4c7d22cb | 1681 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1682 | offset -= mips_abi_regsize (current_gdbarch); |
1683 | } | |
1684 | ||
1685 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1686 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1687 | { | |
1688 | set_reg_offset (this_cache, reg, sp + offset); | |
1689 | offset -= mips_abi_regsize (current_gdbarch); | |
1690 | } | |
1691 | } | |
1692 | ||
1693 | if (this_cache != NULL) | |
1694 | { | |
1695 | this_cache->base = | |
f57d151a UW |
1696 | (frame_unwind_register_signed (next_frame, |
1697 | gdbarch_num_regs (current_gdbarch) | |
1698 | + frame_reg) | |
29639122 JB |
1699 | + frame_offset - frame_adjust); |
1700 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1701 | be able to get rid of the assignment below, evetually. But it's | |
1702 | still needed for now. */ | |
f57d151a UW |
1703 | this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) |
1704 | + mips_regnum (current_gdbarch)->pc] | |
1705 | = this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) | |
1706 | + MIPS_RA_REGNUM]; | |
29639122 JB |
1707 | } |
1708 | ||
1709 | /* If we didn't reach the end of the prologue when scanning the function | |
1710 | instructions, then set end_prologue_addr to the address of the | |
1711 | instruction immediately after the last one we scanned. */ | |
1712 | if (end_prologue_addr == 0) | |
1713 | end_prologue_addr = cur_pc; | |
1714 | ||
1715 | return end_prologue_addr; | |
eec63939 AC |
1716 | } |
1717 | ||
29639122 JB |
1718 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1719 | Procedures that use the 32-bit instruction set are handled by the | |
1720 | mips_insn32 unwinder. */ | |
1721 | ||
1722 | static struct mips_frame_cache * | |
1723 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) | |
eec63939 | 1724 | { |
29639122 | 1725 | struct mips_frame_cache *cache; |
eec63939 AC |
1726 | |
1727 | if ((*this_cache) != NULL) | |
1728 | return (*this_cache); | |
29639122 JB |
1729 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1730 | (*this_cache) = cache; | |
1731 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
eec63939 | 1732 | |
29639122 JB |
1733 | /* Analyze the function prologue. */ |
1734 | { | |
6de5b849 JB |
1735 | const CORE_ADDR pc = |
1736 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 1737 | CORE_ADDR start_addr; |
eec63939 | 1738 | |
29639122 JB |
1739 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1740 | if (start_addr == 0) | |
1741 | start_addr = heuristic_proc_start (pc); | |
1742 | /* We can't analyze the prologue if we couldn't find the begining | |
1743 | of the function. */ | |
1744 | if (start_addr == 0) | |
1745 | return cache; | |
eec63939 | 1746 | |
29639122 JB |
1747 | mips16_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1748 | } | |
1749 | ||
3e8c568d | 1750 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a UW |
1751 | trad_frame_set_value (cache->saved_regs, gdbarch_num_regs (current_gdbarch) |
1752 | + MIPS_SP_REGNUM, cache->base); | |
eec63939 | 1753 | |
29639122 | 1754 | return (*this_cache); |
eec63939 AC |
1755 | } |
1756 | ||
1757 | static void | |
29639122 JB |
1758 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
1759 | struct frame_id *this_id) | |
eec63939 | 1760 | { |
29639122 JB |
1761 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1762 | this_cache); | |
93d42b30 DJ |
1763 | (*this_id) = frame_id_build (info->base, |
1764 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
eec63939 AC |
1765 | } |
1766 | ||
1767 | static void | |
29639122 | 1768 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1769 | void **this_cache, |
1770 | int regnum, int *optimizedp, | |
1771 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 1772 | int *realnump, gdb_byte *valuep) |
eec63939 | 1773 | { |
29639122 JB |
1774 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1775 | this_cache); | |
1776 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1777 | optimizedp, lvalp, addrp, realnump, valuep); | |
eec63939 AC |
1778 | } |
1779 | ||
29639122 | 1780 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1781 | { |
1782 | NORMAL_FRAME, | |
29639122 JB |
1783 | mips_insn16_frame_this_id, |
1784 | mips_insn16_frame_prev_register | |
eec63939 AC |
1785 | }; |
1786 | ||
1787 | static const struct frame_unwind * | |
29639122 | 1788 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 | 1789 | { |
6de5b849 | 1790 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 1791 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
1792 | return &mips_insn16_frame_unwind; |
1793 | return NULL; | |
eec63939 AC |
1794 | } |
1795 | ||
1796 | static CORE_ADDR | |
29639122 JB |
1797 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
1798 | void **this_cache) | |
eec63939 | 1799 | { |
29639122 JB |
1800 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1801 | this_cache); | |
1802 | return info->base; | |
eec63939 AC |
1803 | } |
1804 | ||
29639122 | 1805 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1806 | { |
29639122 JB |
1807 | &mips_insn16_frame_unwind, |
1808 | mips_insn16_frame_base_address, | |
1809 | mips_insn16_frame_base_address, | |
1810 | mips_insn16_frame_base_address | |
eec63939 AC |
1811 | }; |
1812 | ||
1813 | static const struct frame_base * | |
29639122 | 1814 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 1815 | { |
29639122 JB |
1816 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
1817 | return &mips_insn16_frame_base; | |
eec63939 AC |
1818 | else |
1819 | return NULL; | |
edfae063 AC |
1820 | } |
1821 | ||
29639122 JB |
1822 | /* Mark all the registers as unset in the saved_regs array |
1823 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1824 | ||
1825 | void | |
1826 | reset_saved_regs (struct mips_frame_cache *this_cache) | |
c906108c | 1827 | { |
29639122 JB |
1828 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1829 | return; | |
1830 | ||
1831 | { | |
f57d151a | 1832 | const int num_regs = gdbarch_num_regs (current_gdbarch); |
29639122 | 1833 | int i; |
64159455 | 1834 | |
29639122 JB |
1835 | for (i = 0; i < num_regs; i++) |
1836 | { | |
1837 | this_cache->saved_regs[i].addr = -1; | |
1838 | } | |
1839 | } | |
c906108c SS |
1840 | } |
1841 | ||
29639122 JB |
1842 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1843 | the associated FRAME_CACHE if not null. | |
1844 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1845 | |
875e1767 | 1846 | static CORE_ADDR |
29639122 JB |
1847 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1848 | struct frame_info *next_frame, | |
1849 | struct mips_frame_cache *this_cache) | |
c906108c | 1850 | { |
29639122 JB |
1851 | CORE_ADDR cur_pc; |
1852 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1853 | CORE_ADDR sp; | |
1854 | long frame_offset; | |
1855 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1856 | |
29639122 JB |
1857 | CORE_ADDR end_prologue_addr = 0; |
1858 | int seen_sp_adjust = 0; | |
1859 | int load_immediate_bytes = 0; | |
8fa9cfa1 | 1860 | |
29639122 JB |
1861 | /* Can be called when there's no process, and hence when there's no |
1862 | NEXT_FRAME. */ | |
1863 | if (next_frame != NULL) | |
d2ca4222 UW |
1864 | sp = frame_unwind_register_signed (next_frame, |
1865 | gdbarch_num_regs (current_gdbarch) | |
1866 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 1867 | else |
29639122 | 1868 | sp = 0; |
9022177c | 1869 | |
29639122 JB |
1870 | if (limit_pc > start_pc + 200) |
1871 | limit_pc = start_pc + 200; | |
9022177c | 1872 | |
29639122 | 1873 | restart: |
9022177c | 1874 | |
29639122 | 1875 | frame_offset = 0; |
95ac2dcf | 1876 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 1877 | { |
29639122 JB |
1878 | unsigned long inst, high_word, low_word; |
1879 | int reg; | |
9022177c | 1880 | |
29639122 JB |
1881 | /* Fetch the instruction. */ |
1882 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 1883 | |
29639122 JB |
1884 | /* Save some code by pre-extracting some useful fields. */ |
1885 | high_word = (inst >> 16) & 0xffff; | |
1886 | low_word = inst & 0xffff; | |
1887 | reg = high_word & 0x1f; | |
fe29b929 | 1888 | |
29639122 JB |
1889 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1890 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1891 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1892 | { | |
1893 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1894 | frame_offset += 0x10000 - low_word; | |
1895 | else | |
1896 | /* Exit loop if a positive stack adjustment is found, which | |
1897 | usually means that the stack cleanup code in the function | |
1898 | epilogue is reached. */ | |
1899 | break; | |
1900 | seen_sp_adjust = 1; | |
1901 | } | |
1902 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1903 | { | |
1904 | set_reg_offset (this_cache, reg, sp + low_word); | |
1905 | } | |
1906 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1907 | { | |
1908 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
1909 | set_reg_offset (this_cache, reg, sp + low_word); | |
1910 | } | |
1911 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1912 | { | |
1913 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1914 | if ((long) low_word != frame_offset) | |
1915 | frame_addr = sp + low_word; | |
d2ca4222 | 1916 | else if (next_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1917 | { |
1918 | unsigned alloca_adjust; | |
a4b8ebc8 | 1919 | |
29639122 | 1920 | frame_reg = 30; |
d2ca4222 UW |
1921 | frame_addr = frame_unwind_register_signed |
1922 | (next_frame, | |
1923 | gdbarch_num_regs (current_gdbarch) + 30); | |
1924 | ||
29639122 JB |
1925 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
1926 | if (alloca_adjust > 0) | |
1927 | { | |
1928 | /* FP > SP + frame_size. This may be because of | |
1929 | an alloca or somethings similar. Fix sp to | |
1930 | "pre-alloca" value, and try again. */ | |
1931 | sp += alloca_adjust; | |
1932 | /* Need to reset the status of all registers. Otherwise, | |
1933 | we will hit a guard that prevents the new address | |
1934 | for each register to be recomputed during the second | |
1935 | pass. */ | |
1936 | reset_saved_regs (this_cache); | |
1937 | goto restart; | |
1938 | } | |
1939 | } | |
1940 | } | |
1941 | /* move $30,$sp. With different versions of gas this will be either | |
1942 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1943 | Accept any one of these. */ | |
1944 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
1945 | { | |
1946 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
d2ca4222 | 1947 | if (next_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1948 | { |
1949 | unsigned alloca_adjust; | |
c906108c | 1950 | |
29639122 | 1951 | frame_reg = 30; |
d2ca4222 UW |
1952 | frame_addr = frame_unwind_register_signed |
1953 | (next_frame, | |
1954 | gdbarch_num_regs (current_gdbarch) + 30); | |
1955 | ||
29639122 JB |
1956 | alloca_adjust = (unsigned) (frame_addr - sp); |
1957 | if (alloca_adjust > 0) | |
1958 | { | |
1959 | /* FP > SP + frame_size. This may be because of | |
1960 | an alloca or somethings similar. Fix sp to | |
1961 | "pre-alloca" value, and try again. */ | |
1962 | sp = frame_addr; | |
1963 | /* Need to reset the status of all registers. Otherwise, | |
1964 | we will hit a guard that prevents the new address | |
1965 | for each register to be recomputed during the second | |
1966 | pass. */ | |
1967 | reset_saved_regs (this_cache); | |
1968 | goto restart; | |
1969 | } | |
1970 | } | |
1971 | } | |
1972 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ | |
1973 | { | |
1974 | set_reg_offset (this_cache, reg, frame_addr + low_word); | |
1975 | } | |
1976 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
1977 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
1978 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
1979 | || high_word == 0x3c1c /* lui $gp,n */ | |
1980 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
1981 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1982 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
1983 | ) | |
1984 | { | |
1985 | /* These instructions are part of the prologue, but we don't | |
1986 | need to do anything special to handle them. */ | |
1987 | } | |
1988 | /* The instructions below load $at or $t0 with an immediate | |
1989 | value in preparation for a stack adjustment via | |
1990 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
1991 | initialize a local variable, so we accept them only before | |
1992 | a stack adjustment instruction was seen. */ | |
1993 | else if (!seen_sp_adjust | |
1994 | && (high_word == 0x3c01 /* lui $at,n */ | |
1995 | || high_word == 0x3c08 /* lui $t0,n */ | |
1996 | || high_word == 0x3421 /* ori $at,$at,n */ | |
1997 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
1998 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
1999 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2000 | )) | |
2001 | { | |
95ac2dcf | 2002 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2003 | } |
2004 | else | |
2005 | { | |
2006 | /* This instruction is not an instruction typically found | |
2007 | in a prologue, so we must have reached the end of the | |
2008 | prologue. */ | |
2009 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2010 | loop now? Why would we need to continue scanning the function | |
2011 | instructions? */ | |
2012 | if (end_prologue_addr == 0) | |
2013 | end_prologue_addr = cur_pc; | |
2014 | } | |
a4b8ebc8 | 2015 | } |
c906108c | 2016 | |
29639122 JB |
2017 | if (this_cache != NULL) |
2018 | { | |
2019 | this_cache->base = | |
f57d151a UW |
2020 | (frame_unwind_register_signed (next_frame, |
2021 | gdbarch_num_regs (current_gdbarch) | |
2022 | + frame_reg) | |
29639122 JB |
2023 | + frame_offset); |
2024 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2025 | this assignment below, eventually. But it's still needed | |
2026 | for now. */ | |
f57d151a UW |
2027 | this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) |
2028 | + mips_regnum (current_gdbarch)->pc] | |
2029 | = this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) | |
2030 | + MIPS_RA_REGNUM]; | |
29639122 | 2031 | } |
c906108c | 2032 | |
29639122 JB |
2033 | /* If we didn't reach the end of the prologue when scanning the function |
2034 | instructions, then set end_prologue_addr to the address of the | |
2035 | instruction immediately after the last one we scanned. */ | |
2036 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2037 | we may as well be careful and do our best if we have a null | |
2038 | end_prologue_addr. */ | |
2039 | if (end_prologue_addr == 0) | |
2040 | end_prologue_addr = cur_pc; | |
2041 | ||
2042 | /* In a frameless function, we might have incorrectly | |
2043 | skipped some load immediate instructions. Undo the skipping | |
2044 | if the load immediate was not followed by a stack adjustment. */ | |
2045 | if (load_immediate_bytes && !seen_sp_adjust) | |
2046 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2047 | |
29639122 | 2048 | return end_prologue_addr; |
c906108c SS |
2049 | } |
2050 | ||
29639122 JB |
2051 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2052 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2053 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2054 | unwinder. */ | |
c906108c | 2055 | |
29639122 JB |
2056 | static struct mips_frame_cache * |
2057 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 2058 | { |
29639122 | 2059 | struct mips_frame_cache *cache; |
c906108c | 2060 | |
29639122 JB |
2061 | if ((*this_cache) != NULL) |
2062 | return (*this_cache); | |
c5aa993b | 2063 | |
29639122 JB |
2064 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2065 | (*this_cache) = cache; | |
2066 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c5aa993b | 2067 | |
29639122 JB |
2068 | /* Analyze the function prologue. */ |
2069 | { | |
6de5b849 JB |
2070 | const CORE_ADDR pc = |
2071 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 2072 | CORE_ADDR start_addr; |
c906108c | 2073 | |
29639122 JB |
2074 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2075 | if (start_addr == 0) | |
2076 | start_addr = heuristic_proc_start (pc); | |
2077 | /* We can't analyze the prologue if we couldn't find the begining | |
2078 | of the function. */ | |
2079 | if (start_addr == 0) | |
2080 | return cache; | |
c5aa993b | 2081 | |
29639122 JB |
2082 | mips32_scan_prologue (start_addr, pc, next_frame, *this_cache); |
2083 | } | |
2084 | ||
3e8c568d | 2085 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a UW |
2086 | trad_frame_set_value (cache->saved_regs, |
2087 | gdbarch_num_regs (current_gdbarch) + MIPS_SP_REGNUM, | |
2088 | cache->base); | |
c5aa993b | 2089 | |
29639122 | 2090 | return (*this_cache); |
c906108c SS |
2091 | } |
2092 | ||
29639122 JB |
2093 | static void |
2094 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2095 | struct frame_id *this_id) | |
c906108c | 2096 | { |
29639122 JB |
2097 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2098 | this_cache); | |
93d42b30 DJ |
2099 | (*this_id) = frame_id_build (info->base, |
2100 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
29639122 | 2101 | } |
c906108c | 2102 | |
29639122 JB |
2103 | static void |
2104 | mips_insn32_frame_prev_register (struct frame_info *next_frame, | |
2105 | void **this_cache, | |
2106 | int regnum, int *optimizedp, | |
2107 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2108 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2109 | { |
2110 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, | |
2111 | this_cache); | |
2112 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2113 | optimizedp, lvalp, addrp, realnump, valuep); | |
c906108c SS |
2114 | } |
2115 | ||
29639122 JB |
2116 | static const struct frame_unwind mips_insn32_frame_unwind = |
2117 | { | |
2118 | NORMAL_FRAME, | |
2119 | mips_insn32_frame_this_id, | |
2120 | mips_insn32_frame_prev_register | |
2121 | }; | |
c906108c | 2122 | |
29639122 JB |
2123 | static const struct frame_unwind * |
2124 | mips_insn32_frame_sniffer (struct frame_info *next_frame) | |
2125 | { | |
6de5b849 | 2126 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 2127 | if (! mips_pc_is_mips16 (pc)) |
29639122 JB |
2128 | return &mips_insn32_frame_unwind; |
2129 | return NULL; | |
2130 | } | |
c906108c | 2131 | |
1c645fec | 2132 | static CORE_ADDR |
29639122 JB |
2133 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
2134 | void **this_cache) | |
c906108c | 2135 | { |
29639122 JB |
2136 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2137 | this_cache); | |
2138 | return info->base; | |
2139 | } | |
c906108c | 2140 | |
29639122 JB |
2141 | static const struct frame_base mips_insn32_frame_base = |
2142 | { | |
2143 | &mips_insn32_frame_unwind, | |
2144 | mips_insn32_frame_base_address, | |
2145 | mips_insn32_frame_base_address, | |
2146 | mips_insn32_frame_base_address | |
2147 | }; | |
1c645fec | 2148 | |
29639122 JB |
2149 | static const struct frame_base * |
2150 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) | |
2151 | { | |
2152 | if (mips_insn32_frame_sniffer (next_frame) != NULL) | |
2153 | return &mips_insn32_frame_base; | |
a65bbe44 | 2154 | else |
29639122 JB |
2155 | return NULL; |
2156 | } | |
a65bbe44 | 2157 | |
29639122 JB |
2158 | static struct trad_frame_cache * |
2159 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2160 | { | |
2161 | CORE_ADDR pc; | |
2162 | CORE_ADDR start_addr; | |
2163 | CORE_ADDR stack_addr; | |
2164 | struct trad_frame_cache *this_trad_cache; | |
c906108c | 2165 | |
29639122 JB |
2166 | if ((*this_cache) != NULL) |
2167 | return (*this_cache); | |
2168 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2169 | (*this_cache) = this_trad_cache; | |
1c645fec | 2170 | |
29639122 | 2171 | /* The return address is in the link register. */ |
3e8c568d UW |
2172 | trad_frame_set_reg_realreg (this_trad_cache, |
2173 | gdbarch_pc_regnum (current_gdbarch), | |
2174 | MIPS_RA_REGNUM); | |
1c645fec | 2175 | |
29639122 JB |
2176 | /* Frame ID, since it's a frameless / stackless function, no stack |
2177 | space is allocated and SP on entry is the current SP. */ | |
2178 | pc = frame_pc_unwind (next_frame); | |
2179 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
4c7d22cb | 2180 | stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM); |
29639122 | 2181 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); |
1c645fec | 2182 | |
29639122 JB |
2183 | /* Assume that the frame's base is the same as the |
2184 | stack-pointer. */ | |
2185 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2186 | |
29639122 JB |
2187 | return this_trad_cache; |
2188 | } | |
c906108c | 2189 | |
29639122 JB |
2190 | static void |
2191 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2192 | struct frame_id *this_id) | |
2193 | { | |
2194 | struct trad_frame_cache *this_trad_cache | |
2195 | = mips_stub_frame_cache (next_frame, this_cache); | |
2196 | trad_frame_get_id (this_trad_cache, this_id); | |
2197 | } | |
c906108c | 2198 | |
29639122 JB |
2199 | static void |
2200 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2201 | void **this_cache, | |
2202 | int regnum, int *optimizedp, | |
2203 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2204 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2205 | { |
2206 | struct trad_frame_cache *this_trad_cache | |
2207 | = mips_stub_frame_cache (next_frame, this_cache); | |
2208 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2209 | lvalp, addrp, realnump, valuep); | |
2210 | } | |
c906108c | 2211 | |
29639122 JB |
2212 | static const struct frame_unwind mips_stub_frame_unwind = |
2213 | { | |
2214 | NORMAL_FRAME, | |
2215 | mips_stub_frame_this_id, | |
2216 | mips_stub_frame_prev_register | |
2217 | }; | |
c906108c | 2218 | |
29639122 JB |
2219 | static const struct frame_unwind * |
2220 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2221 | { | |
979b38e0 | 2222 | struct obj_section *s; |
93d42b30 | 2223 | CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME); |
979b38e0 | 2224 | |
29639122 JB |
2225 | if (in_plt_section (pc, NULL)) |
2226 | return &mips_stub_frame_unwind; | |
979b38e0 DJ |
2227 | |
2228 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2229 | s = find_pc_section (pc); | |
2230 | ||
2231 | if (s != NULL | |
2232 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2233 | ".MIPS.stubs") == 0) | |
2234 | return &mips_stub_frame_unwind; | |
2235 | ||
2236 | return NULL; | |
29639122 | 2237 | } |
c906108c | 2238 | |
29639122 JB |
2239 | static CORE_ADDR |
2240 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2241 | void **this_cache) | |
2242 | { | |
2243 | struct trad_frame_cache *this_trad_cache | |
2244 | = mips_stub_frame_cache (next_frame, this_cache); | |
2245 | return trad_frame_get_this_base (this_trad_cache); | |
2246 | } | |
0fce0821 | 2247 | |
29639122 JB |
2248 | static const struct frame_base mips_stub_frame_base = |
2249 | { | |
2250 | &mips_stub_frame_unwind, | |
2251 | mips_stub_frame_base_address, | |
2252 | mips_stub_frame_base_address, | |
2253 | mips_stub_frame_base_address | |
2254 | }; | |
2255 | ||
2256 | static const struct frame_base * | |
2257 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2258 | { | |
2259 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2260 | return &mips_stub_frame_base; | |
2261 | else | |
2262 | return NULL; | |
2263 | } | |
2264 | ||
29639122 | 2265 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2266 | |
29639122 JB |
2267 | static CORE_ADDR |
2268 | mips_addr_bits_remove (CORE_ADDR addr) | |
65596487 | 2269 | { |
29639122 JB |
2270 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2271 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
2272 | /* This hack is a work-around for existing boards using PMON, the | |
2273 | simulator, and any other 64-bit targets that doesn't have true | |
2274 | 64-bit addressing. On these targets, the upper 32 bits of | |
2275 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2276 | likely to have been sign extended to all 1s by instruction | |
2277 | sequences that load 32-bit addresses. For example, a typical | |
2278 | piece of code that loads an address is this: | |
65596487 | 2279 | |
29639122 JB |
2280 | lui $r2, <upper 16 bits> |
2281 | ori $r2, <lower 16 bits> | |
65596487 | 2282 | |
29639122 JB |
2283 | But the lui sign-extends the value such that the upper 32 bits |
2284 | may be all 1s. The workaround is simply to mask off these | |
2285 | bits. In the future, gcc may be changed to support true 64-bit | |
2286 | addressing, and this masking will have to be disabled. */ | |
2287 | return addr &= 0xffffffffUL; | |
2288 | else | |
2289 | return addr; | |
65596487 JB |
2290 | } |
2291 | ||
29639122 JB |
2292 | /* mips_software_single_step() is called just before we want to resume |
2293 | the inferior, if we want to single-step it but there is no hardware | |
2294 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2295 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2296 | |
e6590a1b | 2297 | int |
0b1b3e42 | 2298 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2299 | { |
8181d85f | 2300 | CORE_ADDR pc, next_pc; |
65596487 | 2301 | |
0b1b3e42 UW |
2302 | pc = get_frame_pc (frame); |
2303 | next_pc = mips_next_pc (frame, pc); | |
e6590a1b | 2304 | |
e0cd558a | 2305 | insert_single_step_breakpoint (next_pc); |
e6590a1b | 2306 | return 1; |
29639122 | 2307 | } |
a65bbe44 | 2308 | |
29639122 JB |
2309 | /* Test whether the PC points to the return instruction at the |
2310 | end of a function. */ | |
65596487 | 2311 | |
29639122 JB |
2312 | static int |
2313 | mips_about_to_return (CORE_ADDR pc) | |
2314 | { | |
0fe7e7c8 | 2315 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2316 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2317 | generates a "jr $ra"; other times it generates code to load | |
2318 | the return address from the stack to an accessible register (such | |
2319 | as $a3), then a "jr" using that register. This second case | |
2320 | is almost impossible to distinguish from an indirect jump | |
2321 | used for switch statements, so we don't even try. */ | |
2322 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2323 | else | |
2324 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2325 | } | |
c906108c | 2326 | |
c906108c | 2327 | |
29639122 JB |
2328 | /* This fencepost looks highly suspicious to me. Removing it also |
2329 | seems suspicious as it could affect remote debugging across serial | |
2330 | lines. */ | |
c906108c | 2331 | |
29639122 JB |
2332 | static CORE_ADDR |
2333 | heuristic_proc_start (CORE_ADDR pc) | |
2334 | { | |
2335 | CORE_ADDR start_pc; | |
2336 | CORE_ADDR fence; | |
2337 | int instlen; | |
2338 | int seen_adjsp = 0; | |
65596487 | 2339 | |
bf6ae464 | 2340 | pc = gdbarch_addr_bits_remove (current_gdbarch, pc); |
29639122 JB |
2341 | start_pc = pc; |
2342 | fence = start_pc - heuristic_fence_post; | |
2343 | if (start_pc == 0) | |
2344 | return 0; | |
65596487 | 2345 | |
29639122 JB |
2346 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2347 | fence = VM_MIN_ADDRESS; | |
65596487 | 2348 | |
95ac2dcf | 2349 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2350 | |
29639122 JB |
2351 | /* search back for previous return */ |
2352 | for (start_pc -= instlen;; start_pc -= instlen) | |
2353 | if (start_pc < fence) | |
2354 | { | |
2355 | /* It's not clear to me why we reach this point when | |
2356 | stop_soon, but with this test, at least we | |
2357 | don't print out warnings for every child forked (eg, on | |
2358 | decstation). 22apr93 rich@cygnus.com. */ | |
2359 | if (stop_soon == NO_STOP_QUIETLY) | |
2360 | { | |
2361 | static int blurb_printed = 0; | |
98b4dd94 | 2362 | |
8a3fe4f8 | 2363 | warning (_("GDB can't find the start of the function at 0x%s."), |
29639122 JB |
2364 | paddr_nz (pc)); |
2365 | ||
2366 | if (!blurb_printed) | |
2367 | { | |
2368 | /* This actually happens frequently in embedded | |
2369 | development, when you first connect to a board | |
2370 | and your stack pointer and pc are nowhere in | |
2371 | particular. This message needs to give people | |
2372 | in that situation enough information to | |
2373 | determine that it's no big deal. */ | |
2374 | printf_filtered ("\n\ | |
2375 | GDB is unable to find the start of the function at 0x%s\n\ | |
2376 | and thus can't determine the size of that function's stack frame.\n\ | |
2377 | This means that GDB may be unable to access that stack frame, or\n\ | |
2378 | the frames below it.\n\ | |
2379 | This problem is most likely caused by an invalid program counter or\n\ | |
2380 | stack pointer.\n\ | |
2381 | However, if you think GDB should simply search farther back\n\ | |
2382 | from 0x%s for code which looks like the beginning of a\n\ | |
2383 | function, you can increase the range of the search using the `set\n\ | |
2384 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); | |
2385 | blurb_printed = 1; | |
2386 | } | |
2387 | } | |
2388 | ||
2389 | return 0; | |
2390 | } | |
0fe7e7c8 | 2391 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2392 | { |
2393 | unsigned short inst; | |
2394 | ||
2395 | /* On MIPS16, any one of the following is likely to be the | |
2396 | start of a function: | |
193774b3 MR |
2397 | extend save |
2398 | save | |
29639122 JB |
2399 | entry |
2400 | addiu sp,-n | |
2401 | daddiu sp,-n | |
2402 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2403 | inst = mips_fetch_instruction (start_pc); | |
193774b3 MR |
2404 | if ((inst & 0xff80) == 0x6480) /* save */ |
2405 | { | |
2406 | if (start_pc - instlen >= fence) | |
2407 | { | |
2408 | inst = mips_fetch_instruction (start_pc - instlen); | |
2409 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2410 | start_pc -= instlen; | |
2411 | } | |
2412 | break; | |
2413 | } | |
2414 | else if (((inst & 0xf81f) == 0xe809 | |
2415 | && (inst & 0x700) != 0x700) /* entry */ | |
2416 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2417 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2418 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2419 | break; |
2420 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2421 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2422 | seen_adjsp = 1; | |
2423 | else | |
2424 | seen_adjsp = 0; | |
2425 | } | |
2426 | else if (mips_about_to_return (start_pc)) | |
2427 | { | |
4c7d22cb | 2428 | /* Skip return and its delay slot. */ |
95ac2dcf | 2429 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2430 | break; |
2431 | } | |
2432 | ||
2433 | return start_pc; | |
c906108c SS |
2434 | } |
2435 | ||
6c0d6680 DJ |
2436 | struct mips_objfile_private |
2437 | { | |
2438 | bfd_size_type size; | |
2439 | char *contents; | |
2440 | }; | |
2441 | ||
f09ded24 AC |
2442 | /* According to the current ABI, should the type be passed in a |
2443 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2444 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2445 | FP registers and, consequently this returns false - forces FP |
2446 | arguments into integer registers. */ | |
2447 | ||
2448 | static int | |
2449 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2450 | { | |
2451 | return ((typecode == TYPE_CODE_FLT | |
2452 | || (MIPS_EABI | |
6d82d43b AC |
2453 | && (typecode == TYPE_CODE_STRUCT |
2454 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2455 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2456 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2457 | == TYPE_CODE_FLT)) | |
c86b5b38 | 2458 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2459 | } |
2460 | ||
49e790b0 DJ |
2461 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2462 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2463 | ||
2464 | static int | |
2465 | mips_type_needs_double_align (struct type *type) | |
2466 | { | |
2467 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2468 | |
49e790b0 DJ |
2469 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2470 | return 1; | |
2471 | else if (typecode == TYPE_CODE_STRUCT) | |
2472 | { | |
2473 | if (TYPE_NFIELDS (type) < 1) | |
2474 | return 0; | |
2475 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2476 | } | |
2477 | else if (typecode == TYPE_CODE_UNION) | |
2478 | { | |
361d1df0 | 2479 | int i, n; |
49e790b0 DJ |
2480 | |
2481 | n = TYPE_NFIELDS (type); | |
2482 | for (i = 0; i < n; i++) | |
2483 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2484 | return 1; | |
2485 | return 0; | |
2486 | } | |
2487 | return 0; | |
2488 | } | |
2489 | ||
dc604539 AC |
2490 | /* Adjust the address downward (direction of stack growth) so that it |
2491 | is correctly aligned for a new stack frame. */ | |
2492 | static CORE_ADDR | |
2493 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2494 | { | |
5b03f266 | 2495 | return align_down (addr, 16); |
dc604539 AC |
2496 | } |
2497 | ||
f7ab6ec6 | 2498 | static CORE_ADDR |
7d9b040b | 2499 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2500 | struct regcache *regcache, CORE_ADDR bp_addr, |
2501 | int nargs, struct value **args, CORE_ADDR sp, | |
2502 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2503 | { |
2504 | int argreg; | |
2505 | int float_argreg; | |
2506 | int argnum; | |
2507 | int len = 0; | |
2508 | int stack_offset = 0; | |
480d3dd2 | 2509 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2510 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2511 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2512 | |
25ab4790 AC |
2513 | /* For shared libraries, "t9" needs to point at the function |
2514 | address. */ | |
4c7d22cb | 2515 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2516 | |
2517 | /* Set the return address register to point to the entry point of | |
2518 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2519 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2520 | |
c906108c | 2521 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2522 | are properly aligned. The stack has to be at least 64-bit |
2523 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2524 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2525 | aligned, so we round to this widest known alignment. */ | |
2526 | ||
5b03f266 AC |
2527 | sp = align_down (sp, 16); |
2528 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2529 | |
46e0f506 | 2530 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2531 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2532 | passed in registers, but that's OK. */ |
c906108c | 2533 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2534 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2535 | sp -= align_up (len, 16); |
c906108c | 2536 | |
9ace0497 | 2537 | if (mips_debug) |
6d82d43b | 2538 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2539 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2540 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2541 | |
c906108c | 2542 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2543 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2544 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2545 | |
46e0f506 | 2546 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2547 | if (struct_return) |
9ace0497 AC |
2548 | { |
2549 | if (mips_debug) | |
2550 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2551 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2552 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 2553 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2554 | } |
c906108c SS |
2555 | |
2556 | /* Now load as many as possible of the first arguments into | |
2557 | registers, and push the rest onto the stack. Loop thru args | |
2558 | from first to last. */ | |
2559 | for (argnum = 0; argnum < nargs; argnum++) | |
2560 | { | |
47a35522 MK |
2561 | const gdb_byte *val; |
2562 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2563 | struct value *arg = args[argnum]; |
4991999e | 2564 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2565 | int len = TYPE_LENGTH (arg_type); |
2566 | enum type_code typecode = TYPE_CODE (arg_type); | |
2567 | ||
9ace0497 AC |
2568 | if (mips_debug) |
2569 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2570 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2571 | argnum + 1, len, (int) typecode); |
9ace0497 | 2572 | |
c906108c | 2573 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2574 | reference. */ |
1a69e1e4 | 2575 | if (len > regsize |
9ace0497 | 2576 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2577 | { |
1a69e1e4 | 2578 | store_unsigned_integer (valbuf, regsize, VALUE_ADDRESS (arg)); |
c906108c | 2579 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2580 | len = regsize; |
c906108c | 2581 | val = valbuf; |
9ace0497 AC |
2582 | if (mips_debug) |
2583 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2584 | } |
2585 | else | |
47a35522 | 2586 | val = value_contents (arg); |
c906108c SS |
2587 | |
2588 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2589 | even-numbered floating point register. Round the FP register |
2590 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2591 | left. Non MIPS_EABI targets also pass the FP in the integer |
2592 | registers so also round up normal registers. */ | |
1a69e1e4 | 2593 | if (regsize < 8 && fp_register_arg_p (typecode, arg_type)) |
acdb74a0 AC |
2594 | { |
2595 | if ((float_argreg & 1)) | |
2596 | float_argreg++; | |
2597 | } | |
c906108c SS |
2598 | |
2599 | /* Floating point arguments passed in registers have to be | |
2600 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2601 | are passed in register pairs; the even register gets |
2602 | the low word, and the odd register gets the high word. | |
2603 | On non-EABI processors, the first two floating point arguments are | |
2604 | also copied to general registers, because MIPS16 functions | |
2605 | don't use float registers for arguments. This duplication of | |
2606 | arguments in general registers can't hurt non-MIPS16 functions | |
2607 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2608 | /* MIPS_EABI squeezes a struct that contains a single floating |
2609 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2610 | stack. */ |
f09ded24 AC |
2611 | if (fp_register_arg_p (typecode, arg_type) |
2612 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 2613 | { |
6da397e0 KB |
2614 | /* EABI32 will pass doubles in consecutive registers, even on |
2615 | 64-bit cores. At one time, we used to check the size of | |
2616 | `float_argreg' to determine whether or not to pass doubles | |
2617 | in consecutive registers, but this is not sufficient for | |
2618 | making the ABI determination. */ | |
2619 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2620 | { |
4c6b5505 UW |
2621 | int low_offset = gdbarch_byte_order (current_gdbarch) |
2622 | == BFD_ENDIAN_BIG ? 4 : 0; | |
c906108c SS |
2623 | unsigned long regval; |
2624 | ||
2625 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2626 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2627 | if (mips_debug) |
acdb74a0 | 2628 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2629 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2630 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2631 | |
2632 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2633 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2634 | if (mips_debug) |
acdb74a0 | 2635 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2636 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2637 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2638 | } |
2639 | else | |
2640 | { | |
2641 | /* This is a floating point value that fits entirely | |
2642 | in a single register. */ | |
53a5351d | 2643 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2644 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2645 | LONGEST regval = extract_unsigned_integer (val, len); |
2646 | if (mips_debug) | |
acdb74a0 | 2647 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2648 | float_argreg, phex (regval, len)); |
9c9acae0 | 2649 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2650 | } |
2651 | } | |
2652 | else | |
2653 | { | |
2654 | /* Copy the argument to general registers or the stack in | |
2655 | register-sized pieces. Large arguments are split between | |
2656 | registers and stack. */ | |
1a69e1e4 DJ |
2657 | /* Note: structs whose size is not a multiple of regsize |
2658 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
2659 | them in registers where gcc sometimes puts them on the |
2660 | stack. For maximum compatibility, we will put them in | |
2661 | both places. */ | |
1a69e1e4 | 2662 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 2663 | |
f09ded24 | 2664 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2665 | register are only written to memory. */ |
c906108c SS |
2666 | while (len > 0) |
2667 | { | |
ebafbe83 | 2668 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2669 | int stack_used_p = 0; |
1a69e1e4 | 2670 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 2671 | |
acdb74a0 AC |
2672 | if (mips_debug) |
2673 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2674 | partial_len); | |
2675 | ||
566f0f7a | 2676 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2677 | if (argreg > MIPS_LAST_ARG_REGNUM |
2678 | || odd_sized_struct | |
2679 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2680 | { |
c906108c SS |
2681 | /* Should shorter than int integer values be |
2682 | promoted to int before being stored? */ | |
c906108c | 2683 | int longword_offset = 0; |
9ace0497 | 2684 | CORE_ADDR addr; |
566f0f7a | 2685 | stack_used_p = 1; |
4c6b5505 | 2686 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 2687 | { |
1a69e1e4 | 2688 | if (regsize == 8 |
480d3dd2 AC |
2689 | && (typecode == TYPE_CODE_INT |
2690 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2691 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 2692 | longword_offset = regsize - len; |
480d3dd2 AC |
2693 | else if ((typecode == TYPE_CODE_STRUCT |
2694 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
2695 | && TYPE_LENGTH (arg_type) < regsize) |
2696 | longword_offset = regsize - len; | |
7a292a7a | 2697 | } |
c5aa993b | 2698 | |
9ace0497 AC |
2699 | if (mips_debug) |
2700 | { | |
cb3d25d1 MS |
2701 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2702 | paddr_nz (stack_offset)); | |
2703 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2704 | paddr_nz (longword_offset)); | |
9ace0497 | 2705 | } |
361d1df0 | 2706 | |
9ace0497 AC |
2707 | addr = sp + stack_offset + longword_offset; |
2708 | ||
2709 | if (mips_debug) | |
2710 | { | |
2711 | int i; | |
6d82d43b | 2712 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 2713 | paddr_nz (addr)); |
9ace0497 AC |
2714 | for (i = 0; i < partial_len; i++) |
2715 | { | |
6d82d43b | 2716 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2717 | val[i] & 0xff); |
9ace0497 AC |
2718 | } |
2719 | } | |
2720 | write_memory (addr, val, partial_len); | |
c906108c SS |
2721 | } |
2722 | ||
f09ded24 AC |
2723 | /* Note!!! This is NOT an else clause. Odd sized |
2724 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2725 | arguments will not. */ |
566f0f7a | 2726 | /* Write this portion of the argument to a general |
6d82d43b | 2727 | purpose register. */ |
f09ded24 AC |
2728 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2729 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2730 | { |
6d82d43b AC |
2731 | LONGEST regval = |
2732 | extract_unsigned_integer (val, partial_len); | |
c906108c | 2733 | |
9ace0497 | 2734 | if (mips_debug) |
acdb74a0 | 2735 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2736 | argreg, |
1a69e1e4 | 2737 | phex (regval, regsize)); |
9c9acae0 | 2738 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
c906108c | 2739 | argreg++; |
c906108c | 2740 | } |
c5aa993b | 2741 | |
c906108c SS |
2742 | len -= partial_len; |
2743 | val += partial_len; | |
2744 | ||
566f0f7a | 2745 | /* Compute the the offset into the stack at which we |
6d82d43b | 2746 | will copy the next parameter. |
566f0f7a | 2747 | |
566f0f7a | 2748 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2749 | only needs to be adjusted when it has been used. */ |
c906108c | 2750 | |
46e0f506 | 2751 | if (stack_used_p) |
1a69e1e4 | 2752 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
2753 | } |
2754 | } | |
9ace0497 AC |
2755 | if (mips_debug) |
2756 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2757 | } |
2758 | ||
f10683bb | 2759 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2760 | |
0f71a2f6 JM |
2761 | /* Return adjusted stack pointer. */ |
2762 | return sp; | |
2763 | } | |
2764 | ||
a1f5b845 | 2765 | /* Determine the return value convention being used. */ |
6d82d43b | 2766 | |
9c8fdbfa AC |
2767 | static enum return_value_convention |
2768 | mips_eabi_return_value (struct gdbarch *gdbarch, | |
2769 | struct type *type, struct regcache *regcache, | |
47a35522 | 2770 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 2771 | { |
9c8fdbfa AC |
2772 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2773 | return RETURN_VALUE_STRUCT_CONVENTION; | |
2774 | if (readbuf) | |
2775 | memset (readbuf, 0, TYPE_LENGTH (type)); | |
2776 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6d82d43b AC |
2777 | } |
2778 | ||
6d82d43b AC |
2779 | |
2780 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 2781 | |
8d26208a DJ |
2782 | /* Search for a naturally aligned double at OFFSET inside a struct |
2783 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
2784 | registers. */ | |
2785 | ||
2786 | static int | |
2787 | mips_n32n64_fp_arg_chunk_p (struct type *arg_type, int offset) | |
2788 | { | |
2789 | int i; | |
2790 | ||
2791 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
2792 | return 0; | |
2793 | ||
2794 | if (MIPS_FPU_TYPE != MIPS_FPU_DOUBLE) | |
2795 | return 0; | |
2796 | ||
2797 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
2798 | return 0; | |
2799 | ||
2800 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
2801 | { | |
2802 | int pos; | |
2803 | struct type *field_type; | |
2804 | ||
2805 | /* We're only looking at normal fields. */ | |
2806 | if (TYPE_FIELD_STATIC (arg_type, i) | |
2807 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) | |
2808 | continue; | |
2809 | ||
2810 | /* If we have gone past the offset, there is no double to pass. */ | |
2811 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
2812 | if (pos > offset) | |
2813 | return 0; | |
2814 | ||
2815 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
2816 | ||
2817 | /* If this field is entirely before the requested offset, go | |
2818 | on to the next one. */ | |
2819 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
2820 | continue; | |
2821 | ||
2822 | /* If this is our special aligned double, we can stop. */ | |
2823 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
2824 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
2825 | return 1; | |
2826 | ||
2827 | /* This field starts at or before the requested offset, and | |
2828 | overlaps it. If it is a structure, recurse inwards. */ | |
2829 | return mips_n32n64_fp_arg_chunk_p (field_type, offset - pos); | |
2830 | } | |
2831 | ||
2832 | return 0; | |
2833 | } | |
2834 | ||
f7ab6ec6 | 2835 | static CORE_ADDR |
7d9b040b | 2836 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2837 | struct regcache *regcache, CORE_ADDR bp_addr, |
2838 | int nargs, struct value **args, CORE_ADDR sp, | |
2839 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2840 | { |
2841 | int argreg; | |
2842 | int float_argreg; | |
2843 | int argnum; | |
2844 | int len = 0; | |
2845 | int stack_offset = 0; | |
480d3dd2 | 2846 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2847 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 2848 | |
25ab4790 AC |
2849 | /* For shared libraries, "t9" needs to point at the function |
2850 | address. */ | |
4c7d22cb | 2851 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2852 | |
2853 | /* Set the return address register to point to the entry point of | |
2854 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2855 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2856 | |
cb3d25d1 MS |
2857 | /* First ensure that the stack and structure return address (if any) |
2858 | are properly aligned. The stack has to be at least 64-bit | |
2859 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2860 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2861 | aligned, so we round to this widest known alignment. */ | |
2862 | ||
5b03f266 AC |
2863 | sp = align_down (sp, 16); |
2864 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
2865 | |
2866 | /* Now make space on the stack for the args. */ | |
2867 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 2868 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 2869 | sp -= align_up (len, 16); |
cb3d25d1 MS |
2870 | |
2871 | if (mips_debug) | |
6d82d43b | 2872 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2873 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
2874 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
2875 | |
2876 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 2877 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2878 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 2879 | |
46e0f506 | 2880 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
2881 | if (struct_return) |
2882 | { | |
2883 | if (mips_debug) | |
2884 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2885 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2886 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 2887 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
2888 | } |
2889 | ||
2890 | /* Now load as many as possible of the first arguments into | |
2891 | registers, and push the rest onto the stack. Loop thru args | |
2892 | from first to last. */ | |
2893 | for (argnum = 0; argnum < nargs; argnum++) | |
2894 | { | |
47a35522 | 2895 | const gdb_byte *val; |
cb3d25d1 | 2896 | struct value *arg = args[argnum]; |
4991999e | 2897 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
2898 | int len = TYPE_LENGTH (arg_type); |
2899 | enum type_code typecode = TYPE_CODE (arg_type); | |
2900 | ||
2901 | if (mips_debug) | |
2902 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2903 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
2904 | argnum + 1, len, (int) typecode); |
2905 | ||
47a35522 | 2906 | val = value_contents (arg); |
cb3d25d1 MS |
2907 | |
2908 | if (fp_register_arg_p (typecode, arg_type) | |
8d26208a | 2909 | && argreg <= MIPS_LAST_ARG_REGNUM) |
cb3d25d1 MS |
2910 | { |
2911 | /* This is a floating point value that fits entirely | |
2912 | in a single register. */ | |
cb3d25d1 MS |
2913 | LONGEST regval = extract_unsigned_integer (val, len); |
2914 | if (mips_debug) | |
2915 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
2916 | float_argreg, phex (regval, len)); | |
8d26208a | 2917 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
2918 | |
2919 | if (mips_debug) | |
2920 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
2921 | argreg, phex (regval, len)); | |
9c9acae0 | 2922 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
2923 | float_argreg++; |
2924 | argreg++; | |
cb3d25d1 MS |
2925 | } |
2926 | else | |
2927 | { | |
2928 | /* Copy the argument to general registers or the stack in | |
2929 | register-sized pieces. Large arguments are split between | |
2930 | registers and stack. */ | |
1a69e1e4 | 2931 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
2932 | are treated specially: Irix cc passes them in registers |
2933 | where gcc sometimes puts them on the stack. For maximum | |
2934 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
2935 | int odd_sized_struct = (len > MIPS64_REGSIZE |
2936 | && len % MIPS64_REGSIZE != 0); | |
cb3d25d1 | 2937 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2938 | register are only written to memory. */ |
cb3d25d1 MS |
2939 | while (len > 0) |
2940 | { | |
ad018eee | 2941 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 2942 | int stack_used_p = 0; |
1a69e1e4 | 2943 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
2944 | |
2945 | if (mips_debug) | |
2946 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2947 | partial_len); | |
2948 | ||
8d26208a DJ |
2949 | if (fp_register_arg_p (typecode, arg_type)) |
2950 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM); | |
2951 | ||
cb3d25d1 MS |
2952 | /* Write this portion of the argument to the stack. */ |
2953 | if (argreg > MIPS_LAST_ARG_REGNUM | |
8d26208a | 2954 | || odd_sized_struct) |
cb3d25d1 MS |
2955 | { |
2956 | /* Should shorter than int integer values be | |
2957 | promoted to int before being stored? */ | |
2958 | int longword_offset = 0; | |
2959 | CORE_ADDR addr; | |
2960 | stack_used_p = 1; | |
4c6b5505 | 2961 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 2962 | { |
1a69e1e4 DJ |
2963 | if ((typecode == TYPE_CODE_INT |
2964 | || typecode == TYPE_CODE_PTR | |
2965 | || typecode == TYPE_CODE_FLT) | |
2966 | && len <= 4) | |
2967 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
2968 | } |
2969 | ||
2970 | if (mips_debug) | |
2971 | { | |
2972 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
2973 | paddr_nz (stack_offset)); | |
2974 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2975 | paddr_nz (longword_offset)); | |
2976 | } | |
2977 | ||
2978 | addr = sp + stack_offset + longword_offset; | |
2979 | ||
2980 | if (mips_debug) | |
2981 | { | |
2982 | int i; | |
6d82d43b | 2983 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
2984 | paddr_nz (addr)); |
2985 | for (i = 0; i < partial_len; i++) | |
2986 | { | |
6d82d43b | 2987 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
2988 | val[i] & 0xff); |
2989 | } | |
2990 | } | |
2991 | write_memory (addr, val, partial_len); | |
2992 | } | |
2993 | ||
2994 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 2995 | structs may go thru BOTH paths. */ |
cb3d25d1 | 2996 | /* Write this portion of the argument to a general |
6d82d43b | 2997 | purpose register. */ |
8d26208a | 2998 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
cb3d25d1 | 2999 | { |
6d82d43b AC |
3000 | LONGEST regval = |
3001 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3002 | |
3003 | /* A non-floating-point argument being passed in a | |
3004 | general register. If a struct or union, and if | |
3005 | the remaining length is smaller than the register | |
3006 | size, we have to adjust the register value on | |
3007 | big endian targets. | |
3008 | ||
3009 | It does not seem to be necessary to do the | |
1a69e1e4 | 3010 | same for integral types. */ |
cb3d25d1 | 3011 | |
4c6b5505 | 3012 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3013 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3014 | && (typecode == TYPE_CODE_STRUCT |
3015 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3016 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3017 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3018 | |
3019 | if (mips_debug) | |
3020 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3021 | argreg, | |
1a69e1e4 | 3022 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3023 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3024 | |
3025 | if (mips_n32n64_fp_arg_chunk_p (arg_type, | |
3026 | TYPE_LENGTH (arg_type) - len)) | |
3027 | { | |
3028 | if (mips_debug) | |
3029 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3030 | float_argreg, | |
3031 | phex (regval, MIPS64_REGSIZE)); | |
3032 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3033 | regval); | |
3034 | } | |
3035 | ||
3036 | float_argreg++; | |
cb3d25d1 MS |
3037 | argreg++; |
3038 | } | |
3039 | ||
3040 | len -= partial_len; | |
3041 | val += partial_len; | |
3042 | ||
3043 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3044 | will copy the next parameter. |
cb3d25d1 MS |
3045 | |
3046 | In N32 (N64?), the stack_offset only needs to be | |
3047 | adjusted when it has been used. */ | |
3048 | ||
3049 | if (stack_used_p) | |
1a69e1e4 | 3050 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3051 | } |
3052 | } | |
3053 | if (mips_debug) | |
3054 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3055 | } | |
3056 | ||
f10683bb | 3057 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3058 | |
cb3d25d1 MS |
3059 | /* Return adjusted stack pointer. */ |
3060 | return sp; | |
3061 | } | |
3062 | ||
6d82d43b AC |
3063 | static enum return_value_convention |
3064 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3065 | struct type *type, struct regcache *regcache, | |
47a35522 | 3066 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3067 | { |
6d82d43b AC |
3068 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3069 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3070 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3071 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
1a69e1e4 | 3072 | || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3073 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3074 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3075 | && TYPE_LENGTH (type) == 16 | |
3076 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3077 | { | |
3078 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3079 | two registers are used in the same as memory order, so the | |
3080 | eight bytes with the lower memory address are in $f0. */ | |
3081 | if (mips_debug) | |
3082 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
3083 | mips_xfer_register (regcache, | |
f57d151a UW |
3084 | gdbarch_num_regs (current_gdbarch) |
3085 | + mips_regnum (current_gdbarch)->fp0, | |
4c6b5505 UW |
3086 | 8, gdbarch_byte_order (current_gdbarch), |
3087 | readbuf, writebuf, 0); | |
d05f6826 | 3088 | mips_xfer_register (regcache, |
f57d151a UW |
3089 | gdbarch_num_regs (current_gdbarch) |
3090 | + mips_regnum (current_gdbarch)->fp0 + 2, | |
4c6b5505 UW |
3091 | 8, gdbarch_byte_order (current_gdbarch), |
3092 | readbuf ? readbuf + 8 : readbuf, | |
d05f6826 DJ |
3093 | writebuf ? writebuf + 8 : writebuf, 0); |
3094 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3095 | } | |
6d82d43b AC |
3096 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3097 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3098 | { | |
3099 | /* A floating-point value belongs in the least significant part | |
3100 | of FP0. */ | |
3101 | if (mips_debug) | |
3102 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3103 | mips_xfer_register (regcache, | |
f57d151a UW |
3104 | gdbarch_num_regs (current_gdbarch) |
3105 | + mips_regnum (current_gdbarch)->fp0, | |
6d82d43b | 3106 | TYPE_LENGTH (type), |
4c6b5505 UW |
3107 | gdbarch_byte_order (current_gdbarch), |
3108 | readbuf, writebuf, 0); | |
6d82d43b AC |
3109 | return RETURN_VALUE_REGISTER_CONVENTION; |
3110 | } | |
3111 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3112 | && TYPE_NFIELDS (type) <= 2 | |
3113 | && TYPE_NFIELDS (type) >= 1 | |
3114 | && ((TYPE_NFIELDS (type) == 1 | |
3115 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3116 | == TYPE_CODE_FLT)) | |
3117 | || (TYPE_NFIELDS (type) == 2 | |
3118 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3119 | == TYPE_CODE_FLT) | |
3120 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3121 | == TYPE_CODE_FLT))) | |
3122 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3123 | { | |
3124 | /* A struct that contains one or two floats. Each value is part | |
3125 | in the least significant part of their floating point | |
3126 | register.. */ | |
6d82d43b AC |
3127 | int regnum; |
3128 | int field; | |
3129 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3130 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3131 | { | |
3132 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3133 | / TARGET_CHAR_BIT); | |
3134 | if (mips_debug) | |
3135 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3136 | offset); | |
f57d151a UW |
3137 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3138 | + regnum, | |
6d82d43b | 3139 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
4c6b5505 UW |
3140 | gdbarch_byte_order (current_gdbarch), |
3141 | readbuf, writebuf, offset); | |
6d82d43b AC |
3142 | } |
3143 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3144 | } | |
3145 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3146 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3147 | { | |
3148 | /* A structure or union. Extract the left justified value, | |
3149 | regardless of the byte order. I.e. DO NOT USE | |
3150 | mips_xfer_lower. */ | |
3151 | int offset; | |
3152 | int regnum; | |
4c7d22cb | 3153 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3154 | offset < TYPE_LENGTH (type); |
3155 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3156 | { | |
3157 | int xfer = register_size (current_gdbarch, regnum); | |
3158 | if (offset + xfer > TYPE_LENGTH (type)) | |
3159 | xfer = TYPE_LENGTH (type) - offset; | |
3160 | if (mips_debug) | |
3161 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3162 | offset, xfer, regnum); | |
f57d151a UW |
3163 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3164 | + regnum, xfer, | |
6d82d43b AC |
3165 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3166 | } | |
3167 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3168 | } | |
3169 | else | |
3170 | { | |
3171 | /* A scalar extract each part but least-significant-byte | |
3172 | justified. */ | |
3173 | int offset; | |
3174 | int regnum; | |
4c7d22cb | 3175 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3176 | offset < TYPE_LENGTH (type); |
3177 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3178 | { | |
3179 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
3180 | if (offset + xfer > TYPE_LENGTH (type)) |
3181 | xfer = TYPE_LENGTH (type) - offset; | |
3182 | if (mips_debug) | |
3183 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3184 | offset, xfer, regnum); | |
f57d151a UW |
3185 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3186 | + regnum, xfer, | |
4c6b5505 UW |
3187 | gdbarch_byte_order (current_gdbarch), |
3188 | readbuf, writebuf, offset); | |
6d82d43b AC |
3189 | } |
3190 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3191 | } | |
3192 | } | |
3193 | ||
3194 | /* O32 ABI stuff. */ | |
3195 | ||
3196 | static CORE_ADDR | |
7d9b040b | 3197 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3198 | struct regcache *regcache, CORE_ADDR bp_addr, |
3199 | int nargs, struct value **args, CORE_ADDR sp, | |
3200 | int struct_return, CORE_ADDR struct_addr) | |
3201 | { | |
3202 | int argreg; | |
3203 | int float_argreg; | |
3204 | int argnum; | |
3205 | int len = 0; | |
3206 | int stack_offset = 0; | |
3207 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3208 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3209 | |
3210 | /* For shared libraries, "t9" needs to point at the function | |
3211 | address. */ | |
4c7d22cb | 3212 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3213 | |
3214 | /* Set the return address register to point to the entry point of | |
3215 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3216 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3217 | |
3218 | /* First ensure that the stack and structure return address (if any) | |
3219 | are properly aligned. The stack has to be at least 64-bit | |
3220 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3221 | aligned. For n32 and n64, stack frames need to be 128-bit |
3222 | aligned, so we round to this widest known alignment. */ | |
3223 | ||
5b03f266 AC |
3224 | sp = align_down (sp, 16); |
3225 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3226 | |
3227 | /* Now make space on the stack for the args. */ | |
3228 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3229 | { |
3230 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3231 | int arglen = TYPE_LENGTH (arg_type); | |
3232 | ||
3233 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3234 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3235 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3236 | /* Allocate space on the stack. */ |
1a69e1e4 | 3237 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3238 | } |
5b03f266 | 3239 | sp -= align_up (len, 16); |
ebafbe83 MS |
3240 | |
3241 | if (mips_debug) | |
6d82d43b | 3242 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3243 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3244 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3245 | |
3246 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3247 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3248 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3249 | |
bcb0cc15 | 3250 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3251 | if (struct_return) |
3252 | { | |
3253 | if (mips_debug) | |
3254 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3255 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 | 3256 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3257 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3258 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3259 | } |
3260 | ||
3261 | /* Now load as many as possible of the first arguments into | |
3262 | registers, and push the rest onto the stack. Loop thru args | |
3263 | from first to last. */ | |
3264 | for (argnum = 0; argnum < nargs; argnum++) | |
3265 | { | |
47a35522 | 3266 | const gdb_byte *val; |
ebafbe83 | 3267 | struct value *arg = args[argnum]; |
4991999e | 3268 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3269 | int len = TYPE_LENGTH (arg_type); |
3270 | enum type_code typecode = TYPE_CODE (arg_type); | |
3271 | ||
3272 | if (mips_debug) | |
3273 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3274 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3275 | argnum + 1, len, (int) typecode); |
3276 | ||
47a35522 | 3277 | val = value_contents (arg); |
46cac009 AC |
3278 | |
3279 | /* 32-bit ABIs always start floating point arguments in an | |
3280 | even-numbered floating point register. Round the FP register | |
3281 | up before the check to see if there are any FP registers | |
3282 | left. O32/O64 targets also pass the FP in the integer | |
3283 | registers so also round up normal registers. */ | |
2afd3f0a | 3284 | if (fp_register_arg_p (typecode, arg_type)) |
46cac009 AC |
3285 | { |
3286 | if ((float_argreg & 1)) | |
3287 | float_argreg++; | |
3288 | } | |
3289 | ||
3290 | /* Floating point arguments passed in registers have to be | |
3291 | treated specially. On 32-bit architectures, doubles | |
3292 | are passed in register pairs; the even register gets | |
3293 | the low word, and the odd register gets the high word. | |
3294 | On O32/O64, the first two floating point arguments are | |
3295 | also copied to general registers, because MIPS16 functions | |
3296 | don't use float registers for arguments. This duplication of | |
3297 | arguments in general registers can't hurt non-MIPS16 functions | |
3298 | because those registers are normally skipped. */ | |
3299 | ||
3300 | if (fp_register_arg_p (typecode, arg_type) | |
3301 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3302 | { | |
8b07f6d8 | 3303 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3304 | { |
4c6b5505 UW |
3305 | int low_offset = gdbarch_byte_order (current_gdbarch) |
3306 | == BFD_ENDIAN_BIG ? 4 : 0; | |
46cac009 AC |
3307 | unsigned long regval; |
3308 | ||
3309 | /* Write the low word of the double to the even register(s). */ | |
3310 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3311 | if (mips_debug) | |
3312 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3313 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3314 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3315 | if (mips_debug) |
3316 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3317 | argreg, phex (regval, 4)); | |
9c9acae0 | 3318 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3319 | |
3320 | /* Write the high word of the double to the odd register(s). */ | |
3321 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3322 | if (mips_debug) | |
3323 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3324 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3325 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3326 | |
3327 | if (mips_debug) | |
3328 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3329 | argreg, phex (regval, 4)); | |
9c9acae0 | 3330 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3331 | } |
3332 | else | |
3333 | { | |
3334 | /* This is a floating point value that fits entirely | |
3335 | in a single register. */ | |
3336 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3337 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3338 | LONGEST regval = extract_unsigned_integer (val, len); |
3339 | if (mips_debug) | |
3340 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3341 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3342 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 | 3343 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP |
6d82d43b AC |
3344 | registers for each argument. The below is (my |
3345 | guess) to ensure that the corresponding integer | |
3346 | register has reserved the same space. */ | |
46cac009 AC |
3347 | if (mips_debug) |
3348 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3349 | argreg, phex (regval, len)); | |
9c9acae0 | 3350 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 3351 | argreg += 2; |
46cac009 AC |
3352 | } |
3353 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3354 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3355 | } |
3356 | else | |
3357 | { | |
3358 | /* Copy the argument to general registers or the stack in | |
3359 | register-sized pieces. Large arguments are split between | |
3360 | registers and stack. */ | |
1a69e1e4 DJ |
3361 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3362 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3363 | them in registers where gcc sometimes puts them on the |
3364 | stack. For maximum compatibility, we will put them in | |
3365 | both places. */ | |
1a69e1e4 DJ |
3366 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3367 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3368 | /* Structures should be aligned to eight bytes (even arg registers) |
3369 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3370 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3371 | { |
3372 | if ((argreg & 1)) | |
968b5391 MR |
3373 | { |
3374 | argreg++; | |
1a69e1e4 | 3375 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3376 | } |
46cac009 | 3377 | } |
46cac009 AC |
3378 | while (len > 0) |
3379 | { | |
3380 | /* Remember if the argument was written to the stack. */ | |
3381 | int stack_used_p = 0; | |
1a69e1e4 | 3382 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3383 | |
3384 | if (mips_debug) | |
3385 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3386 | partial_len); | |
3387 | ||
3388 | /* Write this portion of the argument to the stack. */ | |
3389 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3390 | || odd_sized_struct) |
46cac009 AC |
3391 | { |
3392 | /* Should shorter than int integer values be | |
3393 | promoted to int before being stored? */ | |
3394 | int longword_offset = 0; | |
3395 | CORE_ADDR addr; | |
3396 | stack_used_p = 1; | |
46cac009 AC |
3397 | |
3398 | if (mips_debug) | |
3399 | { | |
3400 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3401 | paddr_nz (stack_offset)); | |
3402 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3403 | paddr_nz (longword_offset)); | |
3404 | } | |
3405 | ||
3406 | addr = sp + stack_offset + longword_offset; | |
3407 | ||
3408 | if (mips_debug) | |
3409 | { | |
3410 | int i; | |
6d82d43b | 3411 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3412 | paddr_nz (addr)); |
3413 | for (i = 0; i < partial_len; i++) | |
3414 | { | |
6d82d43b | 3415 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3416 | val[i] & 0xff); |
3417 | } | |
3418 | } | |
3419 | write_memory (addr, val, partial_len); | |
3420 | } | |
3421 | ||
3422 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3423 | structs may go thru BOTH paths. */ |
46cac009 | 3424 | /* Write this portion of the argument to a general |
6d82d43b | 3425 | purpose register. */ |
968b5391 | 3426 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
46cac009 AC |
3427 | { |
3428 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3429 | /* Value may need to be sign extended, because |
1b13c4f6 | 3430 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3431 | |
3432 | /* A non-floating-point argument being passed in a | |
3433 | general register. If a struct or union, and if | |
3434 | the remaining length is smaller than the register | |
3435 | size, we have to adjust the register value on | |
3436 | big endian targets. | |
3437 | ||
3438 | It does not seem to be necessary to do the | |
3439 | same for integral types. | |
3440 | ||
3441 | Also don't do this adjustment on O64 binaries. | |
3442 | ||
3443 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3444 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3445 | mips_abi_regsize(), generates a left shift |
3446 | as part of storing the argument in a register | |
3447 | (the left shift isn't generated when | |
1b13c4f6 | 3448 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3449 | it is quite possible that this is GCC |
3450 | contradicting the LE/O32 ABI, GDB has not been | |
3451 | adjusted to accommodate this. Either someone | |
3452 | needs to demonstrate that the LE/O32 ABI | |
3453 | specifies such a left shift OR this new ABI gets | |
3454 | identified as such and GDB gets tweaked | |
3455 | accordingly. */ | |
3456 | ||
4c6b5505 | 3457 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3458 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3459 | && (typecode == TYPE_CODE_STRUCT |
3460 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3461 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3462 | * TARGET_CHAR_BIT); |
46cac009 AC |
3463 | |
3464 | if (mips_debug) | |
3465 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3466 | argreg, | |
1a69e1e4 | 3467 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 3468 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
3469 | argreg++; |
3470 | ||
3471 | /* Prevent subsequent floating point arguments from | |
3472 | being passed in floating point registers. */ | |
3473 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3474 | } | |
3475 | ||
3476 | len -= partial_len; | |
3477 | val += partial_len; | |
3478 | ||
3479 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3480 | will copy the next parameter. |
46cac009 | 3481 | |
6d82d43b AC |
3482 | In older ABIs, the caller reserved space for |
3483 | registers that contained arguments. This was loosely | |
3484 | refered to as their "home". Consequently, space is | |
3485 | always allocated. */ | |
46cac009 | 3486 | |
1a69e1e4 | 3487 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3488 | } |
3489 | } | |
3490 | if (mips_debug) | |
3491 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3492 | } | |
3493 | ||
f10683bb | 3494 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3495 | |
46cac009 AC |
3496 | /* Return adjusted stack pointer. */ |
3497 | return sp; | |
3498 | } | |
3499 | ||
6d82d43b AC |
3500 | static enum return_value_convention |
3501 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3502 | struct regcache *regcache, | |
47a35522 | 3503 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b AC |
3504 | { |
3505 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3506 | ||
3507 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3508 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3509 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3510 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3511 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3512 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3513 | { | |
3514 | /* A single-precision floating-point value. It fits in the | |
3515 | least significant part of FP0. */ | |
3516 | if (mips_debug) | |
3517 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3518 | mips_xfer_register (regcache, | |
f57d151a UW |
3519 | gdbarch_num_regs (current_gdbarch) |
3520 | + mips_regnum (current_gdbarch)->fp0, | |
6d82d43b | 3521 | TYPE_LENGTH (type), |
4c6b5505 UW |
3522 | gdbarch_byte_order (current_gdbarch), |
3523 | readbuf, writebuf, 0); | |
6d82d43b AC |
3524 | return RETURN_VALUE_REGISTER_CONVENTION; |
3525 | } | |
3526 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3527 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3528 | { | |
3529 | /* A double-precision floating-point value. The most | |
3530 | significant part goes in FP1, and the least significant in | |
3531 | FP0. */ | |
3532 | if (mips_debug) | |
3533 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
4c6b5505 | 3534 | switch (gdbarch_byte_order (current_gdbarch)) |
6d82d43b AC |
3535 | { |
3536 | case BFD_ENDIAN_LITTLE: | |
3537 | mips_xfer_register (regcache, | |
f57d151a UW |
3538 | gdbarch_num_regs (current_gdbarch) |
3539 | + mips_regnum (current_gdbarch)->fp0 + | |
4c6b5505 UW |
3540 | 0, 4, gdbarch_byte_order (current_gdbarch), |
3541 | readbuf, writebuf, 0); | |
6d82d43b | 3542 | mips_xfer_register (regcache, |
f57d151a UW |
3543 | gdbarch_num_regs (current_gdbarch) |
3544 | + mips_regnum (current_gdbarch)->fp0 + 1, | |
4c6b5505 UW |
3545 | 4, gdbarch_byte_order (current_gdbarch), |
3546 | readbuf, writebuf, 4); | |
6d82d43b AC |
3547 | break; |
3548 | case BFD_ENDIAN_BIG: | |
3549 | mips_xfer_register (regcache, | |
f57d151a UW |
3550 | gdbarch_num_regs (current_gdbarch) |
3551 | + mips_regnum (current_gdbarch)->fp0 + 1, | |
4c6b5505 UW |
3552 | 4, gdbarch_byte_order (current_gdbarch), |
3553 | readbuf, writebuf, 0); | |
6d82d43b | 3554 | mips_xfer_register (regcache, |
f57d151a UW |
3555 | gdbarch_num_regs (current_gdbarch) |
3556 | + mips_regnum (current_gdbarch)->fp0 + 0, | |
4c6b5505 UW |
3557 | 4, gdbarch_byte_order (current_gdbarch), |
3558 | readbuf, writebuf, 4); | |
6d82d43b AC |
3559 | break; |
3560 | default: | |
e2e0b3e5 | 3561 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3562 | } |
3563 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3564 | } | |
3565 | #if 0 | |
3566 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3567 | && TYPE_NFIELDS (type) <= 2 | |
3568 | && TYPE_NFIELDS (type) >= 1 | |
3569 | && ((TYPE_NFIELDS (type) == 1 | |
3570 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3571 | == TYPE_CODE_FLT)) | |
3572 | || (TYPE_NFIELDS (type) == 2 | |
3573 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3574 | == TYPE_CODE_FLT) | |
3575 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3576 | == TYPE_CODE_FLT))) | |
3577 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3578 | { | |
3579 | /* A struct that contains one or two floats. Each value is part | |
3580 | in the least significant part of their floating point | |
3581 | register.. */ | |
870cd05e | 3582 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
3583 | int regnum; |
3584 | int field; | |
3585 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3586 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3587 | { | |
3588 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3589 | / TARGET_CHAR_BIT); | |
3590 | if (mips_debug) | |
3591 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3592 | offset); | |
f57d151a UW |
3593 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3594 | + regnum, | |
6d82d43b | 3595 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
4c6b5505 UW |
3596 | gdbarch_byte_order (current_gdbarch), |
3597 | readbuf, writebuf, offset); | |
6d82d43b AC |
3598 | } |
3599 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3600 | } | |
3601 | #endif | |
3602 | #if 0 | |
3603 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3604 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3605 | { | |
3606 | /* A structure or union. Extract the left justified value, | |
3607 | regardless of the byte order. I.e. DO NOT USE | |
3608 | mips_xfer_lower. */ | |
3609 | int offset; | |
3610 | int regnum; | |
4c7d22cb | 3611 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3612 | offset < TYPE_LENGTH (type); |
3613 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3614 | { | |
3615 | int xfer = register_size (current_gdbarch, regnum); | |
3616 | if (offset + xfer > TYPE_LENGTH (type)) | |
3617 | xfer = TYPE_LENGTH (type) - offset; | |
3618 | if (mips_debug) | |
3619 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3620 | offset, xfer, regnum); | |
f57d151a UW |
3621 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3622 | + regnum, xfer, | |
6d82d43b AC |
3623 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3624 | } | |
3625 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3626 | } | |
3627 | #endif | |
3628 | else | |
3629 | { | |
3630 | /* A scalar extract each part but least-significant-byte | |
3631 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 3632 | the ISA. */ |
6d82d43b AC |
3633 | int offset; |
3634 | int regnum; | |
4c7d22cb | 3635 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3636 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 3637 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 3638 | { |
1a69e1e4 | 3639 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
3640 | if (offset + xfer > TYPE_LENGTH (type)) |
3641 | xfer = TYPE_LENGTH (type) - offset; | |
3642 | if (mips_debug) | |
3643 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3644 | offset, xfer, regnum); | |
f57d151a UW |
3645 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3646 | + regnum, xfer, | |
4c6b5505 UW |
3647 | gdbarch_byte_order (current_gdbarch), |
3648 | readbuf, writebuf, offset); | |
6d82d43b AC |
3649 | } |
3650 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3651 | } | |
3652 | } | |
3653 | ||
3654 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3655 | ABI. */ | |
46cac009 AC |
3656 | |
3657 | static CORE_ADDR | |
7d9b040b | 3658 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3659 | struct regcache *regcache, CORE_ADDR bp_addr, |
3660 | int nargs, | |
3661 | struct value **args, CORE_ADDR sp, | |
3662 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3663 | { |
3664 | int argreg; | |
3665 | int float_argreg; | |
3666 | int argnum; | |
3667 | int len = 0; | |
3668 | int stack_offset = 0; | |
480d3dd2 | 3669 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3670 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 3671 | |
25ab4790 AC |
3672 | /* For shared libraries, "t9" needs to point at the function |
3673 | address. */ | |
4c7d22cb | 3674 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3675 | |
3676 | /* Set the return address register to point to the entry point of | |
3677 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3678 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3679 | |
46cac009 AC |
3680 | /* First ensure that the stack and structure return address (if any) |
3681 | are properly aligned. The stack has to be at least 64-bit | |
3682 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3683 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3684 | aligned, so we round to this widest known alignment. */ | |
3685 | ||
5b03f266 AC |
3686 | sp = align_down (sp, 16); |
3687 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3688 | |
3689 | /* Now make space on the stack for the args. */ | |
3690 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3691 | { |
3692 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3693 | int arglen = TYPE_LENGTH (arg_type); | |
3694 | ||
968b5391 | 3695 | /* Allocate space on the stack. */ |
1a69e1e4 | 3696 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 3697 | } |
5b03f266 | 3698 | sp -= align_up (len, 16); |
46cac009 AC |
3699 | |
3700 | if (mips_debug) | |
6d82d43b | 3701 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3702 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3703 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3704 | |
3705 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3706 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3707 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3708 | |
3709 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3710 | if (struct_return) | |
3711 | { | |
3712 | if (mips_debug) | |
3713 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3714 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 | 3715 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3716 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3717 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
3718 | } |
3719 | ||
3720 | /* Now load as many as possible of the first arguments into | |
3721 | registers, and push the rest onto the stack. Loop thru args | |
3722 | from first to last. */ | |
3723 | for (argnum = 0; argnum < nargs; argnum++) | |
3724 | { | |
47a35522 | 3725 | const gdb_byte *val; |
46cac009 | 3726 | struct value *arg = args[argnum]; |
4991999e | 3727 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
3728 | int len = TYPE_LENGTH (arg_type); |
3729 | enum type_code typecode = TYPE_CODE (arg_type); | |
3730 | ||
3731 | if (mips_debug) | |
3732 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3733 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3734 | argnum + 1, len, (int) typecode); |
3735 | ||
47a35522 | 3736 | val = value_contents (arg); |
ebafbe83 | 3737 | |
ebafbe83 MS |
3738 | /* Floating point arguments passed in registers have to be |
3739 | treated specially. On 32-bit architectures, doubles | |
3740 | are passed in register pairs; the even register gets | |
3741 | the low word, and the odd register gets the high word. | |
3742 | On O32/O64, the first two floating point arguments are | |
3743 | also copied to general registers, because MIPS16 functions | |
3744 | don't use float registers for arguments. This duplication of | |
3745 | arguments in general registers can't hurt non-MIPS16 functions | |
3746 | because those registers are normally skipped. */ | |
3747 | ||
3748 | if (fp_register_arg_p (typecode, arg_type) | |
3749 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3750 | { | |
2afd3f0a MR |
3751 | LONGEST regval = extract_unsigned_integer (val, len); |
3752 | if (mips_debug) | |
3753 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3754 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3755 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
3756 | if (mips_debug) |
3757 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3758 | argreg, phex (regval, len)); | |
9c9acae0 | 3759 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 3760 | argreg++; |
ebafbe83 | 3761 | /* Reserve space for the FP register. */ |
1a69e1e4 | 3762 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
3763 | } |
3764 | else | |
3765 | { | |
3766 | /* Copy the argument to general registers or the stack in | |
3767 | register-sized pieces. Large arguments are split between | |
3768 | registers and stack. */ | |
1a69e1e4 | 3769 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
3770 | are treated specially: Irix cc passes them in registers |
3771 | where gcc sometimes puts them on the stack. For maximum | |
3772 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
3773 | int odd_sized_struct = (len > MIPS64_REGSIZE |
3774 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
3775 | while (len > 0) |
3776 | { | |
3777 | /* Remember if the argument was written to the stack. */ | |
3778 | int stack_used_p = 0; | |
1a69e1e4 | 3779 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
3780 | |
3781 | if (mips_debug) | |
3782 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3783 | partial_len); | |
3784 | ||
3785 | /* Write this portion of the argument to the stack. */ | |
3786 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3787 | || odd_sized_struct) |
ebafbe83 MS |
3788 | { |
3789 | /* Should shorter than int integer values be | |
3790 | promoted to int before being stored? */ | |
3791 | int longword_offset = 0; | |
3792 | CORE_ADDR addr; | |
3793 | stack_used_p = 1; | |
4c6b5505 | 3794 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 3795 | { |
1a69e1e4 DJ |
3796 | if ((typecode == TYPE_CODE_INT |
3797 | || typecode == TYPE_CODE_PTR | |
3798 | || typecode == TYPE_CODE_FLT) | |
3799 | && len <= 4) | |
3800 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
3801 | } |
3802 | ||
3803 | if (mips_debug) | |
3804 | { | |
3805 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3806 | paddr_nz (stack_offset)); | |
3807 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3808 | paddr_nz (longword_offset)); | |
3809 | } | |
3810 | ||
3811 | addr = sp + stack_offset + longword_offset; | |
3812 | ||
3813 | if (mips_debug) | |
3814 | { | |
3815 | int i; | |
6d82d43b | 3816 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
3817 | paddr_nz (addr)); |
3818 | for (i = 0; i < partial_len; i++) | |
3819 | { | |
6d82d43b | 3820 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
3821 | val[i] & 0xff); |
3822 | } | |
3823 | } | |
3824 | write_memory (addr, val, partial_len); | |
3825 | } | |
3826 | ||
3827 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3828 | structs may go thru BOTH paths. */ |
ebafbe83 | 3829 | /* Write this portion of the argument to a general |
6d82d43b | 3830 | purpose register. */ |
968b5391 | 3831 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
ebafbe83 MS |
3832 | { |
3833 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3834 | /* Value may need to be sign extended, because |
1b13c4f6 | 3835 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
3836 | |
3837 | /* A non-floating-point argument being passed in a | |
3838 | general register. If a struct or union, and if | |
3839 | the remaining length is smaller than the register | |
3840 | size, we have to adjust the register value on | |
3841 | big endian targets. | |
3842 | ||
3843 | It does not seem to be necessary to do the | |
401835eb | 3844 | same for integral types. */ |
480d3dd2 | 3845 | |
4c6b5505 | 3846 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3847 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3848 | && (typecode == TYPE_CODE_STRUCT |
3849 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3850 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3851 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
3852 | |
3853 | if (mips_debug) | |
3854 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3855 | argreg, | |
1a69e1e4 | 3856 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3857 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
3858 | argreg++; |
3859 | ||
3860 | /* Prevent subsequent floating point arguments from | |
3861 | being passed in floating point registers. */ | |
3862 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3863 | } | |
3864 | ||
3865 | len -= partial_len; | |
3866 | val += partial_len; | |
3867 | ||
3868 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3869 | will copy the next parameter. |
ebafbe83 | 3870 | |
6d82d43b AC |
3871 | In older ABIs, the caller reserved space for |
3872 | registers that contained arguments. This was loosely | |
3873 | refered to as their "home". Consequently, space is | |
3874 | always allocated. */ | |
ebafbe83 | 3875 | |
1a69e1e4 | 3876 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
3877 | } |
3878 | } | |
3879 | if (mips_debug) | |
3880 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3881 | } | |
3882 | ||
f10683bb | 3883 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3884 | |
ebafbe83 MS |
3885 | /* Return adjusted stack pointer. */ |
3886 | return sp; | |
3887 | } | |
3888 | ||
9c8fdbfa AC |
3889 | static enum return_value_convention |
3890 | mips_o64_return_value (struct gdbarch *gdbarch, | |
3891 | struct type *type, struct regcache *regcache, | |
47a35522 | 3892 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3893 | { |
7a076fd2 FF |
3894 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3895 | ||
3896 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3897 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3898 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3899 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3900 | else if (fp_register_arg_p (TYPE_CODE (type), type)) | |
3901 | { | |
3902 | /* A floating-point value. It fits in the least significant | |
3903 | part of FP0. */ | |
3904 | if (mips_debug) | |
3905 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3906 | mips_xfer_register (regcache, | |
f57d151a UW |
3907 | gdbarch_num_regs (current_gdbarch) |
3908 | + mips_regnum (current_gdbarch)->fp0, | |
7a076fd2 | 3909 | TYPE_LENGTH (type), |
4c6b5505 UW |
3910 | gdbarch_byte_order (current_gdbarch), |
3911 | readbuf, writebuf, 0); | |
7a076fd2 FF |
3912 | return RETURN_VALUE_REGISTER_CONVENTION; |
3913 | } | |
3914 | else | |
3915 | { | |
3916 | /* A scalar extract each part but least-significant-byte | |
3917 | justified. */ | |
3918 | int offset; | |
3919 | int regnum; | |
3920 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
3921 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 3922 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 3923 | { |
1a69e1e4 | 3924 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
3925 | if (offset + xfer > TYPE_LENGTH (type)) |
3926 | xfer = TYPE_LENGTH (type) - offset; | |
3927 | if (mips_debug) | |
3928 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3929 | offset, xfer, regnum); | |
f57d151a UW |
3930 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3931 | + regnum, xfer, | |
4c6b5505 UW |
3932 | gdbarch_byte_order (current_gdbarch), |
3933 | readbuf, writebuf, offset); | |
7a076fd2 FF |
3934 | } |
3935 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3936 | } | |
6d82d43b AC |
3937 | } |
3938 | ||
dd824b04 DJ |
3939 | /* Floating point register management. |
3940 | ||
3941 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3942 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3943 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3944 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3945 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3946 | double precision floats into two 32-bit chunks and store them in | |
3947 | consecutive fp regs. To display 64-bit floats stored in this | |
3948 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3949 | Throw in user-configurable endianness and you have a real mess. | |
3950 | ||
3951 | The way this works is: | |
3952 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3953 | double-precision value will be split across two logical registers. | |
3954 | The lower-numbered logical register will hold the low-order bits, | |
3955 | regardless of the processor's endianness. | |
3956 | - If we are on a 64-bit processor, and we are looking for a | |
3957 | single-precision value, it will be in the low ordered bits | |
3958 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3959 | save slot in memory. | |
3960 | - If we are in 64-bit mode, everything is straightforward. | |
3961 | ||
3962 | Note that this code only deals with "live" registers at the top of the | |
3963 | stack. We will attempt to deal with saved registers later, when | |
3964 | the raw/cooked register interface is in place. (We need a general | |
3965 | interface that can deal with dynamic saved register sizes -- fp | |
3966 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3967 | and below). */ | |
3968 | ||
67b2c998 DJ |
3969 | static struct type * |
3970 | mips_float_register_type (void) | |
3971 | { | |
8da61cc4 | 3972 | return builtin_type_ieee_single; |
67b2c998 DJ |
3973 | } |
3974 | ||
3975 | static struct type * | |
3976 | mips_double_register_type (void) | |
3977 | { | |
8da61cc4 | 3978 | return builtin_type_ieee_double; |
67b2c998 DJ |
3979 | } |
3980 | ||
dd824b04 DJ |
3981 | /* Copy a 32-bit single-precision value from the current frame |
3982 | into rare_buffer. */ | |
3983 | ||
3984 | static void | |
e11c53d2 | 3985 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 3986 | gdb_byte *rare_buffer) |
dd824b04 | 3987 | { |
719ec221 | 3988 | int raw_size = register_size (current_gdbarch, regno); |
47a35522 | 3989 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 3990 | |
e11c53d2 | 3991 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 UW |
3992 | error (_("can't read register %d (%s)"), |
3993 | regno, gdbarch_register_name (current_gdbarch, regno)); | |
dd824b04 DJ |
3994 | if (raw_size == 8) |
3995 | { | |
3996 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 3997 | 32 bits. */ |
dd824b04 DJ |
3998 | int offset; |
3999 | ||
4c6b5505 | 4000 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4001 | offset = 4; |
4002 | else | |
4003 | offset = 0; | |
4004 | ||
4005 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4006 | } | |
4007 | else | |
4008 | { | |
4009 | memcpy (rare_buffer, raw_buffer, 4); | |
4010 | } | |
4011 | } | |
4012 | ||
4013 | /* Copy a 64-bit double-precision value from the current frame into | |
4014 | rare_buffer. This may include getting half of it from the next | |
4015 | register. */ | |
4016 | ||
4017 | static void | |
e11c53d2 | 4018 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4019 | gdb_byte *rare_buffer) |
dd824b04 | 4020 | { |
719ec221 | 4021 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 | 4022 | |
9c9acae0 | 4023 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4024 | { |
4025 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4026 | all 64 bits. */ |
e11c53d2 | 4027 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 UW |
4028 | error (_("can't read register %d (%s)"), |
4029 | regno, gdbarch_register_name (current_gdbarch, regno)); | |
dd824b04 DJ |
4030 | } |
4031 | else | |
4032 | { | |
56cea623 | 4033 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 | 4034 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4035 | _("mips_read_fp_register_double: bad access to " |
4036 | "odd-numbered FP register")); | |
dd824b04 DJ |
4037 | |
4038 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4039 | each register. */ |
4c6b5505 | 4040 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4041 | { |
e11c53d2 AC |
4042 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4043 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4044 | } |
361d1df0 | 4045 | else |
dd824b04 | 4046 | { |
e11c53d2 AC |
4047 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4048 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4049 | } |
4050 | } | |
4051 | } | |
4052 | ||
c906108c | 4053 | static void |
e11c53d2 AC |
4054 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4055 | int regnum) | |
c5aa993b | 4056 | { /* do values for FP (float) regs */ |
47a35522 | 4057 | gdb_byte *raw_buffer; |
3903d437 AC |
4058 | double doub, flt1; /* doubles extracted from raw hex data */ |
4059 | int inv1, inv2; | |
c5aa993b | 4060 | |
47a35522 MK |
4061 | raw_buffer = alloca (2 * register_size (current_gdbarch, |
4062 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 4063 | |
c9f4d572 UW |
4064 | fprintf_filtered (file, "%s:", |
4065 | gdbarch_register_name (current_gdbarch, regnum)); | |
4066 | fprintf_filtered (file, "%*s", | |
4067 | 4 - (int) strlen (gdbarch_register_name | |
4068 | (current_gdbarch, regnum)), | |
e11c53d2 | 4069 | ""); |
f0ef6b29 | 4070 | |
9c9acae0 | 4071 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4072 | { |
f0ef6b29 KB |
4073 | /* 4-byte registers: Print hex and floating. Also print even |
4074 | numbered registers as doubles. */ | |
e11c53d2 | 4075 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4076 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4077 | |
6d82d43b AC |
4078 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4079 | file); | |
dd824b04 | 4080 | |
e11c53d2 | 4081 | fprintf_filtered (file, " flt: "); |
1adad886 | 4082 | if (inv1) |
e11c53d2 | 4083 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4084 | else |
e11c53d2 | 4085 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4086 | |
f0ef6b29 KB |
4087 | if (regnum % 2 == 0) |
4088 | { | |
e11c53d2 | 4089 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4090 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4091 | &inv2); |
1adad886 | 4092 | |
e11c53d2 | 4093 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4094 | if (inv2) |
e11c53d2 | 4095 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4096 | else |
e11c53d2 | 4097 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4098 | } |
c906108c SS |
4099 | } |
4100 | else | |
dd824b04 | 4101 | { |
f0ef6b29 | 4102 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4103 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4104 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4105 | |
e11c53d2 | 4106 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4107 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4108 | ||
361d1df0 | 4109 | |
6d82d43b AC |
4110 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4111 | file); | |
f0ef6b29 | 4112 | |
e11c53d2 | 4113 | fprintf_filtered (file, " flt: "); |
1adad886 | 4114 | if (inv1) |
e11c53d2 | 4115 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4116 | else |
e11c53d2 | 4117 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4118 | |
e11c53d2 | 4119 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4120 | if (inv2) |
e11c53d2 | 4121 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4122 | else |
e11c53d2 | 4123 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4124 | } |
4125 | } | |
4126 | ||
4127 | static void | |
e11c53d2 | 4128 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4129 | int regnum) |
f0ef6b29 | 4130 | { |
a4b8ebc8 | 4131 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4132 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4133 | int offset; |
1adad886 | 4134 | |
7b9ee6a8 | 4135 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4136 | { |
e11c53d2 | 4137 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4138 | return; |
4139 | } | |
4140 | ||
4141 | /* Get the data in raw format. */ | |
e11c53d2 | 4142 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4143 | { |
c9f4d572 UW |
4144 | fprintf_filtered (file, "%s: [Invalid]", |
4145 | gdbarch_register_name (current_gdbarch, regnum)); | |
f0ef6b29 | 4146 | return; |
c906108c | 4147 | } |
f0ef6b29 | 4148 | |
c9f4d572 | 4149 | fputs_filtered (gdbarch_register_name (current_gdbarch, regnum), file); |
f0ef6b29 KB |
4150 | |
4151 | /* The problem with printing numeric register names (r26, etc.) is that | |
4152 | the user can't use them on input. Probably the best solution is to | |
4153 | fix it so that either the numeric or the funky (a2, etc.) names | |
4154 | are accepted on input. */ | |
4155 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4156 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4157 | else |
e11c53d2 | 4158 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4159 | |
4c6b5505 | 4160 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b AC |
4161 | offset = |
4162 | register_size (current_gdbarch, | |
4163 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
4164 | else |
4165 | offset = 0; | |
4166 | ||
6d82d43b | 4167 | print_scalar_formatted (raw_buffer + offset, |
7b9ee6a8 | 4168 | register_type (gdbarch, regnum), 'x', 0, |
6d82d43b | 4169 | file); |
c906108c SS |
4170 | } |
4171 | ||
f0ef6b29 KB |
4172 | /* Replacement for generic do_registers_info. |
4173 | Print regs in pretty columns. */ | |
4174 | ||
4175 | static int | |
e11c53d2 AC |
4176 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4177 | int regnum) | |
f0ef6b29 | 4178 | { |
e11c53d2 AC |
4179 | fprintf_filtered (file, " "); |
4180 | mips_print_fp_register (file, frame, regnum); | |
4181 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4182 | return regnum + 1; |
4183 | } | |
4184 | ||
4185 | ||
c906108c SS |
4186 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4187 | ||
4188 | static int | |
e11c53d2 | 4189 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4190 | int start_regnum) |
c906108c | 4191 | { |
a4b8ebc8 | 4192 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4193 | /* do values for GP (int) regs */ |
47a35522 | 4194 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4195 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4196 | int col, byte; |
a4b8ebc8 | 4197 | int regnum; |
c906108c SS |
4198 | |
4199 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 4200 | for (col = 0, regnum = start_regnum; |
f57d151a UW |
4201 | col < ncols && regnum < gdbarch_num_regs (current_gdbarch) |
4202 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4203 | regnum++) | |
c906108c | 4204 | { |
c9f4d572 | 4205 | if (*gdbarch_register_name (current_gdbarch, regnum) == '\0') |
c5aa993b | 4206 | continue; /* unused register */ |
7b9ee6a8 | 4207 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4208 | TYPE_CODE_FLT) |
c5aa993b | 4209 | break; /* end the row: reached FP register */ |
0cc93a06 DJ |
4210 | /* Large registers are handled separately. */ |
4211 | if (register_size (current_gdbarch, regnum) | |
4212 | > mips_abi_regsize (current_gdbarch)) | |
4213 | { | |
4214 | if (col > 0) | |
4215 | break; /* End the row before this register. */ | |
4216 | ||
4217 | /* Print this register on a row by itself. */ | |
4218 | mips_print_register (file, frame, regnum); | |
4219 | fprintf_filtered (file, "\n"); | |
4220 | return regnum + 1; | |
4221 | } | |
d05f6826 DJ |
4222 | if (col == 0) |
4223 | fprintf_filtered (file, " "); | |
6d82d43b | 4224 | fprintf_filtered (file, |
d5ac5a39 | 4225 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
c9f4d572 | 4226 | gdbarch_register_name (current_gdbarch, regnum)); |
c906108c SS |
4227 | col++; |
4228 | } | |
d05f6826 DJ |
4229 | |
4230 | if (col == 0) | |
4231 | return regnum; | |
4232 | ||
a4b8ebc8 | 4233 | /* print the R0 to R31 names */ |
f57d151a UW |
4234 | if ((start_regnum % gdbarch_num_regs (current_gdbarch)) < MIPS_NUMREGS) |
4235 | fprintf_filtered (file, "\n R%-4d", | |
4236 | start_regnum % gdbarch_num_regs (current_gdbarch)); | |
20e6603c AC |
4237 | else |
4238 | fprintf_filtered (file, "\n "); | |
c906108c | 4239 | |
c906108c | 4240 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4241 | for (col = 0, regnum = start_regnum; |
f57d151a UW |
4242 | col < ncols && regnum < gdbarch_num_regs (current_gdbarch) |
4243 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4244 | regnum++) | |
c906108c | 4245 | { |
c9f4d572 | 4246 | if (*gdbarch_register_name (current_gdbarch, regnum) == '\0') |
c5aa993b | 4247 | continue; /* unused register */ |
7b9ee6a8 | 4248 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4249 | TYPE_CODE_FLT) |
c5aa993b | 4250 | break; /* end row: reached FP register */ |
0cc93a06 DJ |
4251 | if (register_size (current_gdbarch, regnum) |
4252 | > mips_abi_regsize (current_gdbarch)) | |
4253 | break; /* End row: large register. */ | |
4254 | ||
c906108c | 4255 | /* OK: get the data in raw format. */ |
e11c53d2 | 4256 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 UW |
4257 | error (_("can't read register %d (%s)"), |
4258 | regnum, gdbarch_register_name (current_gdbarch, regnum)); | |
c906108c | 4259 | /* pad small registers */ |
4246e332 | 4260 | for (byte = 0; |
d5ac5a39 | 4261 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 4262 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
4263 | printf_filtered (" "); |
4264 | /* Now print the register value in hex, endian order. */ | |
4c6b5505 | 4265 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b AC |
4266 | for (byte = |
4267 | register_size (current_gdbarch, | |
4268 | regnum) - register_size (current_gdbarch, regnum); | |
4269 | byte < register_size (current_gdbarch, regnum); byte++) | |
47a35522 | 4270 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4271 | else |
c73e8f27 | 4272 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 4273 | byte >= 0; byte--) |
47a35522 | 4274 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4275 | fprintf_filtered (file, " "); |
c906108c SS |
4276 | col++; |
4277 | } | |
c5aa993b | 4278 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4279 | fprintf_filtered (file, "\n"); |
c906108c SS |
4280 | |
4281 | return regnum; | |
4282 | } | |
4283 | ||
4284 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4285 | ||
bf1f5b4c | 4286 | static void |
e11c53d2 AC |
4287 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4288 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4289 | { |
c5aa993b | 4290 | if (regnum != -1) /* do one specified register */ |
c906108c | 4291 | { |
f57d151a | 4292 | gdb_assert (regnum >= gdbarch_num_regs (current_gdbarch)); |
c9f4d572 | 4293 | if (*(gdbarch_register_name (current_gdbarch, regnum)) == '\0') |
8a3fe4f8 | 4294 | error (_("Not a valid register for the current processor type")); |
c906108c | 4295 | |
0cc93a06 | 4296 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4297 | fprintf_filtered (file, "\n"); |
c906108c | 4298 | } |
c5aa993b JM |
4299 | else |
4300 | /* do all (or most) registers */ | |
c906108c | 4301 | { |
f57d151a UW |
4302 | regnum = gdbarch_num_regs (current_gdbarch); |
4303 | while (regnum < gdbarch_num_regs (current_gdbarch) | |
4304 | + gdbarch_num_pseudo_regs (current_gdbarch)) | |
c906108c | 4305 | { |
7b9ee6a8 | 4306 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4307 | TYPE_CODE_FLT) |
e11c53d2 AC |
4308 | { |
4309 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4310 | regnum = print_fp_register_row (file, frame, regnum); | |
4311 | else | |
4312 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4313 | } | |
c906108c | 4314 | else |
e11c53d2 | 4315 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4316 | } |
4317 | } | |
4318 | } | |
4319 | ||
c906108c SS |
4320 | /* Is this a branch with a delay slot? */ |
4321 | ||
c906108c | 4322 | static int |
acdb74a0 | 4323 | is_delayed (unsigned long insn) |
c906108c SS |
4324 | { |
4325 | int i; | |
4326 | for (i = 0; i < NUMOPCODES; ++i) | |
4327 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4328 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4329 | break; | |
4330 | return (i < NUMOPCODES | |
4331 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4332 | | INSN_COND_BRANCH_DELAY | |
4333 | | INSN_COND_BRANCH_LIKELY))); | |
4334 | } | |
4335 | ||
4336 | int | |
3352ef37 AC |
4337 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4338 | struct frame_info *frame) | |
c906108c | 4339 | { |
3352ef37 | 4340 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4341 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4342 | |
4343 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4344 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4345 | return 0; |
4346 | ||
06648491 MK |
4347 | if (!breakpoint_here_p (pc + 4)) |
4348 | return 0; | |
4349 | ||
3352ef37 AC |
4350 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4351 | /* If error reading memory, guess that it is not a delayed | |
4352 | branch. */ | |
c906108c | 4353 | return 0; |
4c7d22cb | 4354 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4355 | } |
4356 | ||
6d82d43b AC |
4357 | /* To skip prologues, I use this predicate. Returns either PC itself |
4358 | if the code at PC does not look like a function prologue; otherwise | |
4359 | returns an address that (if we're lucky) follows the prologue. If | |
4360 | LENIENT, then we must skip everything which is involved in setting | |
4361 | up the frame (it's OK to skip more, just so long as we don't skip | |
4362 | anything which might clobber the registers which are being saved. | |
4363 | We must skip more in the case where part of the prologue is in the | |
4364 | delay slot of a non-prologue instruction). */ | |
4365 | ||
4366 | static CORE_ADDR | |
4367 | mips_skip_prologue (CORE_ADDR pc) | |
4368 | { | |
8b622e6a AC |
4369 | CORE_ADDR limit_pc; |
4370 | CORE_ADDR func_addr; | |
4371 | ||
6d82d43b AC |
4372 | /* See if we can determine the end of the prologue via the symbol table. |
4373 | If so, then return either PC, or the PC after the prologue, whichever | |
4374 | is greater. */ | |
8b622e6a AC |
4375 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4376 | { | |
4377 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
4378 | if (post_prologue_pc != 0) | |
4379 | return max (pc, post_prologue_pc); | |
4380 | } | |
6d82d43b AC |
4381 | |
4382 | /* Can't determine prologue from the symbol table, need to examine | |
4383 | instructions. */ | |
4384 | ||
98b4dd94 JB |
4385 | /* Find an upper limit on the function prologue using the debug |
4386 | information. If the debug information could not be used to provide | |
4387 | that bound, then use an arbitrary large number as the upper bound. */ | |
4388 | limit_pc = skip_prologue_using_sal (pc); | |
4389 | if (limit_pc == 0) | |
4390 | limit_pc = pc + 100; /* Magic. */ | |
4391 | ||
0fe7e7c8 | 4392 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4393 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4394 | else |
a65bbe44 | 4395 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4396 | } |
4397 | ||
a5ea2558 AC |
4398 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4399 | used for all MIPS-specific commands. */ | |
4400 | ||
a5ea2558 | 4401 | static void |
acdb74a0 | 4402 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4403 | { |
4404 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4405 | } | |
4406 | ||
a5ea2558 | 4407 | static void |
acdb74a0 | 4408 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4409 | { |
6d82d43b AC |
4410 | printf_unfiltered |
4411 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4412 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4413 | } | |
4414 | ||
c906108c SS |
4415 | /* Commands to show/set the MIPS FPU type. */ |
4416 | ||
c906108c | 4417 | static void |
acdb74a0 | 4418 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4419 | { |
c906108c SS |
4420 | char *fpu; |
4421 | switch (MIPS_FPU_TYPE) | |
4422 | { | |
4423 | case MIPS_FPU_SINGLE: | |
4424 | fpu = "single-precision"; | |
4425 | break; | |
4426 | case MIPS_FPU_DOUBLE: | |
4427 | fpu = "double-precision"; | |
4428 | break; | |
4429 | case MIPS_FPU_NONE: | |
4430 | fpu = "absent (none)"; | |
4431 | break; | |
93d56215 | 4432 | default: |
e2e0b3e5 | 4433 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4434 | } |
4435 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4436 | printf_unfiltered |
4437 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4438 | fpu); | |
c906108c | 4439 | else |
6d82d43b AC |
4440 | printf_unfiltered |
4441 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4442 | } |
4443 | ||
4444 | ||
c906108c | 4445 | static void |
acdb74a0 | 4446 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4447 | { |
6d82d43b AC |
4448 | printf_unfiltered |
4449 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4450 | show_mipsfpu_command (args, from_tty); |
4451 | } | |
4452 | ||
c906108c | 4453 | static void |
acdb74a0 | 4454 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4455 | { |
8d5838b5 AC |
4456 | struct gdbarch_info info; |
4457 | gdbarch_info_init (&info); | |
c906108c SS |
4458 | mips_fpu_type = MIPS_FPU_SINGLE; |
4459 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4460 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4461 | instead of relying on globals. Doing that would let generic code | |
4462 | handle the search for this specific architecture. */ | |
4463 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4464 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4465 | } |
4466 | ||
c906108c | 4467 | static void |
acdb74a0 | 4468 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4469 | { |
8d5838b5 AC |
4470 | struct gdbarch_info info; |
4471 | gdbarch_info_init (&info); | |
c906108c SS |
4472 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4473 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4474 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4475 | instead of relying on globals. Doing that would let generic code | |
4476 | handle the search for this specific architecture. */ | |
4477 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4478 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4479 | } |
4480 | ||
c906108c | 4481 | static void |
acdb74a0 | 4482 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4483 | { |
8d5838b5 AC |
4484 | struct gdbarch_info info; |
4485 | gdbarch_info_init (&info); | |
c906108c SS |
4486 | mips_fpu_type = MIPS_FPU_NONE; |
4487 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4488 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4489 | instead of relying on globals. Doing that would let generic code | |
4490 | handle the search for this specific architecture. */ | |
4491 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4492 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4493 | } |
4494 | ||
c906108c | 4495 | static void |
acdb74a0 | 4496 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4497 | { |
4498 | mips_fpu_type_auto = 1; | |
4499 | } | |
4500 | ||
c906108c | 4501 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4502 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4503 | the relevant processor still exists (it dates back to '94) and | |
4504 | secondly this is not the way to do this. The processor type should | |
4505 | be set by forcing an architecture change. */ | |
c906108c | 4506 | |
691c0433 AC |
4507 | void |
4508 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4509 | { |
691c0433 | 4510 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
a9614958 | 4511 | ULONGEST prid; |
c906108c | 4512 | |
594f7785 | 4513 | regcache_cooked_read_unsigned (get_current_regcache (), |
a9614958 | 4514 | MIPS_PRID_REGNUM, &prid); |
c906108c | 4515 | if ((prid & ~0xf) == 0x700) |
691c0433 | 4516 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4517 | } |
4518 | ||
4519 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4520 | callable as an sfunc. */ | |
4521 | ||
4522 | static void | |
acdb74a0 AC |
4523 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4524 | struct cmd_list_element *c) | |
c906108c SS |
4525 | { |
4526 | reinit_frame_cache (); | |
4527 | } | |
4528 | ||
a89aa300 AC |
4529 | static int |
4530 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4531 | { |
e5ab0dce | 4532 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 4533 | |
d31431ed AC |
4534 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4535 | disassembler needs to be able to locally determine the ISA, and | |
4536 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4537 | work. */ | |
ec4045ea AC |
4538 | if (mips_pc_is_mips16 (memaddr)) |
4539 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4540 | |
4541 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4542 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4543 | |
e5ab0dce | 4544 | /* Set the disassembler options. */ |
6d82d43b | 4545 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
4546 | { |
4547 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 4548 | register names from libopcodes. */ |
e5ab0dce AC |
4549 | if (tdep->mips_abi == MIPS_ABI_N32) |
4550 | info->disassembler_options = "gpr-names=n32"; | |
4551 | else | |
4552 | info->disassembler_options = "gpr-names=64"; | |
4553 | info->flavour = bfd_target_elf_flavour; | |
4554 | } | |
4555 | else | |
4556 | /* This string is not recognized explicitly by the disassembler, | |
4557 | but it tells the disassembler to not try to guess the ABI from | |
4558 | the bfd elf headers, such that, if the user overrides the ABI | |
4559 | of a program linked as NewABI, the disassembly will follow the | |
4560 | register naming conventions specified by the user. */ | |
4561 | info->disassembler_options = "gpr-names=32"; | |
4562 | ||
c906108c | 4563 | /* Call the appropriate disassembler based on the target endian-ness. */ |
4c6b5505 | 4564 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c SS |
4565 | return print_insn_big_mips (memaddr, info); |
4566 | else | |
4567 | return print_insn_little_mips (memaddr, info); | |
4568 | } | |
4569 | ||
3b3b875c UW |
4570 | /* This function implements gdbarch_breakpoint_from_pc. It uses the program |
4571 | counter value to determine whether a 16- or 32-bit breakpoint should be used. | |
4572 | It returns a pointer to a string of bytes that encode a breakpoint | |
4573 | instruction, stores the length of the string to *lenptr, and adjusts pc (if | |
4574 | necessary) to point to the actual memory location where the breakpoint | |
4575 | should be inserted. */ | |
c906108c | 4576 | |
47a35522 | 4577 | static const gdb_byte * |
6d82d43b | 4578 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 4579 | { |
4c6b5505 | 4580 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 4581 | { |
0fe7e7c8 | 4582 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4583 | { |
47a35522 | 4584 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 4585 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4586 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
4587 | return mips16_big_breakpoint; |
4588 | } | |
4589 | else | |
4590 | { | |
aaab4dba AC |
4591 | /* The IDT board uses an unusual breakpoint value, and |
4592 | sometimes gets confused when it sees the usual MIPS | |
4593 | breakpoint instruction. */ | |
47a35522 MK |
4594 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
4595 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
4596 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 4597 | |
c5aa993b | 4598 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
4599 | |
4600 | if (strcmp (target_shortname, "mips") == 0) | |
4601 | return idt_big_breakpoint; | |
4602 | else if (strcmp (target_shortname, "ddb") == 0 | |
4603 | || strcmp (target_shortname, "pmon") == 0 | |
4604 | || strcmp (target_shortname, "lsi") == 0) | |
4605 | return pmon_big_breakpoint; | |
4606 | else | |
4607 | return big_breakpoint; | |
4608 | } | |
4609 | } | |
4610 | else | |
4611 | { | |
0fe7e7c8 | 4612 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4613 | { |
47a35522 | 4614 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 4615 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4616 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
4617 | return mips16_little_breakpoint; |
4618 | } | |
4619 | else | |
4620 | { | |
47a35522 MK |
4621 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
4622 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
4623 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 4624 | |
c5aa993b | 4625 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
4626 | |
4627 | if (strcmp (target_shortname, "mips") == 0) | |
4628 | return idt_little_breakpoint; | |
4629 | else if (strcmp (target_shortname, "ddb") == 0 | |
4630 | || strcmp (target_shortname, "pmon") == 0 | |
4631 | || strcmp (target_shortname, "lsi") == 0) | |
4632 | return pmon_little_breakpoint; | |
4633 | else | |
4634 | return little_breakpoint; | |
4635 | } | |
4636 | } | |
4637 | } | |
4638 | ||
4639 | /* If PC is in a mips16 call or return stub, return the address of the target | |
4640 | PC, which is either the callee or the caller. There are several | |
4641 | cases which must be handled: | |
4642 | ||
4643 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 4644 | target PC is in $31 ($ra). |
c906108c | 4645 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 4646 | and the target PC is in $2. |
c906108c | 4647 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
4648 | before the jal instruction, this is effectively a call stub |
4649 | and the the target PC is in $2. Otherwise this is effectively | |
4650 | a return stub and the target PC is in $18. | |
c906108c SS |
4651 | |
4652 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 4653 | gory details. */ |
c906108c | 4654 | |
757a7cc6 | 4655 | static CORE_ADDR |
52f729a7 | 4656 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c SS |
4657 | { |
4658 | char *name; | |
4659 | CORE_ADDR start_addr; | |
4660 | ||
4661 | /* Find the starting address and name of the function containing the PC. */ | |
4662 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
4663 | return 0; | |
4664 | ||
4665 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
4666 | target PC is in $31 ($ra). */ | |
4667 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4668 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 4669 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
4670 | |
4671 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4672 | { | |
4673 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
4674 | and the target PC is in $2. */ | |
4675 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 4676 | return get_frame_register_signed (frame, 2); |
c906108c SS |
4677 | |
4678 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
4679 | before the jal instruction, this is effectively a call stub |
4680 | and the the target PC is in $2. Otherwise this is effectively | |
4681 | a return stub and the target PC is in $18. */ | |
c906108c SS |
4682 | else if (name[19] == 's' || name[19] == 'd') |
4683 | { | |
4684 | if (pc == start_addr) | |
4685 | { | |
4686 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
4687 | stub. Such a stub for a function bar might have a name |
4688 | like __fn_stub_bar, and might look like this: | |
4689 | mfc1 $4,$f13 | |
4690 | mfc1 $5,$f12 | |
4691 | mfc1 $6,$f15 | |
4692 | mfc1 $7,$f14 | |
4693 | la $1,bar (becomes a lui/addiu pair) | |
4694 | jr $1 | |
4695 | So scan down to the lui/addi and extract the target | |
4696 | address from those two instructions. */ | |
c906108c | 4697 | |
52f729a7 | 4698 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
d37cca3d | 4699 | ULONGEST inst; |
c906108c SS |
4700 | int i; |
4701 | ||
4702 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
4703 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
4704 | 0) | |
c906108c SS |
4705 | return target_pc; |
4706 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
4707 | && strcmp (name, "etext") != 0 | |
4708 | && strcmp (name, "_etext") != 0) | |
4709 | return target_pc; | |
4710 | ||
4711 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
4712 | The limit on the search is arbitrarily set to 20 |
4713 | instructions. FIXME. */ | |
95ac2dcf | 4714 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 4715 | { |
c5aa993b JM |
4716 | inst = mips_fetch_instruction (target_pc); |
4717 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
4718 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
4719 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
4720 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
4721 | } |
4722 | ||
4723 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
4724 | return target_pc; | |
4725 | } | |
4726 | else | |
4727 | /* This is the 'return' part of a call stub. The return | |
4728 | address is in $r18. */ | |
52f729a7 | 4729 | return get_frame_register_signed (frame, 18); |
c906108c SS |
4730 | } |
4731 | } | |
c5aa993b | 4732 | return 0; /* not a stub */ |
c906108c SS |
4733 | } |
4734 | ||
a4b8ebc8 | 4735 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 4736 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
4737 | |
4738 | static int | |
4739 | mips_stab_reg_to_regnum (int num) | |
4740 | { | |
a4b8ebc8 | 4741 | int regnum; |
2f38ef89 | 4742 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4743 | regnum = num; |
2f38ef89 | 4744 | else if (num >= 38 && num < 70) |
56cea623 | 4745 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 4746 | else if (num == 70) |
56cea623 | 4747 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4748 | else if (num == 71) |
56cea623 | 4749 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4750 | else |
a4b8ebc8 AC |
4751 | /* This will hopefully (eventually) provoke a warning. Should |
4752 | we be calling complaint() here? */ | |
f57d151a UW |
4753 | return gdbarch_num_regs (current_gdbarch) |
4754 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4755 | return gdbarch_num_regs (current_gdbarch) + regnum; | |
88c72b7d AC |
4756 | } |
4757 | ||
2f38ef89 | 4758 | |
a4b8ebc8 | 4759 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 4760 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
4761 | |
4762 | static int | |
2f38ef89 | 4763 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 4764 | { |
a4b8ebc8 | 4765 | int regnum; |
2f38ef89 | 4766 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4767 | regnum = num; |
2f38ef89 | 4768 | else if (num >= 32 && num < 64) |
56cea623 | 4769 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 4770 | else if (num == 64) |
56cea623 | 4771 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4772 | else if (num == 65) |
56cea623 | 4773 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4774 | else |
a4b8ebc8 AC |
4775 | /* This will hopefully (eventually) provoke a warning. Should we |
4776 | be calling complaint() here? */ | |
f57d151a UW |
4777 | return gdbarch_num_regs (current_gdbarch) |
4778 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4779 | return gdbarch_num_regs (current_gdbarch) + regnum; | |
a4b8ebc8 AC |
4780 | } |
4781 | ||
4782 | static int | |
4783 | mips_register_sim_regno (int regnum) | |
4784 | { | |
4785 | /* Only makes sense to supply raw registers. */ | |
f57d151a | 4786 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)); |
a4b8ebc8 AC |
4787 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
4788 | decide if it is valid. Should instead define a standard sim/gdb | |
4789 | register numbering scheme. */ | |
c9f4d572 UW |
4790 | if (gdbarch_register_name (current_gdbarch, |
4791 | gdbarch_num_regs | |
4792 | (current_gdbarch) + regnum) != NULL | |
4793 | && gdbarch_register_name (current_gdbarch, | |
4794 | gdbarch_num_regs | |
4795 | (current_gdbarch) + regnum)[0] != '\0') | |
a4b8ebc8 AC |
4796 | return regnum; |
4797 | else | |
6d82d43b | 4798 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
4799 | } |
4800 | ||
2f38ef89 | 4801 | |
4844f454 CV |
4802 | /* Convert an integer into an address. Extracting the value signed |
4803 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
4804 | |
4805 | static CORE_ADDR | |
79dd2d24 | 4806 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 4807 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 4808 | { |
4844f454 | 4809 | return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type)); |
fc0c74b1 AC |
4810 | } |
4811 | ||
caaa3122 DJ |
4812 | static void |
4813 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
4814 | { | |
4815 | enum mips_abi *abip = (enum mips_abi *) obj; | |
4816 | const char *name = bfd_get_section_name (abfd, sect); | |
4817 | ||
4818 | if (*abip != MIPS_ABI_UNKNOWN) | |
4819 | return; | |
4820 | ||
4821 | if (strncmp (name, ".mdebug.", 8) != 0) | |
4822 | return; | |
4823 | ||
4824 | if (strcmp (name, ".mdebug.abi32") == 0) | |
4825 | *abip = MIPS_ABI_O32; | |
4826 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
4827 | *abip = MIPS_ABI_N32; | |
62a49b2c | 4828 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 4829 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
4830 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
4831 | *abip = MIPS_ABI_O64; | |
4832 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
4833 | *abip = MIPS_ABI_EABI32; | |
4834 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
4835 | *abip = MIPS_ABI_EABI64; | |
4836 | else | |
8a3fe4f8 | 4837 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
4838 | } |
4839 | ||
22e47e37 FF |
4840 | static void |
4841 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
4842 | { | |
4843 | int *lbp = (int *) obj; | |
4844 | const char *name = bfd_get_section_name (abfd, sect); | |
4845 | ||
4846 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
4847 | *lbp = 32; | |
4848 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
4849 | *lbp = 64; | |
4850 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
4851 | warning (_("unrecognized .gcc_compiled_longXX")); | |
4852 | } | |
4853 | ||
2e4ebe70 DJ |
4854 | static enum mips_abi |
4855 | global_mips_abi (void) | |
4856 | { | |
4857 | int i; | |
4858 | ||
4859 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
4860 | if (mips_abi_strings[i] == mips_abi_string) | |
4861 | return (enum mips_abi) i; | |
4862 | ||
e2e0b3e5 | 4863 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
4864 | } |
4865 | ||
29709017 DJ |
4866 | static void |
4867 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
4868 | { | |
4869 | static struct target_desc *tdesc_gp32, *tdesc_gp64; | |
4870 | ||
4871 | if (tdesc_gp32 == NULL) | |
4872 | { | |
4873 | /* Create feature sets with the appropriate properties. The values | |
4874 | are not important. */ | |
4875 | ||
4876 | tdesc_gp32 = allocate_target_description (); | |
4877 | set_tdesc_property (tdesc_gp32, PROPERTY_GP32, ""); | |
4878 | ||
4879 | tdesc_gp64 = allocate_target_description (); | |
4880 | set_tdesc_property (tdesc_gp64, PROPERTY_GP64, ""); | |
4881 | } | |
4882 | ||
4883 | /* If the size matches the set of 32-bit or 64-bit integer registers, | |
4884 | assume that's what we've got. */ | |
4885 | register_remote_g_packet_guess (gdbarch, 38 * 4, tdesc_gp32); | |
4886 | register_remote_g_packet_guess (gdbarch, 38 * 8, tdesc_gp64); | |
4887 | ||
4888 | /* If the size matches the full set of registers GDB traditionally | |
4889 | knows about, including floating point, for either 32-bit or | |
4890 | 64-bit, assume that's what we've got. */ | |
4891 | register_remote_g_packet_guess (gdbarch, 90 * 4, tdesc_gp32); | |
4892 | register_remote_g_packet_guess (gdbarch, 90 * 8, tdesc_gp64); | |
4893 | ||
4894 | /* Otherwise we don't have a useful guess. */ | |
4895 | } | |
4896 | ||
f8b73d13 DJ |
4897 | static struct value * |
4898 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
4899 | { | |
4900 | const int *reg_p = baton; | |
4901 | return value_of_register (*reg_p, frame); | |
4902 | } | |
4903 | ||
c2d11a7d | 4904 | static struct gdbarch * |
6d82d43b | 4905 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 4906 | { |
c2d11a7d JM |
4907 | struct gdbarch *gdbarch; |
4908 | struct gdbarch_tdep *tdep; | |
4909 | int elf_flags; | |
2e4ebe70 | 4910 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 4911 | int i, num_regs; |
8d5838b5 | 4912 | enum mips_fpu_type fpu_type; |
f8b73d13 | 4913 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 4914 | int elf_fpu_type = 0; |
f8b73d13 DJ |
4915 | |
4916 | /* Check any target description for validity. */ | |
4917 | if (tdesc_has_registers (info.target_desc)) | |
4918 | { | |
4919 | static const char *const mips_gprs[] = { | |
4920 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
4921 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
4922 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
4923 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
4924 | }; | |
4925 | static const char *const mips_fprs[] = { | |
4926 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
4927 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
4928 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
4929 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
4930 | }; | |
4931 | ||
4932 | const struct tdesc_feature *feature; | |
4933 | int valid_p; | |
4934 | ||
4935 | feature = tdesc_find_feature (info.target_desc, | |
4936 | "org.gnu.gdb.mips.cpu"); | |
4937 | if (feature == NULL) | |
4938 | return NULL; | |
4939 | ||
4940 | tdesc_data = tdesc_data_alloc (); | |
4941 | ||
4942 | valid_p = 1; | |
4943 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
4944 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
4945 | mips_gprs[i]); | |
4946 | ||
4947 | ||
4948 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4949 | MIPS_EMBED_LO_REGNUM, "lo"); | |
4950 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4951 | MIPS_EMBED_HI_REGNUM, "hi"); | |
4952 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4953 | MIPS_EMBED_PC_REGNUM, "pc"); | |
4954 | ||
4955 | if (!valid_p) | |
4956 | { | |
4957 | tdesc_data_cleanup (tdesc_data); | |
4958 | return NULL; | |
4959 | } | |
4960 | ||
4961 | feature = tdesc_find_feature (info.target_desc, | |
4962 | "org.gnu.gdb.mips.cp0"); | |
4963 | if (feature == NULL) | |
4964 | { | |
4965 | tdesc_data_cleanup (tdesc_data); | |
4966 | return NULL; | |
4967 | } | |
4968 | ||
4969 | valid_p = 1; | |
4970 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4971 | MIPS_EMBED_BADVADDR_REGNUM, | |
4972 | "badvaddr"); | |
4973 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4974 | MIPS_PS_REGNUM, "status"); | |
4975 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4976 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
4977 | ||
4978 | if (!valid_p) | |
4979 | { | |
4980 | tdesc_data_cleanup (tdesc_data); | |
4981 | return NULL; | |
4982 | } | |
4983 | ||
4984 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
4985 | backend is not prepared for that, though. */ | |
4986 | feature = tdesc_find_feature (info.target_desc, | |
4987 | "org.gnu.gdb.mips.fpu"); | |
4988 | if (feature == NULL) | |
4989 | { | |
4990 | tdesc_data_cleanup (tdesc_data); | |
4991 | return NULL; | |
4992 | } | |
4993 | ||
4994 | valid_p = 1; | |
4995 | for (i = 0; i < 32; i++) | |
4996 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
4997 | i + MIPS_EMBED_FP0_REGNUM, | |
4998 | mips_fprs[i]); | |
4999 | ||
5000 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5001 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
5002 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5003 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
5004 | ||
5005 | if (!valid_p) | |
5006 | { | |
5007 | tdesc_data_cleanup (tdesc_data); | |
5008 | return NULL; | |
5009 | } | |
5010 | ||
5011 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
5012 | when only 32-bit registers are provided. */ | |
5013 | } | |
c2d11a7d | 5014 | |
ec03c1ac AC |
5015 | /* First of all, extract the elf_flags, if available. */ |
5016 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5017 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5018 | else if (arches != NULL) |
5019 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5020 | else |
5021 | elf_flags = 0; | |
5022 | if (gdbarch_debug) | |
5023 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5024 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5025 | |
102182a9 | 5026 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5027 | switch ((elf_flags & EF_MIPS_ABI)) |
5028 | { | |
5029 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5030 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5031 | break; |
5032 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5033 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5034 | break; |
5035 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5036 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5037 | break; |
5038 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5039 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5040 | break; |
5041 | default: | |
acdb74a0 | 5042 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5043 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5044 | else |
ec03c1ac | 5045 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5046 | break; |
5047 | } | |
acdb74a0 | 5048 | |
caaa3122 | 5049 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5050 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5051 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5052 | |
dc305454 | 5053 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5054 | MIPS architecture (if there is one). */ |
5055 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5056 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5057 | |
32a6503c | 5058 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5059 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5060 | && info.bfd_arch_info != NULL |
5061 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5062 | { | |
5063 | switch (info.bfd_arch_info->mach) | |
5064 | { | |
5065 | case bfd_mach_mips3900: | |
ec03c1ac | 5066 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5067 | break; |
5068 | case bfd_mach_mips4100: | |
5069 | case bfd_mach_mips5000: | |
ec03c1ac | 5070 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5071 | break; |
1d06468c EZ |
5072 | case bfd_mach_mips8000: |
5073 | case bfd_mach_mips10000: | |
32a6503c KB |
5074 | /* On Irix, ELF64 executables use the N64 ABI. The |
5075 | pseudo-sections which describe the ABI aren't present | |
5076 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5077 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5078 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5079 | found_abi = MIPS_ABI_N64; |
28d169de | 5080 | else |
ec03c1ac | 5081 | found_abi = MIPS_ABI_N32; |
1d06468c | 5082 | break; |
bf64bfd6 AC |
5083 | } |
5084 | } | |
2e4ebe70 | 5085 | |
26c53e50 DJ |
5086 | /* Default 64-bit objects to N64 instead of O32. */ |
5087 | if (found_abi == MIPS_ABI_UNKNOWN | |
5088 | && info.abfd != NULL | |
5089 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5090 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5091 | found_abi = MIPS_ABI_N64; | |
5092 | ||
ec03c1ac AC |
5093 | if (gdbarch_debug) |
5094 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5095 | found_abi); | |
5096 | ||
5097 | /* What has the user specified from the command line? */ | |
5098 | wanted_abi = global_mips_abi (); | |
5099 | if (gdbarch_debug) | |
5100 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5101 | wanted_abi); | |
2e4ebe70 DJ |
5102 | |
5103 | /* Now that we have found what the ABI for this binary would be, | |
5104 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5105 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5106 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5107 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5108 | mips_abi = found_abi; | |
5109 | else | |
5110 | mips_abi = MIPS_ABI_O32; | |
5111 | if (gdbarch_debug) | |
5112 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5113 | mips_abi); | |
2e4ebe70 | 5114 | |
ec03c1ac | 5115 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5116 | if (gdbarch_debug) |
ec03c1ac AC |
5117 | fprintf_unfiltered (gdb_stdlog, |
5118 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5119 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5120 | |
8d5838b5 | 5121 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
5122 | #ifdef HAVE_ELF |
5123 | if (info.abfd | |
5124 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5125 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
5126 | Tag_GNU_MIPS_ABI_FP); | |
5127 | #endif /* HAVE_ELF */ | |
5128 | ||
8d5838b5 AC |
5129 | if (!mips_fpu_type_auto) |
5130 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
5131 | else if (elf_fpu_type != 0) |
5132 | { | |
5133 | switch (elf_fpu_type) | |
5134 | { | |
5135 | case 1: | |
5136 | fpu_type = MIPS_FPU_DOUBLE; | |
5137 | break; | |
5138 | case 2: | |
5139 | fpu_type = MIPS_FPU_SINGLE; | |
5140 | break; | |
5141 | case 3: | |
5142 | default: | |
5143 | /* Soft float or unknown. */ | |
5144 | fpu_type = MIPS_FPU_NONE; | |
5145 | break; | |
5146 | } | |
5147 | } | |
8d5838b5 AC |
5148 | else if (info.bfd_arch_info != NULL |
5149 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5150 | switch (info.bfd_arch_info->mach) | |
5151 | { | |
5152 | case bfd_mach_mips3900: | |
5153 | case bfd_mach_mips4100: | |
5154 | case bfd_mach_mips4111: | |
a9d61c86 | 5155 | case bfd_mach_mips4120: |
8d5838b5 AC |
5156 | fpu_type = MIPS_FPU_NONE; |
5157 | break; | |
5158 | case bfd_mach_mips4650: | |
5159 | fpu_type = MIPS_FPU_SINGLE; | |
5160 | break; | |
5161 | default: | |
5162 | fpu_type = MIPS_FPU_DOUBLE; | |
5163 | break; | |
5164 | } | |
5165 | else if (arches != NULL) | |
5166 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5167 | else | |
5168 | fpu_type = MIPS_FPU_DOUBLE; | |
5169 | if (gdbarch_debug) | |
5170 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5171 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5172 | |
29709017 DJ |
5173 | /* Check for blatant incompatibilities. */ |
5174 | ||
5175 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5176 | ABI. */ | |
5177 | if (info.target_desc | |
5178 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5179 | && mips_abi != MIPS_ABI_EABI32 | |
5180 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5181 | { |
5182 | if (tdesc_data != NULL) | |
5183 | tdesc_data_cleanup (tdesc_data); | |
5184 | return NULL; | |
5185 | } | |
29709017 | 5186 | |
c2d11a7d JM |
5187 | /* try to find a pre-existing architecture */ |
5188 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5189 | arches != NULL; | |
5190 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5191 | { | |
5192 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5193 | using. */ |
9103eae0 | 5194 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5195 | continue; |
9103eae0 | 5196 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5197 | continue; |
719ec221 AC |
5198 | /* Need to be pedantic about which register virtual size is |
5199 | used. */ | |
5200 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5201 | != mips64_transfers_32bit_regs_p) | |
5202 | continue; | |
8d5838b5 AC |
5203 | /* Be pedantic about which FPU is selected. */ |
5204 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5205 | continue; | |
f8b73d13 DJ |
5206 | |
5207 | if (tdesc_data != NULL) | |
5208 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5209 | return arches->gdbarch; |
c2d11a7d JM |
5210 | } |
5211 | ||
102182a9 | 5212 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5213 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5214 | gdbarch = gdbarch_alloc (&info, tdep); | |
5215 | tdep->elf_flags = elf_flags; | |
719ec221 | 5216 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5217 | tdep->found_abi = found_abi; |
5218 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5219 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5220 | tdep->register_size_valid_p = 0; |
5221 | tdep->register_size = 0; | |
5222 | ||
5223 | if (info.target_desc) | |
5224 | { | |
5225 | /* Some useful properties can be inferred from the target. */ | |
5226 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5227 | { | |
5228 | tdep->register_size_valid_p = 1; | |
5229 | tdep->register_size = 4; | |
5230 | } | |
5231 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5232 | { | |
5233 | tdep->register_size_valid_p = 1; | |
5234 | tdep->register_size = 8; | |
5235 | } | |
5236 | } | |
c2d11a7d | 5237 | |
102182a9 | 5238 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5239 | set_gdbarch_short_bit (gdbarch, 16); |
5240 | set_gdbarch_int_bit (gdbarch, 32); | |
5241 | set_gdbarch_float_bit (gdbarch, 32); | |
5242 | set_gdbarch_double_bit (gdbarch, 64); | |
5243 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5244 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5245 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5246 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5247 | |
6d82d43b | 5248 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5249 | mips_elf_make_msymbol_special); |
5250 | ||
16e109ca | 5251 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5252 | { |
16e109ca | 5253 | const char **reg_names; |
56cea623 AC |
5254 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5255 | struct mips_regnum); | |
f8b73d13 DJ |
5256 | if (tdesc_has_registers (info.target_desc)) |
5257 | { | |
5258 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5259 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5260 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5261 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5262 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5263 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5264 | regnum->fp_control_status = 70; | |
5265 | regnum->fp_implementation_revision = 71; | |
5266 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
5267 | reg_names = NULL; | |
5268 | } | |
5269 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
5270 | { |
5271 | regnum->fp0 = 32; | |
5272 | regnum->pc = 64; | |
5273 | regnum->cause = 65; | |
5274 | regnum->badvaddr = 66; | |
5275 | regnum->hi = 67; | |
5276 | regnum->lo = 68; | |
5277 | regnum->fp_control_status = 69; | |
5278 | regnum->fp_implementation_revision = 70; | |
5279 | num_regs = 71; | |
16e109ca | 5280 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5281 | } |
5282 | else | |
5283 | { | |
5284 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5285 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5286 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5287 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5288 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5289 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5290 | regnum->fp_control_status = 70; | |
5291 | regnum->fp_implementation_revision = 71; | |
5292 | num_regs = 90; | |
16e109ca AC |
5293 | if (info.bfd_arch_info != NULL |
5294 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5295 | reg_names = mips_tx39_reg_names; | |
5296 | else | |
5297 | reg_names = mips_generic_reg_names; | |
56cea623 | 5298 | } |
3e8c568d | 5299 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
56cea623 | 5300 | replaced by read_pc? */ |
f10683bb MH |
5301 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5302 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5303 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5304 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5305 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
5306 | set_gdbarch_register_name (gdbarch, mips_register_name); |
5307 | tdep->mips_processor_reg_names = reg_names; | |
5308 | tdep->regnum = regnum; | |
56cea623 | 5309 | } |
fe29b929 | 5310 | |
0dadbba0 | 5311 | switch (mips_abi) |
c2d11a7d | 5312 | { |
0dadbba0 | 5313 | case MIPS_ABI_O32: |
25ab4790 | 5314 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5315 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5316 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5317 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5318 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5319 | set_gdbarch_long_bit (gdbarch, 32); |
5320 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5321 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5322 | break; | |
0dadbba0 | 5323 | case MIPS_ABI_O64: |
25ab4790 | 5324 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5325 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5326 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5327 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5328 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5329 | set_gdbarch_long_bit (gdbarch, 32); |
5330 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5331 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5332 | break; | |
0dadbba0 | 5333 | case MIPS_ABI_EABI32: |
25ab4790 | 5334 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5335 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5336 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5337 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5338 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5339 | set_gdbarch_long_bit (gdbarch, 32); |
5340 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5341 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5342 | break; | |
0dadbba0 | 5343 | case MIPS_ABI_EABI64: |
25ab4790 | 5344 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5345 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5346 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5347 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5348 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5349 | set_gdbarch_long_bit (gdbarch, 64); |
5350 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5351 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5352 | break; | |
0dadbba0 | 5353 | case MIPS_ABI_N32: |
25ab4790 | 5354 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5355 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5356 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5357 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5358 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5359 | set_gdbarch_long_bit (gdbarch, 32); |
5360 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5361 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5362 | set_gdbarch_long_double_bit (gdbarch, 128); |
8da61cc4 | 5363 | set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long); |
28d169de KB |
5364 | break; |
5365 | case MIPS_ABI_N64: | |
25ab4790 | 5366 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5367 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5368 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5369 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5370 | tdep->default_mask_address_p = 0; |
5371 | set_gdbarch_long_bit (gdbarch, 64); | |
5372 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5373 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5374 | set_gdbarch_long_double_bit (gdbarch, 128); |
8da61cc4 | 5375 | set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long); |
0dadbba0 | 5376 | break; |
c2d11a7d | 5377 | default: |
e2e0b3e5 | 5378 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
5379 | } |
5380 | ||
22e47e37 FF |
5381 | /* GCC creates a pseudo-section whose name specifies the size of |
5382 | longs, since -mlong32 or -mlong64 may be used independent of | |
5383 | other options. How those options affect pointer sizes is ABI and | |
5384 | architecture dependent, so use them to override the default sizes | |
5385 | set by the ABI. This table shows the relationship between ABI, | |
5386 | -mlongXX, and size of pointers: | |
5387 | ||
5388 | ABI -mlongXX ptr bits | |
5389 | --- -------- -------- | |
5390 | o32 32 32 | |
5391 | o32 64 32 | |
5392 | n32 32 32 | |
5393 | n32 64 64 | |
5394 | o64 32 32 | |
5395 | o64 64 64 | |
5396 | n64 32 32 | |
5397 | n64 64 64 | |
5398 | eabi32 32 32 | |
5399 | eabi32 64 32 | |
5400 | eabi64 32 32 | |
5401 | eabi64 64 64 | |
5402 | ||
5403 | Note that for o32 and eabi32, pointers are always 32 bits | |
5404 | regardless of any -mlongXX option. For all others, pointers and | |
5405 | longs are the same, as set by -mlongXX or set by defaults. | |
5406 | */ | |
5407 | ||
5408 | if (info.abfd != NULL) | |
5409 | { | |
5410 | int long_bit = 0; | |
5411 | ||
5412 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
5413 | if (long_bit) | |
5414 | { | |
5415 | set_gdbarch_long_bit (gdbarch, long_bit); | |
5416 | switch (mips_abi) | |
5417 | { | |
5418 | case MIPS_ABI_O32: | |
5419 | case MIPS_ABI_EABI32: | |
5420 | break; | |
5421 | case MIPS_ABI_N32: | |
5422 | case MIPS_ABI_O64: | |
5423 | case MIPS_ABI_N64: | |
5424 | case MIPS_ABI_EABI64: | |
5425 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
5426 | break; | |
5427 | default: | |
5428 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
5429 | } | |
5430 | } | |
5431 | } | |
5432 | ||
a5ea2558 AC |
5433 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5434 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5435 | comment: | |
5436 | ||
5437 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5438 | flag in object files because to do so would make it impossible to | |
102182a9 | 5439 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5440 | unnecessarily restrictive. |
361d1df0 | 5441 | |
a5ea2558 AC |
5442 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5443 | but to set this flag before gcc is built with such multilibs will | |
5444 | break too many systems.'' | |
5445 | ||
5446 | But even more unhelpfully, the default linker output target for | |
5447 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5448 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5449 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5450 | this flag to detect 32-bit mode would do the wrong thing given |
5451 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5452 | as 32-bit programs by default. */ |
a5ea2558 | 5453 | |
6c997a34 | 5454 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5455 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 5456 | |
102182a9 MS |
5457 | /* Add/remove bits from an address. The MIPS needs be careful to |
5458 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5459 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5460 | ||
58dfe9ff AC |
5461 | /* Unwind the frame. */ |
5462 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 5463 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
edfae063 | 5464 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 5465 | |
102182a9 | 5466 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5467 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5468 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5469 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5470 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5471 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5472 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5473 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5474 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5475 | |
c2d11a7d JM |
5476 | /* MIPS version of CALL_DUMMY */ |
5477 | ||
9710e734 AC |
5478 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5479 | replaced by a command, and all targets will default to on stack | |
5480 | (regardless of the stack's execute status). */ | |
5481 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5482 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5483 | |
87783b8b AC |
5484 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5485 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5486 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5487 | ||
f7b9e9fc AC |
5488 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5489 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5490 | |
5491 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5492 | |
fc0c74b1 AC |
5493 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5494 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5495 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5496 | |
a4b8ebc8 | 5497 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5498 | |
e11c53d2 | 5499 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5500 | |
e5ab0dce AC |
5501 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
5502 | ||
3a3bc038 AC |
5503 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5504 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5505 | need to all be folded into the target vector. Since they are | |
5506 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5507 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5508 | is sitting on? */ | |
5509 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5510 | ||
e7d6a6d2 | 5511 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 5512 | |
3352ef37 AC |
5513 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
5514 | ||
0d5de010 DJ |
5515 | /* Virtual tables. */ |
5516 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
5517 | ||
29709017 DJ |
5518 | mips_register_g_packet_guesses (gdbarch); |
5519 | ||
6de918a6 | 5520 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 5521 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 5522 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 5523 | |
5792a79b | 5524 | /* Unwind the frame. */ |
2bd0c3d7 | 5525 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eec63939 | 5526 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
45c9dd44 AC |
5527 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
5528 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
2bd0c3d7 | 5529 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 5530 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
5531 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
5532 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 5533 | |
f8b73d13 DJ |
5534 | if (tdesc_data) |
5535 | { | |
5536 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
5537 | tdesc_use_registers (gdbarch, tdesc_data); | |
5538 | ||
5539 | /* Override the normal target description methods to handle our | |
5540 | dual real and pseudo registers. */ | |
5541 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
5542 | set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p); | |
5543 | ||
5544 | num_regs = gdbarch_num_regs (gdbarch); | |
5545 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
5546 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
5547 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
5548 | } | |
5549 | ||
5550 | /* Add ABI-specific aliases for the registers. */ | |
5551 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
5552 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
5553 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
5554 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
5555 | else | |
5556 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
5557 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
5558 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
5559 | ||
5560 | /* Add some other standard aliases. */ | |
5561 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
5562 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
5563 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
5564 | ||
4b9b3959 AC |
5565 | return gdbarch; |
5566 | } | |
5567 | ||
2e4ebe70 | 5568 | static void |
6d82d43b | 5569 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5570 | { |
5571 | struct gdbarch_info info; | |
5572 | ||
5573 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5574 | mips_gdbarch_init will take care of the rest. */ | |
5575 | gdbarch_info_init (&info); | |
5576 | gdbarch_update_p (info); | |
5577 | } | |
5578 | ||
ad188201 KB |
5579 | /* Print out which MIPS ABI is in use. */ |
5580 | ||
5581 | static void | |
1f8ca57c JB |
5582 | show_mips_abi (struct ui_file *file, |
5583 | int from_tty, | |
5584 | struct cmd_list_element *ignored_cmd, | |
5585 | const char *ignored_value) | |
ad188201 KB |
5586 | { |
5587 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
1f8ca57c JB |
5588 | fprintf_filtered |
5589 | (file, | |
5590 | "The MIPS ABI is unknown because the current architecture " | |
5591 | "is not MIPS.\n"); | |
ad188201 KB |
5592 | else |
5593 | { | |
5594 | enum mips_abi global_abi = global_mips_abi (); | |
5595 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
5596 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
5597 | ||
5598 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
5599 | fprintf_filtered |
5600 | (file, | |
5601 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 5602 | actual_abi_str); |
ad188201 | 5603 | else if (global_abi == actual_abi) |
1f8ca57c JB |
5604 | fprintf_filtered |
5605 | (file, | |
5606 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 5607 | actual_abi_str); |
ad188201 KB |
5608 | else |
5609 | { | |
5610 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
5611 | fprintf_filtered |
5612 | (file, | |
5613 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 5614 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
5615 | } |
5616 | } | |
5617 | } | |
5618 | ||
4b9b3959 AC |
5619 | static void |
5620 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
5621 | { | |
5622 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
5623 | if (tdep != NULL) | |
c2d11a7d | 5624 | { |
acdb74a0 AC |
5625 | int ef_mips_arch; |
5626 | int ef_mips_32bitmode; | |
f49e4e6d | 5627 | /* Determine the ISA. */ |
acdb74a0 AC |
5628 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
5629 | { | |
5630 | case E_MIPS_ARCH_1: | |
5631 | ef_mips_arch = 1; | |
5632 | break; | |
5633 | case E_MIPS_ARCH_2: | |
5634 | ef_mips_arch = 2; | |
5635 | break; | |
5636 | case E_MIPS_ARCH_3: | |
5637 | ef_mips_arch = 3; | |
5638 | break; | |
5639 | case E_MIPS_ARCH_4: | |
93d56215 | 5640 | ef_mips_arch = 4; |
acdb74a0 AC |
5641 | break; |
5642 | default: | |
93d56215 | 5643 | ef_mips_arch = 0; |
acdb74a0 AC |
5644 | break; |
5645 | } | |
f49e4e6d | 5646 | /* Determine the size of a pointer. */ |
acdb74a0 | 5647 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
5648 | fprintf_unfiltered (file, |
5649 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5650 | tdep->elf_flags); |
4b9b3959 | 5651 | fprintf_unfiltered (file, |
acdb74a0 AC |
5652 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5653 | ef_mips_32bitmode); | |
5654 | fprintf_unfiltered (file, | |
5655 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5656 | ef_mips_arch); | |
5657 | fprintf_unfiltered (file, | |
5658 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 5659 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5660 | fprintf_unfiltered (file, |
5661 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 5662 | mips_mask_address_p (tdep), |
4014092b | 5663 | tdep->default_mask_address_p); |
c2d11a7d | 5664 | } |
4b9b3959 AC |
5665 | fprintf_unfiltered (file, |
5666 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5667 | MIPS_DEFAULT_FPU_TYPE, | |
5668 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5669 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5670 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5671 | : "???")); | |
6d82d43b | 5672 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
5673 | fprintf_unfiltered (file, |
5674 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5675 | MIPS_FPU_TYPE, | |
5676 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5677 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5678 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5679 | : "???")); | |
c2d11a7d JM |
5680 | } |
5681 | ||
6d82d43b | 5682 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 5683 | |
c906108c | 5684 | void |
acdb74a0 | 5685 | _initialize_mips_tdep (void) |
c906108c SS |
5686 | { |
5687 | static struct cmd_list_element *mipsfpulist = NULL; | |
5688 | struct cmd_list_element *c; | |
5689 | ||
6d82d43b | 5690 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
5691 | if (MIPS_ABI_LAST + 1 |
5692 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 5693 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 5694 | |
4b9b3959 | 5695 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 5696 | |
8d5f9dcb DJ |
5697 | mips_pdr_data = register_objfile_data (); |
5698 | ||
a5ea2558 AC |
5699 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
5700 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 5701 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5702 | &setmipscmdlist, "set mips ", 0, &setlist); |
5703 | ||
5704 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 5705 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5706 | &showmipscmdlist, "show mips ", 0, &showlist); |
5707 | ||
2e4ebe70 | 5708 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
5709 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
5710 | &mips_abi_string, _("\ | |
5711 | Set the MIPS ABI used by this program."), _("\ | |
5712 | Show the MIPS ABI used by this program."), _("\ | |
5713 | This option can be set to one of:\n\ | |
5714 | auto - the default ABI associated with the current binary\n\ | |
5715 | o32\n\ | |
5716 | o64\n\ | |
5717 | n32\n\ | |
5718 | n64\n\ | |
5719 | eabi32\n\ | |
5720 | eabi64"), | |
5721 | mips_abi_update, | |
5722 | show_mips_abi, | |
5723 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 5724 | |
c906108c SS |
5725 | /* Let the user turn off floating point and set the fence post for |
5726 | heuristic_proc_start. */ | |
5727 | ||
5728 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 5729 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
5730 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
5731 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 5732 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
5733 | &mipsfpulist); |
5734 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 5735 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
5736 | &mipsfpulist); |
5737 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
5738 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
5739 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
5740 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 5741 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
5742 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
5743 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
5744 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
5745 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 5746 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
5747 | &mipsfpulist); |
5748 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 5749 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
5750 | &showlist); |
5751 | ||
c906108c SS |
5752 | /* We really would like to have both "0" and "unlimited" work, but |
5753 | command.c doesn't deal with that. So make it a var_zinteger | |
5754 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 5755 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
5756 | &heuristic_fence_post, _("\ |
5757 | Set the distance searched for the start of a function."), _("\ | |
5758 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
5759 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
5760 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 5761 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 5762 | reinit_frame_cache_sfunc, |
7915a72c | 5763 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 5764 | &setlist, &showlist); |
c906108c SS |
5765 | |
5766 | /* Allow the user to control whether the upper bits of 64-bit | |
5767 | addresses should be zeroed. */ | |
7915a72c AC |
5768 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
5769 | &mask_address_var, _("\ | |
5770 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
5771 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
e9e68a56 | 5772 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
7915a72c | 5773 | allow GDB to determine the correct value."), |
08546159 AC |
5774 | NULL, show_mask_address, |
5775 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
5776 | |
5777 | /* Allow the user to control the size of 32 bit registers within the | |
5778 | raw remote packet. */ | |
b3f42336 | 5779 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
5780 | &mips64_transfers_32bit_regs_p, _("\ |
5781 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5782 | _("\ | |
5783 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5784 | _("\ | |
719ec221 AC |
5785 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
5786 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 5787 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 5788 | set_mips64_transfers_32bit_regs, |
7915a72c | 5789 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 5790 | &setlist, &showlist); |
9ace0497 AC |
5791 | |
5792 | /* Debug this files internals. */ | |
6bcadd06 | 5793 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
5794 | &mips_debug, _("\ |
5795 | Set mips debugging."), _("\ | |
5796 | Show mips debugging."), _("\ | |
5797 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 5798 | NULL, |
7915a72c | 5799 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 5800 | &setdebuglist, &showdebuglist); |
c906108c | 5801 | } |