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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
cda5a58a | 3 | Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, |
16e109ca AC |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software |
5 | Foundation, Inc. | |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b JM |
22 | You should have received a copy of the GNU General Public License |
23 | along with this program; if not, write to the Free Software | |
24 | Foundation, Inc., 59 Temple Place - Suite 330, | |
25 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
26 | |
27 | #include "defs.h" | |
28 | #include "gdb_string.h" | |
5e2e9765 | 29 | #include "gdb_assert.h" |
c906108c SS |
30 | #include "frame.h" |
31 | #include "inferior.h" | |
32 | #include "symtab.h" | |
33 | #include "value.h" | |
34 | #include "gdbcmd.h" | |
35 | #include "language.h" | |
36 | #include "gdbcore.h" | |
37 | #include "symfile.h" | |
38 | #include "objfiles.h" | |
39 | #include "gdbtypes.h" | |
40 | #include "target.h" | |
28d069e6 | 41 | #include "arch-utils.h" |
4e052eda | 42 | #include "regcache.h" |
70f80edf | 43 | #include "osabi.h" |
d1973055 | 44 | #include "mips-tdep.h" |
fe898f56 | 45 | #include "block.h" |
a4b8ebc8 | 46 | #include "reggroups.h" |
c906108c | 47 | #include "opcode/mips.h" |
c2d11a7d JM |
48 | #include "elf/mips.h" |
49 | #include "elf-bfd.h" | |
2475bac3 | 50 | #include "symcat.h" |
a4b8ebc8 | 51 | #include "sim-regno.h" |
a89aa300 | 52 | #include "dis-asm.h" |
edfae063 AC |
53 | #include "frame-unwind.h" |
54 | #include "frame-base.h" | |
55 | #include "trad-frame.h" | |
7d9b040b | 56 | #include "infcall.h" |
fed7ba43 | 57 | #include "floatformat.h" |
c906108c | 58 | |
8d5f9dcb DJ |
59 | static const struct objfile_data *mips_pdr_data; |
60 | ||
5bbcb741 | 61 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 62 | |
dd824b04 DJ |
63 | /* A useful bit in the CP0 status register (PS_REGNUM). */ |
64 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | |
65 | #define ST0_FR (1 << 26) | |
66 | ||
b0069a17 AC |
67 | /* The sizes of floating point registers. */ |
68 | ||
69 | enum | |
70 | { | |
71 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
72 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
73 | }; | |
74 | ||
0dadbba0 | 75 | |
2e4ebe70 DJ |
76 | static const char *mips_abi_string; |
77 | ||
78 | static const char *mips_abi_strings[] = { | |
79 | "auto", | |
80 | "n32", | |
81 | "o32", | |
28d169de | 82 | "n64", |
2e4ebe70 DJ |
83 | "o64", |
84 | "eabi32", | |
85 | "eabi64", | |
86 | NULL | |
87 | }; | |
88 | ||
cce74817 | 89 | struct frame_extra_info |
6d82d43b AC |
90 | { |
91 | mips_extra_func_info_t proc_desc; | |
92 | int num_args; | |
93 | }; | |
cce74817 | 94 | |
d929b26f AC |
95 | /* Various MIPS ISA options (related to stack analysis) can be |
96 | overridden dynamically. Establish an enum/array for managing | |
97 | them. */ | |
98 | ||
53904c9e AC |
99 | static const char size_auto[] = "auto"; |
100 | static const char size_32[] = "32"; | |
101 | static const char size_64[] = "64"; | |
d929b26f | 102 | |
53904c9e | 103 | static const char *size_enums[] = { |
d929b26f AC |
104 | size_auto, |
105 | size_32, | |
106 | size_64, | |
a5ea2558 AC |
107 | 0 |
108 | }; | |
109 | ||
7a292a7a | 110 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 111 | support single-precision floating-point operations. */ |
c906108c SS |
112 | |
113 | enum mips_fpu_type | |
6d82d43b AC |
114 | { |
115 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
116 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
117 | MIPS_FPU_NONE /* No floating point. */ | |
118 | }; | |
c906108c SS |
119 | |
120 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
121 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
122 | #endif | |
123 | static int mips_fpu_type_auto = 1; | |
124 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 125 | |
9ace0497 | 126 | static int mips_debug = 0; |
7a292a7a | 127 | |
c2d11a7d JM |
128 | /* MIPS specific per-architecture information */ |
129 | struct gdbarch_tdep | |
6d82d43b AC |
130 | { |
131 | /* from the elf header */ | |
132 | int elf_flags; | |
133 | ||
134 | /* mips options */ | |
135 | enum mips_abi mips_abi; | |
136 | enum mips_abi found_abi; | |
137 | enum mips_fpu_type mips_fpu_type; | |
138 | int mips_last_arg_regnum; | |
139 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
140 | int default_mask_address_p; |
141 | /* Is the target using 64-bit raw integer registers but only | |
142 | storing a left-aligned 32-bit value in each? */ | |
143 | int mips64_transfers_32bit_regs_p; | |
144 | /* Indexes for various registers. IRIX and embedded have | |
145 | different values. This contains the "public" fields. Don't | |
146 | add any that do not need to be public. */ | |
147 | const struct mips_regnum *regnum; | |
148 | /* Register names table for the current register set. */ | |
149 | const char **mips_processor_reg_names; | |
150 | }; | |
c2d11a7d | 151 | |
fed7ba43 JB |
152 | static int |
153 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
154 | const char *from) | |
155 | { | |
156 | return 1; | |
157 | } | |
158 | ||
159 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
160 | They are implemented as a pair of 64bit doubles where the high | |
161 | part holds the result of the operation rounded to double, and | |
162 | the low double holds the difference between the exact result and | |
163 | the rounded result. So "high" + "low" contains the result with | |
164 | added precision. Unfortunately, the floatformat structure used | |
165 | by GDB is not powerful enough to describe this format. As a temporary | |
166 | measure, we define a 128bit floatformat that only uses the high part. | |
167 | We lose a bit of precision but that's probably the best we can do | |
168 | for now with the current infrastructure. */ | |
169 | ||
170 | static const struct floatformat floatformat_n32n64_long_double_big = | |
171 | { | |
172 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
173 | floatformat_intbit_no, | |
174 | "floatformat_ieee_double_big", | |
175 | n32n64_floatformat_always_valid | |
176 | }; | |
177 | ||
56cea623 AC |
178 | const struct mips_regnum * |
179 | mips_regnum (struct gdbarch *gdbarch) | |
180 | { | |
181 | return gdbarch_tdep (gdbarch)->regnum; | |
182 | } | |
183 | ||
184 | static int | |
185 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
186 | { | |
187 | return mips_regnum (gdbarch)->fp0 + 12; | |
188 | } | |
189 | ||
0dadbba0 | 190 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 191 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 192 | |
c2d11a7d | 193 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 194 | |
c2d11a7d | 195 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 196 | |
c2d11a7d | 197 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 198 | |
95404a3e AC |
199 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
200 | functions to test, set, or clear bit 0 of addresses. */ | |
201 | ||
202 | static CORE_ADDR | |
203 | is_mips16_addr (CORE_ADDR addr) | |
204 | { | |
205 | return ((addr) & 1); | |
206 | } | |
207 | ||
95404a3e AC |
208 | static CORE_ADDR |
209 | unmake_mips16_addr (CORE_ADDR addr) | |
210 | { | |
211 | return ((addr) & ~1); | |
212 | } | |
213 | ||
22540ece AC |
214 | /* Return the contents of register REGNUM as a signed integer. */ |
215 | ||
216 | static LONGEST | |
217 | read_signed_register (int regnum) | |
218 | { | |
1d93fe1a AC |
219 | LONGEST val; |
220 | regcache_cooked_read_signed (current_regcache, regnum, &val); | |
221 | return val; | |
22540ece AC |
222 | } |
223 | ||
224 | static LONGEST | |
225 | read_signed_register_pid (int regnum, ptid_t ptid) | |
226 | { | |
227 | ptid_t save_ptid; | |
228 | LONGEST retval; | |
229 | ||
230 | if (ptid_equal (ptid, inferior_ptid)) | |
231 | return read_signed_register (regnum); | |
232 | ||
233 | save_ptid = inferior_ptid; | |
234 | ||
235 | inferior_ptid = ptid; | |
236 | ||
237 | retval = read_signed_register (regnum); | |
238 | ||
239 | inferior_ptid = save_ptid; | |
240 | ||
241 | return retval; | |
242 | } | |
243 | ||
d1973055 KB |
244 | /* Return the MIPS ABI associated with GDBARCH. */ |
245 | enum mips_abi | |
246 | mips_abi (struct gdbarch *gdbarch) | |
247 | { | |
248 | return gdbarch_tdep (gdbarch)->mips_abi; | |
249 | } | |
250 | ||
4246e332 | 251 | int |
1b13c4f6 | 252 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 AC |
253 | { |
254 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word | |
255 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
256 | } | |
257 | ||
480d3dd2 AC |
258 | /* Return the currently configured (or set) saved register size. */ |
259 | ||
1b13c4f6 | 260 | static const char *mips_abi_regsize_string = size_auto; |
480d3dd2 | 261 | |
e6bc2e8a | 262 | unsigned int |
13326b4e | 263 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 264 | { |
1b13c4f6 | 265 | if (mips_abi_regsize_string == size_auto) |
13326b4e AC |
266 | switch (mips_abi (gdbarch)) |
267 | { | |
268 | case MIPS_ABI_EABI32: | |
269 | case MIPS_ABI_O32: | |
270 | return 4; | |
271 | case MIPS_ABI_N32: | |
272 | case MIPS_ABI_N64: | |
273 | case MIPS_ABI_O64: | |
274 | case MIPS_ABI_EABI64: | |
275 | return 8; | |
276 | case MIPS_ABI_UNKNOWN: | |
277 | case MIPS_ABI_LAST: | |
278 | default: | |
279 | internal_error (__FILE__, __LINE__, "bad switch"); | |
280 | } | |
1b13c4f6 | 281 | else if (mips_abi_regsize_string == size_64) |
d929b26f | 282 | return 8; |
1b13c4f6 | 283 | else /* if (mips_abi_regsize_string == size_32) */ |
d929b26f AC |
284 | return 4; |
285 | } | |
286 | ||
71b8ef93 | 287 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 288 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 289 | "info" field is used for this purpose. |
5a89d8aa MS |
290 | |
291 | ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special", | |
292 | i.e. refers to a 16-bit function, and sets a "special" bit in a | |
293 | minimal symbol to mark it as a 16-bit function | |
294 | ||
f594e5e9 | 295 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 296 | |
5a89d8aa | 297 | static void |
6d82d43b AC |
298 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
299 | { | |
300 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
301 | { | |
302 | MSYMBOL_INFO (msym) = (char *) | |
303 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
304 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
305 | } | |
5a89d8aa MS |
306 | } |
307 | ||
71b8ef93 MS |
308 | static int |
309 | msymbol_is_special (struct minimal_symbol *msym) | |
310 | { | |
311 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
312 | } | |
313 | ||
88658117 AC |
314 | /* XFER a value from the big/little/left end of the register. |
315 | Depending on the size of the value it might occupy the entire | |
316 | register or just part of it. Make an allowance for this, aligning | |
317 | things accordingly. */ | |
318 | ||
319 | static void | |
320 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
6d82d43b AC |
321 | enum bfd_endian endian, bfd_byte * in, |
322 | const bfd_byte * out, int buf_offset) | |
88658117 | 323 | { |
88658117 | 324 | int reg_offset = 0; |
a4b8ebc8 | 325 | gdb_assert (reg_num >= NUM_REGS); |
cb1d2653 AC |
326 | /* Need to transfer the left or right part of the register, based on |
327 | the targets byte order. */ | |
88658117 AC |
328 | switch (endian) |
329 | { | |
330 | case BFD_ENDIAN_BIG: | |
719ec221 | 331 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
332 | break; |
333 | case BFD_ENDIAN_LITTLE: | |
334 | reg_offset = 0; | |
335 | break; | |
6d82d43b | 336 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
337 | reg_offset = 0; |
338 | break; | |
339 | default: | |
340 | internal_error (__FILE__, __LINE__, "bad switch"); | |
341 | } | |
342 | if (mips_debug) | |
cb1d2653 AC |
343 | fprintf_unfiltered (gdb_stderr, |
344 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
345 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
346 | if (mips_debug && out != NULL) |
347 | { | |
348 | int i; | |
cb1d2653 | 349 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 350 | for (i = 0; i < length; i++) |
cb1d2653 | 351 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
352 | } |
353 | if (in != NULL) | |
6d82d43b AC |
354 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
355 | in + buf_offset); | |
88658117 | 356 | if (out != NULL) |
6d82d43b AC |
357 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
358 | out + buf_offset); | |
88658117 AC |
359 | if (mips_debug && in != NULL) |
360 | { | |
361 | int i; | |
cb1d2653 | 362 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 363 | for (i = 0; i < length; i++) |
cb1d2653 | 364 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
365 | } |
366 | if (mips_debug) | |
367 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
368 | } | |
369 | ||
dd824b04 DJ |
370 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
371 | compatiblity mode. A return value of 1 means that we have | |
372 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
373 | ||
374 | static int | |
375 | mips2_fp_compat (void) | |
376 | { | |
377 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
378 | meaningful. */ | |
6d82d43b AC |
379 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
380 | 4) | |
dd824b04 DJ |
381 | return 0; |
382 | ||
383 | #if 0 | |
384 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
385 | in all the places we deal with FP registers. PR gdb/413. */ | |
386 | /* Otherwise check the FR bit in the status register - it controls | |
387 | the FP compatiblity mode. If it is clear we are in compatibility | |
388 | mode. */ | |
389 | if ((read_register (PS_REGNUM) & ST0_FR) == 0) | |
390 | return 1; | |
391 | #endif | |
361d1df0 | 392 | |
dd824b04 DJ |
393 | return 0; |
394 | } | |
395 | ||
d929b26f | 396 | /* The amount of space reserved on the stack for registers. This is |
1b13c4f6 | 397 | different to MIPS_ABI_REGSIZE as it determines the alignment of |
d929b26f AC |
398 | data allocated after the registers have run out. */ |
399 | ||
53904c9e | 400 | static const char *mips_stack_argsize_string = size_auto; |
d929b26f AC |
401 | |
402 | static unsigned int | |
13326b4e | 403 | mips_stack_argsize (struct gdbarch *gdbarch) |
d929b26f AC |
404 | { |
405 | if (mips_stack_argsize_string == size_auto) | |
13326b4e | 406 | return mips_abi_regsize (gdbarch); |
d929b26f AC |
407 | else if (mips_stack_argsize_string == size_64) |
408 | return 8; | |
6d82d43b | 409 | else /* if (mips_stack_argsize_string == size_32) */ |
d929b26f AC |
410 | return 4; |
411 | } | |
412 | ||
7a292a7a | 413 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 414 | |
a14ed312 | 415 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 416 | |
a14ed312 | 417 | static CORE_ADDR read_next_frame_reg (struct frame_info *, int); |
c906108c | 418 | |
a14ed312 | 419 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 420 | |
67b2c998 DJ |
421 | static struct type *mips_float_register_type (void); |
422 | static struct type *mips_double_register_type (void); | |
423 | ||
acdb74a0 AC |
424 | /* The list of available "set mips " and "show mips " commands */ |
425 | ||
426 | static struct cmd_list_element *setmipscmdlist = NULL; | |
427 | static struct cmd_list_element *showmipscmdlist = NULL; | |
428 | ||
5e2e9765 KB |
429 | /* Integer registers 0 thru 31 are handled explicitly by |
430 | mips_register_name(). Processor specific registers 32 and above | |
691c0433 AC |
431 | are listed in the followign tables. */ |
432 | ||
6d82d43b AC |
433 | enum |
434 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
435 | |
436 | /* Generic MIPS. */ | |
437 | ||
438 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
439 | "sr", "lo", "hi", "bad", "cause", "pc", |
440 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
441 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
442 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
443 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
444 | "fsr", "fir", "" /*"fp" */ , "", | |
445 | "", "", "", "", "", "", "", "", | |
446 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
447 | }; |
448 | ||
449 | /* Names of IDT R3041 registers. */ | |
450 | ||
451 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
452 | "sr", "lo", "hi", "bad", "cause", "pc", |
453 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
454 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
455 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
456 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
457 | "fsr", "fir", "", /*"fp" */ "", | |
458 | "", "", "bus", "ccfg", "", "", "", "", | |
459 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
460 | }; |
461 | ||
462 | /* Names of tx39 registers. */ | |
463 | ||
464 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
465 | "sr", "lo", "hi", "bad", "cause", "pc", |
466 | "", "", "", "", "", "", "", "", | |
467 | "", "", "", "", "", "", "", "", | |
468 | "", "", "", "", "", "", "", "", | |
469 | "", "", "", "", "", "", "", "", | |
470 | "", "", "", "", | |
471 | "", "", "", "", "", "", "", "", | |
472 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
473 | }; |
474 | ||
475 | /* Names of IRIX registers. */ | |
476 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
477 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
478 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
479 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
480 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
481 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
482 | }; |
483 | ||
cce74817 | 484 | |
5e2e9765 | 485 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 486 | static const char * |
5e2e9765 | 487 | mips_register_name (int regno) |
cce74817 | 488 | { |
691c0433 | 489 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
490 | /* GPR names for all ABIs other than n32/n64. */ |
491 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
492 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
493 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
494 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
495 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
496 | }; |
497 | ||
498 | /* GPR names for n32 and n64 ABIs. */ | |
499 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
500 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
501 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
502 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
503 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
504 | }; |
505 | ||
506 | enum mips_abi abi = mips_abi (current_gdbarch); | |
507 | ||
a4b8ebc8 AC |
508 | /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then |
509 | don't make the raw register names visible. */ | |
510 | int rawnum = regno % NUM_REGS; | |
511 | if (regno < NUM_REGS) | |
512 | return ""; | |
513 | ||
5e2e9765 KB |
514 | /* The MIPS integer registers are always mapped from 0 to 31. The |
515 | names of the registers (which reflects the conventions regarding | |
516 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 517 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
518 | { |
519 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 520 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 521 | else |
a4b8ebc8 | 522 | return mips_gpr_names[rawnum]; |
5e2e9765 | 523 | } |
a4b8ebc8 | 524 | else if (32 <= rawnum && rawnum < NUM_REGS) |
691c0433 AC |
525 | { |
526 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
527 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
528 | } | |
5e2e9765 KB |
529 | else |
530 | internal_error (__FILE__, __LINE__, | |
a4b8ebc8 | 531 | "mips_register_name: bad register number %d", rawnum); |
cce74817 | 532 | } |
5e2e9765 | 533 | |
a4b8ebc8 | 534 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 535 | |
a4b8ebc8 AC |
536 | static int |
537 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
538 | struct reggroup *reggroup) | |
539 | { | |
540 | int vector_p; | |
541 | int float_p; | |
542 | int raw_p; | |
543 | int rawnum = regnum % NUM_REGS; | |
544 | int pseudo = regnum / NUM_REGS; | |
545 | if (reggroup == all_reggroup) | |
546 | return pseudo; | |
547 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
548 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
549 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
550 | (gdbarch), as not all architectures are multi-arch. */ | |
551 | raw_p = rawnum < NUM_REGS; | |
6d82d43b | 552 | if (REGISTER_NAME (regnum) == NULL || REGISTER_NAME (regnum)[0] == '\0') |
a4b8ebc8 AC |
553 | return 0; |
554 | if (reggroup == float_reggroup) | |
555 | return float_p && pseudo; | |
556 | if (reggroup == vector_reggroup) | |
557 | return vector_p && pseudo; | |
558 | if (reggroup == general_reggroup) | |
559 | return (!vector_p && !float_p) && pseudo; | |
560 | /* Save the pseudo registers. Need to make certain that any code | |
561 | extracting register values from a saved register cache also uses | |
562 | pseudo registers. */ | |
563 | if (reggroup == save_reggroup) | |
564 | return raw_p && pseudo; | |
565 | /* Restore the same pseudo register. */ | |
566 | if (reggroup == restore_reggroup) | |
567 | return raw_p && pseudo; | |
6d82d43b | 568 | return 0; |
a4b8ebc8 AC |
569 | } |
570 | ||
571 | /* Map the symbol table registers which live in the range [1 * | |
572 | NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw | |
47ebcfbe | 573 | registers. Take care of alignment and size problems. */ |
c5aa993b | 574 | |
a4b8ebc8 AC |
575 | static void |
576 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
577 | int cookednum, void *buf) | |
578 | { | |
47ebcfbe | 579 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 580 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 581 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 582 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
583 | else if (register_size (gdbarch, rawnum) > |
584 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
585 | { |
586 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
587 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
588 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); | |
589 | else | |
590 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
591 | } | |
592 | else | |
593 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 AC |
594 | } |
595 | ||
596 | static void | |
6d82d43b AC |
597 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
598 | struct regcache *regcache, int cookednum, | |
599 | const void *buf) | |
a4b8ebc8 | 600 | { |
47ebcfbe | 601 | int rawnum = cookednum % NUM_REGS; |
a4b8ebc8 | 602 | gdb_assert (cookednum >= NUM_REGS && cookednum < 2 * NUM_REGS); |
47ebcfbe | 603 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 604 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
605 | else if (register_size (gdbarch, rawnum) > |
606 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
607 | { |
608 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
609 | || TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
610 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); | |
611 | else | |
612 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
613 | } | |
614 | else | |
615 | internal_error (__FILE__, __LINE__, "bad register size"); | |
a4b8ebc8 | 616 | } |
c5aa993b | 617 | |
c906108c | 618 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 619 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
620 | |
621 | /* Heuristic_proc_start may hunt through the text section for a long | |
622 | time across a 2400 baud serial line. Allows the user to limit this | |
623 | search. */ | |
624 | ||
625 | static unsigned int heuristic_fence_post = 0; | |
626 | ||
46cd78fb | 627 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
628 | register N. NOTE: This defines the pseudo register type so need to |
629 | rebuild the architecture vector. */ | |
43e526b9 JM |
630 | |
631 | static int mips64_transfers_32bit_regs_p = 0; | |
632 | ||
719ec221 AC |
633 | static void |
634 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
635 | struct cmd_list_element *c) | |
43e526b9 | 636 | { |
719ec221 AC |
637 | struct gdbarch_info info; |
638 | gdbarch_info_init (&info); | |
639 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
640 | instead of relying on globals. Doing that would let generic code | |
641 | handle the search for this specific architecture. */ | |
642 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 643 | { |
719ec221 AC |
644 | mips64_transfers_32bit_regs_p = 0; |
645 | error ("32-bit compatibility mode not supported"); | |
a4b8ebc8 | 646 | } |
a4b8ebc8 AC |
647 | } |
648 | ||
47ebcfbe | 649 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 650 | |
ff2e87ac AC |
651 | static int |
652 | mips_convert_register_p (int regnum, struct type *type) | |
653 | { | |
654 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
719ec221 | 655 | && register_size (current_gdbarch, regnum) == 4 |
87783b8b AC |
656 | && (regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
657 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 658 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
659 | } |
660 | ||
42c466d7 | 661 | static void |
ff2e87ac AC |
662 | mips_register_to_value (struct frame_info *frame, int regnum, |
663 | struct type *type, void *to) | |
102182a9 | 664 | { |
7f5f525d AC |
665 | get_frame_register (frame, regnum + 0, (char *) to + 4); |
666 | get_frame_register (frame, regnum + 1, (char *) to + 0); | |
102182a9 MS |
667 | } |
668 | ||
42c466d7 | 669 | static void |
ff2e87ac AC |
670 | mips_value_to_register (struct frame_info *frame, int regnum, |
671 | struct type *type, const void *from) | |
102182a9 | 672 | { |
ff2e87ac AC |
673 | put_frame_register (frame, regnum + 0, (const char *) from + 4); |
674 | put_frame_register (frame, regnum + 1, (const char *) from + 0); | |
102182a9 MS |
675 | } |
676 | ||
a4b8ebc8 AC |
677 | /* Return the GDB type object for the "standard" data type of data in |
678 | register REG. */ | |
78fde5f8 KB |
679 | |
680 | static struct type * | |
a4b8ebc8 AC |
681 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
682 | { | |
5ef80fb0 | 683 | gdb_assert (regnum >= 0 && regnum < 2 * NUM_REGS); |
56cea623 AC |
684 | if ((regnum % NUM_REGS) >= mips_regnum (current_gdbarch)->fp0 |
685 | && (regnum % NUM_REGS) < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 686 | { |
5ef80fb0 | 687 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 688 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
5ef80fb0 AC |
689 | switch (gdbarch_byte_order (gdbarch)) |
690 | { | |
691 | case BFD_ENDIAN_BIG: | |
1b13c4f6 | 692 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
693 | return builtin_type_ieee_single_big; |
694 | else | |
695 | return builtin_type_ieee_double_big; | |
696 | case BFD_ENDIAN_LITTLE: | |
1b13c4f6 | 697 | if (mips_isa_regsize (gdbarch) == 4) |
5ef80fb0 AC |
698 | return builtin_type_ieee_single_little; |
699 | else | |
700 | return builtin_type_ieee_double_little; | |
701 | case BFD_ENDIAN_UNKNOWN: | |
702 | default: | |
703 | internal_error (__FILE__, __LINE__, "bad switch"); | |
704 | } | |
a6425924 | 705 | } |
d5ac5a39 AC |
706 | else if (regnum < NUM_REGS) |
707 | { | |
708 | /* The raw or ISA registers. These are all sized according to | |
709 | the ISA regsize. */ | |
710 | if (mips_isa_regsize (gdbarch) == 4) | |
711 | return builtin_type_int32; | |
712 | else | |
713 | return builtin_type_int64; | |
714 | } | |
78fde5f8 | 715 | else |
d5ac5a39 AC |
716 | { |
717 | /* The cooked or ABI registers. These are sized according to | |
718 | the ABI (with a few complications). */ | |
719 | if (regnum >= (NUM_REGS | |
720 | + mips_regnum (current_gdbarch)->fp_control_status) | |
721 | && regnum <= NUM_REGS + LAST_EMBED_REGNUM) | |
722 | /* The pseudo/cooked view of the embedded registers is always | |
723 | 32-bit. The raw view is handled below. */ | |
724 | return builtin_type_int32; | |
725 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
726 | /* The target, while possibly using a 64-bit register buffer, | |
727 | is only transfering 32-bits of each integer register. | |
728 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
729 | return builtin_type_int32; | |
730 | else if (mips_abi_regsize (gdbarch) == 4) | |
731 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
732 | 32- or 64-bit). */ | |
733 | return builtin_type_int32; | |
734 | else | |
735 | /* 64-bit ABI. */ | |
736 | return builtin_type_int64; | |
737 | } | |
78fde5f8 KB |
738 | } |
739 | ||
bcb0cc15 MS |
740 | /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */ |
741 | ||
742 | static CORE_ADDR | |
743 | mips_read_sp (void) | |
744 | { | |
f10683bb | 745 | return read_signed_register (MIPS_SP_REGNUM); |
bcb0cc15 MS |
746 | } |
747 | ||
c906108c | 748 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 749 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
750 | |
751 | static int | |
480d3dd2 | 752 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
753 | { |
754 | switch (mask_address_var) | |
755 | { | |
7f19b9a2 | 756 | case AUTO_BOOLEAN_TRUE: |
4014092b | 757 | return 1; |
7f19b9a2 | 758 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
759 | return 0; |
760 | break; | |
7f19b9a2 | 761 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 762 | return tdep->default_mask_address_p; |
4014092b | 763 | default: |
6d82d43b | 764 | internal_error (__FILE__, __LINE__, "mips_mask_address_p: bad switch"); |
4014092b | 765 | return -1; |
361d1df0 | 766 | } |
4014092b AC |
767 | } |
768 | ||
769 | static void | |
e9e68a56 | 770 | show_mask_address (char *cmd, int from_tty, struct cmd_list_element *c) |
4014092b | 771 | { |
480d3dd2 | 772 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
4014092b AC |
773 | switch (mask_address_var) |
774 | { | |
7f19b9a2 | 775 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
776 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
777 | break; | |
7f19b9a2 | 778 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
779 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
780 | break; | |
7f19b9a2 | 781 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
782 | printf_filtered |
783 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
784 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
785 | break; |
786 | default: | |
6d82d43b | 787 | internal_error (__FILE__, __LINE__, "show_mask_address: bad switch"); |
4014092b | 788 | break; |
361d1df0 | 789 | } |
4014092b | 790 | } |
c906108c | 791 | |
c906108c SS |
792 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
793 | ||
0fe7e7c8 AC |
794 | int |
795 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
796 | { |
797 | struct minimal_symbol *sym; | |
798 | ||
799 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 800 | if (is_mips16_addr (memaddr)) |
c906108c SS |
801 | return 1; |
802 | ||
803 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
804 | the high bit of the info field. Use this to decide if the function is | |
805 | MIPS16 or normal MIPS. */ | |
806 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
807 | if (sym) | |
71b8ef93 | 808 | return msymbol_is_special (sym); |
c906108c SS |
809 | else |
810 | return 0; | |
811 | } | |
812 | ||
b2fa5097 | 813 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
814 | all registers should be sign extended for simplicity? */ |
815 | ||
816 | static CORE_ADDR | |
39f77062 | 817 | mips_read_pc (ptid_t ptid) |
6c997a34 | 818 | { |
b6cb9035 AC |
819 | return read_signed_register_pid (mips_regnum (current_gdbarch)->pc, ptid); |
820 | } | |
821 | ||
58dfe9ff AC |
822 | static CORE_ADDR |
823 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
824 | { | |
edfae063 AC |
825 | return frame_unwind_register_signed (next_frame, |
826 | NUM_REGS + mips_regnum (gdbarch)->pc); | |
827 | } | |
828 | ||
829 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that | |
830 | dummy frame. The frame ID's base needs to match the TOS value | |
831 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
832 | breakpoint. */ | |
833 | ||
834 | static struct frame_id | |
835 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
836 | { | |
f10683bb | 837 | return frame_id_build (frame_unwind_register_signed (next_frame, NUM_REGS + MIPS_SP_REGNUM), |
edfae063 | 838 | frame_pc_unwind (next_frame)); |
58dfe9ff AC |
839 | } |
840 | ||
b6cb9035 AC |
841 | static void |
842 | mips_write_pc (CORE_ADDR pc, ptid_t ptid) | |
843 | { | |
844 | write_register_pid (mips_regnum (current_gdbarch)->pc, pc, ptid); | |
6c997a34 | 845 | } |
c906108c | 846 | |
c906108c SS |
847 | /* Fetch and return instruction from the specified location. If the PC |
848 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
849 | ||
850 | static t_inst | |
acdb74a0 | 851 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 852 | { |
4c7d22cb | 853 | char buf[MIPS32_INSN_SIZE]; |
c906108c SS |
854 | int instlen; |
855 | int status; | |
856 | ||
0fe7e7c8 | 857 | if (mips_pc_is_mips16 (addr)) |
c906108c | 858 | { |
4c7d22cb | 859 | instlen = MIPS16_INSN_SIZE; |
95404a3e | 860 | addr = unmake_mips16_addr (addr); |
c906108c SS |
861 | } |
862 | else | |
4c7d22cb | 863 | instlen = MIPS32_INSN_SIZE; |
1f602b35 | 864 | status = deprecated_read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
865 | if (status) |
866 | memory_error (status, addr); | |
867 | return extract_unsigned_integer (buf, instlen); | |
868 | } | |
869 | ||
c906108c | 870 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
871 | #define mips32_op(x) (x >> 26) |
872 | #define itype_op(x) (x >> 26) | |
873 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 874 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 875 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 876 | |
e135b889 DJ |
877 | #define jtype_op(x) (x >> 26) |
878 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 879 | |
e135b889 DJ |
880 | #define rtype_op(x) (x >> 26) |
881 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
882 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
883 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
884 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
885 | #define rtype_funct(x) (x & 0x3f) | |
c906108c SS |
886 | |
887 | static CORE_ADDR | |
c5aa993b JM |
888 | mips32_relative_offset (unsigned long inst) |
889 | { | |
890 | long x; | |
891 | x = itype_immediate (inst); | |
892 | if (x & 0x8000) /* sign bit set */ | |
c906108c | 893 | { |
c5aa993b | 894 | x |= 0xffff0000; /* sign extension */ |
c906108c | 895 | } |
c5aa993b JM |
896 | x = x << 2; |
897 | return x; | |
c906108c SS |
898 | } |
899 | ||
900 | /* Determine whate to set a single step breakpoint while considering | |
901 | branch prediction */ | |
5a89d8aa | 902 | static CORE_ADDR |
c5aa993b JM |
903 | mips32_next_pc (CORE_ADDR pc) |
904 | { | |
905 | unsigned long inst; | |
906 | int op; | |
907 | inst = mips_fetch_instruction (pc); | |
e135b889 | 908 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 909 | { |
e135b889 | 910 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 911 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 912 | { |
e135b889 | 913 | op = (itype_op (inst) & 0x03); |
c906108c SS |
914 | switch (op) |
915 | { | |
e135b889 DJ |
916 | case 0: /* BEQL */ |
917 | goto equal_branch; | |
918 | case 1: /* BNEL */ | |
919 | goto neq_branch; | |
920 | case 2: /* BLEZL */ | |
921 | goto less_branch; | |
922 | case 3: /* BGTZ */ | |
923 | goto greater_branch; | |
c5aa993b JM |
924 | default: |
925 | pc += 4; | |
c906108c SS |
926 | } |
927 | } | |
e135b889 | 928 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 929 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
930 | { |
931 | int tf = itype_rt (inst) & 0x01; | |
932 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b AC |
933 | int fcrcs = |
934 | read_signed_register (mips_regnum (current_gdbarch)-> | |
935 | fp_control_status); | |
e135b889 DJ |
936 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
937 | ||
938 | if (((cond >> cnum) & 0x01) == tf) | |
939 | pc += mips32_relative_offset (inst) + 4; | |
940 | else | |
941 | pc += 8; | |
942 | } | |
c5aa993b JM |
943 | else |
944 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
945 | } |
946 | else | |
c5aa993b JM |
947 | { /* This gets way messy */ |
948 | ||
c906108c | 949 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 950 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 951 | { |
c5aa993b JM |
952 | case 0: /* SPECIAL */ |
953 | op = rtype_funct (inst); | |
954 | switch (op) | |
955 | { | |
956 | case 8: /* JR */ | |
957 | case 9: /* JALR */ | |
6c997a34 AC |
958 | /* Set PC to that address */ |
959 | pc = read_signed_register (rtype_rs (inst)); | |
c5aa993b JM |
960 | break; |
961 | default: | |
962 | pc += 4; | |
963 | } | |
964 | ||
6d82d43b | 965 | break; /* end SPECIAL */ |
c5aa993b | 966 | case 1: /* REGIMM */ |
c906108c | 967 | { |
e135b889 DJ |
968 | op = itype_rt (inst); /* branch condition */ |
969 | switch (op) | |
c906108c | 970 | { |
c5aa993b | 971 | case 0: /* BLTZ */ |
e135b889 DJ |
972 | case 2: /* BLTZL */ |
973 | case 16: /* BLTZAL */ | |
c5aa993b | 974 | case 18: /* BLTZALL */ |
c906108c | 975 | less_branch: |
6c997a34 | 976 | if (read_signed_register (itype_rs (inst)) < 0) |
c5aa993b JM |
977 | pc += mips32_relative_offset (inst) + 4; |
978 | else | |
979 | pc += 8; /* after the delay slot */ | |
980 | break; | |
e135b889 | 981 | case 1: /* BGEZ */ |
c5aa993b JM |
982 | case 3: /* BGEZL */ |
983 | case 17: /* BGEZAL */ | |
984 | case 19: /* BGEZALL */ | |
6c997a34 | 985 | if (read_signed_register (itype_rs (inst)) >= 0) |
c5aa993b JM |
986 | pc += mips32_relative_offset (inst) + 4; |
987 | else | |
988 | pc += 8; /* after the delay slot */ | |
989 | break; | |
e135b889 | 990 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
991 | default: |
992 | pc += 4; | |
c906108c SS |
993 | } |
994 | } | |
6d82d43b | 995 | break; /* end REGIMM */ |
c5aa993b JM |
996 | case 2: /* J */ |
997 | case 3: /* JAL */ | |
998 | { | |
999 | unsigned long reg; | |
1000 | reg = jtype_target (inst) << 2; | |
e135b889 | 1001 | /* Upper four bits get never changed... */ |
c5aa993b | 1002 | pc = reg + ((pc + 4) & 0xf0000000); |
c906108c | 1003 | } |
c5aa993b JM |
1004 | break; |
1005 | /* FIXME case JALX : */ | |
1006 | { | |
1007 | unsigned long reg; | |
1008 | reg = jtype_target (inst) << 2; | |
1009 | pc = reg + ((pc + 4) & 0xf0000000) + 1; /* yes, +1 */ | |
c906108c SS |
1010 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1011 | } | |
c5aa993b | 1012 | break; /* The new PC will be alternate mode */ |
e135b889 | 1013 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1014 | equal_branch: |
6c997a34 AC |
1015 | if (read_signed_register (itype_rs (inst)) == |
1016 | read_signed_register (itype_rt (inst))) | |
c5aa993b JM |
1017 | pc += mips32_relative_offset (inst) + 4; |
1018 | else | |
1019 | pc += 8; | |
1020 | break; | |
e135b889 | 1021 | case 5: /* BNE, BNEL */ |
c5aa993b | 1022 | neq_branch: |
6c997a34 | 1023 | if (read_signed_register (itype_rs (inst)) != |
e135b889 | 1024 | read_signed_register (itype_rt (inst))) |
c5aa993b JM |
1025 | pc += mips32_relative_offset (inst) + 4; |
1026 | else | |
1027 | pc += 8; | |
1028 | break; | |
e135b889 | 1029 | case 6: /* BLEZ, BLEZL */ |
1fd8cd20 | 1030 | if (read_signed_register (itype_rs (inst)) <= 0) |
c5aa993b JM |
1031 | pc += mips32_relative_offset (inst) + 4; |
1032 | else | |
1033 | pc += 8; | |
1034 | break; | |
1035 | case 7: | |
e135b889 DJ |
1036 | default: |
1037 | greater_branch: /* BGTZ, BGTZL */ | |
1fd8cd20 | 1038 | if (read_signed_register (itype_rs (inst)) > 0) |
c5aa993b JM |
1039 | pc += mips32_relative_offset (inst) + 4; |
1040 | else | |
1041 | pc += 8; | |
1042 | break; | |
c5aa993b JM |
1043 | } /* switch */ |
1044 | } /* else */ | |
1045 | return pc; | |
1046 | } /* mips32_next_pc */ | |
c906108c SS |
1047 | |
1048 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1049 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1050 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1051 | We dont want to set a single step instruction on the extend instruction | |
1052 | either. | |
c5aa993b | 1053 | */ |
c906108c SS |
1054 | |
1055 | /* Lots of mips16 instruction formats */ | |
1056 | /* Predicting jumps requires itype,ritype,i8type | |
1057 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1058 | */ |
c906108c SS |
1059 | enum mips16_inst_fmts |
1060 | { | |
c5aa993b JM |
1061 | itype, /* 0 immediate 5,10 */ |
1062 | ritype, /* 1 5,3,8 */ | |
1063 | rrtype, /* 2 5,3,3,5 */ | |
1064 | rritype, /* 3 5,3,3,5 */ | |
1065 | rrrtype, /* 4 5,3,3,3,2 */ | |
1066 | rriatype, /* 5 5,3,3,1,4 */ | |
1067 | shifttype, /* 6 5,3,3,3,2 */ | |
1068 | i8type, /* 7 5,3,8 */ | |
1069 | i8movtype, /* 8 5,3,3,5 */ | |
1070 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1071 | i64type, /* 10 5,3,8 */ | |
1072 | ri64type, /* 11 5,3,3,5 */ | |
1073 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1074 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1075 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1076 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1077 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1078 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1079 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1080 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1081 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1082 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1083 | }; | |
12f02c2a AC |
1084 | /* I am heaping all the fields of the formats into one structure and |
1085 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1086 | struct upk_mips16 |
6d82d43b AC |
1087 | { |
1088 | CORE_ADDR offset; | |
1089 | unsigned int regx; /* Function in i8 type */ | |
1090 | unsigned int regy; | |
1091 | }; | |
c906108c SS |
1092 | |
1093 | ||
12f02c2a AC |
1094 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1095 | for the bits which make up the immediatate extension. */ | |
c906108c | 1096 | |
12f02c2a AC |
1097 | static CORE_ADDR |
1098 | extended_offset (unsigned int extension) | |
c906108c | 1099 | { |
12f02c2a | 1100 | CORE_ADDR value; |
c5aa993b JM |
1101 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1102 | value = value << 6; | |
1103 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1104 | value = value << 5; | |
1105 | value |= extension & 0x01f; /* extract 4:0 */ | |
1106 | return value; | |
c906108c SS |
1107 | } |
1108 | ||
1109 | /* Only call this function if you know that this is an extendable | |
1110 | instruction, It wont malfunction, but why make excess remote memory references? | |
1111 | If the immediate operands get sign extended or somthing, do it after | |
1112 | the extension is performed. | |
c5aa993b | 1113 | */ |
c906108c SS |
1114 | /* FIXME: Every one of these cases needs to worry about sign extension |
1115 | when the offset is to be used in relative addressing */ | |
1116 | ||
1117 | ||
12f02c2a | 1118 | static unsigned int |
c5aa993b | 1119 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1120 | { |
c5aa993b JM |
1121 | char buf[8]; |
1122 | pc &= 0xfffffffe; /* clear the low order bit */ | |
1123 | target_read_memory (pc, buf, 2); | |
1124 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1125 | } |
1126 | ||
1127 | static void | |
c5aa993b | 1128 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1129 | unsigned int extension, |
1130 | unsigned int inst, | |
6d82d43b | 1131 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1132 | { |
12f02c2a AC |
1133 | CORE_ADDR offset; |
1134 | int regx; | |
1135 | int regy; | |
1136 | switch (insn_format) | |
c906108c | 1137 | { |
c5aa993b | 1138 | case itype: |
c906108c | 1139 | { |
12f02c2a AC |
1140 | CORE_ADDR value; |
1141 | if (extension) | |
c5aa993b JM |
1142 | { |
1143 | value = extended_offset (extension); | |
1144 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1145 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1146 | } |
1147 | else | |
c5aa993b | 1148 | { |
12f02c2a | 1149 | value = inst & 0x7ff; |
c5aa993b | 1150 | /* FIXME : Consider sign extension */ |
c906108c | 1151 | } |
12f02c2a AC |
1152 | offset = value; |
1153 | regx = -1; | |
1154 | regy = -1; | |
c906108c | 1155 | } |
c5aa993b JM |
1156 | break; |
1157 | case ritype: | |
1158 | case i8type: | |
1159 | { /* A register identifier and an offset */ | |
c906108c SS |
1160 | /* Most of the fields are the same as I type but the |
1161 | immediate value is of a different length */ | |
12f02c2a AC |
1162 | CORE_ADDR value; |
1163 | if (extension) | |
c906108c | 1164 | { |
c5aa993b JM |
1165 | value = extended_offset (extension); |
1166 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1167 | value |= inst & 0xff; /* eleven bits from instruction */ |
1168 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1169 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1170 | { | |
1171 | value &= ~0x3fff; /* remove the sign bit */ | |
1172 | value = -value; | |
c906108c SS |
1173 | } |
1174 | } | |
c5aa993b JM |
1175 | else |
1176 | { | |
12f02c2a AC |
1177 | value = inst & 0xff; /* 8 bits */ |
1178 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1179 | /* FIXME: Do sign extension , this format needs it */ |
1180 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1181 | { | |
1182 | value &= 0xef; /* remove the sign bit */ | |
1183 | value = -value; | |
1184 | } | |
c5aa993b | 1185 | } |
12f02c2a AC |
1186 | offset = value; |
1187 | regy = -1; | |
c5aa993b | 1188 | break; |
c906108c | 1189 | } |
c5aa993b | 1190 | case jalxtype: |
c906108c | 1191 | { |
c5aa993b | 1192 | unsigned long value; |
12f02c2a AC |
1193 | unsigned int nexthalf; |
1194 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1195 | value = value << 16; |
1196 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1197 | value |= nexthalf; | |
12f02c2a AC |
1198 | offset = value; |
1199 | regx = -1; | |
1200 | regy = -1; | |
c5aa993b | 1201 | break; |
c906108c SS |
1202 | } |
1203 | default: | |
6d82d43b | 1204 | internal_error (__FILE__, __LINE__, "bad switch"); |
c906108c | 1205 | } |
12f02c2a AC |
1206 | upk->offset = offset; |
1207 | upk->regx = regx; | |
1208 | upk->regy = regy; | |
c906108c SS |
1209 | } |
1210 | ||
1211 | ||
c5aa993b JM |
1212 | static CORE_ADDR |
1213 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1214 | { |
c5aa993b | 1215 | return ((offset << 2) | ((pc + 2) & (0xf0000000))); |
c906108c SS |
1216 | } |
1217 | ||
12f02c2a AC |
1218 | static CORE_ADDR |
1219 | extended_mips16_next_pc (CORE_ADDR pc, | |
6d82d43b | 1220 | unsigned int extension, unsigned int insn) |
c906108c | 1221 | { |
12f02c2a AC |
1222 | int op = (insn >> 11); |
1223 | switch (op) | |
c906108c | 1224 | { |
6d82d43b | 1225 | case 2: /* Branch */ |
12f02c2a AC |
1226 | { |
1227 | CORE_ADDR offset; | |
1228 | struct upk_mips16 upk; | |
1229 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1230 | offset = upk.offset; | |
1231 | if (offset & 0x800) | |
1232 | { | |
1233 | offset &= 0xeff; | |
1234 | offset = -offset; | |
1235 | } | |
1236 | pc += (offset << 1) + 2; | |
1237 | break; | |
1238 | } | |
6d82d43b | 1239 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1240 | { |
1241 | struct upk_mips16 upk; | |
1242 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1243 | pc = add_offset_16 (pc, upk.offset); | |
1244 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1245 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1246 | else | |
1247 | pc |= 0x01; | |
1248 | break; | |
1249 | } | |
6d82d43b | 1250 | case 4: /* beqz */ |
12f02c2a AC |
1251 | { |
1252 | struct upk_mips16 upk; | |
1253 | int reg; | |
1254 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1255 | reg = read_signed_register (upk.regx); | |
1256 | if (reg == 0) | |
1257 | pc += (upk.offset << 1) + 2; | |
1258 | else | |
1259 | pc += 2; | |
1260 | break; | |
1261 | } | |
6d82d43b | 1262 | case 5: /* bnez */ |
12f02c2a AC |
1263 | { |
1264 | struct upk_mips16 upk; | |
1265 | int reg; | |
1266 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
1267 | reg = read_signed_register (upk.regx); | |
1268 | if (reg != 0) | |
1269 | pc += (upk.offset << 1) + 2; | |
1270 | else | |
1271 | pc += 2; | |
1272 | break; | |
1273 | } | |
6d82d43b | 1274 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1275 | { |
1276 | struct upk_mips16 upk; | |
1277 | int reg; | |
1278 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1279 | /* upk.regx contains the opcode */ | |
1280 | reg = read_signed_register (24); /* Test register is 24 */ | |
1281 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ | |
1282 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1283 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1284 | pc += (upk.offset << 1) + 2; | |
1285 | else | |
1286 | pc += 2; | |
1287 | break; | |
1288 | } | |
6d82d43b | 1289 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1290 | { |
1291 | struct upk_mips16 upk; | |
1292 | /* upk.fmt = rrtype; */ | |
1293 | op = insn & 0x1f; | |
1294 | if (op == 0) | |
c5aa993b | 1295 | { |
12f02c2a AC |
1296 | int reg; |
1297 | upk.regx = (insn >> 8) & 0x07; | |
1298 | upk.regy = (insn >> 5) & 0x07; | |
1299 | switch (upk.regy) | |
c5aa993b | 1300 | { |
12f02c2a AC |
1301 | case 0: |
1302 | reg = upk.regx; | |
1303 | break; | |
1304 | case 1: | |
1305 | reg = 31; | |
6d82d43b | 1306 | break; /* Function return instruction */ |
12f02c2a AC |
1307 | case 2: |
1308 | reg = upk.regx; | |
1309 | break; | |
1310 | default: | |
1311 | reg = 31; | |
6d82d43b | 1312 | break; /* BOGUS Guess */ |
c906108c | 1313 | } |
12f02c2a | 1314 | pc = read_signed_register (reg); |
c906108c | 1315 | } |
12f02c2a | 1316 | else |
c5aa993b | 1317 | pc += 2; |
12f02c2a AC |
1318 | break; |
1319 | } | |
1320 | case 30: | |
1321 | /* This is an instruction extension. Fetch the real instruction | |
1322 | (which follows the extension) and decode things based on | |
1323 | that. */ | |
1324 | { | |
1325 | pc += 2; | |
1326 | pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc)); | |
1327 | break; | |
1328 | } | |
1329 | default: | |
1330 | { | |
1331 | pc += 2; | |
1332 | break; | |
1333 | } | |
c906108c | 1334 | } |
c5aa993b | 1335 | return pc; |
12f02c2a | 1336 | } |
c906108c | 1337 | |
5a89d8aa | 1338 | static CORE_ADDR |
12f02c2a AC |
1339 | mips16_next_pc (CORE_ADDR pc) |
1340 | { | |
1341 | unsigned int insn = fetch_mips_16 (pc); | |
1342 | return extended_mips16_next_pc (pc, 0, insn); | |
1343 | } | |
1344 | ||
1345 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1346 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1347 | It works by decoding the current instruction and predicting where a |
1348 | branch will go. This isnt hard because all the data is available. | |
1349 | The MIPS32 and MIPS16 variants are quite different */ | |
c5aa993b JM |
1350 | CORE_ADDR |
1351 | mips_next_pc (CORE_ADDR pc) | |
c906108c | 1352 | { |
c5aa993b JM |
1353 | if (pc & 0x01) |
1354 | return mips16_next_pc (pc); | |
1355 | else | |
1356 | return mips32_next_pc (pc); | |
12f02c2a | 1357 | } |
c906108c | 1358 | |
edfae063 AC |
1359 | struct mips_frame_cache |
1360 | { | |
1361 | CORE_ADDR base; | |
1362 | struct trad_frame_saved_reg *saved_regs; | |
1363 | }; | |
1364 | ||
29639122 JB |
1365 | /* Set a register's saved stack address in temp_saved_regs. If an |
1366 | address has already been set for this register, do nothing; this | |
1367 | way we will only recognize the first save of a given register in a | |
1368 | function prologue. | |
eec63939 | 1369 | |
29639122 JB |
1370 | For simplicity, save the address in both [0 .. NUM_REGS) and |
1371 | [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range | |
1372 | is used as it is only second range (the ABI instead of ISA | |
1373 | registers) that comes into play when finding saved registers in a | |
1374 | frame. */ | |
eec63939 AC |
1375 | |
1376 | static void | |
29639122 JB |
1377 | set_reg_offset (struct mips_frame_cache *this_cache, int regnum, |
1378 | CORE_ADDR offset) | |
eec63939 | 1379 | { |
29639122 JB |
1380 | if (this_cache != NULL |
1381 | && this_cache->saved_regs[regnum].addr == -1) | |
1382 | { | |
1383 | this_cache->saved_regs[regnum + 0 * NUM_REGS].addr = offset; | |
1384 | this_cache->saved_regs[regnum + 1 * NUM_REGS].addr = offset; | |
1385 | } | |
eec63939 AC |
1386 | } |
1387 | ||
eec63939 | 1388 | |
29639122 JB |
1389 | /* Fetch the immediate value from a MIPS16 instruction. |
1390 | If the previous instruction was an EXTEND, use it to extend | |
1391 | the upper bits of the immediate value. This is a helper function | |
1392 | for mips16_scan_prologue. */ | |
eec63939 | 1393 | |
29639122 JB |
1394 | static int |
1395 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1396 | unsigned short inst, /* current instruction */ | |
1397 | int nbits, /* number of bits in imm field */ | |
1398 | int scale, /* scale factor to be applied to imm */ | |
1399 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1400 | { |
29639122 | 1401 | int offset; |
eec63939 | 1402 | |
29639122 JB |
1403 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1404 | { | |
1405 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1406 | if (offset & 0x8000) /* check for negative extend */ | |
1407 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1408 | return offset | (inst & 0x1f); | |
1409 | } | |
eec63939 | 1410 | else |
29639122 JB |
1411 | { |
1412 | int max_imm = 1 << nbits; | |
1413 | int mask = max_imm - 1; | |
1414 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1415 | |
29639122 JB |
1416 | offset = inst & mask; |
1417 | if (is_signed && (offset & sign_bit)) | |
1418 | offset = 0 - (max_imm - offset); | |
1419 | return offset * scale; | |
1420 | } | |
1421 | } | |
eec63939 | 1422 | |
65596487 | 1423 | |
29639122 JB |
1424 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1425 | the associated FRAME_CACHE if not null. | |
1426 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1427 | |
29639122 JB |
1428 | static CORE_ADDR |
1429 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
1430 | struct frame_info *next_frame, | |
1431 | struct mips_frame_cache *this_cache) | |
1432 | { | |
1433 | CORE_ADDR cur_pc; | |
1434 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1435 | CORE_ADDR sp; | |
1436 | long frame_offset = 0; /* Size of stack frame. */ | |
1437 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1438 | int frame_reg = MIPS_SP_REGNUM; | |
1439 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1440 | unsigned inst = 0; /* current instruction */ | |
1441 | unsigned entry_inst = 0; /* the entry instruction */ | |
1442 | int reg, offset; | |
a343eb3c | 1443 | |
29639122 JB |
1444 | int extend_bytes = 0; |
1445 | int prev_extend_bytes; | |
1446 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1447 | |
29639122 JB |
1448 | /* Can be called when there's no process, and hence when there's no |
1449 | NEXT_FRAME. */ | |
1450 | if (next_frame != NULL) | |
1451 | sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM); | |
1452 | else | |
1453 | sp = 0; | |
eec63939 | 1454 | |
29639122 JB |
1455 | if (limit_pc > start_pc + 200) |
1456 | limit_pc = start_pc + 200; | |
eec63939 | 1457 | |
4c7d22cb | 1458 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS16_INSN_SIZE) |
29639122 JB |
1459 | { |
1460 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1461 | the immediate offset extension from it in mips16_get_imm. */ | |
1462 | prev_inst = inst; | |
eec63939 | 1463 | |
29639122 JB |
1464 | /* Fetch and decode the instruction. */ |
1465 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1466 | |
29639122 JB |
1467 | /* Normally we ignore extend instructions. However, if it is |
1468 | not followed by a valid prologue instruction, then this | |
1469 | instruction is not part of the prologue either. We must | |
1470 | remember in this case to adjust the end_prologue_addr back | |
1471 | over the extend. */ | |
1472 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1473 | { | |
4c7d22cb | 1474 | extend_bytes = MIPS16_INSN_SIZE; |
29639122 JB |
1475 | continue; |
1476 | } | |
eec63939 | 1477 | |
29639122 JB |
1478 | prev_extend_bytes = extend_bytes; |
1479 | extend_bytes = 0; | |
eec63939 | 1480 | |
29639122 JB |
1481 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1482 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1483 | { | |
1484 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1485 | if (offset < 0) /* negative stack adjustment? */ | |
1486 | frame_offset -= offset; | |
1487 | else | |
1488 | /* Exit loop if a positive stack adjustment is found, which | |
1489 | usually means that the stack cleanup code in the function | |
1490 | epilogue is reached. */ | |
1491 | break; | |
1492 | } | |
1493 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1494 | { | |
1495 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1496 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
1497 | set_reg_offset (this_cache, reg, sp + offset); | |
1498 | } | |
1499 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1500 | { | |
1501 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1502 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1503 | set_reg_offset (this_cache, reg, sp + offset); | |
1504 | } | |
1505 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1506 | { | |
1507 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4c7d22cb | 1508 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1509 | } |
1510 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1511 | { | |
1512 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
4c7d22cb | 1513 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1514 | } |
1515 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1516 | { | |
1517 | frame_addr = sp; | |
1518 | frame_reg = 17; | |
1519 | } | |
1520 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1521 | { | |
1522 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1523 | frame_addr = sp + offset; | |
1524 | frame_reg = 17; | |
1525 | frame_adjust = offset; | |
1526 | } | |
1527 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1528 | { | |
1529 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1530 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1531 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1532 | } | |
1533 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1534 | { | |
1535 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1536 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1537 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1538 | } | |
1539 | else if ((inst & 0xf81f) == 0xe809 | |
1540 | && (inst & 0x700) != 0x700) /* entry */ | |
1541 | entry_inst = inst; /* save for later processing */ | |
1542 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ | |
4c7d22cb | 1543 | cur_pc += MIPS16_INSN_SIZE; /* 32-bit instruction */ |
29639122 JB |
1544 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1545 | { | |
1546 | /* This instruction is part of the prologue, but we don't | |
1547 | need to do anything special to handle it. */ | |
1548 | } | |
1549 | else | |
1550 | { | |
1551 | /* This instruction is not an instruction typically found | |
1552 | in a prologue, so we must have reached the end of the | |
1553 | prologue. */ | |
1554 | if (end_prologue_addr == 0) | |
1555 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1556 | } | |
1557 | } | |
eec63939 | 1558 | |
29639122 JB |
1559 | /* The entry instruction is typically the first instruction in a function, |
1560 | and it stores registers at offsets relative to the value of the old SP | |
1561 | (before the prologue). But the value of the sp parameter to this | |
1562 | function is the new SP (after the prologue has been executed). So we | |
1563 | can't calculate those offsets until we've seen the entire prologue, | |
1564 | and can calculate what the old SP must have been. */ | |
1565 | if (entry_inst != 0) | |
1566 | { | |
1567 | int areg_count = (entry_inst >> 8) & 7; | |
1568 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1569 | |
29639122 JB |
1570 | /* The entry instruction always subtracts 32 from the SP. */ |
1571 | frame_offset += 32; | |
1572 | ||
1573 | /* Now we can calculate what the SP must have been at the | |
1574 | start of the function prologue. */ | |
1575 | sp += frame_offset; | |
1576 | ||
1577 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1578 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1579 | { | |
1580 | set_reg_offset (this_cache, reg, sp + offset); | |
1581 | offset += mips_abi_regsize (current_gdbarch); | |
1582 | } | |
1583 | ||
1584 | /* Check if the ra register was pushed on the stack. */ | |
1585 | offset = -4; | |
1586 | if (entry_inst & 0x20) | |
1587 | { | |
4c7d22cb | 1588 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1589 | offset -= mips_abi_regsize (current_gdbarch); |
1590 | } | |
1591 | ||
1592 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1593 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1594 | { | |
1595 | set_reg_offset (this_cache, reg, sp + offset); | |
1596 | offset -= mips_abi_regsize (current_gdbarch); | |
1597 | } | |
1598 | } | |
1599 | ||
1600 | if (this_cache != NULL) | |
1601 | { | |
1602 | this_cache->base = | |
1603 | (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg) | |
1604 | + frame_offset - frame_adjust); | |
1605 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1606 | be able to get rid of the assignment below, evetually. But it's | |
1607 | still needed for now. */ | |
1608 | this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
4c7d22cb | 1609 | = this_cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM]; |
29639122 JB |
1610 | } |
1611 | ||
1612 | /* If we didn't reach the end of the prologue when scanning the function | |
1613 | instructions, then set end_prologue_addr to the address of the | |
1614 | instruction immediately after the last one we scanned. */ | |
1615 | if (end_prologue_addr == 0) | |
1616 | end_prologue_addr = cur_pc; | |
1617 | ||
1618 | return end_prologue_addr; | |
eec63939 AC |
1619 | } |
1620 | ||
29639122 JB |
1621 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1622 | Procedures that use the 32-bit instruction set are handled by the | |
1623 | mips_insn32 unwinder. */ | |
1624 | ||
1625 | static struct mips_frame_cache * | |
1626 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) | |
eec63939 | 1627 | { |
29639122 | 1628 | struct mips_frame_cache *cache; |
eec63939 AC |
1629 | |
1630 | if ((*this_cache) != NULL) | |
1631 | return (*this_cache); | |
29639122 JB |
1632 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1633 | (*this_cache) = cache; | |
1634 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
eec63939 | 1635 | |
29639122 JB |
1636 | /* Analyze the function prologue. */ |
1637 | { | |
1638 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1639 | CORE_ADDR start_addr; | |
eec63939 | 1640 | |
29639122 JB |
1641 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1642 | if (start_addr == 0) | |
1643 | start_addr = heuristic_proc_start (pc); | |
1644 | /* We can't analyze the prologue if we couldn't find the begining | |
1645 | of the function. */ | |
1646 | if (start_addr == 0) | |
1647 | return cache; | |
eec63939 | 1648 | |
29639122 JB |
1649 | mips16_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1650 | } | |
1651 | ||
1652 | /* SP_REGNUM, contains the value and not the address. */ | |
1653 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
eec63939 | 1654 | |
29639122 | 1655 | return (*this_cache); |
eec63939 AC |
1656 | } |
1657 | ||
1658 | static void | |
29639122 JB |
1659 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
1660 | struct frame_id *this_id) | |
eec63939 | 1661 | { |
29639122 JB |
1662 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1663 | this_cache); | |
1664 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
eec63939 AC |
1665 | } |
1666 | ||
1667 | static void | |
29639122 | 1668 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1669 | void **this_cache, |
1670 | int regnum, int *optimizedp, | |
1671 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1672 | int *realnump, void *valuep) | |
1673 | { | |
29639122 JB |
1674 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1675 | this_cache); | |
1676 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1677 | optimizedp, lvalp, addrp, realnump, valuep); | |
eec63939 AC |
1678 | } |
1679 | ||
29639122 | 1680 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1681 | { |
1682 | NORMAL_FRAME, | |
29639122 JB |
1683 | mips_insn16_frame_this_id, |
1684 | mips_insn16_frame_prev_register | |
eec63939 AC |
1685 | }; |
1686 | ||
1687 | static const struct frame_unwind * | |
29639122 | 1688 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 AC |
1689 | { |
1690 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
0fe7e7c8 | 1691 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
1692 | return &mips_insn16_frame_unwind; |
1693 | return NULL; | |
eec63939 AC |
1694 | } |
1695 | ||
1696 | static CORE_ADDR | |
29639122 JB |
1697 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
1698 | void **this_cache) | |
eec63939 | 1699 | { |
29639122 JB |
1700 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1701 | this_cache); | |
1702 | return info->base; | |
eec63939 AC |
1703 | } |
1704 | ||
29639122 | 1705 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1706 | { |
29639122 JB |
1707 | &mips_insn16_frame_unwind, |
1708 | mips_insn16_frame_base_address, | |
1709 | mips_insn16_frame_base_address, | |
1710 | mips_insn16_frame_base_address | |
eec63939 AC |
1711 | }; |
1712 | ||
1713 | static const struct frame_base * | |
29639122 | 1714 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 1715 | { |
29639122 JB |
1716 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
1717 | return &mips_insn16_frame_base; | |
eec63939 AC |
1718 | else |
1719 | return NULL; | |
edfae063 AC |
1720 | } |
1721 | ||
29639122 JB |
1722 | /* Mark all the registers as unset in the saved_regs array |
1723 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1724 | ||
1725 | void | |
1726 | reset_saved_regs (struct mips_frame_cache *this_cache) | |
c906108c | 1727 | { |
29639122 JB |
1728 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1729 | return; | |
1730 | ||
1731 | { | |
1732 | const int num_regs = NUM_REGS; | |
1733 | int i; | |
64159455 | 1734 | |
29639122 JB |
1735 | for (i = 0; i < num_regs; i++) |
1736 | { | |
1737 | this_cache->saved_regs[i].addr = -1; | |
1738 | } | |
1739 | } | |
c906108c SS |
1740 | } |
1741 | ||
29639122 JB |
1742 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1743 | the associated FRAME_CACHE if not null. | |
1744 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1745 | |
875e1767 | 1746 | static CORE_ADDR |
29639122 JB |
1747 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1748 | struct frame_info *next_frame, | |
1749 | struct mips_frame_cache *this_cache) | |
c906108c | 1750 | { |
29639122 JB |
1751 | CORE_ADDR cur_pc; |
1752 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1753 | CORE_ADDR sp; | |
1754 | long frame_offset; | |
1755 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1756 | |
29639122 JB |
1757 | CORE_ADDR end_prologue_addr = 0; |
1758 | int seen_sp_adjust = 0; | |
1759 | int load_immediate_bytes = 0; | |
8fa9cfa1 | 1760 | |
29639122 JB |
1761 | /* Can be called when there's no process, and hence when there's no |
1762 | NEXT_FRAME. */ | |
1763 | if (next_frame != NULL) | |
1764 | sp = read_next_frame_reg (next_frame, NUM_REGS + MIPS_SP_REGNUM); | |
8fa9cfa1 | 1765 | else |
29639122 | 1766 | sp = 0; |
9022177c | 1767 | |
29639122 JB |
1768 | if (limit_pc > start_pc + 200) |
1769 | limit_pc = start_pc + 200; | |
9022177c | 1770 | |
29639122 | 1771 | restart: |
9022177c | 1772 | |
29639122 | 1773 | frame_offset = 0; |
4c7d22cb | 1774 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS32_INSN_SIZE) |
9022177c | 1775 | { |
29639122 JB |
1776 | unsigned long inst, high_word, low_word; |
1777 | int reg; | |
9022177c | 1778 | |
29639122 JB |
1779 | /* Fetch the instruction. */ |
1780 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 1781 | |
29639122 JB |
1782 | /* Save some code by pre-extracting some useful fields. */ |
1783 | high_word = (inst >> 16) & 0xffff; | |
1784 | low_word = inst & 0xffff; | |
1785 | reg = high_word & 0x1f; | |
fe29b929 | 1786 | |
29639122 JB |
1787 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1788 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1789 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1790 | { | |
1791 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1792 | frame_offset += 0x10000 - low_word; | |
1793 | else | |
1794 | /* Exit loop if a positive stack adjustment is found, which | |
1795 | usually means that the stack cleanup code in the function | |
1796 | epilogue is reached. */ | |
1797 | break; | |
1798 | seen_sp_adjust = 1; | |
1799 | } | |
1800 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1801 | { | |
1802 | set_reg_offset (this_cache, reg, sp + low_word); | |
1803 | } | |
1804 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1805 | { | |
1806 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
1807 | set_reg_offset (this_cache, reg, sp + low_word); | |
1808 | } | |
1809 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1810 | { | |
1811 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1812 | if ((long) low_word != frame_offset) | |
1813 | frame_addr = sp + low_word; | |
1814 | else if (frame_reg == MIPS_SP_REGNUM) | |
1815 | { | |
1816 | unsigned alloca_adjust; | |
a4b8ebc8 | 1817 | |
29639122 JB |
1818 | frame_reg = 30; |
1819 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); | |
1820 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); | |
1821 | if (alloca_adjust > 0) | |
1822 | { | |
1823 | /* FP > SP + frame_size. This may be because of | |
1824 | an alloca or somethings similar. Fix sp to | |
1825 | "pre-alloca" value, and try again. */ | |
1826 | sp += alloca_adjust; | |
1827 | /* Need to reset the status of all registers. Otherwise, | |
1828 | we will hit a guard that prevents the new address | |
1829 | for each register to be recomputed during the second | |
1830 | pass. */ | |
1831 | reset_saved_regs (this_cache); | |
1832 | goto restart; | |
1833 | } | |
1834 | } | |
1835 | } | |
1836 | /* move $30,$sp. With different versions of gas this will be either | |
1837 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1838 | Accept any one of these. */ | |
1839 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
1840 | { | |
1841 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
1842 | if (frame_reg == MIPS_SP_REGNUM) | |
1843 | { | |
1844 | unsigned alloca_adjust; | |
c906108c | 1845 | |
29639122 JB |
1846 | frame_reg = 30; |
1847 | frame_addr = read_next_frame_reg (next_frame, NUM_REGS + 30); | |
1848 | alloca_adjust = (unsigned) (frame_addr - sp); | |
1849 | if (alloca_adjust > 0) | |
1850 | { | |
1851 | /* FP > SP + frame_size. This may be because of | |
1852 | an alloca or somethings similar. Fix sp to | |
1853 | "pre-alloca" value, and try again. */ | |
1854 | sp = frame_addr; | |
1855 | /* Need to reset the status of all registers. Otherwise, | |
1856 | we will hit a guard that prevents the new address | |
1857 | for each register to be recomputed during the second | |
1858 | pass. */ | |
1859 | reset_saved_regs (this_cache); | |
1860 | goto restart; | |
1861 | } | |
1862 | } | |
1863 | } | |
1864 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ | |
1865 | { | |
1866 | set_reg_offset (this_cache, reg, frame_addr + low_word); | |
1867 | } | |
1868 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
1869 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
1870 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
1871 | || high_word == 0x3c1c /* lui $gp,n */ | |
1872 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
1873 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1874 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
1875 | ) | |
1876 | { | |
1877 | /* These instructions are part of the prologue, but we don't | |
1878 | need to do anything special to handle them. */ | |
1879 | } | |
1880 | /* The instructions below load $at or $t0 with an immediate | |
1881 | value in preparation for a stack adjustment via | |
1882 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
1883 | initialize a local variable, so we accept them only before | |
1884 | a stack adjustment instruction was seen. */ | |
1885 | else if (!seen_sp_adjust | |
1886 | && (high_word == 0x3c01 /* lui $at,n */ | |
1887 | || high_word == 0x3c08 /* lui $t0,n */ | |
1888 | || high_word == 0x3421 /* ori $at,$at,n */ | |
1889 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
1890 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
1891 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
1892 | )) | |
1893 | { | |
4c7d22cb | 1894 | load_immediate_bytes += MIPS32_INSN_SIZE; /* FIXME! */ |
29639122 JB |
1895 | } |
1896 | else | |
1897 | { | |
1898 | /* This instruction is not an instruction typically found | |
1899 | in a prologue, so we must have reached the end of the | |
1900 | prologue. */ | |
1901 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
1902 | loop now? Why would we need to continue scanning the function | |
1903 | instructions? */ | |
1904 | if (end_prologue_addr == 0) | |
1905 | end_prologue_addr = cur_pc; | |
1906 | } | |
a4b8ebc8 | 1907 | } |
c906108c | 1908 | |
29639122 JB |
1909 | if (this_cache != NULL) |
1910 | { | |
1911 | this_cache->base = | |
1912 | (frame_unwind_register_signed (next_frame, NUM_REGS + frame_reg) | |
1913 | + frame_offset); | |
1914 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
1915 | this assignment below, eventually. But it's still needed | |
1916 | for now. */ | |
1917 | this_cache->saved_regs[NUM_REGS + mips_regnum (current_gdbarch)->pc] | |
4c7d22cb | 1918 | = this_cache->saved_regs[NUM_REGS + MIPS_RA_REGNUM]; |
29639122 | 1919 | } |
c906108c | 1920 | |
29639122 JB |
1921 | /* If we didn't reach the end of the prologue when scanning the function |
1922 | instructions, then set end_prologue_addr to the address of the | |
1923 | instruction immediately after the last one we scanned. */ | |
1924 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
1925 | we may as well be careful and do our best if we have a null | |
1926 | end_prologue_addr. */ | |
1927 | if (end_prologue_addr == 0) | |
1928 | end_prologue_addr = cur_pc; | |
1929 | ||
1930 | /* In a frameless function, we might have incorrectly | |
1931 | skipped some load immediate instructions. Undo the skipping | |
1932 | if the load immediate was not followed by a stack adjustment. */ | |
1933 | if (load_immediate_bytes && !seen_sp_adjust) | |
1934 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 1935 | |
29639122 | 1936 | return end_prologue_addr; |
c906108c SS |
1937 | } |
1938 | ||
29639122 JB |
1939 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
1940 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
1941 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
1942 | unwinder. */ | |
c906108c | 1943 | |
29639122 JB |
1944 | static struct mips_frame_cache * |
1945 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 1946 | { |
29639122 | 1947 | struct mips_frame_cache *cache; |
c906108c | 1948 | |
29639122 JB |
1949 | if ((*this_cache) != NULL) |
1950 | return (*this_cache); | |
c5aa993b | 1951 | |
29639122 JB |
1952 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1953 | (*this_cache) = cache; | |
1954 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c5aa993b | 1955 | |
29639122 JB |
1956 | /* Analyze the function prologue. */ |
1957 | { | |
1958 | const CORE_ADDR pc = frame_pc_unwind (next_frame); | |
1959 | CORE_ADDR start_addr; | |
c906108c | 1960 | |
29639122 JB |
1961 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1962 | if (start_addr == 0) | |
1963 | start_addr = heuristic_proc_start (pc); | |
1964 | /* We can't analyze the prologue if we couldn't find the begining | |
1965 | of the function. */ | |
1966 | if (start_addr == 0) | |
1967 | return cache; | |
c5aa993b | 1968 | |
29639122 JB |
1969 | mips32_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1970 | } | |
1971 | ||
1972 | /* SP_REGNUM, contains the value and not the address. */ | |
1973 | trad_frame_set_value (cache->saved_regs, NUM_REGS + MIPS_SP_REGNUM, cache->base); | |
c5aa993b | 1974 | |
29639122 | 1975 | return (*this_cache); |
c906108c SS |
1976 | } |
1977 | ||
29639122 JB |
1978 | static void |
1979 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
1980 | struct frame_id *this_id) | |
c906108c | 1981 | { |
29639122 JB |
1982 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
1983 | this_cache); | |
1984 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
1985 | } | |
c906108c | 1986 | |
29639122 JB |
1987 | static void |
1988 | mips_insn32_frame_prev_register (struct frame_info *next_frame, | |
1989 | void **this_cache, | |
1990 | int regnum, int *optimizedp, | |
1991 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1992 | int *realnump, void *valuep) | |
1993 | { | |
1994 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, | |
1995 | this_cache); | |
1996 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1997 | optimizedp, lvalp, addrp, realnump, valuep); | |
c906108c SS |
1998 | } |
1999 | ||
29639122 JB |
2000 | static const struct frame_unwind mips_insn32_frame_unwind = |
2001 | { | |
2002 | NORMAL_FRAME, | |
2003 | mips_insn32_frame_this_id, | |
2004 | mips_insn32_frame_prev_register | |
2005 | }; | |
c906108c | 2006 | |
29639122 JB |
2007 | static const struct frame_unwind * |
2008 | mips_insn32_frame_sniffer (struct frame_info *next_frame) | |
2009 | { | |
2010 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
0fe7e7c8 | 2011 | if (! mips_pc_is_mips16 (pc)) |
29639122 JB |
2012 | return &mips_insn32_frame_unwind; |
2013 | return NULL; | |
2014 | } | |
c906108c | 2015 | |
1c645fec | 2016 | static CORE_ADDR |
29639122 JB |
2017 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
2018 | void **this_cache) | |
c906108c | 2019 | { |
29639122 JB |
2020 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2021 | this_cache); | |
2022 | return info->base; | |
2023 | } | |
c906108c | 2024 | |
29639122 JB |
2025 | static const struct frame_base mips_insn32_frame_base = |
2026 | { | |
2027 | &mips_insn32_frame_unwind, | |
2028 | mips_insn32_frame_base_address, | |
2029 | mips_insn32_frame_base_address, | |
2030 | mips_insn32_frame_base_address | |
2031 | }; | |
1c645fec | 2032 | |
29639122 JB |
2033 | static const struct frame_base * |
2034 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) | |
2035 | { | |
2036 | if (mips_insn32_frame_sniffer (next_frame) != NULL) | |
2037 | return &mips_insn32_frame_base; | |
a65bbe44 | 2038 | else |
29639122 JB |
2039 | return NULL; |
2040 | } | |
a65bbe44 | 2041 | |
29639122 JB |
2042 | static struct trad_frame_cache * |
2043 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2044 | { | |
2045 | CORE_ADDR pc; | |
2046 | CORE_ADDR start_addr; | |
2047 | CORE_ADDR stack_addr; | |
2048 | struct trad_frame_cache *this_trad_cache; | |
c906108c | 2049 | |
29639122 JB |
2050 | if ((*this_cache) != NULL) |
2051 | return (*this_cache); | |
2052 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2053 | (*this_cache) = this_trad_cache; | |
1c645fec | 2054 | |
29639122 | 2055 | /* The return address is in the link register. */ |
4c7d22cb | 2056 | trad_frame_set_reg_realreg (this_trad_cache, PC_REGNUM, MIPS_RA_REGNUM); |
1c645fec | 2057 | |
29639122 JB |
2058 | /* Frame ID, since it's a frameless / stackless function, no stack |
2059 | space is allocated and SP on entry is the current SP. */ | |
2060 | pc = frame_pc_unwind (next_frame); | |
2061 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
4c7d22cb | 2062 | stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM); |
29639122 | 2063 | trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); |
1c645fec | 2064 | |
29639122 JB |
2065 | /* Assume that the frame's base is the same as the |
2066 | stack-pointer. */ | |
2067 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2068 | |
29639122 JB |
2069 | return this_trad_cache; |
2070 | } | |
c906108c | 2071 | |
29639122 JB |
2072 | static void |
2073 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2074 | struct frame_id *this_id) | |
2075 | { | |
2076 | struct trad_frame_cache *this_trad_cache | |
2077 | = mips_stub_frame_cache (next_frame, this_cache); | |
2078 | trad_frame_get_id (this_trad_cache, this_id); | |
2079 | } | |
c906108c | 2080 | |
29639122 JB |
2081 | static void |
2082 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2083 | void **this_cache, | |
2084 | int regnum, int *optimizedp, | |
2085 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2086 | int *realnump, void *valuep) | |
2087 | { | |
2088 | struct trad_frame_cache *this_trad_cache | |
2089 | = mips_stub_frame_cache (next_frame, this_cache); | |
2090 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2091 | lvalp, addrp, realnump, valuep); | |
2092 | } | |
c906108c | 2093 | |
29639122 JB |
2094 | static const struct frame_unwind mips_stub_frame_unwind = |
2095 | { | |
2096 | NORMAL_FRAME, | |
2097 | mips_stub_frame_this_id, | |
2098 | mips_stub_frame_prev_register | |
2099 | }; | |
c906108c | 2100 | |
29639122 JB |
2101 | static const struct frame_unwind * |
2102 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2103 | { | |
2104 | CORE_ADDR pc = frame_pc_unwind (next_frame); | |
2105 | if (in_plt_section (pc, NULL)) | |
2106 | return &mips_stub_frame_unwind; | |
2107 | else | |
2108 | return NULL; | |
2109 | } | |
c906108c | 2110 | |
29639122 JB |
2111 | static CORE_ADDR |
2112 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2113 | void **this_cache) | |
2114 | { | |
2115 | struct trad_frame_cache *this_trad_cache | |
2116 | = mips_stub_frame_cache (next_frame, this_cache); | |
2117 | return trad_frame_get_this_base (this_trad_cache); | |
2118 | } | |
0fce0821 | 2119 | |
29639122 JB |
2120 | static const struct frame_base mips_stub_frame_base = |
2121 | { | |
2122 | &mips_stub_frame_unwind, | |
2123 | mips_stub_frame_base_address, | |
2124 | mips_stub_frame_base_address, | |
2125 | mips_stub_frame_base_address | |
2126 | }; | |
2127 | ||
2128 | static const struct frame_base * | |
2129 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2130 | { | |
2131 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2132 | return &mips_stub_frame_base; | |
2133 | else | |
2134 | return NULL; | |
2135 | } | |
2136 | ||
2137 | static CORE_ADDR | |
2138 | read_next_frame_reg (struct frame_info *fi, int regno) | |
2139 | { | |
2140 | /* Always a pseudo. */ | |
2141 | gdb_assert (regno >= NUM_REGS); | |
2142 | if (fi == NULL) | |
0fce0821 | 2143 | { |
29639122 JB |
2144 | LONGEST val; |
2145 | regcache_cooked_read_signed (current_regcache, regno, &val); | |
2146 | return val; | |
0fce0821 | 2147 | } |
29639122 JB |
2148 | else |
2149 | return frame_unwind_register_signed (fi, regno); | |
1c645fec | 2150 | |
c906108c SS |
2151 | } |
2152 | ||
29639122 | 2153 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2154 | |
29639122 JB |
2155 | static CORE_ADDR |
2156 | mips_addr_bits_remove (CORE_ADDR addr) | |
65596487 | 2157 | { |
29639122 JB |
2158 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2159 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
2160 | /* This hack is a work-around for existing boards using PMON, the | |
2161 | simulator, and any other 64-bit targets that doesn't have true | |
2162 | 64-bit addressing. On these targets, the upper 32 bits of | |
2163 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2164 | likely to have been sign extended to all 1s by instruction | |
2165 | sequences that load 32-bit addresses. For example, a typical | |
2166 | piece of code that loads an address is this: | |
65596487 | 2167 | |
29639122 JB |
2168 | lui $r2, <upper 16 bits> |
2169 | ori $r2, <lower 16 bits> | |
65596487 | 2170 | |
29639122 JB |
2171 | But the lui sign-extends the value such that the upper 32 bits |
2172 | may be all 1s. The workaround is simply to mask off these | |
2173 | bits. In the future, gcc may be changed to support true 64-bit | |
2174 | addressing, and this masking will have to be disabled. */ | |
2175 | return addr &= 0xffffffffUL; | |
2176 | else | |
2177 | return addr; | |
65596487 JB |
2178 | } |
2179 | ||
29639122 JB |
2180 | /* mips_software_single_step() is called just before we want to resume |
2181 | the inferior, if we want to single-step it but there is no hardware | |
2182 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
2183 | the target of the coming instruction and breakpoint it. | |
1e05a7bf | 2184 | |
29639122 JB |
2185 | single_step is also called just after the inferior stops. If we had |
2186 | set up a simulated single-step, we undo our damage. */ | |
2187 | ||
2188 | void | |
2189 | mips_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
c906108c | 2190 | { |
29639122 JB |
2191 | static CORE_ADDR next_pc; |
2192 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
2193 | static binsn_quantum break_mem; | |
2194 | CORE_ADDR pc; | |
65596487 | 2195 | |
29639122 JB |
2196 | if (insert_breakpoints_p) |
2197 | { | |
2198 | pc = read_register (mips_regnum (current_gdbarch)->pc); | |
2199 | next_pc = mips_next_pc (pc); | |
98b4dd94 | 2200 | |
29639122 JB |
2201 | target_insert_breakpoint (next_pc, break_mem); |
2202 | } | |
a65bbe44 | 2203 | else |
29639122 JB |
2204 | target_remove_breakpoint (next_pc, break_mem); |
2205 | } | |
a65bbe44 | 2206 | |
29639122 | 2207 | static struct mips_extra_func_info temp_proc_desc; |
a65bbe44 | 2208 | |
29639122 JB |
2209 | /* Test whether the PC points to the return instruction at the |
2210 | end of a function. */ | |
65596487 | 2211 | |
29639122 JB |
2212 | static int |
2213 | mips_about_to_return (CORE_ADDR pc) | |
2214 | { | |
0fe7e7c8 | 2215 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2216 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2217 | generates a "jr $ra"; other times it generates code to load | |
2218 | the return address from the stack to an accessible register (such | |
2219 | as $a3), then a "jr" using that register. This second case | |
2220 | is almost impossible to distinguish from an indirect jump | |
2221 | used for switch statements, so we don't even try. */ | |
2222 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2223 | else | |
2224 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2225 | } | |
c906108c | 2226 | |
c906108c | 2227 | |
29639122 JB |
2228 | /* This fencepost looks highly suspicious to me. Removing it also |
2229 | seems suspicious as it could affect remote debugging across serial | |
2230 | lines. */ | |
c906108c | 2231 | |
29639122 JB |
2232 | static CORE_ADDR |
2233 | heuristic_proc_start (CORE_ADDR pc) | |
2234 | { | |
2235 | CORE_ADDR start_pc; | |
2236 | CORE_ADDR fence; | |
2237 | int instlen; | |
2238 | int seen_adjsp = 0; | |
65596487 | 2239 | |
29639122 JB |
2240 | pc = ADDR_BITS_REMOVE (pc); |
2241 | start_pc = pc; | |
2242 | fence = start_pc - heuristic_fence_post; | |
2243 | if (start_pc == 0) | |
2244 | return 0; | |
65596487 | 2245 | |
29639122 JB |
2246 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2247 | fence = VM_MIN_ADDRESS; | |
65596487 | 2248 | |
0fe7e7c8 | 2249 | instlen = mips_pc_is_mips16 (pc) ? MIPS16_INSN_SIZE : MIPS32_INSN_SIZE; |
98b4dd94 | 2250 | |
29639122 JB |
2251 | /* search back for previous return */ |
2252 | for (start_pc -= instlen;; start_pc -= instlen) | |
2253 | if (start_pc < fence) | |
2254 | { | |
2255 | /* It's not clear to me why we reach this point when | |
2256 | stop_soon, but with this test, at least we | |
2257 | don't print out warnings for every child forked (eg, on | |
2258 | decstation). 22apr93 rich@cygnus.com. */ | |
2259 | if (stop_soon == NO_STOP_QUIETLY) | |
2260 | { | |
2261 | static int blurb_printed = 0; | |
98b4dd94 | 2262 | |
29639122 JB |
2263 | warning ("GDB can't find the start of the function at 0x%s.", |
2264 | paddr_nz (pc)); | |
2265 | ||
2266 | if (!blurb_printed) | |
2267 | { | |
2268 | /* This actually happens frequently in embedded | |
2269 | development, when you first connect to a board | |
2270 | and your stack pointer and pc are nowhere in | |
2271 | particular. This message needs to give people | |
2272 | in that situation enough information to | |
2273 | determine that it's no big deal. */ | |
2274 | printf_filtered ("\n\ | |
2275 | GDB is unable to find the start of the function at 0x%s\n\ | |
2276 | and thus can't determine the size of that function's stack frame.\n\ | |
2277 | This means that GDB may be unable to access that stack frame, or\n\ | |
2278 | the frames below it.\n\ | |
2279 | This problem is most likely caused by an invalid program counter or\n\ | |
2280 | stack pointer.\n\ | |
2281 | However, if you think GDB should simply search farther back\n\ | |
2282 | from 0x%s for code which looks like the beginning of a\n\ | |
2283 | function, you can increase the range of the search using the `set\n\ | |
2284 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); | |
2285 | blurb_printed = 1; | |
2286 | } | |
2287 | } | |
2288 | ||
2289 | return 0; | |
2290 | } | |
0fe7e7c8 | 2291 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2292 | { |
2293 | unsigned short inst; | |
2294 | ||
2295 | /* On MIPS16, any one of the following is likely to be the | |
2296 | start of a function: | |
2297 | entry | |
2298 | addiu sp,-n | |
2299 | daddiu sp,-n | |
2300 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2301 | inst = mips_fetch_instruction (start_pc); | |
2302 | if (((inst & 0xf81f) == 0xe809 && (inst & 0x700) != 0x700) /* entry */ | |
2303 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2304 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2305 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
2306 | break; | |
2307 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2308 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2309 | seen_adjsp = 1; | |
2310 | else | |
2311 | seen_adjsp = 0; | |
2312 | } | |
2313 | else if (mips_about_to_return (start_pc)) | |
2314 | { | |
4c7d22cb MK |
2315 | /* Skip return and its delay slot. */ |
2316 | start_pc += 2 * MIPS32_INSN_SIZE; | |
29639122 JB |
2317 | break; |
2318 | } | |
2319 | ||
2320 | return start_pc; | |
c906108c SS |
2321 | } |
2322 | ||
6c0d6680 DJ |
2323 | struct mips_objfile_private |
2324 | { | |
2325 | bfd_size_type size; | |
2326 | char *contents; | |
2327 | }; | |
2328 | ||
c906108c SS |
2329 | /* MIPS stack frames are almost impenetrable. When execution stops, |
2330 | we basically have to look at symbol information for the function | |
2331 | that we stopped in, which tells us *which* register (if any) is | |
2332 | the base of the frame pointer, and what offset from that register | |
361d1df0 | 2333 | the frame itself is at. |
c906108c SS |
2334 | |
2335 | This presents a problem when trying to examine a stack in memory | |
2336 | (that isn't executing at the moment), using the "frame" command. We | |
2337 | don't have a PC, nor do we have any registers except SP. | |
2338 | ||
2339 | This routine takes two arguments, SP and PC, and tries to make the | |
2340 | cached frames look as if these two arguments defined a frame on the | |
2341 | cache. This allows the rest of info frame to extract the important | |
2342 | arguments without difficulty. */ | |
2343 | ||
2344 | struct frame_info * | |
acdb74a0 | 2345 | setup_arbitrary_frame (int argc, CORE_ADDR *argv) |
c906108c SS |
2346 | { |
2347 | if (argc != 2) | |
2348 | error ("MIPS frame specifications require two arguments: sp and pc"); | |
2349 | ||
2350 | return create_new_frame (argv[0], argv[1]); | |
2351 | } | |
2352 | ||
f09ded24 AC |
2353 | /* According to the current ABI, should the type be passed in a |
2354 | floating-point register (assuming that there is space)? When there | |
2355 | is no FPU, FP are not even considered as possibile candidates for | |
2356 | FP registers and, consequently this returns false - forces FP | |
2357 | arguments into integer registers. */ | |
2358 | ||
2359 | static int | |
2360 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2361 | { | |
2362 | return ((typecode == TYPE_CODE_FLT | |
2363 | || (MIPS_EABI | |
6d82d43b AC |
2364 | && (typecode == TYPE_CODE_STRUCT |
2365 | || typecode == TYPE_CODE_UNION) | |
f09ded24 AC |
2366 | && TYPE_NFIELDS (arg_type) == 1 |
2367 | && TYPE_CODE (TYPE_FIELD_TYPE (arg_type, 0)) == TYPE_CODE_FLT)) | |
c86b5b38 | 2368 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2369 | } |
2370 | ||
49e790b0 DJ |
2371 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2372 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2373 | ||
2374 | static int | |
2375 | mips_type_needs_double_align (struct type *type) | |
2376 | { | |
2377 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2378 | |
49e790b0 DJ |
2379 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2380 | return 1; | |
2381 | else if (typecode == TYPE_CODE_STRUCT) | |
2382 | { | |
2383 | if (TYPE_NFIELDS (type) < 1) | |
2384 | return 0; | |
2385 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2386 | } | |
2387 | else if (typecode == TYPE_CODE_UNION) | |
2388 | { | |
361d1df0 | 2389 | int i, n; |
49e790b0 DJ |
2390 | |
2391 | n = TYPE_NFIELDS (type); | |
2392 | for (i = 0; i < n; i++) | |
2393 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2394 | return 1; | |
2395 | return 0; | |
2396 | } | |
2397 | return 0; | |
2398 | } | |
2399 | ||
dc604539 AC |
2400 | /* Adjust the address downward (direction of stack growth) so that it |
2401 | is correctly aligned for a new stack frame. */ | |
2402 | static CORE_ADDR | |
2403 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2404 | { | |
5b03f266 | 2405 | return align_down (addr, 16); |
dc604539 AC |
2406 | } |
2407 | ||
f7ab6ec6 | 2408 | static CORE_ADDR |
7d9b040b | 2409 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2410 | struct regcache *regcache, CORE_ADDR bp_addr, |
2411 | int nargs, struct value **args, CORE_ADDR sp, | |
2412 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2413 | { |
2414 | int argreg; | |
2415 | int float_argreg; | |
2416 | int argnum; | |
2417 | int len = 0; | |
2418 | int stack_offset = 0; | |
480d3dd2 | 2419 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2420 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 2421 | |
25ab4790 AC |
2422 | /* For shared libraries, "t9" needs to point at the function |
2423 | address. */ | |
4c7d22cb | 2424 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2425 | |
2426 | /* Set the return address register to point to the entry point of | |
2427 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2428 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2429 | |
c906108c | 2430 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2431 | are properly aligned. The stack has to be at least 64-bit |
2432 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2433 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2434 | aligned, so we round to this widest known alignment. */ | |
2435 | ||
5b03f266 AC |
2436 | sp = align_down (sp, 16); |
2437 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2438 | |
46e0f506 | 2439 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2440 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2441 | passed in registers, but that's OK. */ |
c906108c | 2442 | for (argnum = 0; argnum < nargs; argnum++) |
6d82d43b | 2443 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 2444 | mips_stack_argsize (gdbarch)); |
5b03f266 | 2445 | sp -= align_up (len, 16); |
c906108c | 2446 | |
9ace0497 | 2447 | if (mips_debug) |
6d82d43b | 2448 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2449 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2450 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2451 | |
c906108c | 2452 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2453 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2454 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2455 | |
46e0f506 | 2456 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2457 | if (struct_return) |
9ace0497 AC |
2458 | { |
2459 | if (mips_debug) | |
2460 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2461 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2462 | argreg, paddr_nz (struct_addr)); |
9ace0497 AC |
2463 | write_register (argreg++, struct_addr); |
2464 | } | |
c906108c SS |
2465 | |
2466 | /* Now load as many as possible of the first arguments into | |
2467 | registers, and push the rest onto the stack. Loop thru args | |
2468 | from first to last. */ | |
2469 | for (argnum = 0; argnum < nargs; argnum++) | |
2470 | { | |
2471 | char *val; | |
d9d9c31f | 2472 | char valbuf[MAX_REGISTER_SIZE]; |
ea7c478f | 2473 | struct value *arg = args[argnum]; |
c906108c SS |
2474 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); |
2475 | int len = TYPE_LENGTH (arg_type); | |
2476 | enum type_code typecode = TYPE_CODE (arg_type); | |
2477 | ||
9ace0497 AC |
2478 | if (mips_debug) |
2479 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2480 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2481 | argnum + 1, len, (int) typecode); |
9ace0497 | 2482 | |
c906108c | 2483 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2484 | reference. */ |
13326b4e | 2485 | if (len > mips_abi_regsize (gdbarch) |
9ace0497 | 2486 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2487 | { |
13326b4e | 2488 | store_unsigned_integer (valbuf, mips_abi_regsize (gdbarch), |
480d3dd2 | 2489 | VALUE_ADDRESS (arg)); |
c906108c | 2490 | typecode = TYPE_CODE_PTR; |
13326b4e | 2491 | len = mips_abi_regsize (gdbarch); |
c906108c | 2492 | val = valbuf; |
9ace0497 AC |
2493 | if (mips_debug) |
2494 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2495 | } |
2496 | else | |
c5aa993b | 2497 | val = (char *) VALUE_CONTENTS (arg); |
c906108c SS |
2498 | |
2499 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2500 | even-numbered floating point register. Round the FP register |
2501 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2502 | left. Non MIPS_EABI targets also pass the FP in the integer |
2503 | registers so also round up normal registers. */ | |
ceae6e75 AC |
2504 | if (mips_abi_regsize (gdbarch) < 8 |
2505 | && fp_register_arg_p (typecode, arg_type)) | |
acdb74a0 AC |
2506 | { |
2507 | if ((float_argreg & 1)) | |
2508 | float_argreg++; | |
2509 | } | |
c906108c SS |
2510 | |
2511 | /* Floating point arguments passed in registers have to be | |
2512 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2513 | are passed in register pairs; the even register gets |
2514 | the low word, and the odd register gets the high word. | |
2515 | On non-EABI processors, the first two floating point arguments are | |
2516 | also copied to general registers, because MIPS16 functions | |
2517 | don't use float registers for arguments. This duplication of | |
2518 | arguments in general registers can't hurt non-MIPS16 functions | |
2519 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2520 | /* MIPS_EABI squeezes a struct that contains a single floating |
2521 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2522 | stack. */ |
f09ded24 AC |
2523 | if (fp_register_arg_p (typecode, arg_type) |
2524 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 2525 | { |
ceae6e75 | 2526 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
c906108c | 2527 | { |
d7449b42 | 2528 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; |
c906108c SS |
2529 | unsigned long regval; |
2530 | ||
2531 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2532 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2533 | if (mips_debug) |
acdb74a0 | 2534 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2535 | float_argreg, phex (regval, 4)); |
c906108c | 2536 | write_register (float_argreg++, regval); |
c906108c SS |
2537 | |
2538 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2539 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2540 | if (mips_debug) |
acdb74a0 | 2541 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2542 | float_argreg, phex (regval, 4)); |
c906108c | 2543 | write_register (float_argreg++, regval); |
c906108c SS |
2544 | } |
2545 | else | |
2546 | { | |
2547 | /* This is a floating point value that fits entirely | |
2548 | in a single register. */ | |
53a5351d | 2549 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2550 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2551 | LONGEST regval = extract_unsigned_integer (val, len); |
2552 | if (mips_debug) | |
acdb74a0 | 2553 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2554 | float_argreg, phex (regval, len)); |
c906108c | 2555 | write_register (float_argreg++, regval); |
c906108c SS |
2556 | } |
2557 | } | |
2558 | else | |
2559 | { | |
2560 | /* Copy the argument to general registers or the stack in | |
2561 | register-sized pieces. Large arguments are split between | |
2562 | registers and stack. */ | |
4246e332 | 2563 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
2564 | mips_abi_regsize() are treated specially: Irix cc passes |
2565 | them in registers where gcc sometimes puts them on the | |
2566 | stack. For maximum compatibility, we will put them in | |
2567 | both places. */ | |
13326b4e AC |
2568 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
2569 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46e0f506 | 2570 | |
f09ded24 | 2571 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2572 | register are only written to memory. */ |
c906108c SS |
2573 | while (len > 0) |
2574 | { | |
ebafbe83 | 2575 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2576 | int stack_used_p = 0; |
13326b4e AC |
2577 | int partial_len = (len < mips_abi_regsize (gdbarch) |
2578 | ? len : mips_abi_regsize (gdbarch)); | |
c906108c | 2579 | |
acdb74a0 AC |
2580 | if (mips_debug) |
2581 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2582 | partial_len); | |
2583 | ||
566f0f7a | 2584 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2585 | if (argreg > MIPS_LAST_ARG_REGNUM |
2586 | || odd_sized_struct | |
2587 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2588 | { |
c906108c SS |
2589 | /* Should shorter than int integer values be |
2590 | promoted to int before being stored? */ | |
c906108c | 2591 | int longword_offset = 0; |
9ace0497 | 2592 | CORE_ADDR addr; |
566f0f7a | 2593 | stack_used_p = 1; |
d7449b42 | 2594 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
7a292a7a | 2595 | { |
13326b4e | 2596 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
2597 | && (typecode == TYPE_CODE_INT |
2598 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2599 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 2600 | longword_offset = mips_stack_argsize (gdbarch) - len; |
480d3dd2 AC |
2601 | else if ((typecode == TYPE_CODE_STRUCT |
2602 | || typecode == TYPE_CODE_UNION) | |
2603 | && (TYPE_LENGTH (arg_type) | |
13326b4e AC |
2604 | < mips_stack_argsize (gdbarch))) |
2605 | longword_offset = mips_stack_argsize (gdbarch) - len; | |
7a292a7a | 2606 | } |
c5aa993b | 2607 | |
9ace0497 AC |
2608 | if (mips_debug) |
2609 | { | |
cb3d25d1 MS |
2610 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2611 | paddr_nz (stack_offset)); | |
2612 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2613 | paddr_nz (longword_offset)); | |
9ace0497 | 2614 | } |
361d1df0 | 2615 | |
9ace0497 AC |
2616 | addr = sp + stack_offset + longword_offset; |
2617 | ||
2618 | if (mips_debug) | |
2619 | { | |
2620 | int i; | |
6d82d43b | 2621 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 2622 | paddr_nz (addr)); |
9ace0497 AC |
2623 | for (i = 0; i < partial_len; i++) |
2624 | { | |
6d82d43b | 2625 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2626 | val[i] & 0xff); |
9ace0497 AC |
2627 | } |
2628 | } | |
2629 | write_memory (addr, val, partial_len); | |
c906108c SS |
2630 | } |
2631 | ||
f09ded24 AC |
2632 | /* Note!!! This is NOT an else clause. Odd sized |
2633 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2634 | arguments will not. */ |
566f0f7a | 2635 | /* Write this portion of the argument to a general |
6d82d43b | 2636 | purpose register. */ |
f09ded24 AC |
2637 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2638 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2639 | { |
6d82d43b AC |
2640 | LONGEST regval = |
2641 | extract_unsigned_integer (val, partial_len); | |
c906108c | 2642 | |
9ace0497 | 2643 | if (mips_debug) |
acdb74a0 | 2644 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2645 | argreg, |
6d82d43b | 2646 | phex (regval, |
13326b4e | 2647 | mips_abi_regsize (gdbarch))); |
c906108c SS |
2648 | write_register (argreg, regval); |
2649 | argreg++; | |
c906108c | 2650 | } |
c5aa993b | 2651 | |
c906108c SS |
2652 | len -= partial_len; |
2653 | val += partial_len; | |
2654 | ||
566f0f7a | 2655 | /* Compute the the offset into the stack at which we |
6d82d43b | 2656 | will copy the next parameter. |
566f0f7a | 2657 | |
566f0f7a | 2658 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2659 | only needs to be adjusted when it has been used. */ |
c906108c | 2660 | |
46e0f506 | 2661 | if (stack_used_p) |
480d3dd2 | 2662 | stack_offset += align_up (partial_len, |
13326b4e | 2663 | mips_stack_argsize (gdbarch)); |
c906108c SS |
2664 | } |
2665 | } | |
9ace0497 AC |
2666 | if (mips_debug) |
2667 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2668 | } |
2669 | ||
f10683bb | 2670 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2671 | |
0f71a2f6 JM |
2672 | /* Return adjusted stack pointer. */ |
2673 | return sp; | |
2674 | } | |
2675 | ||
9c8fdbfa | 2676 | /* Determin the return value convention being used. */ |
6d82d43b | 2677 | |
9c8fdbfa AC |
2678 | static enum return_value_convention |
2679 | mips_eabi_return_value (struct gdbarch *gdbarch, | |
2680 | struct type *type, struct regcache *regcache, | |
2681 | void *readbuf, const void *writebuf) | |
6d82d43b | 2682 | { |
9c8fdbfa AC |
2683 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2684 | return RETURN_VALUE_STRUCT_CONVENTION; | |
2685 | if (readbuf) | |
2686 | memset (readbuf, 0, TYPE_LENGTH (type)); | |
2687 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6d82d43b AC |
2688 | } |
2689 | ||
6d82d43b AC |
2690 | |
2691 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 2692 | |
f7ab6ec6 | 2693 | static CORE_ADDR |
7d9b040b | 2694 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2695 | struct regcache *regcache, CORE_ADDR bp_addr, |
2696 | int nargs, struct value **args, CORE_ADDR sp, | |
2697 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2698 | { |
2699 | int argreg; | |
2700 | int float_argreg; | |
2701 | int argnum; | |
2702 | int len = 0; | |
2703 | int stack_offset = 0; | |
480d3dd2 | 2704 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2705 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 2706 | |
25ab4790 AC |
2707 | /* For shared libraries, "t9" needs to point at the function |
2708 | address. */ | |
4c7d22cb | 2709 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2710 | |
2711 | /* Set the return address register to point to the entry point of | |
2712 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2713 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2714 | |
cb3d25d1 MS |
2715 | /* First ensure that the stack and structure return address (if any) |
2716 | are properly aligned. The stack has to be at least 64-bit | |
2717 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2718 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2719 | aligned, so we round to this widest known alignment. */ | |
2720 | ||
5b03f266 AC |
2721 | sp = align_down (sp, 16); |
2722 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
2723 | |
2724 | /* Now make space on the stack for the args. */ | |
2725 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 2726 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 2727 | mips_stack_argsize (gdbarch)); |
5b03f266 | 2728 | sp -= align_up (len, 16); |
cb3d25d1 MS |
2729 | |
2730 | if (mips_debug) | |
6d82d43b | 2731 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2732 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
2733 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
2734 | |
2735 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 2736 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2737 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 2738 | |
46e0f506 | 2739 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
2740 | if (struct_return) |
2741 | { | |
2742 | if (mips_debug) | |
2743 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2744 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 MS |
2745 | argreg, paddr_nz (struct_addr)); |
2746 | write_register (argreg++, struct_addr); | |
2747 | } | |
2748 | ||
2749 | /* Now load as many as possible of the first arguments into | |
2750 | registers, and push the rest onto the stack. Loop thru args | |
2751 | from first to last. */ | |
2752 | for (argnum = 0; argnum < nargs; argnum++) | |
2753 | { | |
2754 | char *val; | |
cb3d25d1 MS |
2755 | struct value *arg = args[argnum]; |
2756 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
2757 | int len = TYPE_LENGTH (arg_type); | |
2758 | enum type_code typecode = TYPE_CODE (arg_type); | |
2759 | ||
2760 | if (mips_debug) | |
2761 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2762 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
2763 | argnum + 1, len, (int) typecode); |
2764 | ||
2765 | val = (char *) VALUE_CONTENTS (arg); | |
2766 | ||
2767 | if (fp_register_arg_p (typecode, arg_type) | |
2768 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
2769 | { | |
2770 | /* This is a floating point value that fits entirely | |
2771 | in a single register. */ | |
2772 | /* On 32 bit ABI's the float_argreg is further adjusted | |
2773 | above to ensure that it is even register aligned. */ | |
2774 | LONGEST regval = extract_unsigned_integer (val, len); | |
2775 | if (mips_debug) | |
2776 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
2777 | float_argreg, phex (regval, len)); | |
2778 | write_register (float_argreg++, regval); | |
2779 | ||
2780 | if (mips_debug) | |
2781 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
2782 | argreg, phex (regval, len)); | |
2783 | write_register (argreg, regval); | |
2784 | argreg += 1; | |
2785 | } | |
2786 | else | |
2787 | { | |
2788 | /* Copy the argument to general registers or the stack in | |
2789 | register-sized pieces. Large arguments are split between | |
2790 | registers and stack. */ | |
4246e332 | 2791 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
2792 | mips_abi_regsize() are treated specially: Irix cc passes |
2793 | them in registers where gcc sometimes puts them on the | |
2794 | stack. For maximum compatibility, we will put them in | |
2795 | both places. */ | |
13326b4e AC |
2796 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
2797 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
cb3d25d1 | 2798 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2799 | register are only written to memory. */ |
cb3d25d1 MS |
2800 | while (len > 0) |
2801 | { | |
2802 | /* Rememer if the argument was written to the stack. */ | |
2803 | int stack_used_p = 0; | |
13326b4e AC |
2804 | int partial_len = (len < mips_abi_regsize (gdbarch) |
2805 | ? len : mips_abi_regsize (gdbarch)); | |
cb3d25d1 MS |
2806 | |
2807 | if (mips_debug) | |
2808 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2809 | partial_len); | |
2810 | ||
2811 | /* Write this portion of the argument to the stack. */ | |
2812 | if (argreg > MIPS_LAST_ARG_REGNUM | |
2813 | || odd_sized_struct | |
2814 | || fp_register_arg_p (typecode, arg_type)) | |
2815 | { | |
2816 | /* Should shorter than int integer values be | |
2817 | promoted to int before being stored? */ | |
2818 | int longword_offset = 0; | |
2819 | CORE_ADDR addr; | |
2820 | stack_used_p = 1; | |
2821 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2822 | { | |
13326b4e | 2823 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
2824 | && (typecode == TYPE_CODE_INT |
2825 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2826 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 2827 | longword_offset = mips_stack_argsize (gdbarch) - len; |
cb3d25d1 MS |
2828 | } |
2829 | ||
2830 | if (mips_debug) | |
2831 | { | |
2832 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
2833 | paddr_nz (stack_offset)); | |
2834 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2835 | paddr_nz (longword_offset)); | |
2836 | } | |
2837 | ||
2838 | addr = sp + stack_offset + longword_offset; | |
2839 | ||
2840 | if (mips_debug) | |
2841 | { | |
2842 | int i; | |
6d82d43b | 2843 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
2844 | paddr_nz (addr)); |
2845 | for (i = 0; i < partial_len; i++) | |
2846 | { | |
6d82d43b | 2847 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
2848 | val[i] & 0xff); |
2849 | } | |
2850 | } | |
2851 | write_memory (addr, val, partial_len); | |
2852 | } | |
2853 | ||
2854 | /* Note!!! This is NOT an else clause. Odd sized | |
2855 | structs may go thru BOTH paths. Floating point | |
2856 | arguments will not. */ | |
2857 | /* Write this portion of the argument to a general | |
6d82d43b | 2858 | purpose register. */ |
cb3d25d1 MS |
2859 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2860 | && !fp_register_arg_p (typecode, arg_type)) | |
2861 | { | |
6d82d43b AC |
2862 | LONGEST regval = |
2863 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
2864 | |
2865 | /* A non-floating-point argument being passed in a | |
2866 | general register. If a struct or union, and if | |
2867 | the remaining length is smaller than the register | |
2868 | size, we have to adjust the register value on | |
2869 | big endian targets. | |
2870 | ||
2871 | It does not seem to be necessary to do the | |
2872 | same for integral types. | |
2873 | ||
2874 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
2875 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 2876 | mips_abi_regsize(), generates a left shift as |
cb3d25d1 MS |
2877 | part of storing the argument in a register a |
2878 | register (the left shift isn't generated when | |
1b13c4f6 | 2879 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
2880 | it is quite possible that this is GCC |
2881 | contradicting the LE/O32 ABI, GDB has not been | |
2882 | adjusted to accommodate this. Either someone | |
2883 | needs to demonstrate that the LE/O32 ABI | |
2884 | specifies such a left shift OR this new ABI gets | |
2885 | identified as such and GDB gets tweaked | |
2886 | accordingly. */ | |
cb3d25d1 MS |
2887 | |
2888 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
13326b4e | 2889 | && partial_len < mips_abi_regsize (gdbarch) |
cb3d25d1 MS |
2890 | && (typecode == TYPE_CODE_STRUCT || |
2891 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 2892 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
cb3d25d1 MS |
2893 | TARGET_CHAR_BIT); |
2894 | ||
2895 | if (mips_debug) | |
2896 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
2897 | argreg, | |
6d82d43b | 2898 | phex (regval, |
13326b4e | 2899 | mips_abi_regsize (gdbarch))); |
cb3d25d1 MS |
2900 | write_register (argreg, regval); |
2901 | argreg++; | |
2902 | } | |
2903 | ||
2904 | len -= partial_len; | |
2905 | val += partial_len; | |
2906 | ||
2907 | /* Compute the the offset into the stack at which we | |
6d82d43b | 2908 | will copy the next parameter. |
cb3d25d1 MS |
2909 | |
2910 | In N32 (N64?), the stack_offset only needs to be | |
2911 | adjusted when it has been used. */ | |
2912 | ||
2913 | if (stack_used_p) | |
480d3dd2 | 2914 | stack_offset += align_up (partial_len, |
13326b4e | 2915 | mips_stack_argsize (gdbarch)); |
cb3d25d1 MS |
2916 | } |
2917 | } | |
2918 | if (mips_debug) | |
2919 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
2920 | } | |
2921 | ||
f10683bb | 2922 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2923 | |
cb3d25d1 MS |
2924 | /* Return adjusted stack pointer. */ |
2925 | return sp; | |
2926 | } | |
2927 | ||
6d82d43b AC |
2928 | static enum return_value_convention |
2929 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
2930 | struct type *type, struct regcache *regcache, | |
2931 | void *readbuf, const void *writebuf) | |
ebafbe83 | 2932 | { |
6d82d43b AC |
2933 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2934 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2935 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
2936 | || TYPE_CODE (type) == TYPE_CODE_ARRAY | |
13326b4e | 2937 | || TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
6d82d43b AC |
2938 | return RETURN_VALUE_STRUCT_CONVENTION; |
2939 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
2940 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
2941 | { | |
2942 | /* A floating-point value belongs in the least significant part | |
2943 | of FP0. */ | |
2944 | if (mips_debug) | |
2945 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
2946 | mips_xfer_register (regcache, | |
2947 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
2948 | TYPE_LENGTH (type), | |
2949 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
2950 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2951 | } | |
2952 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2953 | && TYPE_NFIELDS (type) <= 2 | |
2954 | && TYPE_NFIELDS (type) >= 1 | |
2955 | && ((TYPE_NFIELDS (type) == 1 | |
2956 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
2957 | == TYPE_CODE_FLT)) | |
2958 | || (TYPE_NFIELDS (type) == 2 | |
2959 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
2960 | == TYPE_CODE_FLT) | |
2961 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
2962 | == TYPE_CODE_FLT))) | |
2963 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
2964 | { | |
2965 | /* A struct that contains one or two floats. Each value is part | |
2966 | in the least significant part of their floating point | |
2967 | register.. */ | |
6d82d43b AC |
2968 | int regnum; |
2969 | int field; | |
2970 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
2971 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
2972 | { | |
2973 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
2974 | / TARGET_CHAR_BIT); | |
2975 | if (mips_debug) | |
2976 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
2977 | offset); | |
2978 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
2979 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
2980 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
2981 | } | |
2982 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2983 | } | |
2984 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
2985 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
2986 | { | |
2987 | /* A structure or union. Extract the left justified value, | |
2988 | regardless of the byte order. I.e. DO NOT USE | |
2989 | mips_xfer_lower. */ | |
2990 | int offset; | |
2991 | int regnum; | |
4c7d22cb | 2992 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
2993 | offset < TYPE_LENGTH (type); |
2994 | offset += register_size (current_gdbarch, regnum), regnum++) | |
2995 | { | |
2996 | int xfer = register_size (current_gdbarch, regnum); | |
2997 | if (offset + xfer > TYPE_LENGTH (type)) | |
2998 | xfer = TYPE_LENGTH (type) - offset; | |
2999 | if (mips_debug) | |
3000 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3001 | offset, xfer, regnum); | |
3002 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3003 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3004 | } | |
3005 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3006 | } | |
3007 | else | |
3008 | { | |
3009 | /* A scalar extract each part but least-significant-byte | |
3010 | justified. */ | |
3011 | int offset; | |
3012 | int regnum; | |
4c7d22cb | 3013 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3014 | offset < TYPE_LENGTH (type); |
3015 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3016 | { | |
3017 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
3018 | if (offset + xfer > TYPE_LENGTH (type)) |
3019 | xfer = TYPE_LENGTH (type) - offset; | |
3020 | if (mips_debug) | |
3021 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3022 | offset, xfer, regnum); | |
3023 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3024 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3025 | } | |
3026 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3027 | } | |
3028 | } | |
3029 | ||
3030 | /* O32 ABI stuff. */ | |
3031 | ||
3032 | static CORE_ADDR | |
7d9b040b | 3033 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3034 | struct regcache *regcache, CORE_ADDR bp_addr, |
3035 | int nargs, struct value **args, CORE_ADDR sp, | |
3036 | int struct_return, CORE_ADDR struct_addr) | |
3037 | { | |
3038 | int argreg; | |
3039 | int float_argreg; | |
3040 | int argnum; | |
3041 | int len = 0; | |
3042 | int stack_offset = 0; | |
3043 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3044 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3045 | |
3046 | /* For shared libraries, "t9" needs to point at the function | |
3047 | address. */ | |
4c7d22cb | 3048 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3049 | |
3050 | /* Set the return address register to point to the entry point of | |
3051 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3052 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3053 | |
3054 | /* First ensure that the stack and structure return address (if any) | |
3055 | are properly aligned. The stack has to be at least 64-bit | |
3056 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3057 | aligned. For n32 and n64, stack frames need to be 128-bit |
3058 | aligned, so we round to this widest known alignment. */ | |
3059 | ||
5b03f266 AC |
3060 | sp = align_down (sp, 16); |
3061 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3062 | |
3063 | /* Now make space on the stack for the args. */ | |
3064 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3065 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3066 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3067 | sp -= align_up (len, 16); |
ebafbe83 MS |
3068 | |
3069 | if (mips_debug) | |
6d82d43b | 3070 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3071 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3072 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3073 | |
3074 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3075 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3076 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3077 | |
bcb0cc15 | 3078 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3079 | if (struct_return) |
3080 | { | |
3081 | if (mips_debug) | |
3082 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3083 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 MS |
3084 | argreg, paddr_nz (struct_addr)); |
3085 | write_register (argreg++, struct_addr); | |
13326b4e | 3086 | stack_offset += mips_stack_argsize (gdbarch); |
ebafbe83 MS |
3087 | } |
3088 | ||
3089 | /* Now load as many as possible of the first arguments into | |
3090 | registers, and push the rest onto the stack. Loop thru args | |
3091 | from first to last. */ | |
3092 | for (argnum = 0; argnum < nargs; argnum++) | |
3093 | { | |
3094 | char *val; | |
ebafbe83 MS |
3095 | struct value *arg = args[argnum]; |
3096 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3097 | int len = TYPE_LENGTH (arg_type); | |
3098 | enum type_code typecode = TYPE_CODE (arg_type); | |
3099 | ||
3100 | if (mips_debug) | |
3101 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3102 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3103 | argnum + 1, len, (int) typecode); |
3104 | ||
3105 | val = (char *) VALUE_CONTENTS (arg); | |
3106 | ||
3107 | /* 32-bit ABIs always start floating point arguments in an | |
3108 | even-numbered floating point register. Round the FP register | |
3109 | up before the check to see if there are any FP registers | |
3110 | left. O32/O64 targets also pass the FP in the integer | |
3111 | registers so also round up normal registers. */ | |
ceae6e75 AC |
3112 | if (mips_abi_regsize (gdbarch) < 8 |
3113 | && fp_register_arg_p (typecode, arg_type)) | |
46cac009 AC |
3114 | { |
3115 | if ((float_argreg & 1)) | |
3116 | float_argreg++; | |
3117 | } | |
3118 | ||
3119 | /* Floating point arguments passed in registers have to be | |
3120 | treated specially. On 32-bit architectures, doubles | |
3121 | are passed in register pairs; the even register gets | |
3122 | the low word, and the odd register gets the high word. | |
3123 | On O32/O64, the first two floating point arguments are | |
3124 | also copied to general registers, because MIPS16 functions | |
3125 | don't use float registers for arguments. This duplication of | |
3126 | arguments in general registers can't hurt non-MIPS16 functions | |
3127 | because those registers are normally skipped. */ | |
3128 | ||
3129 | if (fp_register_arg_p (typecode, arg_type) | |
3130 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3131 | { | |
ceae6e75 | 3132 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
46cac009 AC |
3133 | { |
3134 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3135 | unsigned long regval; | |
3136 | ||
3137 | /* Write the low word of the double to the even register(s). */ | |
3138 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3139 | if (mips_debug) | |
3140 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3141 | float_argreg, phex (regval, 4)); | |
3142 | write_register (float_argreg++, regval); | |
3143 | if (mips_debug) | |
3144 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3145 | argreg, phex (regval, 4)); | |
3146 | write_register (argreg++, regval); | |
3147 | ||
3148 | /* Write the high word of the double to the odd register(s). */ | |
3149 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3150 | if (mips_debug) | |
3151 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3152 | float_argreg, phex (regval, 4)); | |
3153 | write_register (float_argreg++, regval); | |
3154 | ||
3155 | if (mips_debug) | |
3156 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3157 | argreg, phex (regval, 4)); | |
3158 | write_register (argreg++, regval); | |
3159 | } | |
3160 | else | |
3161 | { | |
3162 | /* This is a floating point value that fits entirely | |
3163 | in a single register. */ | |
3164 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3165 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3166 | LONGEST regval = extract_unsigned_integer (val, len); |
3167 | if (mips_debug) | |
3168 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3169 | float_argreg, phex (regval, len)); | |
3170 | write_register (float_argreg++, regval); | |
3171 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
3172 | registers for each argument. The below is (my |
3173 | guess) to ensure that the corresponding integer | |
3174 | register has reserved the same space. */ | |
46cac009 AC |
3175 | if (mips_debug) |
3176 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3177 | argreg, phex (regval, len)); | |
3178 | write_register (argreg, regval); | |
ceae6e75 | 3179 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
46cac009 AC |
3180 | } |
3181 | /* Reserve space for the FP register. */ | |
13326b4e | 3182 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
46cac009 AC |
3183 | } |
3184 | else | |
3185 | { | |
3186 | /* Copy the argument to general registers or the stack in | |
3187 | register-sized pieces. Large arguments are split between | |
3188 | registers and stack. */ | |
4246e332 | 3189 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3190 | mips_abi_regsize() are treated specially: Irix cc passes |
3191 | them in registers where gcc sometimes puts them on the | |
3192 | stack. For maximum compatibility, we will put them in | |
3193 | both places. */ | |
13326b4e AC |
3194 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3195 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
46cac009 AC |
3196 | /* Structures should be aligned to eight bytes (even arg registers) |
3197 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 3198 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 AC |
3199 | && mips_type_needs_double_align (arg_type)) |
3200 | { | |
3201 | if ((argreg & 1)) | |
6d82d43b | 3202 | argreg++; |
46cac009 AC |
3203 | } |
3204 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 3205 | register are only written to memory. */ |
46cac009 AC |
3206 | while (len > 0) |
3207 | { | |
3208 | /* Remember if the argument was written to the stack. */ | |
3209 | int stack_used_p = 0; | |
13326b4e AC |
3210 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3211 | ? len : mips_abi_regsize (gdbarch)); | |
46cac009 AC |
3212 | |
3213 | if (mips_debug) | |
3214 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3215 | partial_len); | |
3216 | ||
3217 | /* Write this portion of the argument to the stack. */ | |
3218 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3219 | || odd_sized_struct | |
3220 | || fp_register_arg_p (typecode, arg_type)) | |
3221 | { | |
3222 | /* Should shorter than int integer values be | |
3223 | promoted to int before being stored? */ | |
3224 | int longword_offset = 0; | |
3225 | CORE_ADDR addr; | |
3226 | stack_used_p = 1; | |
3227 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3228 | { | |
13326b4e | 3229 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3230 | && (typecode == TYPE_CODE_INT |
3231 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3232 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3233 | longword_offset = mips_stack_argsize (gdbarch) - len; |
46cac009 AC |
3234 | } |
3235 | ||
3236 | if (mips_debug) | |
3237 | { | |
3238 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3239 | paddr_nz (stack_offset)); | |
3240 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3241 | paddr_nz (longword_offset)); | |
3242 | } | |
3243 | ||
3244 | addr = sp + stack_offset + longword_offset; | |
3245 | ||
3246 | if (mips_debug) | |
3247 | { | |
3248 | int i; | |
6d82d43b | 3249 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3250 | paddr_nz (addr)); |
3251 | for (i = 0; i < partial_len; i++) | |
3252 | { | |
6d82d43b | 3253 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3254 | val[i] & 0xff); |
3255 | } | |
3256 | } | |
3257 | write_memory (addr, val, partial_len); | |
3258 | } | |
3259 | ||
3260 | /* Note!!! This is NOT an else clause. Odd sized | |
3261 | structs may go thru BOTH paths. Floating point | |
3262 | arguments will not. */ | |
3263 | /* Write this portion of the argument to a general | |
6d82d43b | 3264 | purpose register. */ |
46cac009 AC |
3265 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3266 | && !fp_register_arg_p (typecode, arg_type)) | |
3267 | { | |
3268 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3269 | /* Value may need to be sign extended, because |
1b13c4f6 | 3270 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3271 | |
3272 | /* A non-floating-point argument being passed in a | |
3273 | general register. If a struct or union, and if | |
3274 | the remaining length is smaller than the register | |
3275 | size, we have to adjust the register value on | |
3276 | big endian targets. | |
3277 | ||
3278 | It does not seem to be necessary to do the | |
3279 | same for integral types. | |
3280 | ||
3281 | Also don't do this adjustment on O64 binaries. | |
3282 | ||
3283 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3284 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3285 | mips_abi_regsize(), generates a left shift as |
46cac009 AC |
3286 | part of storing the argument in a register a |
3287 | register (the left shift isn't generated when | |
1b13c4f6 | 3288 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3289 | it is quite possible that this is GCC |
3290 | contradicting the LE/O32 ABI, GDB has not been | |
3291 | adjusted to accommodate this. Either someone | |
3292 | needs to demonstrate that the LE/O32 ABI | |
3293 | specifies such a left shift OR this new ABI gets | |
3294 | identified as such and GDB gets tweaked | |
3295 | accordingly. */ | |
3296 | ||
13326b4e | 3297 | if (mips_abi_regsize (gdbarch) < 8 |
46cac009 | 3298 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 3299 | && partial_len < mips_abi_regsize (gdbarch) |
46cac009 AC |
3300 | && (typecode == TYPE_CODE_STRUCT || |
3301 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3302 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
46cac009 AC |
3303 | TARGET_CHAR_BIT); |
3304 | ||
3305 | if (mips_debug) | |
3306 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3307 | argreg, | |
6d82d43b | 3308 | phex (regval, |
13326b4e | 3309 | mips_abi_regsize (gdbarch))); |
46cac009 AC |
3310 | write_register (argreg, regval); |
3311 | argreg++; | |
3312 | ||
3313 | /* Prevent subsequent floating point arguments from | |
3314 | being passed in floating point registers. */ | |
3315 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3316 | } | |
3317 | ||
3318 | len -= partial_len; | |
3319 | val += partial_len; | |
3320 | ||
3321 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3322 | will copy the next parameter. |
46cac009 | 3323 | |
6d82d43b AC |
3324 | In older ABIs, the caller reserved space for |
3325 | registers that contained arguments. This was loosely | |
3326 | refered to as their "home". Consequently, space is | |
3327 | always allocated. */ | |
46cac009 | 3328 | |
480d3dd2 | 3329 | stack_offset += align_up (partial_len, |
13326b4e | 3330 | mips_stack_argsize (gdbarch)); |
46cac009 AC |
3331 | } |
3332 | } | |
3333 | if (mips_debug) | |
3334 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3335 | } | |
3336 | ||
f10683bb | 3337 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3338 | |
46cac009 AC |
3339 | /* Return adjusted stack pointer. */ |
3340 | return sp; | |
3341 | } | |
3342 | ||
6d82d43b AC |
3343 | static enum return_value_convention |
3344 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3345 | struct regcache *regcache, | |
3346 | void *readbuf, const void *writebuf) | |
3347 | { | |
3348 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3349 | ||
3350 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3351 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3352 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3353 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3354 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3355 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3356 | { | |
3357 | /* A single-precision floating-point value. It fits in the | |
3358 | least significant part of FP0. */ | |
3359 | if (mips_debug) | |
3360 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3361 | mips_xfer_register (regcache, | |
3362 | NUM_REGS + mips_regnum (current_gdbarch)->fp0, | |
3363 | TYPE_LENGTH (type), | |
3364 | TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3365 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3366 | } | |
3367 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3368 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3369 | { | |
3370 | /* A double-precision floating-point value. The most | |
3371 | significant part goes in FP1, and the least significant in | |
3372 | FP0. */ | |
3373 | if (mips_debug) | |
3374 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
3375 | switch (TARGET_BYTE_ORDER) | |
3376 | { | |
3377 | case BFD_ENDIAN_LITTLE: | |
3378 | mips_xfer_register (regcache, | |
3379 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3380 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3381 | mips_xfer_register (regcache, | |
3382 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3383 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3384 | break; | |
3385 | case BFD_ENDIAN_BIG: | |
3386 | mips_xfer_register (regcache, | |
3387 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3388 | 1, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 0); | |
3389 | mips_xfer_register (regcache, | |
3390 | NUM_REGS + mips_regnum (current_gdbarch)->fp0 + | |
3391 | 0, 4, TARGET_BYTE_ORDER, readbuf, writebuf, 4); | |
3392 | break; | |
3393 | default: | |
3394 | internal_error (__FILE__, __LINE__, "bad switch"); | |
3395 | } | |
3396 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3397 | } | |
3398 | #if 0 | |
3399 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3400 | && TYPE_NFIELDS (type) <= 2 | |
3401 | && TYPE_NFIELDS (type) >= 1 | |
3402 | && ((TYPE_NFIELDS (type) == 1 | |
3403 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3404 | == TYPE_CODE_FLT)) | |
3405 | || (TYPE_NFIELDS (type) == 2 | |
3406 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3407 | == TYPE_CODE_FLT) | |
3408 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3409 | == TYPE_CODE_FLT))) | |
3410 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3411 | { | |
3412 | /* A struct that contains one or two floats. Each value is part | |
3413 | in the least significant part of their floating point | |
3414 | register.. */ | |
3415 | bfd_byte reg[MAX_REGISTER_SIZE]; | |
3416 | int regnum; | |
3417 | int field; | |
3418 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3419 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3420 | { | |
3421 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3422 | / TARGET_CHAR_BIT); | |
3423 | if (mips_debug) | |
3424 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3425 | offset); | |
3426 | mips_xfer_register (regcache, NUM_REGS + regnum, | |
3427 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3428 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3429 | } | |
3430 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3431 | } | |
3432 | #endif | |
3433 | #if 0 | |
3434 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3435 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3436 | { | |
3437 | /* A structure or union. Extract the left justified value, | |
3438 | regardless of the byte order. I.e. DO NOT USE | |
3439 | mips_xfer_lower. */ | |
3440 | int offset; | |
3441 | int regnum; | |
4c7d22cb | 3442 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3443 | offset < TYPE_LENGTH (type); |
3444 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3445 | { | |
3446 | int xfer = register_size (current_gdbarch, regnum); | |
3447 | if (offset + xfer > TYPE_LENGTH (type)) | |
3448 | xfer = TYPE_LENGTH (type) - offset; | |
3449 | if (mips_debug) | |
3450 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3451 | offset, xfer, regnum); | |
3452 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3453 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); | |
3454 | } | |
3455 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3456 | } | |
3457 | #endif | |
3458 | else | |
3459 | { | |
3460 | /* A scalar extract each part but least-significant-byte | |
3461 | justified. o32 thinks registers are 4 byte, regardless of | |
3462 | the ISA. mips_stack_argsize controls this. */ | |
3463 | int offset; | |
3464 | int regnum; | |
4c7d22cb | 3465 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3466 | offset < TYPE_LENGTH (type); |
13326b4e | 3467 | offset += mips_stack_argsize (gdbarch), regnum++) |
6d82d43b | 3468 | { |
13326b4e | 3469 | int xfer = mips_stack_argsize (gdbarch); |
6d82d43b AC |
3470 | if (offset + xfer > TYPE_LENGTH (type)) |
3471 | xfer = TYPE_LENGTH (type) - offset; | |
3472 | if (mips_debug) | |
3473 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3474 | offset, xfer, regnum); | |
3475 | mips_xfer_register (regcache, NUM_REGS + regnum, xfer, | |
3476 | TARGET_BYTE_ORDER, readbuf, writebuf, offset); | |
3477 | } | |
3478 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3479 | } | |
3480 | } | |
3481 | ||
3482 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3483 | ABI. */ | |
46cac009 AC |
3484 | |
3485 | static CORE_ADDR | |
7d9b040b | 3486 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3487 | struct regcache *regcache, CORE_ADDR bp_addr, |
3488 | int nargs, | |
3489 | struct value **args, CORE_ADDR sp, | |
3490 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3491 | { |
3492 | int argreg; | |
3493 | int float_argreg; | |
3494 | int argnum; | |
3495 | int len = 0; | |
3496 | int stack_offset = 0; | |
480d3dd2 | 3497 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3498 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 3499 | |
25ab4790 AC |
3500 | /* For shared libraries, "t9" needs to point at the function |
3501 | address. */ | |
4c7d22cb | 3502 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3503 | |
3504 | /* Set the return address register to point to the entry point of | |
3505 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3506 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3507 | |
46cac009 AC |
3508 | /* First ensure that the stack and structure return address (if any) |
3509 | are properly aligned. The stack has to be at least 64-bit | |
3510 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3511 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3512 | aligned, so we round to this widest known alignment. */ | |
3513 | ||
5b03f266 AC |
3514 | sp = align_down (sp, 16); |
3515 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3516 | |
3517 | /* Now make space on the stack for the args. */ | |
3518 | for (argnum = 0; argnum < nargs; argnum++) | |
6d82d43b | 3519 | len += align_up (TYPE_LENGTH (VALUE_TYPE (args[argnum])), |
13326b4e | 3520 | mips_stack_argsize (gdbarch)); |
5b03f266 | 3521 | sp -= align_up (len, 16); |
46cac009 AC |
3522 | |
3523 | if (mips_debug) | |
6d82d43b | 3524 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3525 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3526 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3527 | |
3528 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3529 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3530 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3531 | |
3532 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3533 | if (struct_return) | |
3534 | { | |
3535 | if (mips_debug) | |
3536 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3537 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 AC |
3538 | argreg, paddr_nz (struct_addr)); |
3539 | write_register (argreg++, struct_addr); | |
13326b4e | 3540 | stack_offset += mips_stack_argsize (gdbarch); |
46cac009 AC |
3541 | } |
3542 | ||
3543 | /* Now load as many as possible of the first arguments into | |
3544 | registers, and push the rest onto the stack. Loop thru args | |
3545 | from first to last. */ | |
3546 | for (argnum = 0; argnum < nargs; argnum++) | |
3547 | { | |
3548 | char *val; | |
46cac009 AC |
3549 | struct value *arg = args[argnum]; |
3550 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
3551 | int len = TYPE_LENGTH (arg_type); | |
3552 | enum type_code typecode = TYPE_CODE (arg_type); | |
3553 | ||
3554 | if (mips_debug) | |
3555 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3556 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3557 | argnum + 1, len, (int) typecode); |
3558 | ||
3559 | val = (char *) VALUE_CONTENTS (arg); | |
3560 | ||
3561 | /* 32-bit ABIs always start floating point arguments in an | |
3562 | even-numbered floating point register. Round the FP register | |
3563 | up before the check to see if there are any FP registers | |
3564 | left. O32/O64 targets also pass the FP in the integer | |
3565 | registers so also round up normal registers. */ | |
ceae6e75 AC |
3566 | if (mips_abi_regsize (gdbarch) < 8 |
3567 | && fp_register_arg_p (typecode, arg_type)) | |
ebafbe83 MS |
3568 | { |
3569 | if ((float_argreg & 1)) | |
3570 | float_argreg++; | |
3571 | } | |
3572 | ||
3573 | /* Floating point arguments passed in registers have to be | |
3574 | treated specially. On 32-bit architectures, doubles | |
3575 | are passed in register pairs; the even register gets | |
3576 | the low word, and the odd register gets the high word. | |
3577 | On O32/O64, the first two floating point arguments are | |
3578 | also copied to general registers, because MIPS16 functions | |
3579 | don't use float registers for arguments. This duplication of | |
3580 | arguments in general registers can't hurt non-MIPS16 functions | |
3581 | because those registers are normally skipped. */ | |
3582 | ||
3583 | if (fp_register_arg_p (typecode, arg_type) | |
3584 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3585 | { | |
ceae6e75 | 3586 | if (mips_abi_regsize (gdbarch) < 8 && len == 8) |
ebafbe83 MS |
3587 | { |
3588 | int low_offset = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? 4 : 0; | |
3589 | unsigned long regval; | |
3590 | ||
3591 | /* Write the low word of the double to the even register(s). */ | |
3592 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3593 | if (mips_debug) | |
3594 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3595 | float_argreg, phex (regval, 4)); | |
3596 | write_register (float_argreg++, regval); | |
3597 | if (mips_debug) | |
3598 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3599 | argreg, phex (regval, 4)); | |
3600 | write_register (argreg++, regval); | |
3601 | ||
3602 | /* Write the high word of the double to the odd register(s). */ | |
3603 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3604 | if (mips_debug) | |
3605 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3606 | float_argreg, phex (regval, 4)); | |
3607 | write_register (float_argreg++, regval); | |
3608 | ||
3609 | if (mips_debug) | |
3610 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3611 | argreg, phex (regval, 4)); | |
3612 | write_register (argreg++, regval); | |
3613 | } | |
3614 | else | |
3615 | { | |
3616 | /* This is a floating point value that fits entirely | |
3617 | in a single register. */ | |
3618 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3619 | above to ensure that it is even register aligned. */ |
ebafbe83 MS |
3620 | LONGEST regval = extract_unsigned_integer (val, len); |
3621 | if (mips_debug) | |
3622 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3623 | float_argreg, phex (regval, len)); | |
3624 | write_register (float_argreg++, regval); | |
3625 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP | |
6d82d43b AC |
3626 | registers for each argument. The below is (my |
3627 | guess) to ensure that the corresponding integer | |
3628 | register has reserved the same space. */ | |
ebafbe83 MS |
3629 | if (mips_debug) |
3630 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3631 | argreg, phex (regval, len)); | |
3632 | write_register (argreg, regval); | |
ceae6e75 | 3633 | argreg += (mips_abi_regsize (gdbarch) == 8) ? 1 : 2; |
ebafbe83 MS |
3634 | } |
3635 | /* Reserve space for the FP register. */ | |
13326b4e | 3636 | stack_offset += align_up (len, mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
3637 | } |
3638 | else | |
3639 | { | |
3640 | /* Copy the argument to general registers or the stack in | |
3641 | register-sized pieces. Large arguments are split between | |
3642 | registers and stack. */ | |
4246e332 | 3643 | /* Note: structs whose size is not a multiple of |
d5ac5a39 AC |
3644 | mips_abi_regsize() are treated specially: Irix cc passes |
3645 | them in registers where gcc sometimes puts them on the | |
3646 | stack. For maximum compatibility, we will put them in | |
3647 | both places. */ | |
13326b4e AC |
3648 | int odd_sized_struct = ((len > mips_abi_regsize (gdbarch)) |
3649 | && (len % mips_abi_regsize (gdbarch) != 0)); | |
ebafbe83 MS |
3650 | /* Structures should be aligned to eight bytes (even arg registers) |
3651 | on MIPS_ABI_O32, if their first member has double precision. */ | |
13326b4e | 3652 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 MS |
3653 | && mips_type_needs_double_align (arg_type)) |
3654 | { | |
3655 | if ((argreg & 1)) | |
6d82d43b | 3656 | argreg++; |
ebafbe83 MS |
3657 | } |
3658 | /* Note: Floating-point values that didn't fit into an FP | |
6d82d43b | 3659 | register are only written to memory. */ |
ebafbe83 MS |
3660 | while (len > 0) |
3661 | { | |
3662 | /* Remember if the argument was written to the stack. */ | |
3663 | int stack_used_p = 0; | |
13326b4e AC |
3664 | int partial_len = (len < mips_abi_regsize (gdbarch) |
3665 | ? len : mips_abi_regsize (gdbarch)); | |
ebafbe83 MS |
3666 | |
3667 | if (mips_debug) | |
3668 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3669 | partial_len); | |
3670 | ||
3671 | /* Write this portion of the argument to the stack. */ | |
3672 | if (argreg > MIPS_LAST_ARG_REGNUM | |
3673 | || odd_sized_struct | |
3674 | || fp_register_arg_p (typecode, arg_type)) | |
3675 | { | |
3676 | /* Should shorter than int integer values be | |
3677 | promoted to int before being stored? */ | |
3678 | int longword_offset = 0; | |
3679 | CORE_ADDR addr; | |
3680 | stack_used_p = 1; | |
3681 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3682 | { | |
13326b4e | 3683 | if (mips_stack_argsize (gdbarch) == 8 |
480d3dd2 AC |
3684 | && (typecode == TYPE_CODE_INT |
3685 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3686 | || typecode == TYPE_CODE_FLT) && len <= 4) |
13326b4e | 3687 | longword_offset = mips_stack_argsize (gdbarch) - len; |
ebafbe83 MS |
3688 | } |
3689 | ||
3690 | if (mips_debug) | |
3691 | { | |
3692 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3693 | paddr_nz (stack_offset)); | |
3694 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3695 | paddr_nz (longword_offset)); | |
3696 | } | |
3697 | ||
3698 | addr = sp + stack_offset + longword_offset; | |
3699 | ||
3700 | if (mips_debug) | |
3701 | { | |
3702 | int i; | |
6d82d43b | 3703 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
3704 | paddr_nz (addr)); |
3705 | for (i = 0; i < partial_len; i++) | |
3706 | { | |
6d82d43b | 3707 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
3708 | val[i] & 0xff); |
3709 | } | |
3710 | } | |
3711 | write_memory (addr, val, partial_len); | |
3712 | } | |
3713 | ||
3714 | /* Note!!! This is NOT an else clause. Odd sized | |
3715 | structs may go thru BOTH paths. Floating point | |
3716 | arguments will not. */ | |
3717 | /* Write this portion of the argument to a general | |
6d82d43b | 3718 | purpose register. */ |
ebafbe83 MS |
3719 | if (argreg <= MIPS_LAST_ARG_REGNUM |
3720 | && !fp_register_arg_p (typecode, arg_type)) | |
3721 | { | |
3722 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3723 | /* Value may need to be sign extended, because |
1b13c4f6 | 3724 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
3725 | |
3726 | /* A non-floating-point argument being passed in a | |
3727 | general register. If a struct or union, and if | |
3728 | the remaining length is smaller than the register | |
3729 | size, we have to adjust the register value on | |
3730 | big endian targets. | |
3731 | ||
3732 | It does not seem to be necessary to do the | |
3733 | same for integral types. | |
3734 | ||
3735 | Also don't do this adjustment on O64 binaries. | |
3736 | ||
3737 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3738 | outputting LE O32 with sizeof (struct) < | |
1b13c4f6 | 3739 | mips_abi_regsize(), generates a left shift as |
ebafbe83 MS |
3740 | part of storing the argument in a register a |
3741 | register (the left shift isn't generated when | |
1b13c4f6 | 3742 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3743 | it is quite possible that this is GCC |
3744 | contradicting the LE/O32 ABI, GDB has not been | |
3745 | adjusted to accommodate this. Either someone | |
3746 | needs to demonstrate that the LE/O32 ABI | |
3747 | specifies such a left shift OR this new ABI gets | |
3748 | identified as such and GDB gets tweaked | |
3749 | accordingly. */ | |
3750 | ||
13326b4e | 3751 | if (mips_abi_regsize (gdbarch) < 8 |
ebafbe83 | 3752 | && TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
13326b4e | 3753 | && partial_len < mips_abi_regsize (gdbarch) |
ebafbe83 MS |
3754 | && (typecode == TYPE_CODE_STRUCT || |
3755 | typecode == TYPE_CODE_UNION)) | |
13326b4e | 3756 | regval <<= ((mips_abi_regsize (gdbarch) - partial_len) * |
ebafbe83 MS |
3757 | TARGET_CHAR_BIT); |
3758 | ||
3759 | if (mips_debug) | |
3760 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3761 | argreg, | |
6d82d43b | 3762 | phex (regval, |
13326b4e | 3763 | mips_abi_regsize (gdbarch))); |
ebafbe83 MS |
3764 | write_register (argreg, regval); |
3765 | argreg++; | |
3766 | ||
3767 | /* Prevent subsequent floating point arguments from | |
3768 | being passed in floating point registers. */ | |
3769 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3770 | } | |
3771 | ||
3772 | len -= partial_len; | |
3773 | val += partial_len; | |
3774 | ||
3775 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3776 | will copy the next parameter. |
ebafbe83 | 3777 | |
6d82d43b AC |
3778 | In older ABIs, the caller reserved space for |
3779 | registers that contained arguments. This was loosely | |
3780 | refered to as their "home". Consequently, space is | |
3781 | always allocated. */ | |
ebafbe83 | 3782 | |
480d3dd2 | 3783 | stack_offset += align_up (partial_len, |
13326b4e | 3784 | mips_stack_argsize (gdbarch)); |
ebafbe83 MS |
3785 | } |
3786 | } | |
3787 | if (mips_debug) | |
3788 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3789 | } | |
3790 | ||
f10683bb | 3791 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3792 | |
ebafbe83 MS |
3793 | /* Return adjusted stack pointer. */ |
3794 | return sp; | |
3795 | } | |
3796 | ||
9c8fdbfa AC |
3797 | static enum return_value_convention |
3798 | mips_o64_return_value (struct gdbarch *gdbarch, | |
3799 | struct type *type, struct regcache *regcache, | |
3800 | void *readbuf, const void *writebuf) | |
6d82d43b | 3801 | { |
9c8fdbfa | 3802 | return RETURN_VALUE_STRUCT_CONVENTION; |
6d82d43b AC |
3803 | } |
3804 | ||
dd824b04 DJ |
3805 | /* Floating point register management. |
3806 | ||
3807 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3808 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3809 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3810 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3811 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3812 | double precision floats into two 32-bit chunks and store them in | |
3813 | consecutive fp regs. To display 64-bit floats stored in this | |
3814 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3815 | Throw in user-configurable endianness and you have a real mess. | |
3816 | ||
3817 | The way this works is: | |
3818 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3819 | double-precision value will be split across two logical registers. | |
3820 | The lower-numbered logical register will hold the low-order bits, | |
3821 | regardless of the processor's endianness. | |
3822 | - If we are on a 64-bit processor, and we are looking for a | |
3823 | single-precision value, it will be in the low ordered bits | |
3824 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3825 | save slot in memory. | |
3826 | - If we are in 64-bit mode, everything is straightforward. | |
3827 | ||
3828 | Note that this code only deals with "live" registers at the top of the | |
3829 | stack. We will attempt to deal with saved registers later, when | |
3830 | the raw/cooked register interface is in place. (We need a general | |
3831 | interface that can deal with dynamic saved register sizes -- fp | |
3832 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3833 | and below). */ | |
3834 | ||
67b2c998 DJ |
3835 | static struct type * |
3836 | mips_float_register_type (void) | |
3837 | { | |
361d1df0 | 3838 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3839 | return builtin_type_ieee_single_big; |
3840 | else | |
3841 | return builtin_type_ieee_single_little; | |
3842 | } | |
3843 | ||
3844 | static struct type * | |
3845 | mips_double_register_type (void) | |
3846 | { | |
361d1df0 | 3847 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
67b2c998 DJ |
3848 | return builtin_type_ieee_double_big; |
3849 | else | |
3850 | return builtin_type_ieee_double_little; | |
3851 | } | |
3852 | ||
dd824b04 DJ |
3853 | /* Copy a 32-bit single-precision value from the current frame |
3854 | into rare_buffer. */ | |
3855 | ||
3856 | static void | |
e11c53d2 AC |
3857 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
3858 | char *rare_buffer) | |
dd824b04 | 3859 | { |
719ec221 | 3860 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
3861 | char *raw_buffer = alloca (raw_size); |
3862 | ||
e11c53d2 | 3863 | if (!frame_register_read (frame, regno, raw_buffer)) |
dd824b04 DJ |
3864 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3865 | if (raw_size == 8) | |
3866 | { | |
3867 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 3868 | 32 bits. */ |
dd824b04 DJ |
3869 | int offset; |
3870 | ||
3871 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3872 | offset = 4; | |
3873 | else | |
3874 | offset = 0; | |
3875 | ||
3876 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
3877 | } | |
3878 | else | |
3879 | { | |
3880 | memcpy (rare_buffer, raw_buffer, 4); | |
3881 | } | |
3882 | } | |
3883 | ||
3884 | /* Copy a 64-bit double-precision value from the current frame into | |
3885 | rare_buffer. This may include getting half of it from the next | |
3886 | register. */ | |
3887 | ||
3888 | static void | |
e11c53d2 AC |
3889 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
3890 | char *rare_buffer) | |
dd824b04 | 3891 | { |
719ec221 | 3892 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 DJ |
3893 | |
3894 | if (raw_size == 8 && !mips2_fp_compat ()) | |
3895 | { | |
3896 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 3897 | all 64 bits. */ |
e11c53d2 | 3898 | if (!frame_register_read (frame, regno, rare_buffer)) |
dd824b04 DJ |
3899 | error ("can't read register %d (%s)", regno, REGISTER_NAME (regno)); |
3900 | } | |
3901 | else | |
3902 | { | |
56cea623 | 3903 | if ((regno - mips_regnum (current_gdbarch)->fp0) & 1) |
dd824b04 DJ |
3904 | internal_error (__FILE__, __LINE__, |
3905 | "mips_read_fp_register_double: bad access to " | |
3906 | "odd-numbered FP register"); | |
3907 | ||
3908 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 3909 | each register. */ |
dd824b04 DJ |
3910 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
3911 | { | |
e11c53d2 AC |
3912 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
3913 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 3914 | } |
361d1df0 | 3915 | else |
dd824b04 | 3916 | { |
e11c53d2 AC |
3917 | mips_read_fp_register_single (frame, regno, rare_buffer); |
3918 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
3919 | } |
3920 | } | |
3921 | } | |
3922 | ||
c906108c | 3923 | static void |
e11c53d2 AC |
3924 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
3925 | int regnum) | |
c5aa993b | 3926 | { /* do values for FP (float) regs */ |
dd824b04 | 3927 | char *raw_buffer; |
3903d437 AC |
3928 | double doub, flt1; /* doubles extracted from raw hex data */ |
3929 | int inv1, inv2; | |
c5aa993b | 3930 | |
6d82d43b AC |
3931 | raw_buffer = |
3932 | (char *) alloca (2 * | |
3933 | register_size (current_gdbarch, | |
3934 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 3935 | |
e11c53d2 AC |
3936 | fprintf_filtered (file, "%s:", REGISTER_NAME (regnum)); |
3937 | fprintf_filtered (file, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum)), | |
3938 | ""); | |
f0ef6b29 | 3939 | |
719ec221 | 3940 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat ()) |
c906108c | 3941 | { |
f0ef6b29 KB |
3942 | /* 4-byte registers: Print hex and floating. Also print even |
3943 | numbered registers as doubles. */ | |
e11c53d2 | 3944 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 3945 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 3946 | |
6d82d43b AC |
3947 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
3948 | file); | |
dd824b04 | 3949 | |
e11c53d2 | 3950 | fprintf_filtered (file, " flt: "); |
1adad886 | 3951 | if (inv1) |
e11c53d2 | 3952 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 3953 | else |
e11c53d2 | 3954 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 3955 | |
f0ef6b29 KB |
3956 | if (regnum % 2 == 0) |
3957 | { | |
e11c53d2 | 3958 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 3959 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 3960 | &inv2); |
1adad886 | 3961 | |
e11c53d2 | 3962 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 3963 | if (inv2) |
e11c53d2 | 3964 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 3965 | else |
e11c53d2 | 3966 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 3967 | } |
c906108c SS |
3968 | } |
3969 | else | |
dd824b04 | 3970 | { |
f0ef6b29 | 3971 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 3972 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 3973 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 3974 | |
e11c53d2 | 3975 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
3976 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
3977 | ||
361d1df0 | 3978 | |
6d82d43b AC |
3979 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
3980 | file); | |
f0ef6b29 | 3981 | |
e11c53d2 | 3982 | fprintf_filtered (file, " flt: "); |
1adad886 | 3983 | if (inv1) |
e11c53d2 | 3984 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 3985 | else |
e11c53d2 | 3986 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 3987 | |
e11c53d2 | 3988 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 3989 | if (inv2) |
e11c53d2 | 3990 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 3991 | else |
e11c53d2 | 3992 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
3993 | } |
3994 | } | |
3995 | ||
3996 | static void | |
e11c53d2 AC |
3997 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
3998 | int regnum, int all) | |
f0ef6b29 | 3999 | { |
a4b8ebc8 | 4000 | struct gdbarch *gdbarch = get_frame_arch (frame); |
d9d9c31f | 4001 | char raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4002 | int offset; |
1adad886 | 4003 | |
a4b8ebc8 | 4004 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4005 | { |
e11c53d2 | 4006 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4007 | return; |
4008 | } | |
4009 | ||
4010 | /* Get the data in raw format. */ | |
e11c53d2 | 4011 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4012 | { |
e11c53d2 | 4013 | fprintf_filtered (file, "%s: [Invalid]", REGISTER_NAME (regnum)); |
f0ef6b29 | 4014 | return; |
c906108c | 4015 | } |
f0ef6b29 | 4016 | |
e11c53d2 | 4017 | fputs_filtered (REGISTER_NAME (regnum), file); |
f0ef6b29 KB |
4018 | |
4019 | /* The problem with printing numeric register names (r26, etc.) is that | |
4020 | the user can't use them on input. Probably the best solution is to | |
4021 | fix it so that either the numeric or the funky (a2, etc.) names | |
4022 | are accepted on input. */ | |
4023 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4024 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4025 | else |
e11c53d2 | 4026 | fprintf_filtered (file, ": "); |
f0ef6b29 KB |
4027 | |
4028 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
6d82d43b AC |
4029 | offset = |
4030 | register_size (current_gdbarch, | |
4031 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
4032 | else |
4033 | offset = 0; | |
4034 | ||
6d82d43b AC |
4035 | print_scalar_formatted (raw_buffer + offset, |
4036 | gdbarch_register_type (gdbarch, regnum), 'x', 0, | |
4037 | file); | |
c906108c SS |
4038 | } |
4039 | ||
f0ef6b29 KB |
4040 | /* Replacement for generic do_registers_info. |
4041 | Print regs in pretty columns. */ | |
4042 | ||
4043 | static int | |
e11c53d2 AC |
4044 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4045 | int regnum) | |
f0ef6b29 | 4046 | { |
e11c53d2 AC |
4047 | fprintf_filtered (file, " "); |
4048 | mips_print_fp_register (file, frame, regnum); | |
4049 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4050 | return regnum + 1; |
4051 | } | |
4052 | ||
4053 | ||
c906108c SS |
4054 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4055 | ||
4056 | static int | |
e11c53d2 | 4057 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4058 | int start_regnum) |
c906108c | 4059 | { |
a4b8ebc8 | 4060 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4061 | /* do values for GP (int) regs */ |
d9d9c31f | 4062 | char raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4063 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4064 | int col, byte; |
a4b8ebc8 | 4065 | int regnum; |
c906108c SS |
4066 | |
4067 | /* For GP registers, we print a separate row of names above the vals */ | |
e11c53d2 | 4068 | fprintf_filtered (file, " "); |
a4b8ebc8 | 4069 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4070 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4071 | { |
4072 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4073 | continue; /* unused register */ |
6d82d43b AC |
4074 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4075 | TYPE_CODE_FLT) | |
c5aa993b | 4076 | break; /* end the row: reached FP register */ |
6d82d43b | 4077 | fprintf_filtered (file, |
d5ac5a39 | 4078 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
e11c53d2 | 4079 | REGISTER_NAME (regnum)); |
c906108c SS |
4080 | col++; |
4081 | } | |
a4b8ebc8 | 4082 | /* print the R0 to R31 names */ |
20e6603c AC |
4083 | if ((start_regnum % NUM_REGS) < MIPS_NUMREGS) |
4084 | fprintf_filtered (file, "\n R%-4d", start_regnum % NUM_REGS); | |
4085 | else | |
4086 | fprintf_filtered (file, "\n "); | |
c906108c | 4087 | |
c906108c | 4088 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4089 | for (col = 0, regnum = start_regnum; |
6d82d43b | 4090 | col < ncols && regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
c906108c SS |
4091 | { |
4092 | if (*REGISTER_NAME (regnum) == '\0') | |
c5aa993b | 4093 | continue; /* unused register */ |
6d82d43b AC |
4094 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4095 | TYPE_CODE_FLT) | |
c5aa993b | 4096 | break; /* end row: reached FP register */ |
c906108c | 4097 | /* OK: get the data in raw format. */ |
e11c53d2 | 4098 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c906108c SS |
4099 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4100 | /* pad small registers */ | |
4246e332 | 4101 | for (byte = 0; |
d5ac5a39 | 4102 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 4103 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
4104 | printf_filtered (" "); |
4105 | /* Now print the register value in hex, endian order. */ | |
d7449b42 | 4106 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
6d82d43b AC |
4107 | for (byte = |
4108 | register_size (current_gdbarch, | |
4109 | regnum) - register_size (current_gdbarch, regnum); | |
4110 | byte < register_size (current_gdbarch, regnum); byte++) | |
e11c53d2 | 4111 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
c906108c | 4112 | else |
c73e8f27 | 4113 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 4114 | byte >= 0; byte--) |
e11c53d2 AC |
4115 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[byte]); |
4116 | fprintf_filtered (file, " "); | |
c906108c SS |
4117 | col++; |
4118 | } | |
c5aa993b | 4119 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4120 | fprintf_filtered (file, "\n"); |
c906108c SS |
4121 | |
4122 | return regnum; | |
4123 | } | |
4124 | ||
4125 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4126 | ||
bf1f5b4c | 4127 | static void |
e11c53d2 AC |
4128 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4129 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4130 | { |
c5aa993b | 4131 | if (regnum != -1) /* do one specified register */ |
c906108c | 4132 | { |
a4b8ebc8 | 4133 | gdb_assert (regnum >= NUM_REGS); |
c906108c SS |
4134 | if (*(REGISTER_NAME (regnum)) == '\0') |
4135 | error ("Not a valid register for the current processor type"); | |
4136 | ||
e11c53d2 AC |
4137 | mips_print_register (file, frame, regnum, 0); |
4138 | fprintf_filtered (file, "\n"); | |
c906108c | 4139 | } |
c5aa993b JM |
4140 | else |
4141 | /* do all (or most) registers */ | |
c906108c | 4142 | { |
a4b8ebc8 AC |
4143 | regnum = NUM_REGS; |
4144 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c906108c | 4145 | { |
6d82d43b AC |
4146 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
4147 | TYPE_CODE_FLT) | |
e11c53d2 AC |
4148 | { |
4149 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4150 | regnum = print_fp_register_row (file, frame, regnum); | |
4151 | else | |
4152 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4153 | } | |
c906108c | 4154 | else |
e11c53d2 | 4155 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4156 | } |
4157 | } | |
4158 | } | |
4159 | ||
c906108c SS |
4160 | /* Is this a branch with a delay slot? */ |
4161 | ||
c906108c | 4162 | static int |
acdb74a0 | 4163 | is_delayed (unsigned long insn) |
c906108c SS |
4164 | { |
4165 | int i; | |
4166 | for (i = 0; i < NUMOPCODES; ++i) | |
4167 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4168 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4169 | break; | |
4170 | return (i < NUMOPCODES | |
4171 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4172 | | INSN_COND_BRANCH_DELAY | |
4173 | | INSN_COND_BRANCH_LIKELY))); | |
4174 | } | |
4175 | ||
4176 | int | |
acdb74a0 | 4177 | mips_step_skips_delay (CORE_ADDR pc) |
c906108c | 4178 | { |
4c7d22cb | 4179 | char buf[MIPS32_INSN_SIZE]; |
c906108c SS |
4180 | |
4181 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4182 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4183 | return 0; |
4184 | ||
4c7d22cb | 4185 | if (target_read_memory (pc, buf, sizeof buf) != 0) |
c906108c SS |
4186 | /* If error reading memory, guess that it is not a delayed branch. */ |
4187 | return 0; | |
4c7d22cb | 4188 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4189 | } |
4190 | ||
6d82d43b AC |
4191 | /* To skip prologues, I use this predicate. Returns either PC itself |
4192 | if the code at PC does not look like a function prologue; otherwise | |
4193 | returns an address that (if we're lucky) follows the prologue. If | |
4194 | LENIENT, then we must skip everything which is involved in setting | |
4195 | up the frame (it's OK to skip more, just so long as we don't skip | |
4196 | anything which might clobber the registers which are being saved. | |
4197 | We must skip more in the case where part of the prologue is in the | |
4198 | delay slot of a non-prologue instruction). */ | |
4199 | ||
4200 | static CORE_ADDR | |
4201 | mips_skip_prologue (CORE_ADDR pc) | |
4202 | { | |
8b622e6a AC |
4203 | CORE_ADDR limit_pc; |
4204 | CORE_ADDR func_addr; | |
4205 | ||
6d82d43b AC |
4206 | /* See if we can determine the end of the prologue via the symbol table. |
4207 | If so, then return either PC, or the PC after the prologue, whichever | |
4208 | is greater. */ | |
8b622e6a AC |
4209 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4210 | { | |
4211 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
4212 | if (post_prologue_pc != 0) | |
4213 | return max (pc, post_prologue_pc); | |
4214 | } | |
6d82d43b AC |
4215 | |
4216 | /* Can't determine prologue from the symbol table, need to examine | |
4217 | instructions. */ | |
4218 | ||
98b4dd94 JB |
4219 | /* Find an upper limit on the function prologue using the debug |
4220 | information. If the debug information could not be used to provide | |
4221 | that bound, then use an arbitrary large number as the upper bound. */ | |
4222 | limit_pc = skip_prologue_using_sal (pc); | |
4223 | if (limit_pc == 0) | |
4224 | limit_pc = pc + 100; /* Magic. */ | |
4225 | ||
0fe7e7c8 | 4226 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4227 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4228 | else |
a65bbe44 | 4229 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4230 | } |
4231 | ||
a5ea2558 AC |
4232 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4233 | used for all MIPS-specific commands. */ | |
4234 | ||
a5ea2558 | 4235 | static void |
acdb74a0 | 4236 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4237 | { |
4238 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4239 | } | |
4240 | ||
a5ea2558 | 4241 | static void |
acdb74a0 | 4242 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4243 | { |
6d82d43b AC |
4244 | printf_unfiltered |
4245 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4246 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4247 | } | |
4248 | ||
c906108c SS |
4249 | /* Commands to show/set the MIPS FPU type. */ |
4250 | ||
c906108c | 4251 | static void |
acdb74a0 | 4252 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4253 | { |
c906108c SS |
4254 | char *fpu; |
4255 | switch (MIPS_FPU_TYPE) | |
4256 | { | |
4257 | case MIPS_FPU_SINGLE: | |
4258 | fpu = "single-precision"; | |
4259 | break; | |
4260 | case MIPS_FPU_DOUBLE: | |
4261 | fpu = "double-precision"; | |
4262 | break; | |
4263 | case MIPS_FPU_NONE: | |
4264 | fpu = "absent (none)"; | |
4265 | break; | |
93d56215 AC |
4266 | default: |
4267 | internal_error (__FILE__, __LINE__, "bad switch"); | |
c906108c SS |
4268 | } |
4269 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4270 | printf_unfiltered |
4271 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4272 | fpu); | |
c906108c | 4273 | else |
6d82d43b AC |
4274 | printf_unfiltered |
4275 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4276 | } |
4277 | ||
4278 | ||
c906108c | 4279 | static void |
acdb74a0 | 4280 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4281 | { |
6d82d43b AC |
4282 | printf_unfiltered |
4283 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4284 | show_mipsfpu_command (args, from_tty); |
4285 | } | |
4286 | ||
c906108c | 4287 | static void |
acdb74a0 | 4288 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4289 | { |
8d5838b5 AC |
4290 | struct gdbarch_info info; |
4291 | gdbarch_info_init (&info); | |
c906108c SS |
4292 | mips_fpu_type = MIPS_FPU_SINGLE; |
4293 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4294 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4295 | instead of relying on globals. Doing that would let generic code | |
4296 | handle the search for this specific architecture. */ | |
4297 | if (!gdbarch_update_p (info)) | |
4298 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4299 | } |
4300 | ||
c906108c | 4301 | static void |
acdb74a0 | 4302 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4303 | { |
8d5838b5 AC |
4304 | struct gdbarch_info info; |
4305 | gdbarch_info_init (&info); | |
c906108c SS |
4306 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4307 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4308 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4309 | instead of relying on globals. Doing that would let generic code | |
4310 | handle the search for this specific architecture. */ | |
4311 | if (!gdbarch_update_p (info)) | |
4312 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4313 | } |
4314 | ||
c906108c | 4315 | static void |
acdb74a0 | 4316 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4317 | { |
8d5838b5 AC |
4318 | struct gdbarch_info info; |
4319 | gdbarch_info_init (&info); | |
c906108c SS |
4320 | mips_fpu_type = MIPS_FPU_NONE; |
4321 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4322 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4323 | instead of relying on globals. Doing that would let generic code | |
4324 | handle the search for this specific architecture. */ | |
4325 | if (!gdbarch_update_p (info)) | |
4326 | internal_error (__FILE__, __LINE__, "set mipsfpu failed"); | |
c906108c SS |
4327 | } |
4328 | ||
c906108c | 4329 | static void |
acdb74a0 | 4330 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4331 | { |
4332 | mips_fpu_type_auto = 1; | |
4333 | } | |
4334 | ||
c906108c | 4335 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4336 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4337 | the relevant processor still exists (it dates back to '94) and | |
4338 | secondly this is not the way to do this. The processor type should | |
4339 | be set by forcing an architecture change. */ | |
c906108c | 4340 | |
691c0433 AC |
4341 | void |
4342 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4343 | { |
691c0433 | 4344 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
4345 | CORE_ADDR prid; |
4346 | ||
4347 | prid = read_register (PRID_REGNUM); | |
4348 | ||
4349 | if ((prid & ~0xf) == 0x700) | |
691c0433 | 4350 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4351 | } |
4352 | ||
4353 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4354 | callable as an sfunc. */ | |
4355 | ||
4356 | static void | |
acdb74a0 AC |
4357 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4358 | struct cmd_list_element *c) | |
c906108c SS |
4359 | { |
4360 | reinit_frame_cache (); | |
4361 | } | |
4362 | ||
a89aa300 AC |
4363 | static int |
4364 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4365 | { |
e5ab0dce | 4366 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 4367 | |
d31431ed AC |
4368 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4369 | disassembler needs to be able to locally determine the ISA, and | |
4370 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4371 | work. */ | |
ec4045ea AC |
4372 | if (mips_pc_is_mips16 (memaddr)) |
4373 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4374 | |
4375 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4376 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4377 | |
e5ab0dce | 4378 | /* Set the disassembler options. */ |
6d82d43b | 4379 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
4380 | { |
4381 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 4382 | register names from libopcodes. */ |
e5ab0dce AC |
4383 | if (tdep->mips_abi == MIPS_ABI_N32) |
4384 | info->disassembler_options = "gpr-names=n32"; | |
4385 | else | |
4386 | info->disassembler_options = "gpr-names=64"; | |
4387 | info->flavour = bfd_target_elf_flavour; | |
4388 | } | |
4389 | else | |
4390 | /* This string is not recognized explicitly by the disassembler, | |
4391 | but it tells the disassembler to not try to guess the ABI from | |
4392 | the bfd elf headers, such that, if the user overrides the ABI | |
4393 | of a program linked as NewABI, the disassembly will follow the | |
4394 | register naming conventions specified by the user. */ | |
4395 | info->disassembler_options = "gpr-names=32"; | |
4396 | ||
c906108c | 4397 | /* Call the appropriate disassembler based on the target endian-ness. */ |
d7449b42 | 4398 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
4399 | return print_insn_big_mips (memaddr, info); |
4400 | else | |
4401 | return print_insn_little_mips (memaddr, info); | |
4402 | } | |
4403 | ||
c906108c SS |
4404 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program |
4405 | counter value to determine whether a 16- or 32-bit breakpoint should be | |
4406 | used. It returns a pointer to a string of bytes that encode a breakpoint | |
4407 | instruction, stores the length of the string to *lenptr, and adjusts pc | |
4408 | (if necessary) to point to the actual memory location where the | |
4409 | breakpoint should be inserted. */ | |
4410 | ||
f7ab6ec6 | 4411 | static const unsigned char * |
6d82d43b | 4412 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 4413 | { |
d7449b42 | 4414 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c | 4415 | { |
0fe7e7c8 | 4416 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4417 | { |
6d82d43b | 4418 | static unsigned char mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 4419 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4420 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
4421 | return mips16_big_breakpoint; |
4422 | } | |
4423 | else | |
4424 | { | |
aaab4dba AC |
4425 | /* The IDT board uses an unusual breakpoint value, and |
4426 | sometimes gets confused when it sees the usual MIPS | |
4427 | breakpoint instruction. */ | |
6d82d43b AC |
4428 | static unsigned char big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
4429 | static unsigned char pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
4430 | static unsigned char idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 4431 | |
c5aa993b | 4432 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
4433 | |
4434 | if (strcmp (target_shortname, "mips") == 0) | |
4435 | return idt_big_breakpoint; | |
4436 | else if (strcmp (target_shortname, "ddb") == 0 | |
4437 | || strcmp (target_shortname, "pmon") == 0 | |
4438 | || strcmp (target_shortname, "lsi") == 0) | |
4439 | return pmon_big_breakpoint; | |
4440 | else | |
4441 | return big_breakpoint; | |
4442 | } | |
4443 | } | |
4444 | else | |
4445 | { | |
0fe7e7c8 | 4446 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4447 | { |
6d82d43b | 4448 | static unsigned char mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 4449 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4450 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
4451 | return mips16_little_breakpoint; |
4452 | } | |
4453 | else | |
4454 | { | |
6d82d43b AC |
4455 | static unsigned char little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
4456 | static unsigned char pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
4457 | static unsigned char idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 4458 | |
c5aa993b | 4459 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
4460 | |
4461 | if (strcmp (target_shortname, "mips") == 0) | |
4462 | return idt_little_breakpoint; | |
4463 | else if (strcmp (target_shortname, "ddb") == 0 | |
4464 | || strcmp (target_shortname, "pmon") == 0 | |
4465 | || strcmp (target_shortname, "lsi") == 0) | |
4466 | return pmon_little_breakpoint; | |
4467 | else | |
4468 | return little_breakpoint; | |
4469 | } | |
4470 | } | |
4471 | } | |
4472 | ||
4473 | /* If PC is in a mips16 call or return stub, return the address of the target | |
4474 | PC, which is either the callee or the caller. There are several | |
4475 | cases which must be handled: | |
4476 | ||
4477 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 4478 | target PC is in $31 ($ra). |
c906108c | 4479 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 4480 | and the target PC is in $2. |
c906108c | 4481 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
4482 | before the jal instruction, this is effectively a call stub |
4483 | and the the target PC is in $2. Otherwise this is effectively | |
4484 | a return stub and the target PC is in $18. | |
c906108c SS |
4485 | |
4486 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 4487 | gory details. */ |
c906108c | 4488 | |
757a7cc6 | 4489 | static CORE_ADDR |
e7d6a6d2 | 4490 | mips_skip_trampoline_code (CORE_ADDR pc) |
c906108c SS |
4491 | { |
4492 | char *name; | |
4493 | CORE_ADDR start_addr; | |
4494 | ||
4495 | /* Find the starting address and name of the function containing the PC. */ | |
4496 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
4497 | return 0; | |
4498 | ||
4499 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
4500 | target PC is in $31 ($ra). */ | |
4501 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4502 | || strcmp (name, "__mips16_ret_df") == 0) | |
4c7d22cb | 4503 | return read_signed_register (MIPS_RA_REGNUM); |
c906108c SS |
4504 | |
4505 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4506 | { | |
4507 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
4508 | and the target PC is in $2. */ | |
4509 | if (name[19] >= '0' && name[19] <= '9') | |
6c997a34 | 4510 | return read_signed_register (2); |
c906108c SS |
4511 | |
4512 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
4513 | before the jal instruction, this is effectively a call stub |
4514 | and the the target PC is in $2. Otherwise this is effectively | |
4515 | a return stub and the target PC is in $18. */ | |
c906108c SS |
4516 | else if (name[19] == 's' || name[19] == 'd') |
4517 | { | |
4518 | if (pc == start_addr) | |
4519 | { | |
4520 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
4521 | stub. Such a stub for a function bar might have a name |
4522 | like __fn_stub_bar, and might look like this: | |
4523 | mfc1 $4,$f13 | |
4524 | mfc1 $5,$f12 | |
4525 | mfc1 $6,$f15 | |
4526 | mfc1 $7,$f14 | |
4527 | la $1,bar (becomes a lui/addiu pair) | |
4528 | jr $1 | |
4529 | So scan down to the lui/addi and extract the target | |
4530 | address from those two instructions. */ | |
c906108c | 4531 | |
6c997a34 | 4532 | CORE_ADDR target_pc = read_signed_register (2); |
c906108c SS |
4533 | t_inst inst; |
4534 | int i; | |
4535 | ||
4536 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
4537 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
4538 | 0) | |
c906108c SS |
4539 | return target_pc; |
4540 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
4541 | && strcmp (name, "etext") != 0 | |
4542 | && strcmp (name, "_etext") != 0) | |
4543 | return target_pc; | |
4544 | ||
4545 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
4546 | The limit on the search is arbitrarily set to 20 |
4547 | instructions. FIXME. */ | |
4c7d22cb | 4548 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS32_INSN_SIZE) |
c906108c | 4549 | { |
c5aa993b JM |
4550 | inst = mips_fetch_instruction (target_pc); |
4551 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
4552 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
4553 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
4554 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
4555 | } |
4556 | ||
4557 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
4558 | return target_pc; | |
4559 | } | |
4560 | else | |
4561 | /* This is the 'return' part of a call stub. The return | |
4562 | address is in $r18. */ | |
6c997a34 | 4563 | return read_signed_register (18); |
c906108c SS |
4564 | } |
4565 | } | |
c5aa993b | 4566 | return 0; /* not a stub */ |
c906108c SS |
4567 | } |
4568 | ||
4569 | ||
4570 | /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline). | |
4571 | This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */ | |
4572 | ||
757a7cc6 | 4573 | static int |
acdb74a0 | 4574 | mips_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
4575 | { |
4576 | CORE_ADDR start_addr; | |
4577 | ||
4578 | /* Find the starting address of the function containing the PC. If the | |
4579 | caller didn't give us a name, look it up at the same time. */ | |
6d82d43b AC |
4580 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == |
4581 | 0) | |
c906108c SS |
4582 | return 0; |
4583 | ||
4584 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4585 | { | |
4586 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */ | |
4587 | if (name[19] >= '0' && name[19] <= '9') | |
4588 | return 1; | |
4589 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 4590 | before the jal instruction, this is effectively a call stub. */ |
c906108c SS |
4591 | else if (name[19] == 's' || name[19] == 'd') |
4592 | return pc == start_addr; | |
4593 | } | |
4594 | ||
c5aa993b | 4595 | return 0; /* not a stub */ |
c906108c SS |
4596 | } |
4597 | ||
4598 | ||
c5115f39 AC |
4599 | /* Return non-zero if the PC is inside a return thunk (aka stub or |
4600 | trampoline). */ | |
c906108c | 4601 | |
e41b17f0 | 4602 | static int |
c5115f39 | 4603 | mips_in_solib_return_trampoline (CORE_ADDR pc, char *name) |
c906108c SS |
4604 | { |
4605 | CORE_ADDR start_addr; | |
4606 | ||
4607 | /* Find the starting address of the function containing the PC. */ | |
4608 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
4609 | return 0; | |
4610 | ||
4611 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */ | |
4612 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4613 | || strcmp (name, "__mips16_ret_df") == 0) | |
4614 | return 1; | |
4615 | ||
4616 | /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start, | |
c5aa993b | 4617 | i.e. after the jal instruction, this is effectively a return stub. */ |
c906108c | 4618 | if (strncmp (name, "__mips16_call_stub_", 19) == 0 |
6d82d43b | 4619 | && (name[19] == 's' || name[19] == 'd') && pc != start_addr) |
c906108c SS |
4620 | return 1; |
4621 | ||
c5aa993b | 4622 | return 0; /* not a stub */ |
c906108c SS |
4623 | } |
4624 | ||
4625 | ||
a53c66de AC |
4626 | /* Return non-zero if the PC is in a library helper function that |
4627 | should be ignored. This implements the | |
4628 | DEPRECATED_IGNORE_HELPER_CALL macro. */ | |
c906108c SS |
4629 | |
4630 | int | |
acdb74a0 | 4631 | mips_ignore_helper (CORE_ADDR pc) |
c906108c SS |
4632 | { |
4633 | char *name; | |
4634 | ||
4635 | /* Find the starting address and name of the function containing the PC. */ | |
4636 | if (find_pc_partial_function (pc, &name, NULL, NULL) == 0) | |
4637 | return 0; | |
4638 | ||
4639 | /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function | |
4640 | that we want to ignore. */ | |
4641 | return (strcmp (name, "__mips16_ret_sf") == 0 | |
4642 | || strcmp (name, "__mips16_ret_df") == 0); | |
4643 | } | |
4644 | ||
4645 | ||
a4b8ebc8 AC |
4646 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
4647 | [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
4648 | |
4649 | static int | |
4650 | mips_stab_reg_to_regnum (int num) | |
4651 | { | |
a4b8ebc8 | 4652 | int regnum; |
2f38ef89 | 4653 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4654 | regnum = num; |
2f38ef89 | 4655 | else if (num >= 38 && num < 70) |
56cea623 | 4656 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 4657 | else if (num == 70) |
56cea623 | 4658 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4659 | else if (num == 71) |
56cea623 | 4660 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4661 | else |
a4b8ebc8 AC |
4662 | /* This will hopefully (eventually) provoke a warning. Should |
4663 | we be calling complaint() here? */ | |
4664 | return NUM_REGS + NUM_PSEUDO_REGS; | |
4665 | return NUM_REGS + regnum; | |
88c72b7d AC |
4666 | } |
4667 | ||
2f38ef89 | 4668 | |
a4b8ebc8 AC |
4669 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
4670 | NUM_REGS .. 2 * NUM_REGS) REGNUM. */ | |
88c72b7d AC |
4671 | |
4672 | static int | |
2f38ef89 | 4673 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 4674 | { |
a4b8ebc8 | 4675 | int regnum; |
2f38ef89 | 4676 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4677 | regnum = num; |
2f38ef89 | 4678 | else if (num >= 32 && num < 64) |
56cea623 | 4679 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 4680 | else if (num == 64) |
56cea623 | 4681 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4682 | else if (num == 65) |
56cea623 | 4683 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4684 | else |
a4b8ebc8 AC |
4685 | /* This will hopefully (eventually) provoke a warning. Should we |
4686 | be calling complaint() here? */ | |
4687 | return NUM_REGS + NUM_PSEUDO_REGS; | |
4688 | return NUM_REGS + regnum; | |
4689 | } | |
4690 | ||
4691 | static int | |
4692 | mips_register_sim_regno (int regnum) | |
4693 | { | |
4694 | /* Only makes sense to supply raw registers. */ | |
4695 | gdb_assert (regnum >= 0 && regnum < NUM_REGS); | |
4696 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to | |
4697 | decide if it is valid. Should instead define a standard sim/gdb | |
4698 | register numbering scheme. */ | |
4699 | if (REGISTER_NAME (NUM_REGS + regnum) != NULL | |
4700 | && REGISTER_NAME (NUM_REGS + regnum)[0] != '\0') | |
4701 | return regnum; | |
4702 | else | |
6d82d43b | 4703 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
4704 | } |
4705 | ||
2f38ef89 | 4706 | |
fc0c74b1 AC |
4707 | /* Convert an integer into an address. By first converting the value |
4708 | into a pointer and then extracting it signed, the address is | |
4709 | guarenteed to be correctly sign extended. */ | |
4710 | ||
4711 | static CORE_ADDR | |
4712 | mips_integer_to_address (struct type *type, void *buf) | |
4713 | { | |
4714 | char *tmp = alloca (TYPE_LENGTH (builtin_type_void_data_ptr)); | |
4715 | LONGEST val = unpack_long (type, buf); | |
4716 | store_signed_integer (tmp, TYPE_LENGTH (builtin_type_void_data_ptr), val); | |
4717 | return extract_signed_integer (tmp, | |
4718 | TYPE_LENGTH (builtin_type_void_data_ptr)); | |
4719 | } | |
4720 | ||
caaa3122 DJ |
4721 | static void |
4722 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
4723 | { | |
4724 | enum mips_abi *abip = (enum mips_abi *) obj; | |
4725 | const char *name = bfd_get_section_name (abfd, sect); | |
4726 | ||
4727 | if (*abip != MIPS_ABI_UNKNOWN) | |
4728 | return; | |
4729 | ||
4730 | if (strncmp (name, ".mdebug.", 8) != 0) | |
4731 | return; | |
4732 | ||
4733 | if (strcmp (name, ".mdebug.abi32") == 0) | |
4734 | *abip = MIPS_ABI_O32; | |
4735 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
4736 | *abip = MIPS_ABI_N32; | |
62a49b2c | 4737 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 4738 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
4739 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
4740 | *abip = MIPS_ABI_O64; | |
4741 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
4742 | *abip = MIPS_ABI_EABI32; | |
4743 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
4744 | *abip = MIPS_ABI_EABI64; | |
4745 | else | |
4746 | warning ("unsupported ABI %s.", name + 8); | |
4747 | } | |
4748 | ||
2e4ebe70 DJ |
4749 | static enum mips_abi |
4750 | global_mips_abi (void) | |
4751 | { | |
4752 | int i; | |
4753 | ||
4754 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
4755 | if (mips_abi_strings[i] == mips_abi_string) | |
4756 | return (enum mips_abi) i; | |
4757 | ||
6d82d43b | 4758 | internal_error (__FILE__, __LINE__, "unknown ABI string"); |
2e4ebe70 DJ |
4759 | } |
4760 | ||
c2d11a7d | 4761 | static struct gdbarch * |
6d82d43b | 4762 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 4763 | { |
c2d11a7d JM |
4764 | struct gdbarch *gdbarch; |
4765 | struct gdbarch_tdep *tdep; | |
4766 | int elf_flags; | |
2e4ebe70 | 4767 | enum mips_abi mips_abi, found_abi, wanted_abi; |
a4b8ebc8 | 4768 | int num_regs; |
8d5838b5 | 4769 | enum mips_fpu_type fpu_type; |
c2d11a7d | 4770 | |
ec03c1ac AC |
4771 | /* First of all, extract the elf_flags, if available. */ |
4772 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
4773 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
4774 | else if (arches != NULL) |
4775 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
4776 | else |
4777 | elf_flags = 0; | |
4778 | if (gdbarch_debug) | |
4779 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 4780 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 4781 | |
102182a9 | 4782 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
4783 | switch ((elf_flags & EF_MIPS_ABI)) |
4784 | { | |
4785 | case E_MIPS_ABI_O32: | |
ec03c1ac | 4786 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
4787 | break; |
4788 | case E_MIPS_ABI_O64: | |
ec03c1ac | 4789 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
4790 | break; |
4791 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 4792 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
4793 | break; |
4794 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 4795 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
4796 | break; |
4797 | default: | |
acdb74a0 | 4798 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 4799 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 4800 | else |
ec03c1ac | 4801 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
4802 | break; |
4803 | } | |
acdb74a0 | 4804 | |
caaa3122 | 4805 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
4806 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
4807 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 4808 | |
dc305454 | 4809 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
4810 | MIPS architecture (if there is one). */ |
4811 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
4812 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 4813 | |
32a6503c | 4814 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 4815 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
4816 | && info.bfd_arch_info != NULL |
4817 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4818 | { | |
4819 | switch (info.bfd_arch_info->mach) | |
4820 | { | |
4821 | case bfd_mach_mips3900: | |
ec03c1ac | 4822 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
4823 | break; |
4824 | case bfd_mach_mips4100: | |
4825 | case bfd_mach_mips5000: | |
ec03c1ac | 4826 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 4827 | break; |
1d06468c EZ |
4828 | case bfd_mach_mips8000: |
4829 | case bfd_mach_mips10000: | |
32a6503c KB |
4830 | /* On Irix, ELF64 executables use the N64 ABI. The |
4831 | pseudo-sections which describe the ABI aren't present | |
4832 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
4833 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
4834 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 4835 | found_abi = MIPS_ABI_N64; |
28d169de | 4836 | else |
ec03c1ac | 4837 | found_abi = MIPS_ABI_N32; |
1d06468c | 4838 | break; |
bf64bfd6 AC |
4839 | } |
4840 | } | |
2e4ebe70 | 4841 | |
ec03c1ac AC |
4842 | if (gdbarch_debug) |
4843 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
4844 | found_abi); | |
4845 | ||
4846 | /* What has the user specified from the command line? */ | |
4847 | wanted_abi = global_mips_abi (); | |
4848 | if (gdbarch_debug) | |
4849 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
4850 | wanted_abi); | |
2e4ebe70 DJ |
4851 | |
4852 | /* Now that we have found what the ABI for this binary would be, | |
4853 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
4854 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
4855 | mips_abi = wanted_abi; | |
ec03c1ac AC |
4856 | else if (found_abi != MIPS_ABI_UNKNOWN) |
4857 | mips_abi = found_abi; | |
4858 | else | |
4859 | mips_abi = MIPS_ABI_O32; | |
4860 | if (gdbarch_debug) | |
4861 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
4862 | mips_abi); | |
2e4ebe70 | 4863 | |
ec03c1ac | 4864 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 4865 | if (gdbarch_debug) |
ec03c1ac AC |
4866 | fprintf_unfiltered (gdb_stdlog, |
4867 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
4868 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 4869 | |
8d5838b5 AC |
4870 | /* Determine the MIPS FPU type. */ |
4871 | if (!mips_fpu_type_auto) | |
4872 | fpu_type = mips_fpu_type; | |
4873 | else if (info.bfd_arch_info != NULL | |
4874 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
4875 | switch (info.bfd_arch_info->mach) | |
4876 | { | |
4877 | case bfd_mach_mips3900: | |
4878 | case bfd_mach_mips4100: | |
4879 | case bfd_mach_mips4111: | |
a9d61c86 | 4880 | case bfd_mach_mips4120: |
8d5838b5 AC |
4881 | fpu_type = MIPS_FPU_NONE; |
4882 | break; | |
4883 | case bfd_mach_mips4650: | |
4884 | fpu_type = MIPS_FPU_SINGLE; | |
4885 | break; | |
4886 | default: | |
4887 | fpu_type = MIPS_FPU_DOUBLE; | |
4888 | break; | |
4889 | } | |
4890 | else if (arches != NULL) | |
4891 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
4892 | else | |
4893 | fpu_type = MIPS_FPU_DOUBLE; | |
4894 | if (gdbarch_debug) | |
4895 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 4896 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 4897 | |
c2d11a7d JM |
4898 | /* try to find a pre-existing architecture */ |
4899 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
4900 | arches != NULL; | |
4901 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4902 | { | |
4903 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 4904 | using. */ |
9103eae0 | 4905 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 4906 | continue; |
9103eae0 | 4907 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 4908 | continue; |
719ec221 AC |
4909 | /* Need to be pedantic about which register virtual size is |
4910 | used. */ | |
4911 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
4912 | != mips64_transfers_32bit_regs_p) | |
4913 | continue; | |
8d5838b5 AC |
4914 | /* Be pedantic about which FPU is selected. */ |
4915 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
4916 | continue; | |
4be87837 | 4917 | return arches->gdbarch; |
c2d11a7d JM |
4918 | } |
4919 | ||
102182a9 | 4920 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
4921 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
4922 | gdbarch = gdbarch_alloc (&info, tdep); | |
4923 | tdep->elf_flags = elf_flags; | |
719ec221 | 4924 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
4925 | tdep->found_abi = found_abi; |
4926 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 4927 | tdep->mips_fpu_type = fpu_type; |
c2d11a7d | 4928 | |
102182a9 | 4929 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
4930 | set_gdbarch_short_bit (gdbarch, 16); |
4931 | set_gdbarch_int_bit (gdbarch, 32); | |
4932 | set_gdbarch_float_bit (gdbarch, 32); | |
4933 | set_gdbarch_double_bit (gdbarch, 64); | |
4934 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
4935 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
4936 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
4937 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 4938 | |
6d82d43b | 4939 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
4940 | mips_elf_make_msymbol_special); |
4941 | ||
16e109ca | 4942 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 4943 | { |
16e109ca | 4944 | const char **reg_names; |
56cea623 AC |
4945 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
4946 | struct mips_regnum); | |
56cea623 AC |
4947 | if (info.osabi == GDB_OSABI_IRIX) |
4948 | { | |
4949 | regnum->fp0 = 32; | |
4950 | regnum->pc = 64; | |
4951 | regnum->cause = 65; | |
4952 | regnum->badvaddr = 66; | |
4953 | regnum->hi = 67; | |
4954 | regnum->lo = 68; | |
4955 | regnum->fp_control_status = 69; | |
4956 | regnum->fp_implementation_revision = 70; | |
4957 | num_regs = 71; | |
16e109ca | 4958 | reg_names = mips_irix_reg_names; |
56cea623 AC |
4959 | } |
4960 | else | |
4961 | { | |
4962 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
4963 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
4964 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
4965 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
4966 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
4967 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
4968 | regnum->fp_control_status = 70; | |
4969 | regnum->fp_implementation_revision = 71; | |
4970 | num_regs = 90; | |
16e109ca AC |
4971 | if (info.bfd_arch_info != NULL |
4972 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
4973 | reg_names = mips_tx39_reg_names; | |
4974 | else | |
4975 | reg_names = mips_generic_reg_names; | |
56cea623 AC |
4976 | } |
4977 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been | |
4978 | replaced by read_pc? */ | |
f10683bb MH |
4979 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
4980 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
4981 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
4982 | set_gdbarch_num_regs (gdbarch, num_regs); | |
4983 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca AC |
4984 | set_gdbarch_register_name (gdbarch, mips_register_name); |
4985 | tdep->mips_processor_reg_names = reg_names; | |
4986 | tdep->regnum = regnum; | |
56cea623 | 4987 | } |
fe29b929 | 4988 | |
0dadbba0 | 4989 | switch (mips_abi) |
c2d11a7d | 4990 | { |
0dadbba0 | 4991 | case MIPS_ABI_O32: |
25ab4790 | 4992 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 4993 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 4994 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 4995 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 4996 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
4997 | set_gdbarch_long_bit (gdbarch, 32); |
4998 | set_gdbarch_ptr_bit (gdbarch, 32); | |
4999 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5000 | break; | |
0dadbba0 | 5001 | case MIPS_ABI_O64: |
25ab4790 | 5002 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5003 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5004 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5005 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5006 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5007 | set_gdbarch_long_bit (gdbarch, 32); |
5008 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5009 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5010 | break; | |
0dadbba0 | 5011 | case MIPS_ABI_EABI32: |
25ab4790 | 5012 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5013 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5014 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5015 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5016 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5017 | set_gdbarch_long_bit (gdbarch, 32); |
5018 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5019 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5020 | break; | |
0dadbba0 | 5021 | case MIPS_ABI_EABI64: |
25ab4790 | 5022 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5023 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5024 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5025 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5026 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5027 | set_gdbarch_long_bit (gdbarch, 64); |
5028 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5029 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5030 | break; | |
0dadbba0 | 5031 | case MIPS_ABI_N32: |
25ab4790 | 5032 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5033 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5034 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5035 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5036 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5037 | set_gdbarch_long_bit (gdbarch, 32); |
5038 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5039 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
5040 | set_gdbarch_long_double_bit (gdbarch, 128); |
5041 | set_gdbarch_long_double_format (gdbarch, | |
5042 | &floatformat_n32n64_long_double_big); | |
28d169de KB |
5043 | break; |
5044 | case MIPS_ABI_N64: | |
25ab4790 | 5045 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5046 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5047 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5048 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5049 | tdep->default_mask_address_p = 0; |
5050 | set_gdbarch_long_bit (gdbarch, 64); | |
5051 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5052 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 JB |
5053 | set_gdbarch_long_double_bit (gdbarch, 128); |
5054 | set_gdbarch_long_double_format (gdbarch, | |
5055 | &floatformat_n32n64_long_double_big); | |
0dadbba0 | 5056 | break; |
c2d11a7d | 5057 | default: |
6d82d43b | 5058 | internal_error (__FILE__, __LINE__, "unknown ABI in switch"); |
c2d11a7d JM |
5059 | } |
5060 | ||
a5ea2558 AC |
5061 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5062 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5063 | comment: | |
5064 | ||
5065 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5066 | flag in object files because to do so would make it impossible to | |
102182a9 | 5067 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5068 | unnecessarily restrictive. |
361d1df0 | 5069 | |
a5ea2558 AC |
5070 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5071 | but to set this flag before gcc is built with such multilibs will | |
5072 | break too many systems.'' | |
5073 | ||
5074 | But even more unhelpfully, the default linker output target for | |
5075 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5076 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5077 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5078 | this flag to detect 32-bit mode would do the wrong thing given |
5079 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5080 | as 32-bit programs by default. */ |
a5ea2558 | 5081 | |
6c997a34 | 5082 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5083 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
bcb0cc15 | 5084 | set_gdbarch_read_sp (gdbarch, mips_read_sp); |
c2d11a7d | 5085 | |
102182a9 MS |
5086 | /* Add/remove bits from an address. The MIPS needs be careful to |
5087 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5088 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5089 | ||
58dfe9ff AC |
5090 | /* Unwind the frame. */ |
5091 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
edfae063 | 5092 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 5093 | |
102182a9 | 5094 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5095 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5096 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5097 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5098 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5099 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5100 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5101 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5102 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5103 | |
c2d11a7d JM |
5104 | /* MIPS version of CALL_DUMMY */ |
5105 | ||
9710e734 AC |
5106 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5107 | replaced by a command, and all targets will default to on stack | |
5108 | (regardless of the stack's execute status). */ | |
5109 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5110 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5111 | |
87783b8b AC |
5112 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5113 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5114 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5115 | ||
f7b9e9fc AC |
5116 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5117 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5118 | |
5119 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5120 | |
fc0c74b1 AC |
5121 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5122 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5123 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5124 | |
a4b8ebc8 | 5125 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5126 | |
e11c53d2 | 5127 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5128 | |
e5ab0dce AC |
5129 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
5130 | ||
3a3bc038 AC |
5131 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5132 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5133 | need to all be folded into the target vector. Since they are | |
5134 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5135 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5136 | is sitting on? */ | |
5137 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5138 | ||
e7d6a6d2 | 5139 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 5140 | |
6de918a6 DJ |
5141 | /* NOTE drow/2004-02-11: We overload the core solib trampoline code |
5142 | to support MIPS16. This is a bad thing. Make sure not to do it | |
5143 | if we have an OS ABI that actually supports shared libraries, since | |
5144 | shared library support is more important. If we have an OS someday | |
5145 | that supports both shared libraries and MIPS16, we'll have to find | |
5146 | a better place for these. */ | |
5147 | if (info.osabi == GDB_OSABI_UNKNOWN) | |
5148 | { | |
5149 | set_gdbarch_in_solib_call_trampoline (gdbarch, mips_in_call_stub); | |
c5115f39 | 5150 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_solib_return_trampoline); |
6de918a6 DJ |
5151 | } |
5152 | ||
5153 | /* Hook in OS ABI-specific overrides, if they have been registered. */ | |
5154 | gdbarch_init_osabi (info, gdbarch); | |
757a7cc6 | 5155 | |
5792a79b | 5156 | /* Unwind the frame. */ |
eec63939 | 5157 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
45c9dd44 AC |
5158 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
5159 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
eec63939 | 5160 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
5161 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
5162 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 5163 | |
4b9b3959 AC |
5164 | return gdbarch; |
5165 | } | |
5166 | ||
2e4ebe70 | 5167 | static void |
6d82d43b | 5168 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5169 | { |
5170 | struct gdbarch_info info; | |
5171 | ||
5172 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5173 | mips_gdbarch_init will take care of the rest. */ | |
5174 | gdbarch_info_init (&info); | |
5175 | gdbarch_update_p (info); | |
5176 | } | |
5177 | ||
ad188201 KB |
5178 | /* Print out which MIPS ABI is in use. */ |
5179 | ||
5180 | static void | |
5181 | show_mips_abi (char *ignore_args, int from_tty) | |
5182 | { | |
5183 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
6d82d43b AC |
5184 | printf_filtered |
5185 | ("The MIPS ABI is unknown because the current architecture is not MIPS.\n"); | |
ad188201 KB |
5186 | else |
5187 | { | |
5188 | enum mips_abi global_abi = global_mips_abi (); | |
5189 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
5190 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
5191 | ||
5192 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6d82d43b AC |
5193 | printf_filtered |
5194 | ("The MIPS ABI is set automatically (currently \"%s\").\n", | |
5195 | actual_abi_str); | |
ad188201 | 5196 | else if (global_abi == actual_abi) |
6d82d43b AC |
5197 | printf_filtered |
5198 | ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
5199 | actual_abi_str); | |
ad188201 KB |
5200 | else |
5201 | { | |
5202 | /* Probably shouldn't happen... */ | |
6d82d43b AC |
5203 | printf_filtered |
5204 | ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
5205 | actual_abi_str, mips_abi_strings[global_abi]); | |
ad188201 KB |
5206 | } |
5207 | } | |
5208 | } | |
5209 | ||
4b9b3959 AC |
5210 | static void |
5211 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
5212 | { | |
5213 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
5214 | if (tdep != NULL) | |
c2d11a7d | 5215 | { |
acdb74a0 AC |
5216 | int ef_mips_arch; |
5217 | int ef_mips_32bitmode; | |
5218 | /* determine the ISA */ | |
5219 | switch (tdep->elf_flags & EF_MIPS_ARCH) | |
5220 | { | |
5221 | case E_MIPS_ARCH_1: | |
5222 | ef_mips_arch = 1; | |
5223 | break; | |
5224 | case E_MIPS_ARCH_2: | |
5225 | ef_mips_arch = 2; | |
5226 | break; | |
5227 | case E_MIPS_ARCH_3: | |
5228 | ef_mips_arch = 3; | |
5229 | break; | |
5230 | case E_MIPS_ARCH_4: | |
93d56215 | 5231 | ef_mips_arch = 4; |
acdb74a0 AC |
5232 | break; |
5233 | default: | |
93d56215 | 5234 | ef_mips_arch = 0; |
acdb74a0 AC |
5235 | break; |
5236 | } | |
5237 | /* determine the size of a pointer */ | |
5238 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); | |
4b9b3959 AC |
5239 | fprintf_unfiltered (file, |
5240 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5241 | tdep->elf_flags); |
4b9b3959 | 5242 | fprintf_unfiltered (file, |
acdb74a0 AC |
5243 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5244 | ef_mips_32bitmode); | |
5245 | fprintf_unfiltered (file, | |
5246 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5247 | ef_mips_arch); | |
5248 | fprintf_unfiltered (file, | |
5249 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 5250 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5251 | fprintf_unfiltered (file, |
5252 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 5253 | mips_mask_address_p (tdep), |
4014092b | 5254 | tdep->default_mask_address_p); |
c2d11a7d | 5255 | } |
4b9b3959 AC |
5256 | fprintf_unfiltered (file, |
5257 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5258 | MIPS_DEFAULT_FPU_TYPE, | |
5259 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5260 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5261 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5262 | : "???")); | |
6d82d43b | 5263 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
5264 | fprintf_unfiltered (file, |
5265 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5266 | MIPS_FPU_TYPE, | |
5267 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5268 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5269 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5270 | : "???")); | |
4b9b3959 | 5271 | fprintf_unfiltered (file, |
480d3dd2 | 5272 | "mips_dump_tdep: mips_stack_argsize() = %d\n", |
13326b4e | 5273 | mips_stack_argsize (current_gdbarch)); |
2475bac3 AC |
5274 | fprintf_unfiltered (file, |
5275 | "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n", | |
6d82d43b | 5276 | XSTRING (ADDR_BITS_REMOVE (ADDR))); |
2475bac3 AC |
5277 | fprintf_unfiltered (file, |
5278 | "mips_dump_tdep: ATTACH_DETACH # %s\n", | |
5279 | XSTRING (ATTACH_DETACH)); | |
2475bac3 AC |
5280 | fprintf_unfiltered (file, |
5281 | "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n", | |
5282 | XSTRING (DWARF_REG_TO_REGNUM (REGNUM))); | |
5283 | fprintf_unfiltered (file, | |
5284 | "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n", | |
5285 | XSTRING (ECOFF_REG_TO_REGNUM (REGNUM))); | |
2475bac3 AC |
5286 | fprintf_unfiltered (file, |
5287 | "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n", | |
5288 | FIRST_EMBED_REGNUM); | |
2475bac3 | 5289 | fprintf_unfiltered (file, |
a53c66de AC |
5290 | "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n", |
5291 | XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC))); | |
2475bac3 AC |
5292 | fprintf_unfiltered (file, |
5293 | "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n", | |
5294 | XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC, NAME))); | |
2475bac3 AC |
5295 | fprintf_unfiltered (file, |
5296 | "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n", | |
5297 | LAST_EMBED_REGNUM); | |
2475bac3 AC |
5298 | #ifdef MACHINE_CPROC_FP_OFFSET |
5299 | fprintf_unfiltered (file, | |
5300 | "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n", | |
5301 | MACHINE_CPROC_FP_OFFSET); | |
5302 | #endif | |
5303 | #ifdef MACHINE_CPROC_PC_OFFSET | |
5304 | fprintf_unfiltered (file, | |
5305 | "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n", | |
5306 | MACHINE_CPROC_PC_OFFSET); | |
5307 | #endif | |
5308 | #ifdef MACHINE_CPROC_SP_OFFSET | |
5309 | fprintf_unfiltered (file, | |
5310 | "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n", | |
5311 | MACHINE_CPROC_SP_OFFSET); | |
5312 | #endif | |
6d82d43b | 5313 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n"); |
2475bac3 AC |
5314 | fprintf_unfiltered (file, |
5315 | "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n"); | |
2475bac3 | 5316 | fprintf_unfiltered (file, |
acdb74a0 AC |
5317 | "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n", |
5318 | MIPS_LAST_ARG_REGNUM, | |
4c7d22cb | 5319 | MIPS_LAST_ARG_REGNUM - MIPS_A0_REGNUM + 1); |
2475bac3 | 5320 | fprintf_unfiltered (file, |
6d82d43b | 5321 | "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS); |
2475bac3 | 5322 | fprintf_unfiltered (file, |
1b13c4f6 | 5323 | "mips_dump_tdep: mips_abi_regsize() = %d\n", |
13326b4e | 5324 | mips_abi_regsize (current_gdbarch)); |
2475bac3 | 5325 | fprintf_unfiltered (file, |
6d82d43b | 5326 | "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM); |
2475bac3 AC |
5327 | fprintf_unfiltered (file, |
5328 | "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n"); | |
5329 | fprintf_unfiltered (file, | |
5330 | "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n"); | |
6d82d43b AC |
5331 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FRAME_REG = function?\n"); |
5332 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_MASK = function?\n"); | |
5333 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n"); | |
5334 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n"); | |
5335 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_LOW_ADDR = function?\n"); | |
5336 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_PC_REG = function?\n"); | |
5337 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_MASK = function?\n"); | |
5338 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_REG_OFFSET = function?\n"); | |
5339 | fprintf_unfiltered (file, "mips_dump_tdep: PROC_SYMBOL = function?\n"); | |
5340 | fprintf_unfiltered (file, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM); | |
2475bac3 AC |
5341 | #ifdef SAVED_BYTES |
5342 | fprintf_unfiltered (file, | |
6d82d43b | 5343 | "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES); |
2475bac3 AC |
5344 | #endif |
5345 | #ifdef SAVED_FP | |
6d82d43b | 5346 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP); |
2475bac3 AC |
5347 | #endif |
5348 | #ifdef SAVED_PC | |
6d82d43b | 5349 | fprintf_unfiltered (file, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC); |
2475bac3 AC |
5350 | #endif |
5351 | fprintf_unfiltered (file, | |
5352 | "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n", | |
5353 | XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS, ARGS))); | |
2475bac3 AC |
5354 | fprintf_unfiltered (file, |
5355 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n", | |
5356 | XSTRING (SOFTWARE_SINGLE_STEP (SIG, BP_P))); | |
5357 | fprintf_unfiltered (file, | |
b0ed3589 AC |
5358 | "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n", |
5359 | SOFTWARE_SINGLE_STEP_P ()); | |
2475bac3 AC |
5360 | fprintf_unfiltered (file, |
5361 | "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n", | |
5362 | XSTRING (STAB_REG_TO_REGNUM (REGNUM))); | |
5363 | #ifdef STACK_END_ADDR | |
5364 | fprintf_unfiltered (file, | |
5365 | "mips_dump_tdep: STACK_END_ADDR = %d\n", | |
5366 | STACK_END_ADDR); | |
5367 | #endif | |
5368 | fprintf_unfiltered (file, | |
5369 | "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n", | |
5370 | XSTRING (STEP_SKIPS_DELAY (PC))); | |
5371 | fprintf_unfiltered (file, | |
5372 | "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n", | |
5373 | STEP_SKIPS_DELAY_P); | |
5374 | fprintf_unfiltered (file, | |
5375 | "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n", | |
5376 | XSTRING (STOPPED_BY_WATCHPOINT (WS))); | |
2475bac3 AC |
5377 | fprintf_unfiltered (file, |
5378 | "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n"); | |
5379 | fprintf_unfiltered (file, | |
5380 | "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n", | |
6d82d43b AC |
5381 | XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT |
5382 | (TYPE, CNT, OTHERTYPE))); | |
2475bac3 AC |
5383 | #ifdef TRACE_CLEAR |
5384 | fprintf_unfiltered (file, | |
5385 | "mips_dump_tdep: TRACE_CLEAR # %s\n", | |
5386 | XSTRING (TRACE_CLEAR (THREAD, STATE))); | |
5387 | #endif | |
5388 | #ifdef TRACE_FLAVOR | |
5389 | fprintf_unfiltered (file, | |
6d82d43b | 5390 | "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR); |
2475bac3 AC |
5391 | #endif |
5392 | #ifdef TRACE_FLAVOR_SIZE | |
5393 | fprintf_unfiltered (file, | |
5394 | "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n", | |
5395 | TRACE_FLAVOR_SIZE); | |
5396 | #endif | |
5397 | #ifdef TRACE_SET | |
5398 | fprintf_unfiltered (file, | |
5399 | "mips_dump_tdep: TRACE_SET # %s\n", | |
6d82d43b | 5400 | XSTRING (TRACE_SET (X, STATE))); |
2475bac3 | 5401 | #endif |
2475bac3 AC |
5402 | #ifdef UNUSED_REGNUM |
5403 | fprintf_unfiltered (file, | |
6d82d43b | 5404 | "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM); |
2475bac3 | 5405 | #endif |
2475bac3 AC |
5406 | fprintf_unfiltered (file, |
5407 | "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n", | |
5408 | (long) VM_MIN_ADDRESS); | |
c2d11a7d JM |
5409 | } |
5410 | ||
6d82d43b | 5411 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 5412 | |
c906108c | 5413 | void |
acdb74a0 | 5414 | _initialize_mips_tdep (void) |
c906108c SS |
5415 | { |
5416 | static struct cmd_list_element *mipsfpulist = NULL; | |
5417 | struct cmd_list_element *c; | |
5418 | ||
6d82d43b | 5419 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
5420 | if (MIPS_ABI_LAST + 1 |
5421 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
5422 | internal_error (__FILE__, __LINE__, "mips_abi_strings out of sync"); | |
5423 | ||
4b9b3959 | 5424 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 5425 | |
8d5f9dcb DJ |
5426 | mips_pdr_data = register_objfile_data (); |
5427 | ||
a5ea2558 AC |
5428 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
5429 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
5430 | "Various MIPS specific commands.", | |
5431 | &setmipscmdlist, "set mips ", 0, &setlist); | |
5432 | ||
5433 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
5434 | "Various MIPS specific commands.", | |
5435 | &showmipscmdlist, "show mips ", 0, &showlist); | |
5436 | ||
5437 | /* Allow the user to override the saved register size. */ | |
1b295c3d AC |
5438 | add_setshow_enum_cmd ("saved-gpreg-size", class_obscure, |
5439 | size_enums, &mips_abi_regsize_string, "\ | |
5440 | Set size of general purpose registers saved on the stack.\n", "\ | |
5441 | Show size of general purpose registers saved on the stack.\n", "\ | |
a5ea2558 AC |
5442 | This option can be set to one of:\n\ |
5443 | 32 - Force GDB to treat saved GP registers as 32-bit\n\ | |
5444 | 64 - Force GDB to treat saved GP registers as 64-bit\n\ | |
5445 | auto - Allow GDB to use the target's default setting or autodetect the\n\ | |
5446 | saved GP register size from information contained in the executable.\n\ | |
1b295c3d AC |
5447 | (default: auto)", "\ |
5448 | Size of general purpose registers saved on the stack is %s.\n", | |
5449 | NULL, NULL, &setmipscmdlist, &showmipscmdlist); | |
a5ea2558 | 5450 | |
d929b26f | 5451 | /* Allow the user to override the argument stack size. */ |
1b295c3d AC |
5452 | add_setshow_enum_cmd ("stack-arg-size", class_obscure, |
5453 | size_enums, &mips_stack_argsize_string, "\ | |
5454 | Set the amount of stack space reserved for each argument.\n", "\ | |
5455 | Show the amount of stack space reserved for each argument.\n", "\ | |
d929b26f AC |
5456 | This option can be set to one of:\n\ |
5457 | 32 - Force GDB to allocate 32-bit chunks per argument\n\ | |
5458 | 64 - Force GDB to allocate 64-bit chunks per argument\n\ | |
5459 | auto - Allow GDB to determine the correct setting from the current\n\ | |
1b295c3d AC |
5460 | target and executable (default)", "\ |
5461 | The amount of stack space reserved for each argument is %s.\n", | |
5462 | NULL, NULL, &setmipscmdlist, &showmipscmdlist); | |
d929b26f | 5463 | |
2e4ebe70 DJ |
5464 | /* Allow the user to override the ABI. */ |
5465 | c = add_set_enum_cmd | |
5466 | ("abi", class_obscure, mips_abi_strings, &mips_abi_string, | |
5467 | "Set the ABI used by this program.\n" | |
5468 | "This option can be set to one of:\n" | |
5469 | " auto - the default ABI associated with the current binary\n" | |
5470 | " o32\n" | |
6d82d43b | 5471 | " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist); |
2e4ebe70 | 5472 | set_cmd_sfunc (c, mips_abi_update); |
ad188201 | 5473 | add_cmd ("abi", class_obscure, show_mips_abi, |
6d82d43b | 5474 | "Show ABI in use by MIPS target", &showmipscmdlist); |
2e4ebe70 | 5475 | |
c906108c SS |
5476 | /* Let the user turn off floating point and set the fence post for |
5477 | heuristic_proc_start. */ | |
5478 | ||
5479 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
5480 | "Set use of MIPS floating-point coprocessor.", | |
5481 | &mipsfpulist, "set mipsfpu ", 0, &setlist); | |
5482 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
5483 | "Select single-precision MIPS floating-point coprocessor.", | |
5484 | &mipsfpulist); | |
5485 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
8e1a459b | 5486 | "Select double-precision MIPS floating-point coprocessor.", |
c906108c SS |
5487 | &mipsfpulist); |
5488 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
5489 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
5490 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
5491 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
6d82d43b | 5492 | "Select no MIPS floating-point coprocessor.", &mipsfpulist); |
c906108c SS |
5493 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
5494 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
5495 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
5496 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
5497 | "Select MIPS floating-point coprocessor automatically.", | |
5498 | &mipsfpulist); | |
5499 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
5500 | "Show current use of MIPS floating-point coprocessor target.", | |
5501 | &showlist); | |
5502 | ||
c906108c SS |
5503 | /* We really would like to have both "0" and "unlimited" work, but |
5504 | command.c doesn't deal with that. So make it a var_zinteger | |
5505 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 AC |
5506 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
5507 | &heuristic_fence_post, "\ | |
5508 | Set the distance searched for the start of a function.\n", "\ | |
5509 | Show the distance searched for the start of a function.\n", "\ | |
c906108c SS |
5510 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
5511 | program for the start of a function. This command sets the distance of the\n\ | |
6bcadd06 AC |
5512 | search. The only need to set it is when debugging a stripped executable.", "\ |
5513 | The distance searched for the start of a function is %s.\n", | |
5514 | reinit_frame_cache_sfunc, NULL, | |
5515 | &setlist, &showlist); | |
c906108c SS |
5516 | |
5517 | /* Allow the user to control whether the upper bits of 64-bit | |
5518 | addresses should be zeroed. */ | |
e9e68a56 | 5519 | add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, "\ |
3b64bf98 AC |
5520 | Set zeroing of upper 32 bits of 64-bit addresses.", "\ |
5521 | Show zeroing of upper 32 bits of 64-bit addresses.", "\ | |
e9e68a56 AC |
5522 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
5523 | allow GDB to determine the correct value.\n", "\ | |
3b64bf98 | 5524 | Zerroing of upper 32 bits of 64-bit address is %s.", |
6d82d43b | 5525 | NULL, show_mask_address, &setmipscmdlist, &showmipscmdlist); |
43e526b9 JM |
5526 | |
5527 | /* Allow the user to control the size of 32 bit registers within the | |
5528 | raw remote packet. */ | |
b3f42336 AC |
5529 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
5530 | &mips64_transfers_32bit_regs_p, "\ | |
3b64bf98 AC |
5531 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\ |
5532 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\ | |
719ec221 AC |
5533 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
5534 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
6d82d43b | 5535 | 64 bits for others. Use \"off\" to disable compatibility mode", "\ |
3b64bf98 AC |
5536 | Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.", |
5537 | set_mips64_transfers_32bit_regs, NULL, &setlist, &showlist); | |
9ace0497 AC |
5538 | |
5539 | /* Debug this files internals. */ | |
6bcadd06 AC |
5540 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
5541 | &mips_debug, "\ | |
5542 | Set mips debugging.\n", "\ | |
5543 | Show mips debugging.\n", "\ | |
5544 | When non-zero, mips specific debugging is enabled.\n", "\ | |
5545 | Mips debugging is currently %s.\n", | |
5546 | NULL, NULL, | |
5547 | &setdebuglist, &showdebuglist); | |
c906108c | 5548 | } |