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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
1d506c26 | 3 | Copyright (C) 1988-2024 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
c906108c SS |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "symtab.h" | |
27 | #include "value.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "language.h" | |
30 | #include "gdbcore.h" | |
31 | #include "symfile.h" | |
32 | #include "objfiles.h" | |
33 | #include "gdbtypes.h" | |
34 | #include "target.h" | |
28d069e6 | 35 | #include "arch-utils.h" |
4e052eda | 36 | #include "regcache.h" |
70f80edf | 37 | #include "osabi.h" |
d1973055 | 38 | #include "mips-tdep.h" |
fe898f56 | 39 | #include "block.h" |
a4b8ebc8 | 40 | #include "reggroups.h" |
c906108c | 41 | #include "opcode/mips.h" |
c2d11a7d JM |
42 | #include "elf/mips.h" |
43 | #include "elf-bfd.h" | |
2475bac3 | 44 | #include "symcat.h" |
a4b8ebc8 | 45 | #include "sim-regno.h" |
a89aa300 | 46 | #include "dis-asm.h" |
e47ad6c0 | 47 | #include "disasm.h" |
edfae063 AC |
48 | #include "frame-unwind.h" |
49 | #include "frame-base.h" | |
50 | #include "trad-frame.h" | |
7d9b040b | 51 | #include "infcall.h" |
29709017 DJ |
52 | #include "remote.h" |
53 | #include "target-descriptions.h" | |
82ca8957 | 54 | #include "dwarf2/frame.h" |
f8b73d13 | 55 | #include "user-regs.h" |
79a45b7d | 56 | #include "valprint.h" |
175ff332 | 57 | #include "ax.h" |
f69fdf9b | 58 | #include "target-float.h" |
325fac50 | 59 | #include <algorithm> |
c906108c | 60 | |
5bbcb741 | 61 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 62 | |
ab50adb6 MR |
63 | static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, |
64 | ULONGEST inst); | |
65 | static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32); | |
66 | static int mips16_instruction_has_delay_slot (unsigned short inst, | |
67 | int mustbe32); | |
68 | ||
69 | static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
70 | CORE_ADDR addr); | |
71 | static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
72 | CORE_ADDR addr, int mustbe32); | |
73 | static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
74 | CORE_ADDR addr, int mustbe32); | |
4cc0665f | 75 | |
1bab7383 | 76 | static void mips_print_float_info (struct gdbarch *, struct ui_file *, |
9efe17a3 | 77 | frame_info_ptr, const char *); |
1bab7383 | 78 | |
24e05951 | 79 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
80 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
81 | #define ST0_FR (1 << 26) | |
82 | ||
b0069a17 AC |
83 | /* The sizes of floating point registers. */ |
84 | ||
85 | enum | |
86 | { | |
87 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
88 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
89 | }; | |
90 | ||
1a69e1e4 DJ |
91 | enum |
92 | { | |
93 | MIPS32_REGSIZE = 4, | |
94 | MIPS64_REGSIZE = 8 | |
95 | }; | |
0dadbba0 | 96 | |
2e4ebe70 DJ |
97 | static const char *mips_abi_string; |
98 | ||
40478521 | 99 | static const char *const mips_abi_strings[] = { |
2e4ebe70 DJ |
100 | "auto", |
101 | "n32", | |
102 | "o32", | |
28d169de | 103 | "n64", |
2e4ebe70 DJ |
104 | "o64", |
105 | "eabi32", | |
106 | "eabi64", | |
107 | NULL | |
108 | }; | |
109 | ||
44f1c4d7 YQ |
110 | /* Enum describing the different kinds of breakpoints. */ |
111 | ||
112 | enum mips_breakpoint_kind | |
113 | { | |
114 | /* 16-bit MIPS16 mode breakpoint. */ | |
115 | MIPS_BP_KIND_MIPS16 = 2, | |
116 | ||
117 | /* 16-bit microMIPS mode breakpoint. */ | |
118 | MIPS_BP_KIND_MICROMIPS16 = 3, | |
119 | ||
120 | /* 32-bit standard MIPS mode breakpoint. */ | |
121 | MIPS_BP_KIND_MIPS32 = 4, | |
122 | ||
123 | /* 32-bit microMIPS mode breakpoint. */ | |
124 | MIPS_BP_KIND_MICROMIPS32 = 5, | |
125 | }; | |
126 | ||
4cc0665f MR |
127 | /* For backwards compatibility we default to MIPS16. This flag is |
128 | overridden as soon as unambiguous ELF file flags tell us the | |
129 | compressed ISA encoding used. */ | |
130 | static const char mips_compression_mips16[] = "mips16"; | |
131 | static const char mips_compression_micromips[] = "micromips"; | |
132 | static const char *const mips_compression_strings[] = | |
133 | { | |
134 | mips_compression_mips16, | |
135 | mips_compression_micromips, | |
136 | NULL | |
137 | }; | |
138 | ||
139 | static const char *mips_compression_string = mips_compression_mips16; | |
140 | ||
f8b73d13 DJ |
141 | /* The standard register names, and all the valid aliases for them. */ |
142 | struct register_alias | |
143 | { | |
144 | const char *name; | |
145 | int regnum; | |
146 | }; | |
147 | ||
148 | /* Aliases for o32 and most other ABIs. */ | |
149 | const struct register_alias mips_o32_aliases[] = { | |
150 | { "ta0", 12 }, | |
151 | { "ta1", 13 }, | |
152 | { "ta2", 14 }, | |
153 | { "ta3", 15 } | |
154 | }; | |
155 | ||
156 | /* Aliases for n32 and n64. */ | |
157 | const struct register_alias mips_n32_n64_aliases[] = { | |
158 | { "ta0", 8 }, | |
159 | { "ta1", 9 }, | |
160 | { "ta2", 10 }, | |
161 | { "ta3", 11 } | |
162 | }; | |
163 | ||
164 | /* Aliases for ABI-independent registers. */ | |
165 | const struct register_alias mips_register_aliases[] = { | |
166 | /* The architecture manuals specify these ABI-independent names for | |
167 | the GPRs. */ | |
168 | #define R(n) { "r" #n, n } | |
169 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
170 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
171 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
172 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
173 | #undef R | |
174 | ||
175 | /* k0 and k1 are sometimes called these instead (for "kernel | |
176 | temp"). */ | |
177 | { "kt0", 26 }, | |
178 | { "kt1", 27 }, | |
179 | ||
180 | /* This is the traditional GDB name for the CP0 status register. */ | |
181 | { "sr", MIPS_PS_REGNUM }, | |
182 | ||
183 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
184 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
185 | ||
186 | /* This is the traditional GDB name for the FCSR. */ | |
187 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
188 | }; | |
189 | ||
865093a3 AR |
190 | const struct register_alias mips_numeric_register_aliases[] = { |
191 | #define R(n) { #n, n } | |
192 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
193 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
194 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
195 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
196 | #undef R | |
197 | }; | |
198 | ||
c906108c SS |
199 | #ifndef MIPS_DEFAULT_FPU_TYPE |
200 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
201 | #endif | |
202 | static int mips_fpu_type_auto = 1; | |
203 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 204 | |
ccce17b0 | 205 | static unsigned int mips_debug = 0; |
7a292a7a | 206 | |
29709017 DJ |
207 | /* Properties (for struct target_desc) describing the g/G packet |
208 | layout. */ | |
209 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
210 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
211 | ||
4eb0ad19 DJ |
212 | struct target_desc *mips_tdesc_gp32; |
213 | struct target_desc *mips_tdesc_gp64; | |
214 | ||
471b9d15 MR |
215 | /* The current set of options to be passed to the disassembler. */ |
216 | static char *mips_disassembler_options; | |
217 | ||
218 | /* Implicit disassembler options for individual ABIs. These tell | |
219 | libopcodes to use general-purpose register names corresponding | |
220 | to the ABI we have selected, perhaps via a `set mips abi ...' | |
221 | override, rather than ones inferred from the ABI set in the ELF | |
222 | headers of the binary file selected for debugging. */ | |
223 | static const char mips_disassembler_options_o32[] = "gpr-names=32"; | |
224 | static const char mips_disassembler_options_n32[] = "gpr-names=n32"; | |
225 | static const char mips_disassembler_options_n64[] = "gpr-names=64"; | |
226 | ||
56cea623 AC |
227 | const struct mips_regnum * |
228 | mips_regnum (struct gdbarch *gdbarch) | |
229 | { | |
08106042 | 230 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
345bd07c | 231 | return tdep->regnum; |
56cea623 AC |
232 | } |
233 | ||
234 | static int | |
235 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
236 | { | |
237 | return mips_regnum (gdbarch)->fp0 + 12; | |
238 | } | |
239 | ||
004159a2 MR |
240 | /* Return 1 if REGNUM refers to a floating-point general register, raw |
241 | or cooked. Otherwise return 0. */ | |
242 | ||
243 | static int | |
244 | mips_float_register_p (struct gdbarch *gdbarch, int regnum) | |
245 | { | |
246 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
247 | ||
248 | return (rawnum >= mips_regnum (gdbarch)->fp0 | |
249 | && rawnum < mips_regnum (gdbarch)->fp0 + 32); | |
250 | } | |
251 | ||
345bd07c SM |
252 | static bool |
253 | mips_eabi (gdbarch *arch) | |
254 | { | |
08106042 | 255 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch); |
345bd07c SM |
256 | return (tdep->mips_abi == MIPS_ABI_EABI32 \ |
257 | || tdep->mips_abi == MIPS_ABI_EABI64); | |
258 | } | |
c2d11a7d | 259 | |
345bd07c SM |
260 | static int |
261 | mips_last_fp_arg_regnum (gdbarch *arch) | |
262 | { | |
08106042 | 263 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch); |
345bd07c SM |
264 | return tdep->mips_last_fp_arg_regnum; |
265 | } | |
c2d11a7d | 266 | |
345bd07c SM |
267 | static int |
268 | mips_last_arg_regnum (gdbarch *arch) | |
269 | { | |
08106042 | 270 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch); |
345bd07c SM |
271 | return tdep->mips_last_arg_regnum; |
272 | } | |
c2d11a7d | 273 | |
345bd07c SM |
274 | static enum mips_fpu_type |
275 | mips_get_fpu_type (gdbarch *arch) | |
276 | { | |
08106042 | 277 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch); |
345bd07c SM |
278 | return tdep->mips_fpu_type; |
279 | } | |
c2d11a7d | 280 | |
d1973055 KB |
281 | /* Return the MIPS ABI associated with GDBARCH. */ |
282 | enum mips_abi | |
283 | mips_abi (struct gdbarch *gdbarch) | |
284 | { | |
08106042 | 285 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
345bd07c | 286 | return tdep->mips_abi; |
d1973055 KB |
287 | } |
288 | ||
4246e332 | 289 | int |
1b13c4f6 | 290 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 291 | { |
08106042 | 292 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
29709017 DJ |
293 | |
294 | /* If we know how big the registers are, use that size. */ | |
295 | if (tdep->register_size_valid_p) | |
296 | return tdep->register_size; | |
297 | ||
298 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
299 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
300 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
301 | } | |
302 | ||
b3464d03 PA |
303 | /* Max saved register size. */ |
304 | #define MAX_MIPS_ABI_REGSIZE 8 | |
305 | ||
025bb325 | 306 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 307 | |
e6bc2e8a | 308 | unsigned int |
13326b4e | 309 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 310 | { |
1a69e1e4 DJ |
311 | switch (mips_abi (gdbarch)) |
312 | { | |
313 | case MIPS_ABI_EABI32: | |
314 | case MIPS_ABI_O32: | |
315 | return 4; | |
316 | case MIPS_ABI_N32: | |
317 | case MIPS_ABI_N64: | |
318 | case MIPS_ABI_O64: | |
319 | case MIPS_ABI_EABI64: | |
320 | return 8; | |
321 | case MIPS_ABI_UNKNOWN: | |
322 | case MIPS_ABI_LAST: | |
323 | default: | |
f34652de | 324 | internal_error (_("bad switch")); |
1a69e1e4 | 325 | } |
d929b26f AC |
326 | } |
327 | ||
4cc0665f MR |
328 | /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here |
329 | are some functions to handle addresses associated with compressed | |
330 | code including but not limited to testing, setting, or clearing | |
331 | bit 0 of such addresses. */ | |
742c84f6 | 332 | |
4cc0665f MR |
333 | /* Return one iff compressed code is the MIPS16 instruction set. */ |
334 | ||
335 | static int | |
336 | is_mips16_isa (struct gdbarch *gdbarch) | |
337 | { | |
08106042 | 338 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
345bd07c | 339 | return tdep->mips_isa == ISA_MIPS16; |
4cc0665f MR |
340 | } |
341 | ||
342 | /* Return one iff compressed code is the microMIPS instruction set. */ | |
343 | ||
344 | static int | |
345 | is_micromips_isa (struct gdbarch *gdbarch) | |
346 | { | |
08106042 | 347 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
345bd07c | 348 | return tdep->mips_isa == ISA_MICROMIPS; |
4cc0665f MR |
349 | } |
350 | ||
351 | /* Return one iff ADDR denotes compressed code. */ | |
352 | ||
353 | static int | |
354 | is_compact_addr (CORE_ADDR addr) | |
742c84f6 MR |
355 | { |
356 | return ((addr) & 1); | |
357 | } | |
358 | ||
4cc0665f MR |
359 | /* Return one iff ADDR denotes standard ISA code. */ |
360 | ||
361 | static int | |
362 | is_mips_addr (CORE_ADDR addr) | |
363 | { | |
364 | return !is_compact_addr (addr); | |
365 | } | |
366 | ||
367 | /* Return one iff ADDR denotes MIPS16 code. */ | |
368 | ||
369 | static int | |
370 | is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
371 | { | |
372 | return is_compact_addr (addr) && is_mips16_isa (gdbarch); | |
373 | } | |
374 | ||
375 | /* Return one iff ADDR denotes microMIPS code. */ | |
376 | ||
377 | static int | |
378 | is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
379 | { | |
380 | return is_compact_addr (addr) && is_micromips_isa (gdbarch); | |
381 | } | |
382 | ||
383 | /* Strip the ISA (compression) bit off from ADDR. */ | |
384 | ||
742c84f6 | 385 | static CORE_ADDR |
4cc0665f | 386 | unmake_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
387 | { |
388 | return ((addr) & ~(CORE_ADDR) 1); | |
389 | } | |
390 | ||
4cc0665f MR |
391 | /* Add the ISA (compression) bit to ADDR. */ |
392 | ||
742c84f6 | 393 | static CORE_ADDR |
4cc0665f | 394 | make_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
395 | { |
396 | return ((addr) | (CORE_ADDR) 1); | |
397 | } | |
398 | ||
3e29f34a MR |
399 | /* Extern version of unmake_compact_addr; we use a separate function |
400 | so that unmake_compact_addr can be inlined throughout this file. */ | |
401 | ||
402 | CORE_ADDR | |
403 | mips_unmake_compact_addr (CORE_ADDR addr) | |
404 | { | |
405 | return unmake_compact_addr (addr); | |
406 | } | |
407 | ||
71b8ef93 | 408 | /* Functions for setting and testing a bit in a minimal symbol that |
4cc0665f MR |
409 | marks it as MIPS16 or microMIPS function. The MSB of the minimal |
410 | symbol's "info" field is used for this purpose. | |
5a89d8aa | 411 | |
4cc0665f MR |
412 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is |
413 | "special", i.e. refers to a MIPS16 or microMIPS function, and sets | |
414 | one of the "special" bits in a minimal symbol to mark it accordingly. | |
415 | The test checks an ELF-private flag that is valid for true function | |
1bbce132 MR |
416 | symbols only; for synthetic symbols such as for PLT stubs that have |
417 | no ELF-private part at all the MIPS BFD backend arranges for this | |
418 | information to be carried in the asymbol's udata field instead. | |
5a89d8aa | 419 | |
4cc0665f MR |
420 | msymbol_is_mips16 and msymbol_is_micromips test the "special" bit |
421 | in a minimal symbol. */ | |
5a89d8aa | 422 | |
5a89d8aa | 423 | static void |
6d82d43b AC |
424 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
425 | { | |
4cc0665f | 426 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
1bbce132 | 427 | unsigned char st_other; |
4cc0665f | 428 | |
1bbce132 MR |
429 | if ((sym->flags & BSF_SYNTHETIC) == 0) |
430 | st_other = elfsym->internal_elf_sym.st_other; | |
431 | else if ((sym->flags & BSF_FUNCTION) != 0) | |
432 | st_other = sym->udata.i; | |
433 | else | |
4cc0665f MR |
434 | return; |
435 | ||
1bbce132 | 436 | if (ELF_ST_IS_MICROMIPS (st_other)) |
3e29f34a | 437 | { |
e165fcef | 438 | SET_MSYMBOL_TARGET_FLAG_MICROMIPS (msym); |
93d50cd8 | 439 | CORE_ADDR fixed = CORE_ADDR (msym->unrelocated_address ()) | 1; |
9675da25 | 440 | msym->set_unrelocated_address (unrelocated_addr (fixed)); |
3e29f34a | 441 | } |
1bbce132 | 442 | else if (ELF_ST_IS_MIPS16 (st_other)) |
3e29f34a | 443 | { |
e165fcef | 444 | SET_MSYMBOL_TARGET_FLAG_MIPS16 (msym); |
93d50cd8 | 445 | CORE_ADDR fixed = CORE_ADDR (msym->unrelocated_address ()) | 1; |
9675da25 | 446 | msym->set_unrelocated_address (unrelocated_addr (fixed)); |
3e29f34a | 447 | } |
4cc0665f MR |
448 | } |
449 | ||
450 | /* Return one iff MSYM refers to standard ISA code. */ | |
451 | ||
452 | static int | |
453 | msymbol_is_mips (struct minimal_symbol *msym) | |
454 | { | |
f161c171 | 455 | return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym) |
febb368c | 456 | || MSYMBOL_TARGET_FLAG_MICROMIPS (msym)); |
5a89d8aa MS |
457 | } |
458 | ||
4cc0665f MR |
459 | /* Return one iff MSYM refers to MIPS16 code. */ |
460 | ||
71b8ef93 | 461 | static int |
4cc0665f | 462 | msymbol_is_mips16 (struct minimal_symbol *msym) |
71b8ef93 | 463 | { |
f161c171 | 464 | return MSYMBOL_TARGET_FLAG_MIPS16 (msym); |
71b8ef93 MS |
465 | } |
466 | ||
4cc0665f MR |
467 | /* Return one iff MSYM refers to microMIPS code. */ |
468 | ||
469 | static int | |
470 | msymbol_is_micromips (struct minimal_symbol *msym) | |
471 | { | |
f161c171 | 472 | return MSYMBOL_TARGET_FLAG_MICROMIPS (msym); |
4cc0665f MR |
473 | } |
474 | ||
3e29f34a MR |
475 | /* Set the ISA bit in the main symbol too, complementing the corresponding |
476 | minimal symbol setting and reflecting the run-time value of the symbol. | |
477 | The need for comes from the ISA bit having been cleared as code in | |
478 | `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's | |
479 | `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values | |
480 | of symbols referring to compressed code different in GDB to the values | |
481 | used by actual code. That in turn makes them evaluate incorrectly in | |
482 | expressions, producing results different to what the same expressions | |
483 | yield when compiled into the program being debugged. */ | |
484 | ||
485 | static void | |
486 | mips_make_symbol_special (struct symbol *sym, struct objfile *objfile) | |
487 | { | |
66d7f48f | 488 | if (sym->aclass () == LOC_BLOCK) |
3e29f34a MR |
489 | { |
490 | /* We are in symbol reading so it is OK to cast away constness. */ | |
4aeddc50 | 491 | struct block *block = (struct block *) sym->value_block (); |
3e29f34a MR |
492 | CORE_ADDR compact_block_start; |
493 | struct bound_minimal_symbol msym; | |
494 | ||
4b8791e1 | 495 | compact_block_start = block->start () | 1; |
3e29f34a MR |
496 | msym = lookup_minimal_symbol_by_pc (compact_block_start); |
497 | if (msym.minsym && !msymbol_is_mips (msym.minsym)) | |
498 | { | |
4b8791e1 | 499 | block->set_start (compact_block_start); |
3e29f34a MR |
500 | } |
501 | } | |
502 | } | |
503 | ||
88658117 AC |
504 | /* XFER a value from the big/little/left end of the register. |
505 | Depending on the size of the value it might occupy the entire | |
506 | register or just part of it. Make an allowance for this, aligning | |
507 | things accordingly. */ | |
508 | ||
509 | static void | |
ba32f989 DJ |
510 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
511 | int reg_num, int length, | |
870cd05e MK |
512 | enum bfd_endian endian, gdb_byte *in, |
513 | const gdb_byte *out, int buf_offset) | |
88658117 | 514 | { |
88658117 | 515 | int reg_offset = 0; |
72a155b4 UW |
516 | |
517 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
518 | /* Need to transfer the left or right part of the register, based on |
519 | the targets byte order. */ | |
88658117 AC |
520 | switch (endian) |
521 | { | |
522 | case BFD_ENDIAN_BIG: | |
72a155b4 | 523 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
524 | break; |
525 | case BFD_ENDIAN_LITTLE: | |
526 | reg_offset = 0; | |
527 | break; | |
6d82d43b | 528 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
529 | reg_offset = 0; |
530 | break; | |
531 | default: | |
f34652de | 532 | internal_error (_("bad switch")); |
88658117 AC |
533 | } |
534 | if (mips_debug) | |
6cb06a8c TT |
535 | gdb_printf (gdb_stderr, |
536 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
537 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
538 | if (mips_debug && out != NULL) |
539 | { | |
540 | int i; | |
6cb06a8c | 541 | gdb_printf (gdb_stdlog, "out "); |
88658117 | 542 | for (i = 0; i < length; i++) |
6cb06a8c | 543 | gdb_printf (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
544 | } |
545 | if (in != NULL) | |
73bb0000 | 546 | regcache->cooked_read_part (reg_num, reg_offset, length, in + buf_offset); |
88658117 | 547 | if (out != NULL) |
e4c4a59b | 548 | regcache->cooked_write_part (reg_num, reg_offset, length, out + buf_offset); |
88658117 AC |
549 | if (mips_debug && in != NULL) |
550 | { | |
551 | int i; | |
6cb06a8c | 552 | gdb_printf (gdb_stdlog, "in "); |
88658117 | 553 | for (i = 0; i < length; i++) |
6cb06a8c | 554 | gdb_printf (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
555 | } |
556 | if (mips_debug) | |
6cb06a8c | 557 | gdb_printf (gdb_stdlog, "\n"); |
88658117 AC |
558 | } |
559 | ||
dd824b04 DJ |
560 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
561 | compatiblity mode. A return value of 1 means that we have | |
562 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
563 | ||
564 | static int | |
bd2b40ac | 565 | mips2_fp_compat (frame_info_ptr frame) |
dd824b04 | 566 | { |
72a155b4 | 567 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
568 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
569 | meaningful. */ | |
72a155b4 | 570 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
571 | return 0; |
572 | ||
573 | #if 0 | |
574 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
575 | in all the places we deal with FP registers. PR gdb/413. */ | |
576 | /* Otherwise check the FR bit in the status register - it controls | |
577 | the FP compatiblity mode. If it is clear we are in compatibility | |
578 | mode. */ | |
9c9acae0 | 579 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
580 | return 1; |
581 | #endif | |
361d1df0 | 582 | |
dd824b04 DJ |
583 | return 0; |
584 | } | |
585 | ||
7a292a7a | 586 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 587 | |
74ed0bb4 | 588 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 589 | |
025bb325 | 590 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
591 | |
592 | static struct cmd_list_element *setmipscmdlist = NULL; | |
593 | static struct cmd_list_element *showmipscmdlist = NULL; | |
594 | ||
5e2e9765 KB |
595 | /* Integer registers 0 thru 31 are handled explicitly by |
596 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 597 | are listed in the following tables. */ |
691c0433 | 598 | |
6d82d43b AC |
599 | enum |
600 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
601 | |
602 | /* Generic MIPS. */ | |
603 | ||
27087b7f | 604 | static const char * const mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
6d82d43b AC |
605 | "sr", "lo", "hi", "bad", "cause", "pc", |
606 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
607 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
608 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
609 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
1faeff08 | 610 | "fsr", "fir", |
691c0433 AC |
611 | }; |
612 | ||
691c0433 AC |
613 | /* Names of tx39 registers. */ |
614 | ||
27087b7f | 615 | static const char * const mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
6d82d43b AC |
616 | "sr", "lo", "hi", "bad", "cause", "pc", |
617 | "", "", "", "", "", "", "", "", | |
618 | "", "", "", "", "", "", "", "", | |
619 | "", "", "", "", "", "", "", "", | |
620 | "", "", "", "", "", "", "", "", | |
621 | "", "", "", "", | |
622 | "", "", "", "", "", "", "", "", | |
1faeff08 | 623 | "", "", "config", "cache", "debug", "depc", "epc", |
691c0433 AC |
624 | }; |
625 | ||
44099a67 | 626 | /* Names of registers with Linux kernels. */ |
27087b7f | 627 | static const char * const mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
1faeff08 MR |
628 | "sr", "lo", "hi", "bad", "cause", "pc", |
629 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
630 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
631 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
632 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
633 | "fsr", "fir" | |
634 | }; | |
635 | ||
cce74817 | 636 | |
5e2e9765 | 637 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 638 | static const char * |
d93859e2 | 639 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 640 | { |
08106042 | 641 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
5e2e9765 | 642 | /* GPR names for all ABIs other than n32/n64. */ |
a121b7c1 | 643 | static const char *mips_gpr_names[] = { |
6d82d43b AC |
644 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
645 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
646 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
647 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
648 | }; |
649 | ||
650 | /* GPR names for n32 and n64 ABIs. */ | |
a121b7c1 | 651 | static const char *mips_n32_n64_gpr_names[] = { |
6d82d43b AC |
652 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
653 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
654 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
655 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
656 | }; |
657 | ||
d93859e2 | 658 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 659 | |
f57d151a | 660 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
661 | but then don't make the raw register names visible. This (upper) |
662 | range of user visible register numbers are the pseudo-registers. | |
663 | ||
664 | This approach was adopted accommodate the following scenario: | |
665 | It is possible to debug a 64-bit device using a 32-bit | |
666 | programming model. In such instances, the raw registers are | |
667 | configured to be 64-bits wide, while the pseudo registers are | |
668 | configured to be 32-bits wide. The registers that the user | |
669 | sees - the pseudo registers - match the users expectations | |
670 | given the programming model being used. */ | |
d93859e2 UW |
671 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
672 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
673 | return ""; |
674 | ||
5e2e9765 KB |
675 | /* The MIPS integer registers are always mapped from 0 to 31. The |
676 | names of the registers (which reflects the conventions regarding | |
677 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 678 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
679 | { |
680 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 681 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 682 | else |
a4b8ebc8 | 683 | return mips_gpr_names[rawnum]; |
5e2e9765 | 684 | } |
d93859e2 UW |
685 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
686 | return tdesc_register_name (gdbarch, rawnum); | |
687 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
688 | { |
689 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
1faeff08 MR |
690 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
691 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
692 | return ""; | |
691c0433 | 693 | } |
5e2e9765 | 694 | else |
f34652de | 695 | internal_error (_("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 696 | } |
5e2e9765 | 697 | |
a4b8ebc8 | 698 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 699 | |
a4b8ebc8 AC |
700 | static int |
701 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 702 | const struct reggroup *reggroup) |
a4b8ebc8 AC |
703 | { |
704 | int vector_p; | |
705 | int float_p; | |
706 | int raw_p; | |
72a155b4 UW |
707 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
708 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
709 | if (reggroup == all_reggroup) |
710 | return pseudo; | |
bd63c870 | 711 | vector_p = register_type (gdbarch, regnum)->is_vector (); |
78134374 | 712 | float_p = register_type (gdbarch, regnum)->code () == TYPE_CODE_FLT; |
a4b8ebc8 AC |
713 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs |
714 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 | 715 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
637b2f86 | 716 | if (gdbarch_register_name (gdbarch, regnum)[0] == '\0') |
a4b8ebc8 AC |
717 | return 0; |
718 | if (reggroup == float_reggroup) | |
719 | return float_p && pseudo; | |
720 | if (reggroup == vector_reggroup) | |
721 | return vector_p && pseudo; | |
722 | if (reggroup == general_reggroup) | |
723 | return (!vector_p && !float_p) && pseudo; | |
724 | /* Save the pseudo registers. Need to make certain that any code | |
725 | extracting register values from a saved register cache also uses | |
726 | pseudo registers. */ | |
727 | if (reggroup == save_reggroup) | |
728 | return raw_p && pseudo; | |
729 | /* Restore the same pseudo register. */ | |
730 | if (reggroup == restore_reggroup) | |
731 | return raw_p && pseudo; | |
6d82d43b | 732 | return 0; |
a4b8ebc8 AC |
733 | } |
734 | ||
f8b73d13 DJ |
735 | /* Return the groups that a MIPS register can be categorised into. |
736 | This version is only used if we have a target description which | |
737 | describes real registers (and their groups). */ | |
738 | ||
739 | static int | |
740 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 741 | const struct reggroup *reggroup) |
f8b73d13 DJ |
742 | { |
743 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
744 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
745 | int ret; | |
746 | ||
747 | /* Only save, restore, and display the pseudo registers. Need to | |
748 | make certain that any code extracting register values from a | |
749 | saved register cache also uses pseudo registers. | |
750 | ||
751 | Note: saving and restoring the pseudo registers is slightly | |
752 | strange; if we have 64 bits, we should save and restore all | |
753 | 64 bits. But this is hard and has little benefit. */ | |
754 | if (!pseudo) | |
755 | return 0; | |
756 | ||
757 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
758 | if (ret != -1) | |
759 | return ret; | |
760 | ||
761 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
762 | } | |
763 | ||
a4b8ebc8 | 764 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 765 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 766 | registers. Take care of alignment and size problems. */ |
c5aa993b | 767 | |
05d1431c | 768 | static enum register_status |
849d0ba8 | 769 | mips_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
47a35522 | 770 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 771 | { |
72a155b4 UW |
772 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
773 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
774 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 775 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
03f50fc8 | 776 | return regcache->raw_read (rawnum, buf); |
6d82d43b AC |
777 | else if (register_size (gdbarch, rawnum) > |
778 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 779 | { |
08106042 | 780 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
345bd07c SM |
781 | |
782 | if (tdep->mips64_transfers_32bit_regs_p) | |
03f50fc8 | 783 | return regcache->raw_read_part (rawnum, 0, 4, buf); |
47ebcfbe | 784 | else |
8bdf35dc KB |
785 | { |
786 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
787 | LONGEST regval; | |
05d1431c PA |
788 | enum register_status status; |
789 | ||
03f50fc8 | 790 | status = regcache->raw_read (rawnum, ®val); |
05d1431c PA |
791 | if (status == REG_VALID) |
792 | store_signed_integer (buf, 4, byte_order, regval); | |
793 | return status; | |
8bdf35dc | 794 | } |
47ebcfbe AC |
795 | } |
796 | else | |
f34652de | 797 | internal_error (_("bad register size")); |
a4b8ebc8 AC |
798 | } |
799 | ||
800 | static void | |
6d82d43b AC |
801 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
802 | struct regcache *regcache, int cookednum, | |
47a35522 | 803 | const gdb_byte *buf) |
a4b8ebc8 | 804 | { |
72a155b4 UW |
805 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
806 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
807 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 808 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
10eaee5f | 809 | regcache->raw_write (rawnum, buf); |
6d82d43b AC |
810 | else if (register_size (gdbarch, rawnum) > |
811 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 812 | { |
08106042 | 813 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
345bd07c SM |
814 | |
815 | if (tdep->mips64_transfers_32bit_regs_p) | |
4f0420fd | 816 | regcache->raw_write_part (rawnum, 0, 4, buf); |
47ebcfbe | 817 | else |
8bdf35dc KB |
818 | { |
819 | /* Sign extend the shortened version of the register prior | |
820 | to placing it in the raw register. This is required for | |
821 | some mips64 parts in order to avoid unpredictable behavior. */ | |
822 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
823 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
824 | regcache_raw_write_signed (regcache, rawnum, regval); | |
825 | } | |
47ebcfbe AC |
826 | } |
827 | else | |
f34652de | 828 | internal_error (_("bad register size")); |
a4b8ebc8 | 829 | } |
c5aa993b | 830 | |
175ff332 HZ |
831 | static int |
832 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
833 | struct agent_expr *ax, int reg) | |
834 | { | |
835 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
836 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
837 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
838 | ||
839 | ax_reg_mask (ax, rawnum); | |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
844 | static int | |
845 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
846 | struct agent_expr *ax, int reg) | |
847 | { | |
848 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
849 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
850 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
851 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
852 | { | |
853 | ax_reg (ax, rawnum); | |
854 | ||
855 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
dda83cd7 | 856 | { |
345bd07c | 857 | mips_gdbarch_tdep *tdep |
08106042 | 858 | = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
345bd07c SM |
859 | |
860 | if (!tdep->mips64_transfers_32bit_regs_p | |
175ff332 HZ |
861 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) |
862 | { | |
863 | ax_const_l (ax, 32); | |
864 | ax_simple (ax, aop_lsh); | |
865 | } | |
866 | ax_const_l (ax, 32); | |
867 | ax_simple (ax, aop_rsh_signed); | |
868 | } | |
869 | } | |
870 | else | |
f34652de | 871 | internal_error (_("bad register size")); |
175ff332 HZ |
872 | |
873 | return 0; | |
874 | } | |
875 | ||
4cc0665f | 876 | /* Table to translate 3-bit register field to actual register number. */ |
d467df4e | 877 | static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
878 | |
879 | /* Heuristic_proc_start may hunt through the text section for a long | |
880 | time across a 2400 baud serial line. Allows the user to limit this | |
881 | search. */ | |
882 | ||
44096aee | 883 | static int heuristic_fence_post = 0; |
c906108c | 884 | |
46cd78fb | 885 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
886 | register N. NOTE: This defines the pseudo register type so need to |
887 | rebuild the architecture vector. */ | |
43e526b9 | 888 | |
491144b5 | 889 | static bool mips64_transfers_32bit_regs_p = false; |
43e526b9 | 890 | |
719ec221 | 891 | static void |
eb4c3f4a | 892 | set_mips64_transfers_32bit_regs (const char *args, int from_tty, |
719ec221 | 893 | struct cmd_list_element *c) |
43e526b9 | 894 | { |
719ec221 | 895 | struct gdbarch_info info; |
719ec221 AC |
896 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
897 | instead of relying on globals. Doing that would let generic code | |
898 | handle the search for this specific architecture. */ | |
899 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 900 | { |
719ec221 | 901 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 902 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 903 | } |
a4b8ebc8 AC |
904 | } |
905 | ||
47ebcfbe | 906 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 907 | |
ee51a8c7 KB |
908 | /* This predicate tests for the case of an 8 byte floating point |
909 | value that is being transferred to or from a pair of floating point | |
910 | registers each of which are (or are considered to be) only 4 bytes | |
911 | wide. */ | |
ff2e87ac | 912 | static int |
ee51a8c7 KB |
913 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
914 | struct type *type) | |
ff2e87ac | 915 | { |
0abe36f5 MD |
916 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
917 | && register_size (gdbarch, regnum) == 4 | |
004159a2 | 918 | && mips_float_register_p (gdbarch, regnum) |
df86565b | 919 | && type->code () == TYPE_CODE_FLT && type->length () == 8); |
ff2e87ac AC |
920 | } |
921 | ||
ee51a8c7 KB |
922 | /* This predicate tests for the case of a value of less than 8 |
923 | bytes in width that is being transfered to or from an 8 byte | |
924 | general purpose register. */ | |
925 | static int | |
926 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
927 | struct type *type) | |
928 | { | |
929 | int num_regs = gdbarch_num_regs (gdbarch); | |
930 | ||
931 | return (register_size (gdbarch, regnum) == 8 | |
dda83cd7 | 932 | && regnum % num_regs > 0 && regnum % num_regs < 32 |
df86565b | 933 | && type->length () < 8); |
ee51a8c7 KB |
934 | } |
935 | ||
936 | static int | |
025bb325 MS |
937 | mips_convert_register_p (struct gdbarch *gdbarch, |
938 | int regnum, struct type *type) | |
ee51a8c7 | 939 | { |
eaa05d59 MR |
940 | return (mips_convert_register_float_case_p (gdbarch, regnum, type) |
941 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); | |
ee51a8c7 KB |
942 | } |
943 | ||
8dccd430 | 944 | static int |
bd2b40ac | 945 | mips_register_to_value (frame_info_ptr frame, int regnum, |
8dccd430 PA |
946 | struct type *type, gdb_byte *to, |
947 | int *optimizedp, int *unavailablep) | |
102182a9 | 948 | { |
ee51a8c7 | 949 | struct gdbarch *gdbarch = get_frame_arch (frame); |
9fc79b42 | 950 | frame_info_ptr next_frame = get_next_frame_sentinel_okay (frame); |
ee51a8c7 KB |
951 | |
952 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
953 | { | |
954 | get_frame_register (frame, regnum + 0, to + 4); | |
955 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 | 956 | |
9fc79b42 | 957 | if (!get_frame_register_bytes (next_frame, regnum + 0, 0, { to + 4, 4 }, |
8dccd430 PA |
958 | optimizedp, unavailablep)) |
959 | return 0; | |
960 | ||
9fc79b42 | 961 | if (!get_frame_register_bytes (next_frame, regnum + 1, 0, { to + 0, 4 }, |
8dccd430 PA |
962 | optimizedp, unavailablep)) |
963 | return 0; | |
964 | *optimizedp = *unavailablep = 0; | |
965 | return 1; | |
ee51a8c7 KB |
966 | } |
967 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
968 | { | |
df86565b | 969 | size_t len = type->length (); |
8dccd430 PA |
970 | CORE_ADDR offset; |
971 | ||
972 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
9fc79b42 | 973 | if (!get_frame_register_bytes (next_frame, regnum, offset, { to, len }, |
8dccd430 PA |
974 | optimizedp, unavailablep)) |
975 | return 0; | |
976 | ||
977 | *optimizedp = *unavailablep = 0; | |
978 | return 1; | |
ee51a8c7 KB |
979 | } |
980 | else | |
981 | { | |
f34652de | 982 | internal_error (_("mips_register_to_value: unrecognized case")); |
ee51a8c7 | 983 | } |
102182a9 MS |
984 | } |
985 | ||
42c466d7 | 986 | static void |
bd2b40ac | 987 | mips_value_to_register (frame_info_ptr frame, int regnum, |
47a35522 | 988 | struct type *type, const gdb_byte *from) |
102182a9 | 989 | { |
ee51a8c7 KB |
990 | struct gdbarch *gdbarch = get_frame_arch (frame); |
991 | ||
992 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
993 | { | |
f6e3d557 | 994 | auto from_view = gdb::make_array_view (from, 8); |
584468de SM |
995 | frame_info_ptr next_frame = get_next_frame_sentinel_okay (frame); |
996 | put_frame_register (next_frame, regnum, from_view.slice (4)); | |
997 | put_frame_register (next_frame, regnum + 1, from_view.slice (0, 4)); | |
ee51a8c7 KB |
998 | } |
999 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
1000 | { | |
1001 | gdb_byte fill[8]; | |
df86565b | 1002 | size_t len = type->length (); |
534dcbcb SM |
1003 | frame_info_ptr next_frame = get_next_frame_sentinel_okay (frame); |
1004 | ||
ee51a8c7 | 1005 | /* Sign extend values, irrespective of type, that are stored to |
dda83cd7 | 1006 | a 64-bit general purpose register. (32-bit unsigned values |
ee51a8c7 KB |
1007 | are stored as signed quantities within a 64-bit register. |
1008 | When performing an operation, in compiled code, that combines | |
1009 | a 32-bit unsigned value with a signed 64-bit value, a type | |
1010 | conversion is first performed that zeroes out the high 32 bits.) */ | |
1011 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
1012 | { | |
1013 | if (from[0] & 0x80) | |
1014 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
1015 | else | |
1016 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
534dcbcb SM |
1017 | put_frame_register_bytes (next_frame, regnum, 0, {fill, 8 - len}); |
1018 | put_frame_register_bytes (next_frame, regnum, 8 - len, {from, len}); | |
ee51a8c7 KB |
1019 | } |
1020 | else | |
1021 | { | |
1022 | if (from[len-1] & 0x80) | |
1023 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
1024 | else | |
1025 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
534dcbcb SM |
1026 | put_frame_register_bytes (next_frame, regnum, 0, {from, len}); |
1027 | put_frame_register_bytes (next_frame, regnum, len, {fill, 8 - len}); | |
ee51a8c7 KB |
1028 | } |
1029 | } | |
1030 | else | |
1031 | { | |
f34652de | 1032 | internal_error (_("mips_value_to_register: unrecognized case")); |
ee51a8c7 | 1033 | } |
102182a9 MS |
1034 | } |
1035 | ||
a4b8ebc8 AC |
1036 | /* Return the GDB type object for the "standard" data type of data in |
1037 | register REG. */ | |
78fde5f8 KB |
1038 | |
1039 | static struct type * | |
a4b8ebc8 AC |
1040 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
1041 | { | |
72a155b4 | 1042 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
004159a2 | 1043 | if (mips_float_register_p (gdbarch, regnum)) |
a6425924 | 1044 | { |
5ef80fb0 | 1045 | /* The floating-point registers raw, or cooked, always match |
dda83cd7 | 1046 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 1047 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 1048 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 1049 | else |
27067745 | 1050 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 1051 | } |
72a155b4 | 1052 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
1053 | { |
1054 | /* The raw or ISA registers. These are all sized according to | |
1055 | the ISA regsize. */ | |
1056 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 1057 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 1058 | else |
df4df182 | 1059 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 1060 | } |
78fde5f8 | 1061 | else |
d5ac5a39 | 1062 | { |
1faeff08 | 1063 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
08106042 | 1064 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
1faeff08 | 1065 | |
d5ac5a39 AC |
1066 | /* The cooked or ABI registers. These are sized according to |
1067 | the ABI (with a few complications). */ | |
1faeff08 MR |
1068 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
1069 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
1070 | return builtin_type (gdbarch)->builtin_int32; | |
de4bfa86 | 1071 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
1faeff08 MR |
1072 | && rawnum >= MIPS_FIRST_EMBED_REGNUM |
1073 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
1074 | /* The pseudo/cooked view of the embedded registers is always |
1075 | 32-bit. The raw view is handled below. */ | |
df4df182 | 1076 | return builtin_type (gdbarch)->builtin_int32; |
345bd07c | 1077 | else if (tdep->mips64_transfers_32bit_regs_p) |
d5ac5a39 AC |
1078 | /* The target, while possibly using a 64-bit register buffer, |
1079 | is only transfering 32-bits of each integer register. | |
1080 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 1081 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1082 | else if (mips_abi_regsize (gdbarch) == 4) |
1083 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
1084 | 32- or 64-bit). */ | |
df4df182 | 1085 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1086 | else |
1087 | /* 64-bit ABI. */ | |
df4df182 | 1088 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 1089 | } |
78fde5f8 KB |
1090 | } |
1091 | ||
f8b73d13 DJ |
1092 | /* Return the GDB type for the pseudo register REGNUM, which is the |
1093 | ABI-level view. This function is only called if there is a target | |
1094 | description which includes registers, so we know precisely the | |
1095 | types of hardware registers. */ | |
1096 | ||
1097 | static struct type * | |
1098 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
1099 | { | |
1100 | const int num_regs = gdbarch_num_regs (gdbarch); | |
f8b73d13 DJ |
1101 | int rawnum = regnum % num_regs; |
1102 | struct type *rawtype; | |
1103 | ||
1104 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
1105 | ||
1106 | /* Absent registers are still absent. */ | |
1107 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
df86565b | 1108 | if (rawtype->length () == 0) |
f8b73d13 DJ |
1109 | return rawtype; |
1110 | ||
a6912260 MR |
1111 | /* Present the floating point registers however the hardware did; |
1112 | do not try to convert between FPU layouts. */ | |
de13fcf2 | 1113 | if (mips_float_register_p (gdbarch, rawnum)) |
f8b73d13 DJ |
1114 | return rawtype; |
1115 | ||
78b86327 MR |
1116 | /* Floating-point control registers are always 32-bit even though for |
1117 | backwards compatibility reasons 64-bit targets will transfer them | |
1118 | as 64-bit quantities even if using XML descriptions. */ | |
1119 | if (rawnum == mips_regnum (gdbarch)->fp_control_status | |
1120 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
1121 | return builtin_type (gdbarch)->builtin_int32; | |
1122 | ||
f8b73d13 DJ |
1123 | /* Use pointer types for registers if we can. For n32 we can not, |
1124 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb | 1125 | if (mips_abi_regsize (gdbarch) |
df86565b | 1126 | == builtin_type (gdbarch)->builtin_data_ptr->length()) |
f8b73d13 | 1127 | { |
1faeff08 MR |
1128 | if (rawnum == MIPS_SP_REGNUM |
1129 | || rawnum == mips_regnum (gdbarch)->badvaddr) | |
0dfff4cb | 1130 | return builtin_type (gdbarch)->builtin_data_ptr; |
1faeff08 | 1131 | else if (rawnum == mips_regnum (gdbarch)->pc) |
0dfff4cb | 1132 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
1133 | } |
1134 | ||
df86565b | 1135 | if (mips_abi_regsize (gdbarch) == 4 && rawtype->length () == 8 |
1faeff08 MR |
1136 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
1137 | || rawnum == mips_regnum (gdbarch)->lo | |
1138 | || rawnum == mips_regnum (gdbarch)->hi | |
1139 | || rawnum == mips_regnum (gdbarch)->badvaddr | |
1140 | || rawnum == mips_regnum (gdbarch)->cause | |
1141 | || rawnum == mips_regnum (gdbarch)->pc | |
1142 | || (mips_regnum (gdbarch)->dspacc != -1 | |
1143 | && rawnum >= mips_regnum (gdbarch)->dspacc | |
1144 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) | |
df4df182 | 1145 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 | 1146 | |
a6912260 MR |
1147 | /* The pseudo/cooked view of embedded registers is always |
1148 | 32-bit, even if the target transfers 64-bit values for them. | |
1149 | New targets relying on XML descriptions should only transfer | |
1150 | the necessary 32 bits, but older versions of GDB expected 64, | |
1151 | so allow the target to provide 64 bits without interfering | |
1152 | with the displayed type. */ | |
de4bfa86 | 1153 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
78b86327 | 1154 | && rawnum >= MIPS_FIRST_EMBED_REGNUM |
1faeff08 | 1155 | && rawnum <= MIPS_LAST_EMBED_REGNUM) |
a6912260 | 1156 | return builtin_type (gdbarch)->builtin_int32; |
1faeff08 | 1157 | |
f8b73d13 DJ |
1158 | /* For all other registers, pass through the hardware type. */ |
1159 | return rawtype; | |
1160 | } | |
bcb0cc15 | 1161 | |
025bb325 | 1162 | /* Should the upper word of 64-bit addresses be zeroed? */ |
ea33cd92 | 1163 | static enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
1164 | |
1165 | static int | |
345bd07c | 1166 | mips_mask_address_p (mips_gdbarch_tdep *tdep) |
4014092b AC |
1167 | { |
1168 | switch (mask_address_var) | |
1169 | { | |
7f19b9a2 | 1170 | case AUTO_BOOLEAN_TRUE: |
4014092b | 1171 | return 1; |
7f19b9a2 | 1172 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1173 | return 0; |
1174 | break; | |
7f19b9a2 | 1175 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 1176 | return tdep->default_mask_address_p; |
4014092b | 1177 | default: |
f34652de | 1178 | internal_error (_("mips_mask_address_p: bad switch")); |
4014092b | 1179 | return -1; |
361d1df0 | 1180 | } |
4014092b AC |
1181 | } |
1182 | ||
1183 | static void | |
08546159 AC |
1184 | show_mask_address (struct ui_file *file, int from_tty, |
1185 | struct cmd_list_element *c, const char *value) | |
4014092b | 1186 | { |
52abb4de AB |
1187 | const char *additional_text = ""; |
1188 | if (mask_address_var == AUTO_BOOLEAN_AUTO) | |
4014092b | 1189 | { |
99d9c3b9 SM |
1190 | if (gdbarch_bfd_arch_info (current_inferior ()->arch ())->arch |
1191 | != bfd_arch_mips) | |
52abb4de AB |
1192 | additional_text = _(" (current architecture is not MIPS)"); |
1193 | else | |
1194 | { | |
1195 | mips_gdbarch_tdep *tdep | |
99d9c3b9 | 1196 | = gdbarch_tdep<mips_gdbarch_tdep> (current_inferior ()->arch ()); |
52abb4de AB |
1197 | |
1198 | if (mips_mask_address_p (tdep)) | |
1199 | additional_text = _(" (currently \"on\")"); | |
1200 | else | |
1201 | additional_text = _(" (currently \"off\")"); | |
1202 | } | |
361d1df0 | 1203 | } |
52abb4de AB |
1204 | |
1205 | gdb_printf (file, _("Zeroing of upper 32 bits of 64-bit addresses is \"%s\"%s.\n"), | |
1206 | value, additional_text); | |
4014092b | 1207 | } |
c906108c | 1208 | |
4cc0665f MR |
1209 | /* Tell if the program counter value in MEMADDR is in a standard ISA |
1210 | function. */ | |
1211 | ||
1212 | int | |
1213 | mips_pc_is_mips (CORE_ADDR memaddr) | |
1214 | { | |
7cbd4a93 | 1215 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1216 | |
1217 | /* Flags indicating that this is a MIPS16 or microMIPS function is | |
1218 | stored by elfread.c in the high bit of the info field. Use this | |
1219 | to decide if the function is standard MIPS. Otherwise if bit 0 | |
1220 | of the address is clear, then this is a standard MIPS function. */ | |
3e29f34a | 1221 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1222 | if (sym.minsym) |
1223 | return msymbol_is_mips (sym.minsym); | |
4cc0665f MR |
1224 | else |
1225 | return is_mips_addr (memaddr); | |
1226 | } | |
1227 | ||
c906108c SS |
1228 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
1229 | ||
0fe7e7c8 | 1230 | int |
4cc0665f | 1231 | mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
c906108c | 1232 | { |
7cbd4a93 | 1233 | struct bound_minimal_symbol sym; |
c906108c | 1234 | |
91912e4d MR |
1235 | /* A flag indicating that this is a MIPS16 function is stored by |
1236 | elfread.c in the high bit of the info field. Use this to decide | |
4cc0665f MR |
1237 | if the function is MIPS16. Otherwise if bit 0 of the address is |
1238 | set, then ELF file flags will tell if this is a MIPS16 function. */ | |
3e29f34a | 1239 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1240 | if (sym.minsym) |
1241 | return msymbol_is_mips16 (sym.minsym); | |
4cc0665f MR |
1242 | else |
1243 | return is_mips16_addr (gdbarch, memaddr); | |
1244 | } | |
1245 | ||
1246 | /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ | |
1247 | ||
1248 | int | |
1249 | mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1250 | { | |
7cbd4a93 | 1251 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1252 | |
1253 | /* A flag indicating that this is a microMIPS function is stored by | |
1254 | elfread.c in the high bit of the info field. Use this to decide | |
1255 | if the function is microMIPS. Otherwise if bit 0 of the address | |
1256 | is set, then ELF file flags will tell if this is a microMIPS | |
1257 | function. */ | |
3e29f34a | 1258 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1259 | if (sym.minsym) |
1260 | return msymbol_is_micromips (sym.minsym); | |
4cc0665f MR |
1261 | else |
1262 | return is_micromips_addr (gdbarch, memaddr); | |
1263 | } | |
1264 | ||
1265 | /* Tell the ISA type of the function the program counter value in MEMADDR | |
1266 | is in. */ | |
1267 | ||
1268 | static enum mips_isa | |
1269 | mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1270 | { | |
7cbd4a93 | 1271 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1272 | |
1273 | /* A flag indicating that this is a MIPS16 or a microMIPS function | |
1274 | is stored by elfread.c in the high bit of the info field. Use | |
1275 | this to decide if the function is MIPS16 or microMIPS or normal | |
1276 | MIPS. Otherwise if bit 0 of the address is set, then ELF file | |
1277 | flags will tell if this is a MIPS16 or a microMIPS function. */ | |
3e29f34a | 1278 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 | 1279 | if (sym.minsym) |
4cc0665f | 1280 | { |
7cbd4a93 | 1281 | if (msymbol_is_micromips (sym.minsym)) |
4cc0665f | 1282 | return ISA_MICROMIPS; |
7cbd4a93 | 1283 | else if (msymbol_is_mips16 (sym.minsym)) |
4cc0665f MR |
1284 | return ISA_MIPS16; |
1285 | else | |
1286 | return ISA_MIPS; | |
1287 | } | |
c906108c | 1288 | else |
4cc0665f MR |
1289 | { |
1290 | if (is_mips_addr (memaddr)) | |
1291 | return ISA_MIPS; | |
1292 | else if (is_micromips_addr (gdbarch, memaddr)) | |
1293 | return ISA_MICROMIPS; | |
1294 | else | |
1295 | return ISA_MIPS16; | |
1296 | } | |
c906108c SS |
1297 | } |
1298 | ||
3e29f34a MR |
1299 | /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery. |
1300 | The need for comes from the ISA bit having been cleared, making | |
1301 | addresses in FDE, range records, etc. referring to compressed code | |
1302 | different to those in line information, the symbol table and finally | |
1303 | the PC register. That in turn confuses many operations. */ | |
1304 | ||
1305 | static CORE_ADDR | |
1306 | mips_adjust_dwarf2_addr (CORE_ADDR pc) | |
1307 | { | |
1308 | pc = unmake_compact_addr (pc); | |
1309 | return mips_pc_is_mips (pc) ? pc : make_compact_addr (pc); | |
1310 | } | |
1311 | ||
1312 | /* Recalculate the line record requested so that the resulting PC has | |
1313 | the ISA bit set correctly, used by DWARF-2 machinery. The need for | |
1314 | this adjustment comes from some records associated with compressed | |
1315 | code having the ISA bit cleared, most notably at function prologue | |
1316 | ends. The ISA bit is in this context retrieved from the minimal | |
1317 | symbol covering the address requested, which in turn has been | |
1318 | constructed from the binary's symbol table rather than DWARF-2 | |
1319 | information. The correct setting of the ISA bit is required for | |
1320 | breakpoint addresses to correctly match against the stop PC. | |
1321 | ||
1322 | As line entries can specify relative address adjustments we need to | |
1323 | keep track of the absolute value of the last line address recorded | |
1324 | in line information, so that we can calculate the actual address to | |
1325 | apply the ISA bit adjustment to. We use PC for this tracking and | |
1326 | keep the original address there. | |
1327 | ||
1328 | As such relative address adjustments can be odd within compressed | |
1329 | code we need to keep track of the last line address with the ISA | |
1330 | bit adjustment applied too, as the original address may or may not | |
1331 | have had the ISA bit set. We use ADJ_PC for this tracking and keep | |
1332 | the adjusted address there. | |
1333 | ||
1334 | For relative address adjustments we then use these variables to | |
1335 | calculate the address intended by line information, which will be | |
1336 | PC-relative, and return an updated adjustment carrying ISA bit | |
1337 | information, which will be ADJ_PC-relative. For absolute address | |
1338 | adjustments we just return the same address that we store in ADJ_PC | |
1339 | too. | |
1340 | ||
1341 | As the first line entry can be relative to an implied address value | |
1342 | of 0 we need to have the initial address set up that we store in PC | |
1343 | and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1' | |
1344 | that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */ | |
1345 | ||
1346 | static CORE_ADDR | |
1347 | mips_adjust_dwarf2_line (CORE_ADDR addr, int rel) | |
1348 | { | |
1349 | static CORE_ADDR adj_pc; | |
1350 | static CORE_ADDR pc; | |
1351 | CORE_ADDR isa_pc; | |
1352 | ||
1353 | pc = rel ? pc + addr : addr; | |
1354 | isa_pc = mips_adjust_dwarf2_addr (pc); | |
1355 | addr = rel ? isa_pc - adj_pc : isa_pc; | |
1356 | adj_pc = isa_pc; | |
1357 | return addr; | |
1358 | } | |
1359 | ||
14132e89 MR |
1360 | /* Various MIPS16 thunk (aka stub or trampoline) names. */ |
1361 | ||
1362 | static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; | |
1363 | static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; | |
1364 | static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; | |
1365 | static const char mips_str_call_stub[] = "__call_stub_"; | |
1366 | static const char mips_str_fn_stub[] = "__fn_stub_"; | |
1367 | ||
1368 | /* This is used as a PIC thunk prefix. */ | |
1369 | ||
1370 | static const char mips_str_pic[] = ".pic."; | |
1371 | ||
1372 | /* Return non-zero if the PC is inside a call thunk (aka stub or | |
1373 | trampoline) that should be treated as a temporary frame. */ | |
1374 | ||
1375 | static int | |
1376 | mips_in_frame_stub (CORE_ADDR pc) | |
1377 | { | |
1378 | CORE_ADDR start_addr; | |
1379 | const char *name; | |
1380 | ||
1381 | /* Find the starting address of the function containing the PC. */ | |
1382 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1383 | return 0; | |
1384 | ||
1385 | /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ | |
61012eef | 1386 | if (startswith (name, mips_str_mips16_call_stub)) |
14132e89 MR |
1387 | return 1; |
1388 | /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ | |
61012eef | 1389 | if (startswith (name, mips_str_call_stub)) |
14132e89 MR |
1390 | return 1; |
1391 | /* If the PC is in __fn_stub_*, this is a call stub. */ | |
61012eef | 1392 | if (startswith (name, mips_str_fn_stub)) |
14132e89 MR |
1393 | return 1; |
1394 | ||
1395 | return 0; /* Not a stub. */ | |
1396 | } | |
1397 | ||
b2fa5097 | 1398 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1399 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1400 | |
1401 | static CORE_ADDR | |
c113ed0c | 1402 | mips_read_pc (readable_regcache *regcache) |
6c997a34 | 1403 | { |
ac7936df | 1404 | int regnum = gdbarch_pc_regnum (regcache->arch ()); |
70242eb1 | 1405 | LONGEST pc; |
8376de04 | 1406 | |
c113ed0c | 1407 | regcache->cooked_read (regnum, &pc); |
61a1198a | 1408 | return pc; |
b6cb9035 AC |
1409 | } |
1410 | ||
58dfe9ff | 1411 | static CORE_ADDR |
bd2b40ac | 1412 | mips_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame) |
58dfe9ff | 1413 | { |
14132e89 | 1414 | CORE_ADDR pc; |
930bd0e0 | 1415 | |
8376de04 | 1416 | pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); |
14132e89 MR |
1417 | /* macro/2012-04-20: This hack skips over MIPS16 call thunks as |
1418 | intermediate frames. In this case we can get the caller's address | |
1419 | from $ra, or if $ra contains an address within a thunk as well, then | |
1420 | it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} | |
1421 | and thus the caller's address is in $s2. */ | |
1422 | if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) | |
1423 | { | |
1424 | pc = frame_unwind_register_signed | |
1425 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
14132e89 | 1426 | if (mips_in_frame_stub (pc)) |
3e29f34a MR |
1427 | pc = frame_unwind_register_signed |
1428 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
14132e89 | 1429 | } |
930bd0e0 | 1430 | return pc; |
edfae063 AC |
1431 | } |
1432 | ||
30244cd8 | 1433 | static CORE_ADDR |
bd2b40ac | 1434 | mips_unwind_sp (struct gdbarch *gdbarch, frame_info_ptr next_frame) |
30244cd8 | 1435 | { |
72a155b4 UW |
1436 | return frame_unwind_register_signed |
1437 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1438 | } |
1439 | ||
b8a22b94 | 1440 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1441 | dummy frame. The frame ID's base needs to match the TOS value |
1442 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1443 | breakpoint. */ | |
1444 | ||
1445 | static struct frame_id | |
bd2b40ac | 1446 | mips_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame) |
edfae063 | 1447 | { |
f57d151a | 1448 | return frame_id_build |
b8a22b94 DJ |
1449 | (get_frame_register_signed (this_frame, |
1450 | gdbarch_num_regs (gdbarch) | |
1451 | + MIPS_SP_REGNUM), | |
1452 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1453 | } |
1454 | ||
5a439849 MR |
1455 | /* Implement the "write_pc" gdbarch method. */ |
1456 | ||
1457 | void | |
61a1198a | 1458 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1459 | { |
ac7936df | 1460 | int regnum = gdbarch_pc_regnum (regcache->arch ()); |
8376de04 | 1461 | |
3e29f34a | 1462 | regcache_cooked_write_unsigned (regcache, regnum, pc); |
6c997a34 | 1463 | } |
c906108c | 1464 | |
4cc0665f MR |
1465 | /* Fetch and return instruction from the specified location. Handle |
1466 | MIPS16/microMIPS as appropriate. */ | |
c906108c | 1467 | |
d37cca3d | 1468 | static ULONGEST |
4cc0665f | 1469 | mips_fetch_instruction (struct gdbarch *gdbarch, |
d09f2c3f | 1470 | enum mips_isa isa, CORE_ADDR addr, int *errp) |
c906108c | 1471 | { |
e17a4113 | 1472 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1473 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c | 1474 | int instlen; |
d09f2c3f | 1475 | int err; |
c906108c | 1476 | |
4cc0665f | 1477 | switch (isa) |
c906108c | 1478 | { |
4cc0665f MR |
1479 | case ISA_MICROMIPS: |
1480 | case ISA_MIPS16: | |
95ac2dcf | 1481 | instlen = MIPS_INSN16_SIZE; |
4cc0665f MR |
1482 | addr = unmake_compact_addr (addr); |
1483 | break; | |
1484 | case ISA_MIPS: | |
1485 | instlen = MIPS_INSN32_SIZE; | |
1486 | break; | |
1487 | default: | |
f34652de | 1488 | internal_error (_("invalid ISA")); |
4cc0665f | 1489 | break; |
c906108c | 1490 | } |
d09f2c3f PA |
1491 | err = target_read_memory (addr, buf, instlen); |
1492 | if (errp != NULL) | |
1493 | *errp = err; | |
1494 | if (err != 0) | |
4cc0665f | 1495 | { |
d09f2c3f PA |
1496 | if (errp == NULL) |
1497 | memory_error (TARGET_XFER_E_IO, addr); | |
4cc0665f MR |
1498 | return 0; |
1499 | } | |
e17a4113 | 1500 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1501 | } |
1502 | ||
025bb325 | 1503 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1504 | #define mips32_op(x) (x >> 26) |
1505 | #define itype_op(x) (x >> 26) | |
1506 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1507 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1508 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1509 | |
e135b889 DJ |
1510 | #define jtype_op(x) (x >> 26) |
1511 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1512 | |
e135b889 DJ |
1513 | #define rtype_op(x) (x >> 26) |
1514 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1515 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1516 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1517 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1518 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1519 | |
4cc0665f MR |
1520 | /* MicroMIPS instruction fields. */ |
1521 | #define micromips_op(x) ((x) >> 10) | |
1522 | ||
1523 | /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest | |
1524 | bit and the size respectively of the field extracted. */ | |
1525 | #define b0s4_imm(x) ((x) & 0xf) | |
1526 | #define b0s5_imm(x) ((x) & 0x1f) | |
1527 | #define b0s5_reg(x) ((x) & 0x1f) | |
1528 | #define b0s7_imm(x) ((x) & 0x7f) | |
1529 | #define b0s10_imm(x) ((x) & 0x3ff) | |
1530 | #define b1s4_imm(x) (((x) >> 1) & 0xf) | |
1531 | #define b1s9_imm(x) (((x) >> 1) & 0x1ff) | |
1532 | #define b2s3_cc(x) (((x) >> 2) & 0x7) | |
1533 | #define b4s2_regl(x) (((x) >> 4) & 0x3) | |
1534 | #define b5s5_op(x) (((x) >> 5) & 0x1f) | |
1535 | #define b5s5_reg(x) (((x) >> 5) & 0x1f) | |
1536 | #define b6s4_op(x) (((x) >> 6) & 0xf) | |
1537 | #define b7s3_reg(x) (((x) >> 7) & 0x7) | |
1538 | ||
1539 | /* 32-bit instruction formats, B and S refer to the lowest bit and the size | |
1540 | respectively of the field extracted. */ | |
1541 | #define b0s6_op(x) ((x) & 0x3f) | |
1542 | #define b0s11_op(x) ((x) & 0x7ff) | |
1543 | #define b0s12_imm(x) ((x) & 0xfff) | |
1544 | #define b0s16_imm(x) ((x) & 0xffff) | |
1545 | #define b0s26_imm(x) ((x) & 0x3ffffff) | |
1546 | #define b6s10_ext(x) (((x) >> 6) & 0x3ff) | |
1547 | #define b11s5_reg(x) (((x) >> 11) & 0x1f) | |
1548 | #define b12s4_op(x) (((x) >> 12) & 0xf) | |
1549 | ||
1550 | /* Return the size in bytes of the instruction INSN encoded in the ISA | |
1551 | instruction set. */ | |
1552 | ||
1553 | static int | |
1554 | mips_insn_size (enum mips_isa isa, ULONGEST insn) | |
1555 | { | |
1556 | switch (isa) | |
1557 | { | |
1558 | case ISA_MICROMIPS: | |
100b4f2e MR |
1559 | if ((micromips_op (insn) & 0x4) == 0x4 |
1560 | || (micromips_op (insn) & 0x7) == 0x0) | |
dda83cd7 | 1561 | return 2 * MIPS_INSN16_SIZE; |
4cc0665f | 1562 | else |
dda83cd7 | 1563 | return MIPS_INSN16_SIZE; |
4cc0665f MR |
1564 | case ISA_MIPS16: |
1565 | if ((insn & 0xf800) == 0xf000) | |
1566 | return 2 * MIPS_INSN16_SIZE; | |
1567 | else | |
1568 | return MIPS_INSN16_SIZE; | |
1569 | case ISA_MIPS: | |
1570 | return MIPS_INSN32_SIZE; | |
1571 | } | |
f34652de | 1572 | internal_error (_("invalid ISA")); |
4cc0665f MR |
1573 | } |
1574 | ||
06987e64 MK |
1575 | static LONGEST |
1576 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1577 | { |
06987e64 | 1578 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1579 | } |
1580 | ||
a385295e MR |
1581 | /* Determine the address of the next instruction executed after the INST |
1582 | floating condition branch instruction at PC. COUNT specifies the | |
1583 | number of the floating condition bits tested by the branch. */ | |
1584 | ||
1585 | static CORE_ADDR | |
7113a196 | 1586 | mips32_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, |
a385295e MR |
1587 | ULONGEST inst, CORE_ADDR pc, int count) |
1588 | { | |
1589 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1590 | int cnum = (itype_rt (inst) >> 2) & (count - 1); | |
1591 | int tf = itype_rt (inst) & 1; | |
1592 | int mask = (1 << count) - 1; | |
1593 | ULONGEST fcs; | |
1594 | int cond; | |
1595 | ||
1596 | if (fcsr == -1) | |
1597 | /* No way to handle; it'll most likely trap anyway. */ | |
1598 | return pc; | |
1599 | ||
7113a196 | 1600 | fcs = regcache_raw_get_unsigned (regcache, fcsr); |
a385295e MR |
1601 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
1602 | ||
1603 | if (((cond >> cnum) & mask) != mask * !tf) | |
1604 | pc += mips32_relative_offset (inst); | |
1605 | else | |
1606 | pc += 4; | |
1607 | ||
1608 | return pc; | |
1609 | } | |
1610 | ||
f94363d7 AP |
1611 | /* Return nonzero if the gdbarch is an Octeon series. */ |
1612 | ||
1613 | static int | |
1614 | is_octeon (struct gdbarch *gdbarch) | |
1615 | { | |
1616 | const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); | |
1617 | ||
1618 | return (info->mach == bfd_mach_mips_octeon | |
dda83cd7 SM |
1619 | || info->mach == bfd_mach_mips_octeonp |
1620 | || info->mach == bfd_mach_mips_octeon2); | |
f94363d7 AP |
1621 | } |
1622 | ||
1623 | /* Return true if the OP represents the Octeon's BBIT instruction. */ | |
1624 | ||
1625 | static int | |
1626 | is_octeon_bbit_op (int op, struct gdbarch *gdbarch) | |
1627 | { | |
1628 | if (!is_octeon (gdbarch)) | |
1629 | return 0; | |
1630 | /* BBIT0 is encoded as LWC2: 110 010. */ | |
1631 | /* BBIT032 is encoded as LDC2: 110 110. */ | |
1632 | /* BBIT1 is encoded as SWC2: 111 010. */ | |
1633 | /* BBIT132 is encoded as SDC2: 111 110. */ | |
1634 | if (op == 50 || op == 54 || op == 58 || op == 62) | |
1635 | return 1; | |
1636 | return 0; | |
1637 | } | |
1638 | ||
1639 | ||
f49e4e6d MS |
1640 | /* Determine where to set a single step breakpoint while considering |
1641 | branch prediction. */ | |
78a59c2f | 1642 | |
5a89d8aa | 1643 | static CORE_ADDR |
7113a196 | 1644 | mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) |
c5aa993b | 1645 | { |
ac7936df | 1646 | struct gdbarch *gdbarch = regcache->arch (); |
c5aa993b JM |
1647 | unsigned long inst; |
1648 | int op; | |
4cc0665f | 1649 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
4f5bcb50 | 1650 | op = itype_op (inst); |
025bb325 MS |
1651 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1652 | instruction. */ | |
c5aa993b | 1653 | { |
4f5bcb50 | 1654 | if (op >> 2 == 5) |
6d82d43b | 1655 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1656 | { |
4f5bcb50 | 1657 | switch (op & 0x03) |
c906108c | 1658 | { |
e135b889 DJ |
1659 | case 0: /* BEQL */ |
1660 | goto equal_branch; | |
1661 | case 1: /* BNEL */ | |
1662 | goto neq_branch; | |
1663 | case 2: /* BLEZL */ | |
1664 | goto less_branch; | |
313628cc | 1665 | case 3: /* BGTZL */ |
e135b889 | 1666 | goto greater_branch; |
c5aa993b JM |
1667 | default: |
1668 | pc += 4; | |
c906108c SS |
1669 | } |
1670 | } | |
4f5bcb50 | 1671 | else if (op == 17 && itype_rs (inst) == 8) |
6d82d43b | 1672 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
7113a196 | 1673 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1); |
4f5bcb50 | 1674 | else if (op == 17 && itype_rs (inst) == 9 |
a385295e MR |
1675 | && (itype_rt (inst) & 2) == 0) |
1676 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ | |
7113a196 | 1677 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2); |
4f5bcb50 | 1678 | else if (op == 17 && itype_rs (inst) == 10 |
a385295e MR |
1679 | && (itype_rt (inst) & 2) == 0) |
1680 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ | |
7113a196 | 1681 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4); |
4f5bcb50 | 1682 | else if (op == 29) |
9e8da49c MR |
1683 | /* JALX: 011101 */ |
1684 | /* The new PC will be alternate mode. */ | |
1685 | { | |
1686 | unsigned long reg; | |
1687 | ||
1688 | reg = jtype_target (inst) << 2; | |
1689 | /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ | |
1690 | pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; | |
1691 | } | |
f94363d7 AP |
1692 | else if (is_octeon_bbit_op (op, gdbarch)) |
1693 | { | |
1694 | int bit, branch_if; | |
1695 | ||
1696 | branch_if = op == 58 || op == 62; | |
1697 | bit = itype_rt (inst); | |
1698 | ||
1699 | /* Take into account the *32 instructions. */ | |
1700 | if (op == 54 || op == 62) | |
1701 | bit += 32; | |
1702 | ||
7113a196 YQ |
1703 | if (((regcache_raw_get_signed (regcache, |
1704 | itype_rs (inst)) >> bit) & 1) | |
dda83cd7 | 1705 | == branch_if) |
f94363d7 | 1706 | pc += mips32_relative_offset (inst) + 4; |
dda83cd7 | 1707 | else |
f94363d7 AP |
1708 | pc += 8; /* After the delay slot. */ |
1709 | } | |
1710 | ||
c5aa993b | 1711 | else |
025bb325 | 1712 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1713 | } |
1714 | else | |
025bb325 | 1715 | { /* This gets way messy. */ |
c5aa993b | 1716 | |
025bb325 | 1717 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
4f5bcb50 | 1718 | switch (op & 0x07) /* Extract bits 28,27,26. */ |
c906108c | 1719 | { |
c5aa993b JM |
1720 | case 0: /* SPECIAL */ |
1721 | op = rtype_funct (inst); | |
1722 | switch (op) | |
1723 | { | |
1724 | case 8: /* JR */ | |
1725 | case 9: /* JALR */ | |
025bb325 | 1726 | /* Set PC to that address. */ |
7113a196 | 1727 | pc = regcache_raw_get_signed (regcache, rtype_rs (inst)); |
c5aa993b | 1728 | break; |
e38d4e1a DJ |
1729 | case 12: /* SYSCALL */ |
1730 | { | |
345bd07c | 1731 | mips_gdbarch_tdep *tdep |
08106042 | 1732 | = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
e38d4e1a | 1733 | |
e38d4e1a | 1734 | if (tdep->syscall_next_pc != NULL) |
7113a196 | 1735 | pc = tdep->syscall_next_pc (get_current_frame ()); |
e38d4e1a DJ |
1736 | else |
1737 | pc += 4; | |
1738 | } | |
1739 | break; | |
c5aa993b JM |
1740 | default: |
1741 | pc += 4; | |
1742 | } | |
1743 | ||
6d82d43b | 1744 | break; /* end SPECIAL */ |
025bb325 | 1745 | case 1: /* REGIMM */ |
c906108c | 1746 | { |
e135b889 DJ |
1747 | op = itype_rt (inst); /* branch condition */ |
1748 | switch (op) | |
c906108c | 1749 | { |
c5aa993b | 1750 | case 0: /* BLTZ */ |
e135b889 DJ |
1751 | case 2: /* BLTZL */ |
1752 | case 16: /* BLTZAL */ | |
c5aa993b | 1753 | case 18: /* BLTZALL */ |
c906108c | 1754 | less_branch: |
7113a196 | 1755 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0) |
c5aa993b JM |
1756 | pc += mips32_relative_offset (inst) + 4; |
1757 | else | |
1758 | pc += 8; /* after the delay slot */ | |
1759 | break; | |
e135b889 | 1760 | case 1: /* BGEZ */ |
c5aa993b JM |
1761 | case 3: /* BGEZL */ |
1762 | case 17: /* BGEZAL */ | |
1763 | case 19: /* BGEZALL */ | |
7113a196 | 1764 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) >= 0) |
c5aa993b JM |
1765 | pc += mips32_relative_offset (inst) + 4; |
1766 | else | |
1767 | pc += 8; /* after the delay slot */ | |
1768 | break; | |
a385295e MR |
1769 | case 0x1c: /* BPOSGE32 */ |
1770 | case 0x1e: /* BPOSGE64 */ | |
1771 | pc += 4; | |
1772 | if (itype_rs (inst) == 0) | |
1773 | { | |
1774 | unsigned int pos = (op & 2) ? 64 : 32; | |
1775 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1776 | ||
1777 | if (dspctl == -1) | |
1778 | /* No way to handle; it'll most likely trap anyway. */ | |
1779 | break; | |
1780 | ||
7113a196 YQ |
1781 | if ((regcache_raw_get_unsigned (regcache, |
1782 | dspctl) & 0x7f) >= pos) | |
a385295e MR |
1783 | pc += mips32_relative_offset (inst); |
1784 | else | |
1785 | pc += 4; | |
1786 | } | |
1787 | break; | |
e135b889 | 1788 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1789 | default: |
1790 | pc += 4; | |
c906108c SS |
1791 | } |
1792 | } | |
6d82d43b | 1793 | break; /* end REGIMM */ |
c5aa993b JM |
1794 | case 2: /* J */ |
1795 | case 3: /* JAL */ | |
1796 | { | |
1797 | unsigned long reg; | |
1798 | reg = jtype_target (inst) << 2; | |
025bb325 | 1799 | /* Upper four bits get never changed... */ |
5b652102 | 1800 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1801 | } |
c5aa993b | 1802 | break; |
e135b889 | 1803 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1804 | equal_branch: |
7113a196 YQ |
1805 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) == |
1806 | regcache_raw_get_signed (regcache, itype_rt (inst))) | |
c5aa993b JM |
1807 | pc += mips32_relative_offset (inst) + 4; |
1808 | else | |
1809 | pc += 8; | |
1810 | break; | |
e135b889 | 1811 | case 5: /* BNE, BNEL */ |
c5aa993b | 1812 | neq_branch: |
7113a196 YQ |
1813 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) != |
1814 | regcache_raw_get_signed (regcache, itype_rt (inst))) | |
c5aa993b JM |
1815 | pc += mips32_relative_offset (inst) + 4; |
1816 | else | |
1817 | pc += 8; | |
1818 | break; | |
e135b889 | 1819 | case 6: /* BLEZ, BLEZL */ |
7113a196 | 1820 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) <= 0) |
c5aa993b JM |
1821 | pc += mips32_relative_offset (inst) + 4; |
1822 | else | |
1823 | pc += 8; | |
1824 | break; | |
1825 | case 7: | |
e135b889 DJ |
1826 | default: |
1827 | greater_branch: /* BGTZ, BGTZL */ | |
7113a196 | 1828 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0) |
c5aa993b JM |
1829 | pc += mips32_relative_offset (inst) + 4; |
1830 | else | |
1831 | pc += 8; | |
1832 | break; | |
c5aa993b JM |
1833 | } /* switch */ |
1834 | } /* else */ | |
1835 | return pc; | |
1836 | } /* mips32_next_pc */ | |
c906108c | 1837 | |
4cc0665f MR |
1838 | /* Extract the 7-bit signed immediate offset from the microMIPS instruction |
1839 | INSN. */ | |
1840 | ||
1841 | static LONGEST | |
1842 | micromips_relative_offset7 (ULONGEST insn) | |
1843 | { | |
1844 | return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; | |
1845 | } | |
1846 | ||
1847 | /* Extract the 10-bit signed immediate offset from the microMIPS instruction | |
1848 | INSN. */ | |
1849 | ||
1850 | static LONGEST | |
1851 | micromips_relative_offset10 (ULONGEST insn) | |
1852 | { | |
1853 | return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; | |
1854 | } | |
1855 | ||
1856 | /* Extract the 16-bit signed immediate offset from the microMIPS instruction | |
1857 | INSN. */ | |
1858 | ||
1859 | static LONGEST | |
1860 | micromips_relative_offset16 (ULONGEST insn) | |
1861 | { | |
1862 | return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; | |
1863 | } | |
1864 | ||
1865 | /* Return the size in bytes of the microMIPS instruction at the address PC. */ | |
1866 | ||
1867 | static int | |
1868 | micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1869 | { | |
1870 | ULONGEST insn; | |
1871 | ||
1872 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1873 | return mips_insn_size (ISA_MICROMIPS, insn); | |
1874 | } | |
1875 | ||
1876 | /* Calculate the address of the next microMIPS instruction to execute | |
1877 | after the INSN coprocessor 1 conditional branch instruction at the | |
1878 | address PC. COUNT denotes the number of coprocessor condition bits | |
1879 | examined by the branch. */ | |
1880 | ||
1881 | static CORE_ADDR | |
7113a196 | 1882 | micromips_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, |
4cc0665f MR |
1883 | ULONGEST insn, CORE_ADDR pc, int count) |
1884 | { | |
1885 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1886 | int cnum = b2s3_cc (insn >> 16) & (count - 1); | |
1887 | int tf = b5s5_op (insn >> 16) & 1; | |
1888 | int mask = (1 << count) - 1; | |
1889 | ULONGEST fcs; | |
1890 | int cond; | |
1891 | ||
1892 | if (fcsr == -1) | |
1893 | /* No way to handle; it'll most likely trap anyway. */ | |
1894 | return pc; | |
1895 | ||
7113a196 | 1896 | fcs = regcache_raw_get_unsigned (regcache, fcsr); |
4cc0665f MR |
1897 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
1898 | ||
1899 | if (((cond >> cnum) & mask) != mask * !tf) | |
1900 | pc += micromips_relative_offset16 (insn); | |
1901 | else | |
1902 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1903 | ||
1904 | return pc; | |
1905 | } | |
1906 | ||
1907 | /* Calculate the address of the next microMIPS instruction to execute | |
1908 | after the instruction at the address PC. */ | |
1909 | ||
1910 | static CORE_ADDR | |
7113a196 | 1911 | micromips_next_pc (struct regcache *regcache, CORE_ADDR pc) |
4cc0665f | 1912 | { |
ac7936df | 1913 | struct gdbarch *gdbarch = regcache->arch (); |
4cc0665f MR |
1914 | ULONGEST insn; |
1915 | ||
1916 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1917 | pc += MIPS_INSN16_SIZE; | |
1918 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
1919 | { | |
4cc0665f MR |
1920 | /* 32-bit instructions. */ |
1921 | case 2 * MIPS_INSN16_SIZE: | |
1922 | insn <<= 16; | |
1923 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1924 | pc += MIPS_INSN16_SIZE; | |
1925 | switch (micromips_op (insn >> 16)) | |
1926 | { | |
1927 | case 0x00: /* POOL32A: bits 000000 */ | |
6592ceed MR |
1928 | switch (b0s6_op (insn)) |
1929 | { | |
1930 | case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */ | |
1931 | switch (b6s10_ext (insn)) | |
1932 | { | |
1933 | case 0x3c: /* JALR: 000000 0000111100 111100 */ | |
1934 | case 0x7c: /* JALR.HB: 000000 0001111100 111100 */ | |
1935 | case 0x13c: /* JALRS: 000000 0100111100 111100 */ | |
1936 | case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */ | |
1937 | pc = regcache_raw_get_signed (regcache, | |
1938 | b0s5_reg (insn >> 16)); | |
1939 | break; | |
1940 | case 0x22d: /* SYSCALL: 000000 1000101101 111100 */ | |
1941 | { | |
345bd07c | 1942 | mips_gdbarch_tdep *tdep |
08106042 | 1943 | = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
6592ceed | 1944 | |
6592ceed MR |
1945 | if (tdep->syscall_next_pc != NULL) |
1946 | pc = tdep->syscall_next_pc (get_current_frame ()); | |
1947 | } | |
1948 | break; | |
1949 | } | |
1950 | break; | |
1951 | } | |
4cc0665f MR |
1952 | break; |
1953 | ||
1954 | case 0x10: /* POOL32I: bits 010000 */ | |
1955 | switch (b5s5_op (insn >> 16)) | |
1956 | { | |
1957 | case 0x00: /* BLTZ: bits 010000 00000 */ | |
1958 | case 0x01: /* BLTZAL: bits 010000 00001 */ | |
1959 | case 0x11: /* BLTZALS: bits 010000 10001 */ | |
7113a196 YQ |
1960 | if (regcache_raw_get_signed (regcache, |
1961 | b0s5_reg (insn >> 16)) < 0) | |
4cc0665f MR |
1962 | pc += micromips_relative_offset16 (insn); |
1963 | else | |
1964 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1965 | break; | |
1966 | ||
1967 | case 0x02: /* BGEZ: bits 010000 00010 */ | |
1968 | case 0x03: /* BGEZAL: bits 010000 00011 */ | |
1969 | case 0x13: /* BGEZALS: bits 010000 10011 */ | |
7113a196 YQ |
1970 | if (regcache_raw_get_signed (regcache, |
1971 | b0s5_reg (insn >> 16)) >= 0) | |
4cc0665f MR |
1972 | pc += micromips_relative_offset16 (insn); |
1973 | else | |
1974 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1975 | break; | |
1976 | ||
1977 | case 0x04: /* BLEZ: bits 010000 00100 */ | |
7113a196 YQ |
1978 | if (regcache_raw_get_signed (regcache, |
1979 | b0s5_reg (insn >> 16)) <= 0) | |
4cc0665f MR |
1980 | pc += micromips_relative_offset16 (insn); |
1981 | else | |
1982 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1983 | break; | |
1984 | ||
1985 | case 0x05: /* BNEZC: bits 010000 00101 */ | |
7113a196 YQ |
1986 | if (regcache_raw_get_signed (regcache, |
1987 | b0s5_reg (insn >> 16)) != 0) | |
4cc0665f MR |
1988 | pc += micromips_relative_offset16 (insn); |
1989 | break; | |
1990 | ||
1991 | case 0x06: /* BGTZ: bits 010000 00110 */ | |
7113a196 YQ |
1992 | if (regcache_raw_get_signed (regcache, |
1993 | b0s5_reg (insn >> 16)) > 0) | |
4cc0665f MR |
1994 | pc += micromips_relative_offset16 (insn); |
1995 | else | |
1996 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1997 | break; | |
1998 | ||
1999 | case 0x07: /* BEQZC: bits 010000 00111 */ | |
7113a196 YQ |
2000 | if (regcache_raw_get_signed (regcache, |
2001 | b0s5_reg (insn >> 16)) == 0) | |
4cc0665f MR |
2002 | pc += micromips_relative_offset16 (insn); |
2003 | break; | |
2004 | ||
2005 | case 0x14: /* BC2F: bits 010000 10100 xxx00 */ | |
2006 | case 0x15: /* BC2T: bits 010000 10101 xxx00 */ | |
2007 | if (((insn >> 16) & 0x3) == 0x0) | |
2008 | /* BC2F, BC2T: don't know how to handle these. */ | |
2009 | break; | |
2010 | break; | |
2011 | ||
2012 | case 0x1a: /* BPOSGE64: bits 010000 11010 */ | |
2013 | case 0x1b: /* BPOSGE32: bits 010000 11011 */ | |
2014 | { | |
2015 | unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; | |
2016 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
2017 | ||
2018 | if (dspctl == -1) | |
2019 | /* No way to handle; it'll most likely trap anyway. */ | |
2020 | break; | |
2021 | ||
7113a196 YQ |
2022 | if ((regcache_raw_get_unsigned (regcache, |
2023 | dspctl) & 0x7f) >= pos) | |
4cc0665f MR |
2024 | pc += micromips_relative_offset16 (insn); |
2025 | else | |
2026 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2027 | } | |
2028 | break; | |
2029 | ||
2030 | case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ | |
2031 | /* BC1ANY2F: bits 010000 11100 xxx01 */ | |
2032 | case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ | |
2033 | /* BC1ANY2T: bits 010000 11101 xxx01 */ | |
2034 | if (((insn >> 16) & 0x2) == 0x0) | |
7113a196 | 2035 | pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, |
4cc0665f MR |
2036 | ((insn >> 16) & 0x1) + 1); |
2037 | break; | |
2038 | ||
2039 | case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ | |
2040 | case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ | |
2041 | if (((insn >> 16) & 0x3) == 0x1) | |
7113a196 | 2042 | pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, 4); |
4cc0665f MR |
2043 | break; |
2044 | } | |
2045 | break; | |
2046 | ||
2047 | case 0x1d: /* JALS: bits 011101 */ | |
2048 | case 0x35: /* J: bits 110101 */ | |
2049 | case 0x3d: /* JAL: bits 111101 */ | |
2050 | pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); | |
2051 | break; | |
2052 | ||
2053 | case 0x25: /* BEQ: bits 100101 */ | |
7113a196 YQ |
2054 | if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) |
2055 | == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) | |
4cc0665f MR |
2056 | pc += micromips_relative_offset16 (insn); |
2057 | else | |
2058 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2059 | break; | |
2060 | ||
2061 | case 0x2d: /* BNE: bits 101101 */ | |
7113a196 YQ |
2062 | if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) |
2063 | != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) | |
4cc0665f | 2064 | pc += micromips_relative_offset16 (insn); |
492325c4 | 2065 | else |
4cc0665f MR |
2066 | pc += micromips_pc_insn_size (gdbarch, pc); |
2067 | break; | |
2068 | ||
2069 | case 0x3c: /* JALX: bits 111100 */ | |
2070 | pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); | |
2071 | break; | |
2072 | } | |
2073 | break; | |
2074 | ||
2075 | /* 16-bit instructions. */ | |
2076 | case MIPS_INSN16_SIZE: | |
2077 | switch (micromips_op (insn)) | |
2078 | { | |
2079 | case 0x11: /* POOL16C: bits 010001 */ | |
2080 | if ((b5s5_op (insn) & 0x1c) == 0xc) | |
2081 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
7113a196 | 2082 | pc = regcache_raw_get_signed (regcache, b0s5_reg (insn)); |
4cc0665f MR |
2083 | else if (b5s5_op (insn) == 0x18) |
2084 | /* JRADDIUSP: bits 010001 11000 */ | |
7113a196 | 2085 | pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM); |
4cc0665f MR |
2086 | break; |
2087 | ||
2088 | case 0x23: /* BEQZ16: bits 100011 */ | |
2089 | { | |
2090 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
2091 | ||
7113a196 | 2092 | if (regcache_raw_get_signed (regcache, rs) == 0) |
4cc0665f MR |
2093 | pc += micromips_relative_offset7 (insn); |
2094 | else | |
2095 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2096 | } | |
2097 | break; | |
2098 | ||
2099 | case 0x2b: /* BNEZ16: bits 101011 */ | |
2100 | { | |
2101 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
2102 | ||
7113a196 | 2103 | if (regcache_raw_get_signed (regcache, rs) != 0) |
4cc0665f MR |
2104 | pc += micromips_relative_offset7 (insn); |
2105 | else | |
2106 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2107 | } | |
2108 | break; | |
2109 | ||
2110 | case 0x33: /* B16: bits 110011 */ | |
2111 | pc += micromips_relative_offset10 (insn); | |
2112 | break; | |
2113 | } | |
2114 | break; | |
2115 | } | |
2116 | ||
2117 | return pc; | |
2118 | } | |
2119 | ||
c906108c | 2120 | /* Decoding the next place to set a breakpoint is irregular for the |
025bb325 MS |
2121 | mips 16 variant, but fortunately, there fewer instructions. We have |
2122 | to cope ith extensions for 16 bit instructions and a pair of actual | |
2123 | 32 bit instructions. We dont want to set a single step instruction | |
2124 | on the extend instruction either. */ | |
c906108c SS |
2125 | |
2126 | /* Lots of mips16 instruction formats */ | |
2127 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 2128 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
2129 | enum mips16_inst_fmts |
2130 | { | |
c5aa993b JM |
2131 | itype, /* 0 immediate 5,10 */ |
2132 | ritype, /* 1 5,3,8 */ | |
2133 | rrtype, /* 2 5,3,3,5 */ | |
2134 | rritype, /* 3 5,3,3,5 */ | |
2135 | rrrtype, /* 4 5,3,3,3,2 */ | |
2136 | rriatype, /* 5 5,3,3,1,4 */ | |
2137 | shifttype, /* 6 5,3,3,3,2 */ | |
2138 | i8type, /* 7 5,3,8 */ | |
2139 | i8movtype, /* 8 5,3,3,5 */ | |
2140 | i8mov32rtype, /* 9 5,3,5,3 */ | |
2141 | i64type, /* 10 5,3,8 */ | |
2142 | ri64type, /* 11 5,3,3,5 */ | |
2143 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
2144 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
2145 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
2146 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
2147 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
2148 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
2149 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
2150 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
2151 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
2152 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
2153 | }; | |
12f02c2a | 2154 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 2155 | then, only the fields which are involved in instruction extension. */ |
c906108c | 2156 | struct upk_mips16 |
6d82d43b AC |
2157 | { |
2158 | CORE_ADDR offset; | |
025bb325 | 2159 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
2160 | unsigned int regy; |
2161 | }; | |
c906108c SS |
2162 | |
2163 | ||
12f02c2a | 2164 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 2165 | for the bits which make up the immediate extension. */ |
c906108c | 2166 | |
12f02c2a AC |
2167 | static CORE_ADDR |
2168 | extended_offset (unsigned int extension) | |
c906108c | 2169 | { |
12f02c2a | 2170 | CORE_ADDR value; |
130854df | 2171 | |
4c2051c6 | 2172 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 2173 | value = value << 6; |
4c2051c6 | 2174 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 2175 | value = value << 5; |
130854df MR |
2176 | value |= extension & 0x1f; /* Extract 4:0. */ |
2177 | ||
c5aa993b | 2178 | return value; |
c906108c SS |
2179 | } |
2180 | ||
2181 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
2182 | instruction. It won't malfunction, but why make excess remote memory |
2183 | references? If the immediate operands get sign extended or something, | |
2184 | do it after the extension is performed. */ | |
c906108c | 2185 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 2186 | when the offset is to be used in relative addressing. */ |
c906108c | 2187 | |
12f02c2a | 2188 | static unsigned int |
e17a4113 | 2189 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 2190 | { |
e17a4113 | 2191 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 2192 | gdb_byte buf[8]; |
a2fb2cee MR |
2193 | |
2194 | pc = unmake_compact_addr (pc); /* Clear the low order bit. */ | |
c5aa993b | 2195 | target_read_memory (pc, buf, 2); |
e17a4113 | 2196 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
2197 | } |
2198 | ||
2199 | static void | |
e17a4113 | 2200 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
2201 | unsigned int extension, |
2202 | unsigned int inst, | |
6d82d43b | 2203 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 2204 | { |
12f02c2a AC |
2205 | CORE_ADDR offset; |
2206 | int regx; | |
2207 | int regy; | |
2208 | switch (insn_format) | |
c906108c | 2209 | { |
c5aa993b | 2210 | case itype: |
c906108c | 2211 | { |
12f02c2a AC |
2212 | CORE_ADDR value; |
2213 | if (extension) | |
c5aa993b | 2214 | { |
4c2051c6 MR |
2215 | value = extended_offset ((extension << 16) | inst); |
2216 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
2217 | } |
2218 | else | |
c5aa993b | 2219 | { |
12f02c2a | 2220 | value = inst & 0x7ff; |
4c2051c6 | 2221 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 2222 | } |
12f02c2a AC |
2223 | offset = value; |
2224 | regx = -1; | |
2225 | regy = -1; | |
c906108c | 2226 | } |
c5aa993b JM |
2227 | break; |
2228 | case ritype: | |
2229 | case i8type: | |
025bb325 | 2230 | { /* A register identifier and an offset. */ |
c906108c | 2231 | /* Most of the fields are the same as I type but the |
025bb325 | 2232 | immediate value is of a different length. */ |
12f02c2a AC |
2233 | CORE_ADDR value; |
2234 | if (extension) | |
c906108c | 2235 | { |
4c2051c6 MR |
2236 | value = extended_offset ((extension << 16) | inst); |
2237 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 2238 | } |
c5aa993b JM |
2239 | else |
2240 | { | |
4c2051c6 MR |
2241 | value = inst & 0xff; /* 8 bits */ |
2242 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 2243 | } |
12f02c2a | 2244 | offset = value; |
4c2051c6 | 2245 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 2246 | regy = -1; |
c5aa993b | 2247 | break; |
c906108c | 2248 | } |
c5aa993b | 2249 | case jalxtype: |
c906108c | 2250 | { |
c5aa993b | 2251 | unsigned long value; |
12f02c2a AC |
2252 | unsigned int nexthalf; |
2253 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 2254 | value = value << 16; |
4cc0665f MR |
2255 | nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); |
2256 | /* Low bit still set. */ | |
c5aa993b | 2257 | value |= nexthalf; |
12f02c2a AC |
2258 | offset = value; |
2259 | regx = -1; | |
2260 | regy = -1; | |
c5aa993b | 2261 | break; |
c906108c SS |
2262 | } |
2263 | default: | |
f34652de | 2264 | internal_error (_("bad switch")); |
c906108c | 2265 | } |
12f02c2a AC |
2266 | upk->offset = offset; |
2267 | upk->regx = regx; | |
2268 | upk->regy = regy; | |
c906108c SS |
2269 | } |
2270 | ||
2271 | ||
484933d1 MR |
2272 | /* Calculate the destination of a branch whose 16-bit opcode word is at PC, |
2273 | and having a signed 16-bit OFFSET. */ | |
2274 | ||
c5aa993b JM |
2275 | static CORE_ADDR |
2276 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 2277 | { |
484933d1 | 2278 | return pc + (offset << 1) + 2; |
c906108c SS |
2279 | } |
2280 | ||
12f02c2a | 2281 | static CORE_ADDR |
7113a196 | 2282 | extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc, |
6d82d43b | 2283 | unsigned int extension, unsigned int insn) |
c906108c | 2284 | { |
ac7936df | 2285 | struct gdbarch *gdbarch = regcache->arch (); |
12f02c2a AC |
2286 | int op = (insn >> 11); |
2287 | switch (op) | |
c906108c | 2288 | { |
6d82d43b | 2289 | case 2: /* Branch */ |
12f02c2a | 2290 | { |
12f02c2a | 2291 | struct upk_mips16 upk; |
e17a4113 | 2292 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
484933d1 | 2293 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2294 | break; |
2295 | } | |
025bb325 MS |
2296 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
2297 | instructions. */ | |
12f02c2a AC |
2298 | { |
2299 | struct upk_mips16 upk; | |
e17a4113 | 2300 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
484933d1 | 2301 | pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2); |
12f02c2a | 2302 | if ((insn >> 10) & 0x01) /* Exchange mode */ |
025bb325 | 2303 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
2304 | else |
2305 | pc |= 0x01; | |
2306 | break; | |
2307 | } | |
6d82d43b | 2308 | case 4: /* beqz */ |
12f02c2a AC |
2309 | { |
2310 | struct upk_mips16 upk; | |
2311 | int reg; | |
e17a4113 | 2312 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
7113a196 | 2313 | reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); |
12f02c2a | 2314 | if (reg == 0) |
484933d1 | 2315 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2316 | else |
2317 | pc += 2; | |
2318 | break; | |
2319 | } | |
6d82d43b | 2320 | case 5: /* bnez */ |
12f02c2a AC |
2321 | { |
2322 | struct upk_mips16 upk; | |
2323 | int reg; | |
e17a4113 | 2324 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
7113a196 | 2325 | reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); |
12f02c2a | 2326 | if (reg != 0) |
484933d1 | 2327 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2328 | else |
2329 | pc += 2; | |
2330 | break; | |
2331 | } | |
6d82d43b | 2332 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
2333 | { |
2334 | struct upk_mips16 upk; | |
2335 | int reg; | |
e17a4113 | 2336 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 2337 | /* upk.regx contains the opcode */ |
7113a196 YQ |
2338 | /* Test register is 24 */ |
2339 | reg = regcache_raw_get_signed (regcache, 24); | |
12f02c2a AC |
2340 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
2341 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
484933d1 | 2342 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2343 | else |
2344 | pc += 2; | |
2345 | break; | |
2346 | } | |
6d82d43b | 2347 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
2348 | { |
2349 | struct upk_mips16 upk; | |
2350 | /* upk.fmt = rrtype; */ | |
2351 | op = insn & 0x1f; | |
2352 | if (op == 0) | |
c5aa993b | 2353 | { |
12f02c2a AC |
2354 | int reg; |
2355 | upk.regx = (insn >> 8) & 0x07; | |
2356 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 | 2357 | if ((upk.regy & 1) == 0) |
4cc0665f | 2358 | reg = mips_reg3_to_reg[upk.regx]; |
4c2051c6 MR |
2359 | else |
2360 | reg = 31; /* Function return instruction. */ | |
7113a196 | 2361 | pc = regcache_raw_get_signed (regcache, reg); |
c906108c | 2362 | } |
12f02c2a | 2363 | else |
c5aa993b | 2364 | pc += 2; |
12f02c2a AC |
2365 | break; |
2366 | } | |
2367 | case 30: | |
2368 | /* This is an instruction extension. Fetch the real instruction | |
dda83cd7 SM |
2369 | (which follows the extension) and decode things based on |
2370 | that. */ | |
12f02c2a AC |
2371 | { |
2372 | pc += 2; | |
7113a196 | 2373 | pc = extended_mips16_next_pc (regcache, pc, insn, |
e17a4113 | 2374 | fetch_mips_16 (gdbarch, pc)); |
12f02c2a AC |
2375 | break; |
2376 | } | |
2377 | default: | |
2378 | { | |
2379 | pc += 2; | |
2380 | break; | |
2381 | } | |
c906108c | 2382 | } |
c5aa993b | 2383 | return pc; |
12f02c2a | 2384 | } |
c906108c | 2385 | |
5a89d8aa | 2386 | static CORE_ADDR |
7113a196 | 2387 | mips16_next_pc (struct regcache *regcache, CORE_ADDR pc) |
12f02c2a | 2388 | { |
ac7936df | 2389 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 2390 | unsigned int insn = fetch_mips_16 (gdbarch, pc); |
7113a196 | 2391 | return extended_mips16_next_pc (regcache, pc, 0, insn); |
12f02c2a AC |
2392 | } |
2393 | ||
2394 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 2395 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 2396 | It works by decoding the current instruction and predicting where a |
1aee363c | 2397 | branch will go. This isn't hard because all the data is available. |
4cc0665f | 2398 | The MIPS32, MIPS16 and microMIPS variants are quite different. */ |
ad527d2e | 2399 | static CORE_ADDR |
7113a196 | 2400 | mips_next_pc (struct regcache *regcache, CORE_ADDR pc) |
c906108c | 2401 | { |
ac7936df | 2402 | struct gdbarch *gdbarch = regcache->arch (); |
4cc0665f MR |
2403 | |
2404 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
7113a196 | 2405 | return mips16_next_pc (regcache, pc); |
4cc0665f | 2406 | else if (mips_pc_is_micromips (gdbarch, pc)) |
7113a196 | 2407 | return micromips_next_pc (regcache, pc); |
c5aa993b | 2408 | else |
7113a196 | 2409 | return mips32_next_pc (regcache, pc); |
12f02c2a | 2410 | } |
c906108c | 2411 | |
ab50adb6 MR |
2412 | /* Return non-zero if the MIPS16 instruction INSN is a compact branch |
2413 | or jump. */ | |
2414 | ||
2415 | static int | |
2416 | mips16_instruction_is_compact_branch (unsigned short insn) | |
2417 | { | |
2418 | switch (insn & 0xf800) | |
2419 | { | |
2420 | case 0xe800: | |
2421 | return (insn & 0x009f) == 0x80; /* JALRC/JRC */ | |
2422 | case 0x6000: | |
2423 | return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */ | |
2424 | case 0x2800: /* BNEZ */ | |
2425 | case 0x2000: /* BEQZ */ | |
2426 | case 0x1000: /* B */ | |
2427 | return 1; | |
2428 | default: | |
2429 | return 0; | |
2430 | } | |
2431 | } | |
2432 | ||
2433 | /* Return non-zero if the microMIPS instruction INSN is a compact branch | |
2434 | or jump. */ | |
2435 | ||
2436 | static int | |
2437 | micromips_instruction_is_compact_branch (unsigned short insn) | |
2438 | { | |
2439 | switch (micromips_op (insn)) | |
2440 | { | |
2441 | case 0x11: /* POOL16C: bits 010001 */ | |
2442 | return (b5s5_op (insn) == 0x18 | |
2443 | /* JRADDIUSP: bits 010001 11000 */ | |
2444 | || b5s5_op (insn) == 0xd); | |
2445 | /* JRC: bits 010011 01101 */ | |
2446 | case 0x10: /* POOL32I: bits 010000 */ | |
2447 | return (b5s5_op (insn) & 0x1d) == 0x5; | |
2448 | /* BEQZC/BNEZC: bits 010000 001x1 */ | |
2449 | default: | |
2450 | return 0; | |
2451 | } | |
2452 | } | |
2453 | ||
edfae063 AC |
2454 | struct mips_frame_cache |
2455 | { | |
2456 | CORE_ADDR base; | |
098caef4 | 2457 | trad_frame_saved_reg *saved_regs; |
edfae063 AC |
2458 | }; |
2459 | ||
29639122 JB |
2460 | /* Set a register's saved stack address in temp_saved_regs. If an |
2461 | address has already been set for this register, do nothing; this | |
2462 | way we will only recognize the first save of a given register in a | |
2463 | function prologue. | |
eec63939 | 2464 | |
f57d151a UW |
2465 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
2466 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
2467 | Strictly speaking, only the second range is used as it is only second | |
2468 | range (the ABI instead of ISA registers) that comes into play when finding | |
2469 | saved registers in a frame. */ | |
eec63939 AC |
2470 | |
2471 | static void | |
74ed0bb4 MD |
2472 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
2473 | int regnum, CORE_ADDR offset) | |
eec63939 | 2474 | { |
29639122 | 2475 | if (this_cache != NULL |
a9a87d35 LM |
2476 | && this_cache->saved_regs[regnum].is_realreg () |
2477 | && this_cache->saved_regs[regnum].realreg () == regnum) | |
29639122 | 2478 | { |
098caef4 LM |
2479 | this_cache->saved_regs[regnum + 0 |
2480 | * gdbarch_num_regs (gdbarch)].set_addr (offset); | |
2481 | this_cache->saved_regs[regnum + 1 | |
2482 | * gdbarch_num_regs (gdbarch)].set_addr (offset); | |
29639122 | 2483 | } |
eec63939 AC |
2484 | } |
2485 | ||
eec63939 | 2486 | |
29639122 JB |
2487 | /* Fetch the immediate value from a MIPS16 instruction. |
2488 | If the previous instruction was an EXTEND, use it to extend | |
2489 | the upper bits of the immediate value. This is a helper function | |
2490 | for mips16_scan_prologue. */ | |
eec63939 | 2491 | |
29639122 JB |
2492 | static int |
2493 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
2494 | unsigned short inst, /* current instruction */ | |
2495 | int nbits, /* number of bits in imm field */ | |
2496 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 2497 | int is_signed) /* is the imm field signed? */ |
eec63939 | 2498 | { |
29639122 | 2499 | int offset; |
eec63939 | 2500 | |
29639122 JB |
2501 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
2502 | { | |
2503 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
2504 | if (offset & 0x8000) /* check for negative extend */ | |
2505 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
2506 | return offset | (inst & 0x1f); | |
2507 | } | |
eec63939 | 2508 | else |
29639122 JB |
2509 | { |
2510 | int max_imm = 1 << nbits; | |
2511 | int mask = max_imm - 1; | |
2512 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 2513 | |
29639122 JB |
2514 | offset = inst & mask; |
2515 | if (is_signed && (offset & sign_bit)) | |
2516 | offset = 0 - (max_imm - offset); | |
2517 | return offset * scale; | |
2518 | } | |
2519 | } | |
eec63939 | 2520 | |
65596487 | 2521 | |
29639122 JB |
2522 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2523 | the associated FRAME_CACHE if not null. | |
2524 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 2525 | |
29639122 | 2526 | static CORE_ADDR |
e17a4113 UW |
2527 | mips16_scan_prologue (struct gdbarch *gdbarch, |
2528 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
bd2b40ac | 2529 | frame_info_ptr this_frame, |
dda83cd7 | 2530 | struct mips_frame_cache *this_cache) |
29639122 | 2531 | { |
ab50adb6 MR |
2532 | int prev_non_prologue_insn = 0; |
2533 | int this_non_prologue_insn; | |
2534 | int non_prologue_insns = 0; | |
2535 | CORE_ADDR prev_pc; | |
29639122 | 2536 | CORE_ADDR cur_pc; |
025bb325 | 2537 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
2538 | CORE_ADDR sp; |
2539 | long frame_offset = 0; /* Size of stack frame. */ | |
2540 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2541 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 2542 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
2543 | unsigned inst = 0; /* current instruction */ |
2544 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 2545 | unsigned save_inst = 0; /* the save instruction */ |
ab50adb6 MR |
2546 | int prev_delay_slot = 0; |
2547 | int in_delay_slot; | |
29639122 | 2548 | int reg, offset; |
a343eb3c | 2549 | |
29639122 | 2550 | int extend_bytes = 0; |
ab50adb6 MR |
2551 | int prev_extend_bytes = 0; |
2552 | CORE_ADDR end_prologue_addr; | |
a343eb3c | 2553 | |
29639122 | 2554 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2555 | THIS_FRAME. */ |
2556 | if (this_frame != NULL) | |
2557 | sp = get_frame_register_signed (this_frame, | |
2558 | gdbarch_num_regs (gdbarch) | |
2559 | + MIPS_SP_REGNUM); | |
29639122 JB |
2560 | else |
2561 | sp = 0; | |
eec63939 | 2562 | |
29639122 JB |
2563 | if (limit_pc > start_pc + 200) |
2564 | limit_pc = start_pc + 200; | |
ab50adb6 | 2565 | prev_pc = start_pc; |
eec63939 | 2566 | |
ab50adb6 MR |
2567 | /* Permit at most one non-prologue non-control-transfer instruction |
2568 | in the middle which may have been reordered by the compiler for | |
2569 | optimisation. */ | |
95ac2dcf | 2570 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 | 2571 | { |
ab50adb6 MR |
2572 | this_non_prologue_insn = 0; |
2573 | in_delay_slot = 0; | |
2574 | ||
29639122 | 2575 | /* Save the previous instruction. If it's an EXTEND, we'll extract |
dda83cd7 | 2576 | the immediate offset extension from it in mips16_get_imm. */ |
29639122 | 2577 | prev_inst = inst; |
eec63939 | 2578 | |
025bb325 | 2579 | /* Fetch and decode the instruction. */ |
4cc0665f MR |
2580 | inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, |
2581 | cur_pc, NULL); | |
eec63939 | 2582 | |
29639122 | 2583 | /* Normally we ignore extend instructions. However, if it is |
dda83cd7 SM |
2584 | not followed by a valid prologue instruction, then this |
2585 | instruction is not part of the prologue either. We must | |
2586 | remember in this case to adjust the end_prologue_addr back | |
2587 | over the extend. */ | |
29639122 | 2588 | if ((inst & 0xf800) == 0xf000) /* extend */ |
dda83cd7 SM |
2589 | { |
2590 | extend_bytes = MIPS_INSN16_SIZE; | |
2591 | continue; | |
2592 | } | |
eec63939 | 2593 | |
29639122 JB |
2594 | prev_extend_bytes = extend_bytes; |
2595 | extend_bytes = 0; | |
eec63939 | 2596 | |
29639122 JB |
2597 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
2598 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2599 | { | |
2600 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 2601 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
2602 | frame_offset -= offset; |
2603 | else | |
2604 | /* Exit loop if a positive stack adjustment is found, which | |
2605 | usually means that the stack cleanup code in the function | |
2606 | epilogue is reached. */ | |
2607 | break; | |
2608 | } | |
2609 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2610 | { | |
2611 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4cc0665f | 2612 | reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; |
74ed0bb4 | 2613 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2614 | } |
2615 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2616 | { | |
2617 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2618 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2619 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2620 | } |
2621 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2622 | { | |
2623 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 2624 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2625 | } |
2626 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2627 | { | |
2628 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 2629 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2630 | } |
2631 | else if (inst == 0x673d) /* move $s1, $sp */ | |
2632 | { | |
2633 | frame_addr = sp; | |
2634 | frame_reg = 17; | |
2635 | } | |
2636 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2637 | { | |
2638 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2639 | frame_addr = sp + offset; | |
2640 | frame_reg = 17; | |
2641 | frame_adjust = offset; | |
2642 | } | |
2643 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2644 | { | |
2645 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
4cc0665f | 2646 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2647 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2648 | } |
2649 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2650 | { | |
2651 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2652 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2653 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2654 | } |
2655 | else if ((inst & 0xf81f) == 0xe809 | |
dda83cd7 | 2656 | && (inst & 0x700) != 0x700) /* entry */ |
025bb325 | 2657 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
2658 | else if ((inst & 0xff80) == 0x6480) /* save */ |
2659 | { | |
025bb325 | 2660 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
2661 | if (prev_extend_bytes) /* extend */ |
2662 | save_inst |= prev_inst << 16; | |
2663 | } | |
29639122 | 2664 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
dda83cd7 SM |
2665 | { |
2666 | /* This instruction is part of the prologue, but we don't | |
2667 | need to do anything special to handle it. */ | |
2668 | } | |
ab50adb6 MR |
2669 | else if (mips16_instruction_has_delay_slot (inst, 0)) |
2670 | /* JAL/JALR/JALX/JR */ | |
2671 | { | |
2672 | /* The instruction in the delay slot can be a part | |
2673 | of the prologue, so move forward once more. */ | |
2674 | in_delay_slot = 1; | |
2675 | if (mips16_instruction_has_delay_slot (inst, 1)) | |
2676 | /* JAL/JALX */ | |
2677 | { | |
2678 | prev_extend_bytes = MIPS_INSN16_SIZE; | |
2679 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ | |
2680 | } | |
2681 | } | |
29639122 | 2682 | else |
dda83cd7 | 2683 | { |
ab50adb6 | 2684 | this_non_prologue_insn = 1; |
dda83cd7 | 2685 | } |
ab50adb6 MR |
2686 | |
2687 | non_prologue_insns += this_non_prologue_insn; | |
2688 | ||
2689 | /* A jump or branch, or enough non-prologue insns seen? If so, | |
dda83cd7 | 2690 | then we must have reached the end of the prologue by now. */ |
ab50adb6 MR |
2691 | if (prev_delay_slot || non_prologue_insns > 1 |
2692 | || mips16_instruction_is_compact_branch (inst)) | |
2693 | break; | |
2694 | ||
2695 | prev_non_prologue_insn = this_non_prologue_insn; | |
2696 | prev_delay_slot = in_delay_slot; | |
2697 | prev_pc = cur_pc - prev_extend_bytes; | |
29639122 | 2698 | } |
eec63939 | 2699 | |
29639122 JB |
2700 | /* The entry instruction is typically the first instruction in a function, |
2701 | and it stores registers at offsets relative to the value of the old SP | |
2702 | (before the prologue). But the value of the sp parameter to this | |
2703 | function is the new SP (after the prologue has been executed). So we | |
2704 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 2705 | and can calculate what the old SP must have been. */ |
29639122 JB |
2706 | if (entry_inst != 0) |
2707 | { | |
2708 | int areg_count = (entry_inst >> 8) & 7; | |
2709 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 2710 | |
29639122 JB |
2711 | /* The entry instruction always subtracts 32 from the SP. */ |
2712 | frame_offset += 32; | |
2713 | ||
2714 | /* Now we can calculate what the SP must have been at the | |
dda83cd7 | 2715 | start of the function prologue. */ |
29639122 JB |
2716 | sp += frame_offset; |
2717 | ||
2718 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
2719 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2720 | { | |
74ed0bb4 | 2721 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2722 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
2723 | } |
2724 | ||
2725 | /* Check if the ra register was pushed on the stack. */ | |
2726 | offset = -4; | |
2727 | if (entry_inst & 0x20) | |
2728 | { | |
74ed0bb4 | 2729 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 2730 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2731 | } |
2732 | ||
2733 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
2734 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2735 | { | |
74ed0bb4 | 2736 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2737 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2738 | } |
2739 | } | |
2740 | ||
2207132d MR |
2741 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
2742 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
2743 | size of the frame is specified as an immediate field of instruction | |
2744 | and an extended variation exists which lets additional registers and | |
2745 | frame space to be specified. The instruction always treats registers | |
2746 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
2747 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
2748 | { | |
2749 | static int args_table[16] = { | |
2750 | 0, 0, 0, 0, 1, 1, 1, 1, | |
2751 | 2, 2, 2, 0, 3, 3, 4, -1, | |
2752 | }; | |
2753 | static int astatic_table[16] = { | |
2754 | 0, 1, 2, 3, 0, 1, 2, 3, | |
2755 | 0, 1, 2, 4, 0, 1, 0, -1, | |
2756 | }; | |
2757 | int aregs = (save_inst >> 16) & 0xf; | |
2758 | int xsregs = (save_inst >> 24) & 0x7; | |
2759 | int args = args_table[aregs]; | |
2760 | int astatic = astatic_table[aregs]; | |
2761 | long frame_size; | |
2762 | ||
2763 | if (args < 0) | |
2764 | { | |
2765 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
2766 | args = 0; | |
2767 | } | |
2768 | if (astatic < 0) | |
2769 | { | |
2770 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
2771 | astatic = 0; | |
2772 | } | |
2773 | ||
2774 | /* For standard SAVE the frame size of 0 means 128. */ | |
2775 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
2776 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
2777 | frame_size = 16; | |
2778 | frame_size *= 8; | |
2779 | frame_offset += frame_size; | |
2780 | ||
2781 | /* Now we can calculate what the SP must have been at the | |
dda83cd7 | 2782 | start of the function prologue. */ |
2207132d MR |
2783 | sp += frame_offset; |
2784 | ||
2785 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
2786 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
2787 | { | |
74ed0bb4 | 2788 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2789 | offset += mips_abi_regsize (gdbarch); |
2790 | } | |
2791 | ||
2792 | offset = -4; | |
2793 | ||
2794 | /* Check if the RA register was pushed on the stack. */ | |
2795 | if (save_inst & 0x40) | |
2796 | { | |
74ed0bb4 | 2797 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
2798 | offset -= mips_abi_regsize (gdbarch); |
2799 | } | |
2800 | ||
2801 | /* Check if the S8 register was pushed on the stack. */ | |
2802 | if (xsregs > 6) | |
2803 | { | |
74ed0bb4 | 2804 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
2805 | offset -= mips_abi_regsize (gdbarch); |
2806 | xsregs--; | |
2807 | } | |
2808 | /* Check if S2-S7 were pushed on the stack. */ | |
2809 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
2810 | { | |
74ed0bb4 | 2811 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2812 | offset -= mips_abi_regsize (gdbarch); |
2813 | } | |
2814 | ||
2815 | /* Check if the S1 register was pushed on the stack. */ | |
2816 | if (save_inst & 0x10) | |
2817 | { | |
74ed0bb4 | 2818 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
2819 | offset -= mips_abi_regsize (gdbarch); |
2820 | } | |
2821 | /* Check if the S0 register was pushed on the stack. */ | |
2822 | if (save_inst & 0x20) | |
2823 | { | |
74ed0bb4 | 2824 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
2825 | offset -= mips_abi_regsize (gdbarch); |
2826 | } | |
2827 | ||
4cc0665f MR |
2828 | /* Check if A0-A3 were pushed on the stack. */ |
2829 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
2830 | { | |
2831 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); | |
2832 | offset -= mips_abi_regsize (gdbarch); | |
2833 | } | |
2834 | } | |
2835 | ||
2836 | if (this_cache != NULL) | |
2837 | { | |
2838 | this_cache->base = | |
dda83cd7 | 2839 | (get_frame_register_signed (this_frame, |
4cc0665f | 2840 | gdbarch_num_regs (gdbarch) + frame_reg) |
dda83cd7 | 2841 | + frame_offset - frame_adjust); |
4cc0665f | 2842 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
dda83cd7 SM |
2843 | be able to get rid of the assignment below, evetually. But it's |
2844 | still needed for now. */ | |
4cc0665f MR |
2845 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2846 | + mips_regnum (gdbarch)->pc] | |
dda83cd7 | 2847 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
4cc0665f MR |
2848 | } |
2849 | ||
ab50adb6 MR |
2850 | /* Set end_prologue_addr to the address of the instruction immediately |
2851 | after the last one we scanned. Unless the last one looked like a | |
2852 | non-prologue instruction (and we looked ahead), in which case use | |
2853 | its address instead. */ | |
2854 | end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot | |
2855 | ? prev_pc : cur_pc - prev_extend_bytes); | |
4cc0665f MR |
2856 | |
2857 | return end_prologue_addr; | |
2858 | } | |
2859 | ||
2860 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). | |
2861 | Procedures that use the 32-bit instruction set are handled by the | |
2862 | mips_insn32 unwinder. */ | |
2863 | ||
2864 | static struct mips_frame_cache * | |
bd2b40ac | 2865 | mips_insn16_frame_cache (frame_info_ptr this_frame, void **this_cache) |
4cc0665f MR |
2866 | { |
2867 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2868 | struct mips_frame_cache *cache; | |
2869 | ||
2870 | if ((*this_cache) != NULL) | |
19ba03f4 | 2871 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f MR |
2872 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2873 | (*this_cache) = cache; | |
2874 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2875 | ||
2876 | /* Analyze the function prologue. */ | |
2877 | { | |
2878 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); | |
2879 | CORE_ADDR start_addr; | |
2880 | ||
2881 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2882 | if (start_addr == 0) | |
2883 | start_addr = heuristic_proc_start (gdbarch, pc); | |
2884 | /* We can't analyze the prologue if we couldn't find the begining | |
2885 | of the function. */ | |
2886 | if (start_addr == 0) | |
2887 | return cache; | |
2888 | ||
19ba03f4 SM |
2889 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, |
2890 | (struct mips_frame_cache *) *this_cache); | |
4cc0665f MR |
2891 | } |
2892 | ||
2893 | /* gdbarch_sp_regnum contains the value and not the address. */ | |
a9a87d35 LM |
2894 | cache->saved_regs[gdbarch_num_regs (gdbarch) |
2895 | + MIPS_SP_REGNUM].set_value (cache->base); | |
4cc0665f | 2896 | |
19ba03f4 | 2897 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f MR |
2898 | } |
2899 | ||
2900 | static void | |
bd2b40ac | 2901 | mips_insn16_frame_this_id (frame_info_ptr this_frame, void **this_cache, |
4cc0665f MR |
2902 | struct frame_id *this_id) |
2903 | { | |
2904 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2905 | this_cache); | |
2906 | /* This marks the outermost frame. */ | |
2907 | if (info->base == 0) | |
2908 | return; | |
2909 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); | |
2910 | } | |
2911 | ||
2912 | static struct value * | |
bd2b40ac | 2913 | mips_insn16_frame_prev_register (frame_info_ptr this_frame, |
4cc0665f MR |
2914 | void **this_cache, int regnum) |
2915 | { | |
2916 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2917 | this_cache); | |
2918 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2919 | } | |
2920 | ||
2921 | static int | |
2922 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 2923 | frame_info_ptr this_frame, void **this_cache) |
4cc0665f MR |
2924 | { |
2925 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2926 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2927 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2928 | return 1; | |
2929 | return 0; | |
2930 | } | |
2931 | ||
2932 | static const struct frame_unwind mips_insn16_frame_unwind = | |
2933 | { | |
a154d838 | 2934 | "mips insn16 prologue", |
4cc0665f MR |
2935 | NORMAL_FRAME, |
2936 | default_frame_unwind_stop_reason, | |
2937 | mips_insn16_frame_this_id, | |
2938 | mips_insn16_frame_prev_register, | |
2939 | NULL, | |
2940 | mips_insn16_frame_sniffer | |
2941 | }; | |
2942 | ||
2943 | static CORE_ADDR | |
bd2b40ac | 2944 | mips_insn16_frame_base_address (frame_info_ptr this_frame, |
4cc0665f MR |
2945 | void **this_cache) |
2946 | { | |
2947 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2948 | this_cache); | |
2949 | return info->base; | |
2950 | } | |
2951 | ||
2952 | static const struct frame_base mips_insn16_frame_base = | |
2953 | { | |
2954 | &mips_insn16_frame_unwind, | |
2955 | mips_insn16_frame_base_address, | |
2956 | mips_insn16_frame_base_address, | |
2957 | mips_insn16_frame_base_address | |
2958 | }; | |
2959 | ||
2960 | static const struct frame_base * | |
bd2b40ac | 2961 | mips_insn16_frame_base_sniffer (frame_info_ptr this_frame) |
4cc0665f MR |
2962 | { |
2963 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2964 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2965 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2966 | return &mips_insn16_frame_base; | |
2967 | else | |
2968 | return NULL; | |
2969 | } | |
2970 | ||
2971 | /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped | |
2972 | to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are | |
2973 | interpreted directly, and then multiplied by 4. */ | |
2974 | ||
2975 | static int | |
2976 | micromips_decode_imm9 (int imm) | |
2977 | { | |
2978 | imm = (imm ^ 0x100) - 0x100; | |
2979 | if (imm > -3 && imm < 2) | |
2980 | imm ^= 0x100; | |
2981 | return imm << 2; | |
2982 | } | |
2983 | ||
2984 | /* Analyze the function prologue from START_PC to LIMIT_PC. Return | |
2985 | the address of the first instruction past the prologue. */ | |
2986 | ||
2987 | static CORE_ADDR | |
2988 | micromips_scan_prologue (struct gdbarch *gdbarch, | |
2989 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
bd2b40ac | 2990 | frame_info_ptr this_frame, |
4cc0665f MR |
2991 | struct mips_frame_cache *this_cache) |
2992 | { | |
ab50adb6 | 2993 | CORE_ADDR end_prologue_addr; |
4cc0665f MR |
2994 | int prev_non_prologue_insn = 0; |
2995 | int frame_reg = MIPS_SP_REGNUM; | |
2996 | int this_non_prologue_insn; | |
2997 | int non_prologue_insns = 0; | |
2998 | long frame_offset = 0; /* Size of stack frame. */ | |
2999 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
ab50adb6 MR |
3000 | int prev_delay_slot = 0; |
3001 | int in_delay_slot; | |
4cc0665f MR |
3002 | CORE_ADDR prev_pc; |
3003 | CORE_ADDR cur_pc; | |
3004 | ULONGEST insn; /* current instruction */ | |
3005 | CORE_ADDR sp; | |
3006 | long offset; | |
3007 | long sp_adj; | |
3008 | long v1_off = 0; /* The assumption is LUI will replace it. */ | |
3009 | int reglist; | |
3010 | int breg; | |
3011 | int dreg; | |
3012 | int sreg; | |
3013 | int treg; | |
3014 | int loc; | |
3015 | int op; | |
3016 | int s; | |
3017 | int i; | |
3018 | ||
3019 | /* Can be called when there's no process, and hence when there's no | |
3020 | THIS_FRAME. */ | |
3021 | if (this_frame != NULL) | |
3022 | sp = get_frame_register_signed (this_frame, | |
3023 | gdbarch_num_regs (gdbarch) | |
3024 | + MIPS_SP_REGNUM); | |
3025 | else | |
3026 | sp = 0; | |
3027 | ||
3028 | if (limit_pc > start_pc + 200) | |
3029 | limit_pc = start_pc + 200; | |
3030 | prev_pc = start_pc; | |
3031 | ||
3032 | /* Permit at most one non-prologue non-control-transfer instruction | |
3033 | in the middle which may have been reordered by the compiler for | |
3034 | optimisation. */ | |
3035 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) | |
3036 | { | |
3037 | this_non_prologue_insn = 0; | |
ab50adb6 | 3038 | in_delay_slot = 0; |
4cc0665f MR |
3039 | sp_adj = 0; |
3040 | loc = 0; | |
3041 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); | |
3042 | loc += MIPS_INSN16_SIZE; | |
3043 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
3044 | { | |
4cc0665f MR |
3045 | /* 32-bit instructions. */ |
3046 | case 2 * MIPS_INSN16_SIZE: | |
3047 | insn <<= 16; | |
3048 | insn |= mips_fetch_instruction (gdbarch, | |
3049 | ISA_MICROMIPS, cur_pc + loc, NULL); | |
3050 | loc += MIPS_INSN16_SIZE; | |
3051 | switch (micromips_op (insn >> 16)) | |
3052 | { | |
3053 | /* Record $sp/$fp adjustment. */ | |
3054 | /* Discard (D)ADDU $gp,$jp used for PIC code. */ | |
3055 | case 0x0: /* POOL32A: bits 000000 */ | |
3056 | case 0x16: /* POOL32S: bits 010110 */ | |
3057 | op = b0s11_op (insn); | |
3058 | sreg = b0s5_reg (insn >> 16); | |
3059 | treg = b5s5_reg (insn >> 16); | |
3060 | dreg = b11s5_reg (insn); | |
3061 | if (op == 0x1d0 | |
3062 | /* SUBU: bits 000000 00111010000 */ | |
3063 | /* DSUBU: bits 010110 00111010000 */ | |
3064 | && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM | |
3065 | && treg == 3) | |
3066 | /* (D)SUBU $sp, $v1 */ | |
3067 | sp_adj = v1_off; | |
3068 | else if (op != 0x150 | |
3069 | /* ADDU: bits 000000 00101010000 */ | |
3070 | /* DADDU: bits 010110 00101010000 */ | |
3071 | || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) | |
3072 | this_non_prologue_insn = 1; | |
3073 | break; | |
3074 | ||
3075 | case 0x8: /* POOL32B: bits 001000 */ | |
3076 | op = b12s4_op (insn); | |
3077 | breg = b0s5_reg (insn >> 16); | |
3078 | reglist = sreg = b5s5_reg (insn >> 16); | |
3079 | offset = (b0s12_imm (insn) ^ 0x800) - 0x800; | |
3080 | if ((op == 0x9 || op == 0xc) | |
3081 | /* SWP: bits 001000 1001 */ | |
3082 | /* SDP: bits 001000 1100 */ | |
3083 | && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) | |
3084 | /* S[DW]P reg,offset($sp) */ | |
3085 | { | |
3086 | s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); | |
3087 | set_reg_offset (gdbarch, this_cache, | |
3088 | sreg, sp + offset); | |
3089 | set_reg_offset (gdbarch, this_cache, | |
3090 | sreg + 1, sp + offset + s); | |
3091 | } | |
3092 | else if ((op == 0xd || op == 0xf) | |
3093 | /* SWM: bits 001000 1101 */ | |
3094 | /* SDM: bits 001000 1111 */ | |
3095 | && breg == MIPS_SP_REGNUM | |
3096 | /* SWM reglist,offset($sp) */ | |
3097 | && ((reglist >= 1 && reglist <= 9) | |
3098 | || (reglist >= 16 && reglist <= 25))) | |
3099 | { | |
325fac50 | 3100 | int sreglist = std::min(reglist & 0xf, 8); |
4cc0665f MR |
3101 | |
3102 | s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); | |
3103 | for (i = 0; i < sreglist; i++) | |
3104 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); | |
3105 | if ((reglist & 0xf) > 8) | |
3106 | set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); | |
3107 | if ((reglist & 0x10) == 0x10) | |
3108 | set_reg_offset (gdbarch, this_cache, | |
3109 | MIPS_RA_REGNUM, sp + s * i++); | |
3110 | } | |
3111 | else | |
3112 | this_non_prologue_insn = 1; | |
3113 | break; | |
3114 | ||
3115 | /* Record $sp/$fp adjustment. */ | |
3116 | /* Discard (D)ADDIU $gp used for PIC code. */ | |
3117 | case 0xc: /* ADDIU: bits 001100 */ | |
3118 | case 0x17: /* DADDIU: bits 010111 */ | |
3119 | sreg = b0s5_reg (insn >> 16); | |
3120 | dreg = b5s5_reg (insn >> 16); | |
3121 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
3122 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) | |
3123 | /* (D)ADDIU $sp, imm */ | |
3124 | sp_adj = offset; | |
3125 | else if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
3126 | /* (D)ADDIU $fp, $sp, imm */ | |
3127 | { | |
4cc0665f MR |
3128 | frame_adjust = offset; |
3129 | frame_reg = 30; | |
3130 | } | |
3131 | else if (sreg != 28 || dreg != 28) | |
3132 | /* (D)ADDIU $gp, imm */ | |
3133 | this_non_prologue_insn = 1; | |
3134 | break; | |
3135 | ||
3136 | /* LUI $v1 is used for larger $sp adjustments. */ | |
3356937a | 3137 | /* Discard LUI $gp used for PIC code. */ |
4cc0665f MR |
3138 | case 0x10: /* POOL32I: bits 010000 */ |
3139 | if (b5s5_op (insn >> 16) == 0xd | |
3140 | /* LUI: bits 010000 001101 */ | |
3141 | && b0s5_reg (insn >> 16) == 3) | |
3142 | /* LUI $v1, imm */ | |
3143 | v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; | |
3144 | else if (b5s5_op (insn >> 16) != 0xd | |
3145 | /* LUI: bits 010000 001101 */ | |
3146 | || b0s5_reg (insn >> 16) != 28) | |
3147 | /* LUI $gp, imm */ | |
3148 | this_non_prologue_insn = 1; | |
3149 | break; | |
3150 | ||
3151 | /* ORI $v1 is used for larger $sp adjustments. */ | |
3152 | case 0x14: /* ORI: bits 010100 */ | |
3153 | sreg = b0s5_reg (insn >> 16); | |
3154 | dreg = b5s5_reg (insn >> 16); | |
3155 | if (sreg == 3 && dreg == 3) | |
3156 | /* ORI $v1, imm */ | |
3157 | v1_off |= b0s16_imm (insn); | |
3158 | else | |
3159 | this_non_prologue_insn = 1; | |
3160 | break; | |
3161 | ||
3162 | case 0x26: /* SWC1: bits 100110 */ | |
3163 | case 0x2e: /* SDC1: bits 101110 */ | |
3164 | breg = b0s5_reg (insn >> 16); | |
3165 | if (breg != MIPS_SP_REGNUM) | |
3166 | /* S[DW]C1 reg,offset($sp) */ | |
3167 | this_non_prologue_insn = 1; | |
3168 | break; | |
3169 | ||
3170 | case 0x36: /* SD: bits 110110 */ | |
3171 | case 0x3e: /* SW: bits 111110 */ | |
3172 | breg = b0s5_reg (insn >> 16); | |
3173 | sreg = b5s5_reg (insn >> 16); | |
3174 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
3175 | if (breg == MIPS_SP_REGNUM) | |
3176 | /* S[DW] reg,offset($sp) */ | |
3177 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3178 | else | |
3179 | this_non_prologue_insn = 1; | |
3180 | break; | |
3181 | ||
3182 | default: | |
ab50adb6 | 3183 | /* The instruction in the delay slot can be a part |
dda83cd7 | 3184 | of the prologue, so move forward once more. */ |
ab50adb6 MR |
3185 | if (micromips_instruction_has_delay_slot (insn, 0)) |
3186 | in_delay_slot = 1; | |
3187 | else | |
3188 | this_non_prologue_insn = 1; | |
4cc0665f MR |
3189 | break; |
3190 | } | |
ab50adb6 | 3191 | insn >>= 16; |
4cc0665f MR |
3192 | break; |
3193 | ||
3194 | /* 16-bit instructions. */ | |
3195 | case MIPS_INSN16_SIZE: | |
3196 | switch (micromips_op (insn)) | |
3197 | { | |
3198 | case 0x3: /* MOVE: bits 000011 */ | |
3199 | sreg = b0s5_reg (insn); | |
3200 | dreg = b5s5_reg (insn); | |
3201 | if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
3202 | /* MOVE $fp, $sp */ | |
78cc6c2d | 3203 | frame_reg = 30; |
4cc0665f MR |
3204 | else if ((sreg & 0x1c) != 0x4) |
3205 | /* MOVE reg, $a0-$a3 */ | |
3206 | this_non_prologue_insn = 1; | |
3207 | break; | |
3208 | ||
3209 | case 0x11: /* POOL16C: bits 010001 */ | |
3210 | if (b6s4_op (insn) == 0x5) | |
3211 | /* SWM: bits 010001 0101 */ | |
3212 | { | |
3213 | offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; | |
3214 | reglist = b4s2_regl (insn); | |
3215 | for (i = 0; i <= reglist; i++) | |
3216 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); | |
3217 | set_reg_offset (gdbarch, this_cache, | |
3218 | MIPS_RA_REGNUM, sp + 4 * i++); | |
3219 | } | |
3220 | else | |
3221 | this_non_prologue_insn = 1; | |
3222 | break; | |
3223 | ||
3224 | case 0x13: /* POOL16D: bits 010011 */ | |
3225 | if ((insn & 0x1) == 0x1) | |
3226 | /* ADDIUSP: bits 010011 1 */ | |
3227 | sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); | |
3228 | else if (b5s5_reg (insn) == MIPS_SP_REGNUM) | |
3229 | /* ADDIUS5: bits 010011 0 */ | |
3230 | /* ADDIUS5 $sp, imm */ | |
3231 | sp_adj = (b1s4_imm (insn) ^ 8) - 8; | |
3232 | else | |
3233 | this_non_prologue_insn = 1; | |
3234 | break; | |
3235 | ||
3236 | case 0x32: /* SWSP: bits 110010 */ | |
3237 | offset = b0s5_imm (insn) << 2; | |
3238 | sreg = b5s5_reg (insn); | |
3239 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3240 | break; | |
3241 | ||
3242 | default: | |
ab50adb6 | 3243 | /* The instruction in the delay slot can be a part |
dda83cd7 | 3244 | of the prologue, so move forward once more. */ |
ab50adb6 MR |
3245 | if (micromips_instruction_has_delay_slot (insn << 16, 0)) |
3246 | in_delay_slot = 1; | |
3247 | else | |
3248 | this_non_prologue_insn = 1; | |
4cc0665f MR |
3249 | break; |
3250 | } | |
3251 | break; | |
3252 | } | |
3253 | if (sp_adj < 0) | |
3254 | frame_offset -= sp_adj; | |
3255 | ||
3256 | non_prologue_insns += this_non_prologue_insn; | |
ab50adb6 MR |
3257 | |
3258 | /* A jump or branch, enough non-prologue insns seen or positive | |
dda83cd7 SM |
3259 | stack adjustment? If so, then we must have reached the end |
3260 | of the prologue by now. */ | |
ab50adb6 MR |
3261 | if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0 |
3262 | || micromips_instruction_is_compact_branch (insn)) | |
3263 | break; | |
3264 | ||
4cc0665f | 3265 | prev_non_prologue_insn = this_non_prologue_insn; |
ab50adb6 | 3266 | prev_delay_slot = in_delay_slot; |
4cc0665f | 3267 | prev_pc = cur_pc; |
2207132d MR |
3268 | } |
3269 | ||
29639122 JB |
3270 | if (this_cache != NULL) |
3271 | { | |
3272 | this_cache->base = | |
4cc0665f | 3273 | (get_frame_register_signed (this_frame, |
b8a22b94 | 3274 | gdbarch_num_regs (gdbarch) + frame_reg) |
4cc0665f | 3275 | + frame_offset - frame_adjust); |
29639122 | 3276 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
4cc0665f MR |
3277 | be able to get rid of the assignment below, evetually. But it's |
3278 | still needed for now. */ | |
72a155b4 UW |
3279 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3280 | + mips_regnum (gdbarch)->pc] | |
4cc0665f | 3281 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
29639122 JB |
3282 | } |
3283 | ||
ab50adb6 MR |
3284 | /* Set end_prologue_addr to the address of the instruction immediately |
3285 | after the last one we scanned. Unless the last one looked like a | |
3286 | non-prologue instruction (and we looked ahead), in which case use | |
3287 | its address instead. */ | |
3288 | end_prologue_addr | |
3289 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; | |
29639122 JB |
3290 | |
3291 | return end_prologue_addr; | |
eec63939 AC |
3292 | } |
3293 | ||
4cc0665f | 3294 | /* Heuristic unwinder for procedures using microMIPS instructions. |
29639122 | 3295 | Procedures that use the 32-bit instruction set are handled by the |
4cc0665f | 3296 | mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ |
29639122 JB |
3297 | |
3298 | static struct mips_frame_cache * | |
bd2b40ac | 3299 | mips_micro_frame_cache (frame_info_ptr this_frame, void **this_cache) |
eec63939 | 3300 | { |
e17a4113 | 3301 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3302 | struct mips_frame_cache *cache; |
eec63939 AC |
3303 | |
3304 | if ((*this_cache) != NULL) | |
19ba03f4 | 3305 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f | 3306 | |
29639122 JB |
3307 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3308 | (*this_cache) = cache; | |
b8a22b94 | 3309 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 3310 | |
29639122 JB |
3311 | /* Analyze the function prologue. */ |
3312 | { | |
b8a22b94 | 3313 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3314 | CORE_ADDR start_addr; |
eec63939 | 3315 | |
29639122 JB |
3316 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3317 | if (start_addr == 0) | |
4cc0665f | 3318 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
3319 | /* We can't analyze the prologue if we couldn't find the begining |
3320 | of the function. */ | |
3321 | if (start_addr == 0) | |
3322 | return cache; | |
eec63939 | 3323 | |
19ba03f4 SM |
3324 | micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, |
3325 | (struct mips_frame_cache *) *this_cache); | |
29639122 | 3326 | } |
4cc0665f | 3327 | |
3e8c568d | 3328 | /* gdbarch_sp_regnum contains the value and not the address. */ |
a9a87d35 LM |
3329 | cache->saved_regs[gdbarch_num_regs (gdbarch) |
3330 | + MIPS_SP_REGNUM].set_value (cache->base); | |
eec63939 | 3331 | |
19ba03f4 | 3332 | return (struct mips_frame_cache *) (*this_cache); |
eec63939 AC |
3333 | } |
3334 | ||
3335 | static void | |
bd2b40ac | 3336 | mips_micro_frame_this_id (frame_info_ptr this_frame, void **this_cache, |
4cc0665f | 3337 | struct frame_id *this_id) |
eec63939 | 3338 | { |
4cc0665f MR |
3339 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3340 | this_cache); | |
21327321 DJ |
3341 | /* This marks the outermost frame. */ |
3342 | if (info->base == 0) | |
3343 | return; | |
b8a22b94 | 3344 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
3345 | } |
3346 | ||
b8a22b94 | 3347 | static struct value * |
bd2b40ac | 3348 | mips_micro_frame_prev_register (frame_info_ptr this_frame, |
4cc0665f | 3349 | void **this_cache, int regnum) |
eec63939 | 3350 | { |
4cc0665f MR |
3351 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3352 | this_cache); | |
b8a22b94 DJ |
3353 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3354 | } | |
3355 | ||
3356 | static int | |
4cc0665f | 3357 | mips_micro_frame_sniffer (const struct frame_unwind *self, |
bd2b40ac | 3358 | frame_info_ptr this_frame, void **this_cache) |
b8a22b94 | 3359 | { |
4cc0665f | 3360 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3361 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3362 | |
3363 | if (mips_pc_is_micromips (gdbarch, pc)) | |
b8a22b94 DJ |
3364 | return 1; |
3365 | return 0; | |
eec63939 AC |
3366 | } |
3367 | ||
4cc0665f | 3368 | static const struct frame_unwind mips_micro_frame_unwind = |
eec63939 | 3369 | { |
a154d838 | 3370 | "mips micro prologue", |
eec63939 | 3371 | NORMAL_FRAME, |
8fbca658 | 3372 | default_frame_unwind_stop_reason, |
4cc0665f MR |
3373 | mips_micro_frame_this_id, |
3374 | mips_micro_frame_prev_register, | |
b8a22b94 | 3375 | NULL, |
4cc0665f | 3376 | mips_micro_frame_sniffer |
eec63939 AC |
3377 | }; |
3378 | ||
eec63939 | 3379 | static CORE_ADDR |
bd2b40ac | 3380 | mips_micro_frame_base_address (frame_info_ptr this_frame, |
4cc0665f | 3381 | void **this_cache) |
eec63939 | 3382 | { |
4cc0665f MR |
3383 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3384 | this_cache); | |
29639122 | 3385 | return info->base; |
eec63939 AC |
3386 | } |
3387 | ||
4cc0665f | 3388 | static const struct frame_base mips_micro_frame_base = |
eec63939 | 3389 | { |
4cc0665f MR |
3390 | &mips_micro_frame_unwind, |
3391 | mips_micro_frame_base_address, | |
3392 | mips_micro_frame_base_address, | |
3393 | mips_micro_frame_base_address | |
eec63939 AC |
3394 | }; |
3395 | ||
3396 | static const struct frame_base * | |
bd2b40ac | 3397 | mips_micro_frame_base_sniffer (frame_info_ptr this_frame) |
eec63939 | 3398 | { |
4cc0665f | 3399 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3400 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3401 | |
3402 | if (mips_pc_is_micromips (gdbarch, pc)) | |
3403 | return &mips_micro_frame_base; | |
eec63939 AC |
3404 | else |
3405 | return NULL; | |
edfae063 AC |
3406 | } |
3407 | ||
29639122 JB |
3408 | /* Mark all the registers as unset in the saved_regs array |
3409 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
3410 | ||
74ed0bb4 MD |
3411 | static void |
3412 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 3413 | { |
29639122 JB |
3414 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
3415 | return; | |
3416 | ||
3417 | { | |
74ed0bb4 | 3418 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 3419 | int i; |
64159455 | 3420 | |
a9a87d35 LM |
3421 | /* Reset the register values to their default state. Register i's value |
3422 | is in register i. */ | |
29639122 | 3423 | for (i = 0; i < num_regs; i++) |
a9a87d35 | 3424 | this_cache->saved_regs[i].set_realreg (i); |
29639122 | 3425 | } |
c906108c SS |
3426 | } |
3427 | ||
025bb325 | 3428 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
3429 | the associated FRAME_CACHE if not null. |
3430 | Return the address of the first instruction past the prologue. */ | |
c906108c | 3431 | |
875e1767 | 3432 | static CORE_ADDR |
e17a4113 UW |
3433 | mips32_scan_prologue (struct gdbarch *gdbarch, |
3434 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
bd2b40ac | 3435 | frame_info_ptr this_frame, |
dda83cd7 | 3436 | struct mips_frame_cache *this_cache) |
c906108c | 3437 | { |
ab50adb6 MR |
3438 | int prev_non_prologue_insn; |
3439 | int this_non_prologue_insn; | |
3440 | int non_prologue_insns; | |
025bb325 MS |
3441 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
3442 | frame-pointer. */ | |
ab50adb6 MR |
3443 | int prev_delay_slot; |
3444 | CORE_ADDR prev_pc; | |
3445 | CORE_ADDR cur_pc; | |
29639122 JB |
3446 | CORE_ADDR sp; |
3447 | long frame_offset; | |
3448 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 3449 | |
ab50adb6 | 3450 | CORE_ADDR end_prologue_addr; |
29639122 JB |
3451 | int seen_sp_adjust = 0; |
3452 | int load_immediate_bytes = 0; | |
ab50adb6 | 3453 | int in_delay_slot; |
7d1e6fb8 | 3454 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 3455 | |
29639122 | 3456 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
3457 | THIS_FRAME. */ |
3458 | if (this_frame != NULL) | |
3459 | sp = get_frame_register_signed (this_frame, | |
3460 | gdbarch_num_regs (gdbarch) | |
3461 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 3462 | else |
29639122 | 3463 | sp = 0; |
9022177c | 3464 | |
29639122 JB |
3465 | if (limit_pc > start_pc + 200) |
3466 | limit_pc = start_pc + 200; | |
9022177c | 3467 | |
29639122 | 3468 | restart: |
ab50adb6 MR |
3469 | prev_non_prologue_insn = 0; |
3470 | non_prologue_insns = 0; | |
3471 | prev_delay_slot = 0; | |
3472 | prev_pc = start_pc; | |
9022177c | 3473 | |
ab50adb6 MR |
3474 | /* Permit at most one non-prologue non-control-transfer instruction |
3475 | in the middle which may have been reordered by the compiler for | |
3476 | optimisation. */ | |
29639122 | 3477 | frame_offset = 0; |
95ac2dcf | 3478 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 3479 | { |
eaa6a9a4 MR |
3480 | unsigned long inst, high_word; |
3481 | long offset; | |
29639122 | 3482 | int reg; |
9022177c | 3483 | |
ab50adb6 MR |
3484 | this_non_prologue_insn = 0; |
3485 | in_delay_slot = 0; | |
3486 | ||
025bb325 | 3487 | /* Fetch the instruction. */ |
4cc0665f MR |
3488 | inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, |
3489 | cur_pc, NULL); | |
9022177c | 3490 | |
29639122 JB |
3491 | /* Save some code by pre-extracting some useful fields. */ |
3492 | high_word = (inst >> 16) & 0xffff; | |
eaa6a9a4 | 3493 | offset = ((inst & 0xffff) ^ 0x8000) - 0x8000; |
29639122 | 3494 | reg = high_word & 0x1f; |
fe29b929 | 3495 | |
025bb325 | 3496 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
3497 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
3498 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
3499 | { | |
eaa6a9a4 | 3500 | if (offset < 0) /* Negative stack adjustment? */ |
dda83cd7 | 3501 | frame_offset -= offset; |
29639122 JB |
3502 | else |
3503 | /* Exit loop if a positive stack adjustment is found, which | |
3504 | usually means that the stack cleanup code in the function | |
3505 | epilogue is reached. */ | |
3506 | break; | |
dda83cd7 | 3507 | seen_sp_adjust = 1; |
29639122 | 3508 | } |
7d1e6fb8 | 3509 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
dda83cd7 | 3510 | && !regsize_is_64_bits) |
29639122 | 3511 | { |
eaa6a9a4 | 3512 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 | 3513 | } |
7d1e6fb8 | 3514 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
dda83cd7 | 3515 | && regsize_is_64_bits) |
29639122 JB |
3516 | { |
3517 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
eaa6a9a4 | 3518 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
3519 | } |
3520 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
3521 | { | |
3522 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
eaa6a9a4 MR |
3523 | if (offset != frame_offset) |
3524 | frame_addr = sp + offset; | |
b8a22b94 | 3525 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3526 | { |
3527 | unsigned alloca_adjust; | |
a4b8ebc8 | 3528 | |
29639122 | 3529 | frame_reg = 30; |
b8a22b94 DJ |
3530 | frame_addr = get_frame_register_signed |
3531 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
ca9c94ef | 3532 | frame_offset = 0; |
d2ca4222 | 3533 | |
eaa6a9a4 | 3534 | alloca_adjust = (unsigned) (frame_addr - (sp + offset)); |
29639122 JB |
3535 | if (alloca_adjust > 0) |
3536 | { | |
dda83cd7 SM |
3537 | /* FP > SP + frame_size. This may be because of |
3538 | an alloca or somethings similar. Fix sp to | |
3539 | "pre-alloca" value, and try again. */ | |
29639122 | 3540 | sp += alloca_adjust; |
dda83cd7 SM |
3541 | /* Need to reset the status of all registers. Otherwise, |
3542 | we will hit a guard that prevents the new address | |
3543 | for each register to be recomputed during the second | |
3544 | pass. */ | |
3545 | reset_saved_regs (gdbarch, this_cache); | |
29639122 JB |
3546 | goto restart; |
3547 | } | |
3548 | } | |
3549 | } | |
3550 | /* move $30,$sp. With different versions of gas this will be either | |
dda83cd7 SM |
3551 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. |
3552 | Accept any one of these. */ | |
29639122 JB |
3553 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
3554 | { | |
3555 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 3556 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3557 | { |
3558 | unsigned alloca_adjust; | |
c906108c | 3559 | |
29639122 | 3560 | frame_reg = 30; |
b8a22b94 DJ |
3561 | frame_addr = get_frame_register_signed |
3562 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 3563 | |
29639122 JB |
3564 | alloca_adjust = (unsigned) (frame_addr - sp); |
3565 | if (alloca_adjust > 0) | |
dda83cd7 SM |
3566 | { |
3567 | /* FP > SP + frame_size. This may be because of | |
3568 | an alloca or somethings similar. Fix sp to | |
3569 | "pre-alloca" value, and try again. */ | |
3570 | sp = frame_addr; | |
3571 | /* Need to reset the status of all registers. Otherwise, | |
3572 | we will hit a guard that prevents the new address | |
3573 | for each register to be recomputed during the second | |
3574 | pass. */ | |
3575 | reset_saved_regs (gdbarch, this_cache); | |
3576 | goto restart; | |
3577 | } | |
29639122 JB |
3578 | } |
3579 | } | |
7d1e6fb8 | 3580 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
dda83cd7 | 3581 | && !regsize_is_64_bits) |
29639122 | 3582 | { |
eaa6a9a4 | 3583 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
3584 | } |
3585 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
dda83cd7 SM |
3586 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ |
3587 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
3588 | || high_word == 0x3c1c /* lui $gp,n */ | |
3589 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
f8b786e2 | 3590 | || high_word == 0x679c /* daddiu $gp,$gp,n */ |
dda83cd7 SM |
3591 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ |
3592 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
f8b786e2 YT |
3593 | || inst == 0x0399e02d /* daddu $gp,$gp,$t9 */ |
3594 | || inst == 0x033ce02d /* daddu $gp,$t9,$gp */ | |
dda83cd7 | 3595 | ) |
19080931 MR |
3596 | { |
3597 | /* These instructions are part of the prologue, but we don't | |
3598 | need to do anything special to handle them. */ | |
3599 | } | |
29639122 | 3600 | /* The instructions below load $at or $t0 with an immediate |
dda83cd7 SM |
3601 | value in preparation for a stack adjustment via |
3602 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
3603 | initialize a local variable, so we accept them only before | |
3604 | a stack adjustment instruction was seen. */ | |
29639122 | 3605 | else if (!seen_sp_adjust |
ab50adb6 | 3606 | && !prev_delay_slot |
19080931 MR |
3607 | && (high_word == 0x3c01 /* lui $at,n */ |
3608 | || high_word == 0x3c08 /* lui $t0,n */ | |
3609 | || high_word == 0x3421 /* ori $at,$at,n */ | |
3610 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
3611 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
3612 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
3613 | )) | |
3614 | { | |
ab50adb6 | 3615 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
19080931 | 3616 | } |
ab50adb6 | 3617 | /* Check for branches and jumps. The instruction in the delay |
dda83cd7 | 3618 | slot can be a part of the prologue, so move forward once more. */ |
ab50adb6 MR |
3619 | else if (mips32_instruction_has_delay_slot (gdbarch, inst)) |
3620 | { | |
3621 | in_delay_slot = 1; | |
3622 | } | |
3623 | /* This instruction is not an instruction typically found | |
dda83cd7 SM |
3624 | in a prologue, so we must have reached the end of the |
3625 | prologue. */ | |
29639122 | 3626 | else |
19080931 | 3627 | { |
ab50adb6 | 3628 | this_non_prologue_insn = 1; |
19080931 | 3629 | } |
db5f024e | 3630 | |
ab50adb6 MR |
3631 | non_prologue_insns += this_non_prologue_insn; |
3632 | ||
3633 | /* A jump or branch, or enough non-prologue insns seen? If so, | |
dda83cd7 | 3634 | then we must have reached the end of the prologue by now. */ |
ab50adb6 | 3635 | if (prev_delay_slot || non_prologue_insns > 1) |
db5f024e | 3636 | break; |
ab50adb6 MR |
3637 | |
3638 | prev_non_prologue_insn = this_non_prologue_insn; | |
3639 | prev_delay_slot = in_delay_slot; | |
3640 | prev_pc = cur_pc; | |
a4b8ebc8 | 3641 | } |
c906108c | 3642 | |
29639122 JB |
3643 | if (this_cache != NULL) |
3644 | { | |
3645 | this_cache->base = | |
dda83cd7 | 3646 | (get_frame_register_signed (this_frame, |
b8a22b94 | 3647 | gdbarch_num_regs (gdbarch) + frame_reg) |
dda83cd7 | 3648 | + frame_offset); |
29639122 | 3649 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of |
dda83cd7 SM |
3650 | this assignment below, eventually. But it's still needed |
3651 | for now. */ | |
72a155b4 UW |
3652 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3653 | + mips_regnum (gdbarch)->pc] | |
dda83cd7 | 3654 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
f57d151a | 3655 | + MIPS_RA_REGNUM]; |
29639122 | 3656 | } |
c906108c | 3657 | |
ab50adb6 MR |
3658 | /* Set end_prologue_addr to the address of the instruction immediately |
3659 | after the last one we scanned. Unless the last one looked like a | |
3660 | non-prologue instruction (and we looked ahead), in which case use | |
3661 | its address instead. */ | |
3662 | end_prologue_addr | |
3663 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; | |
29639122 JB |
3664 | |
3665 | /* In a frameless function, we might have incorrectly | |
025bb325 | 3666 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
3667 | if the load immediate was not followed by a stack adjustment. */ |
3668 | if (load_immediate_bytes && !seen_sp_adjust) | |
3669 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 3670 | |
29639122 | 3671 | return end_prologue_addr; |
c906108c SS |
3672 | } |
3673 | ||
29639122 JB |
3674 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
3675 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
3676 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
4cc0665f | 3677 | unwinder. Likewise microMIPS and the mips_micro unwinder. */ |
c906108c | 3678 | |
29639122 | 3679 | static struct mips_frame_cache * |
bd2b40ac | 3680 | mips_insn32_frame_cache (frame_info_ptr this_frame, void **this_cache) |
c906108c | 3681 | { |
e17a4113 | 3682 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3683 | struct mips_frame_cache *cache; |
c906108c | 3684 | |
29639122 | 3685 | if ((*this_cache) != NULL) |
19ba03f4 | 3686 | return (struct mips_frame_cache *) (*this_cache); |
c5aa993b | 3687 | |
29639122 JB |
3688 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3689 | (*this_cache) = cache; | |
b8a22b94 | 3690 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 3691 | |
29639122 JB |
3692 | /* Analyze the function prologue. */ |
3693 | { | |
b8a22b94 | 3694 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3695 | CORE_ADDR start_addr; |
c906108c | 3696 | |
29639122 JB |
3697 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3698 | if (start_addr == 0) | |
e17a4113 | 3699 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
3700 | /* We can't analyze the prologue if we couldn't find the begining |
3701 | of the function. */ | |
3702 | if (start_addr == 0) | |
3703 | return cache; | |
c5aa993b | 3704 | |
19ba03f4 SM |
3705 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, |
3706 | (struct mips_frame_cache *) *this_cache); | |
29639122 JB |
3707 | } |
3708 | ||
3e8c568d | 3709 | /* gdbarch_sp_regnum contains the value and not the address. */ |
a9a87d35 LM |
3710 | cache->saved_regs[gdbarch_num_regs (gdbarch) |
3711 | + MIPS_SP_REGNUM].set_value (cache->base); | |
c5aa993b | 3712 | |
19ba03f4 | 3713 | return (struct mips_frame_cache *) (*this_cache); |
c906108c SS |
3714 | } |
3715 | ||
29639122 | 3716 | static void |
bd2b40ac | 3717 | mips_insn32_frame_this_id (frame_info_ptr this_frame, void **this_cache, |
29639122 | 3718 | struct frame_id *this_id) |
c906108c | 3719 | { |
b8a22b94 | 3720 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3721 | this_cache); |
21327321 DJ |
3722 | /* This marks the outermost frame. */ |
3723 | if (info->base == 0) | |
3724 | return; | |
b8a22b94 | 3725 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 3726 | } |
c906108c | 3727 | |
b8a22b94 | 3728 | static struct value * |
bd2b40ac | 3729 | mips_insn32_frame_prev_register (frame_info_ptr this_frame, |
b8a22b94 | 3730 | void **this_cache, int regnum) |
29639122 | 3731 | { |
b8a22b94 | 3732 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3733 | this_cache); |
b8a22b94 DJ |
3734 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3735 | } | |
3736 | ||
3737 | static int | |
3738 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 3739 | frame_info_ptr this_frame, void **this_cache) |
b8a22b94 DJ |
3740 | { |
3741 | CORE_ADDR pc = get_frame_pc (this_frame); | |
4cc0665f | 3742 | if (mips_pc_is_mips (pc)) |
b8a22b94 DJ |
3743 | return 1; |
3744 | return 0; | |
c906108c SS |
3745 | } |
3746 | ||
29639122 JB |
3747 | static const struct frame_unwind mips_insn32_frame_unwind = |
3748 | { | |
a154d838 | 3749 | "mips insn32 prologue", |
29639122 | 3750 | NORMAL_FRAME, |
8fbca658 | 3751 | default_frame_unwind_stop_reason, |
29639122 | 3752 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
3753 | mips_insn32_frame_prev_register, |
3754 | NULL, | |
3755 | mips_insn32_frame_sniffer | |
29639122 | 3756 | }; |
c906108c | 3757 | |
1c645fec | 3758 | static CORE_ADDR |
bd2b40ac | 3759 | mips_insn32_frame_base_address (frame_info_ptr this_frame, |
29639122 | 3760 | void **this_cache) |
c906108c | 3761 | { |
b8a22b94 | 3762 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
3763 | this_cache); |
3764 | return info->base; | |
3765 | } | |
c906108c | 3766 | |
29639122 JB |
3767 | static const struct frame_base mips_insn32_frame_base = |
3768 | { | |
3769 | &mips_insn32_frame_unwind, | |
3770 | mips_insn32_frame_base_address, | |
3771 | mips_insn32_frame_base_address, | |
3772 | mips_insn32_frame_base_address | |
3773 | }; | |
1c645fec | 3774 | |
29639122 | 3775 | static const struct frame_base * |
bd2b40ac | 3776 | mips_insn32_frame_base_sniffer (frame_info_ptr this_frame) |
29639122 | 3777 | { |
b8a22b94 | 3778 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f | 3779 | if (mips_pc_is_mips (pc)) |
29639122 | 3780 | return &mips_insn32_frame_base; |
a65bbe44 | 3781 | else |
29639122 JB |
3782 | return NULL; |
3783 | } | |
a65bbe44 | 3784 | |
29639122 | 3785 | static struct trad_frame_cache * |
bd2b40ac | 3786 | mips_stub_frame_cache (frame_info_ptr this_frame, void **this_cache) |
29639122 JB |
3787 | { |
3788 | CORE_ADDR pc; | |
3789 | CORE_ADDR start_addr; | |
3790 | CORE_ADDR stack_addr; | |
3791 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
3792 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3793 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 3794 | |
29639122 | 3795 | if ((*this_cache) != NULL) |
19ba03f4 | 3796 | return (struct trad_frame_cache *) (*this_cache); |
b8a22b94 | 3797 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 3798 | (*this_cache) = this_trad_cache; |
1c645fec | 3799 | |
29639122 | 3800 | /* The return address is in the link register. */ |
3e8c568d | 3801 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 3802 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 3803 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 3804 | |
29639122 JB |
3805 | /* Frame ID, since it's a frameless / stackless function, no stack |
3806 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 3807 | pc = get_frame_pc (this_frame); |
29639122 | 3808 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
3809 | stack_addr = get_frame_register_signed (this_frame, |
3810 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 3811 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 3812 | |
29639122 JB |
3813 | /* Assume that the frame's base is the same as the |
3814 | stack-pointer. */ | |
3815 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 3816 | |
29639122 JB |
3817 | return this_trad_cache; |
3818 | } | |
c906108c | 3819 | |
29639122 | 3820 | static void |
bd2b40ac | 3821 | mips_stub_frame_this_id (frame_info_ptr this_frame, void **this_cache, |
29639122 JB |
3822 | struct frame_id *this_id) |
3823 | { | |
3824 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3825 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3826 | trad_frame_get_id (this_trad_cache, this_id); |
3827 | } | |
c906108c | 3828 | |
b8a22b94 | 3829 | static struct value * |
bd2b40ac | 3830 | mips_stub_frame_prev_register (frame_info_ptr this_frame, |
b8a22b94 | 3831 | void **this_cache, int regnum) |
29639122 JB |
3832 | { |
3833 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
3834 | = mips_stub_frame_cache (this_frame, this_cache); |
3835 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 3836 | } |
c906108c | 3837 | |
b8a22b94 DJ |
3838 | static int |
3839 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 3840 | frame_info_ptr this_frame, void **this_cache) |
29639122 | 3841 | { |
aa6c981f | 3842 | gdb_byte dummy[4]; |
b8a22b94 | 3843 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
7cbd4a93 | 3844 | struct bound_minimal_symbol msym; |
979b38e0 | 3845 | |
aa6c981f | 3846 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
3847 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
3848 | return 1; | |
aa6c981f | 3849 | |
3e5d3a5a | 3850 | if (in_plt_section (pc) || in_mips_stubs_section (pc)) |
b8a22b94 | 3851 | return 1; |
979b38e0 | 3852 | |
db5f024e DJ |
3853 | /* Calling a PIC function from a non-PIC function passes through a |
3854 | stub. The stub for foo is named ".pic.foo". */ | |
3855 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 3856 | if (msym.minsym != NULL |
c9d95fa3 CB |
3857 | && msym.minsym->linkage_name () != NULL |
3858 | && startswith (msym.minsym->linkage_name (), ".pic.")) | |
db5f024e DJ |
3859 | return 1; |
3860 | ||
b8a22b94 | 3861 | return 0; |
29639122 | 3862 | } |
c906108c | 3863 | |
b8a22b94 DJ |
3864 | static const struct frame_unwind mips_stub_frame_unwind = |
3865 | { | |
a154d838 | 3866 | "mips stub", |
b8a22b94 | 3867 | NORMAL_FRAME, |
8fbca658 | 3868 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
3869 | mips_stub_frame_this_id, |
3870 | mips_stub_frame_prev_register, | |
3871 | NULL, | |
3872 | mips_stub_frame_sniffer | |
3873 | }; | |
3874 | ||
29639122 | 3875 | static CORE_ADDR |
bd2b40ac | 3876 | mips_stub_frame_base_address (frame_info_ptr this_frame, |
29639122 JB |
3877 | void **this_cache) |
3878 | { | |
3879 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3880 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3881 | return trad_frame_get_this_base (this_trad_cache); |
3882 | } | |
0fce0821 | 3883 | |
29639122 JB |
3884 | static const struct frame_base mips_stub_frame_base = |
3885 | { | |
3886 | &mips_stub_frame_unwind, | |
3887 | mips_stub_frame_base_address, | |
3888 | mips_stub_frame_base_address, | |
3889 | mips_stub_frame_base_address | |
3890 | }; | |
3891 | ||
3892 | static const struct frame_base * | |
bd2b40ac | 3893 | mips_stub_frame_base_sniffer (frame_info_ptr this_frame) |
29639122 | 3894 | { |
b8a22b94 | 3895 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
3896 | return &mips_stub_frame_base; |
3897 | else | |
3898 | return NULL; | |
3899 | } | |
3900 | ||
29639122 | 3901 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 3902 | |
29639122 | 3903 | static CORE_ADDR |
24568a2c | 3904 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 3905 | { |
08106042 | 3906 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
930bd0e0 | 3907 | |
29639122 JB |
3908 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
3909 | /* This hack is a work-around for existing boards using PMON, the | |
3910 | simulator, and any other 64-bit targets that doesn't have true | |
3911 | 64-bit addressing. On these targets, the upper 32 bits of | |
3912 | addresses are ignored by the hardware. Thus, the PC or SP are | |
3913 | likely to have been sign extended to all 1s by instruction | |
3914 | sequences that load 32-bit addresses. For example, a typical | |
3915 | piece of code that loads an address is this: | |
65596487 | 3916 | |
29639122 JB |
3917 | lui $r2, <upper 16 bits> |
3918 | ori $r2, <lower 16 bits> | |
65596487 | 3919 | |
29639122 JB |
3920 | But the lui sign-extends the value such that the upper 32 bits |
3921 | may be all 1s. The workaround is simply to mask off these | |
3922 | bits. In the future, gcc may be changed to support true 64-bit | |
3923 | addressing, and this masking will have to be disabled. */ | |
3924 | return addr &= 0xffffffffUL; | |
3925 | else | |
3926 | return addr; | |
65596487 JB |
3927 | } |
3928 | ||
3d5f6d12 DJ |
3929 | |
3930 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
3931 | instruction and ending with a SC/SCD instruction. If such a sequence | |
3932 | is found, attempt to step through it. A breakpoint is placed at the end of | |
3933 | the sequence. */ | |
3934 | ||
4cc0665f MR |
3935 | /* Instructions used during single-stepping of atomic sequences, standard |
3936 | ISA version. */ | |
3937 | #define LL_OPCODE 0x30 | |
3938 | #define LLD_OPCODE 0x34 | |
3939 | #define SC_OPCODE 0x38 | |
3940 | #define SCD_OPCODE 0x3c | |
3941 | ||
a0ff9e1a | 3942 | static std::vector<CORE_ADDR> |
93f9a11f | 3943 | mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) |
3d5f6d12 | 3944 | { |
70ab8ccd | 3945 | CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; |
3d5f6d12 DJ |
3946 | CORE_ADDR loc = pc; |
3947 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
4cc0665f | 3948 | ULONGEST insn; |
3d5f6d12 DJ |
3949 | int insn_count; |
3950 | int index; | |
3951 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3952 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3953 | ||
4cc0665f | 3954 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3955 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
3956 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
a0ff9e1a | 3957 | return {}; |
3d5f6d12 DJ |
3958 | |
3959 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
3960 | instructions. */ | |
3961 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
3962 | { | |
3963 | int is_branch = 0; | |
3964 | loc += MIPS_INSN32_SIZE; | |
4cc0665f | 3965 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3966 | |
3967 | /* Assume that there is at most one branch in the atomic | |
3968 | sequence. If a branch is found, put a breakpoint in its | |
3969 | destination address. */ | |
3970 | switch (itype_op (insn)) | |
3971 | { | |
3972 | case 0: /* SPECIAL */ | |
3973 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
a0ff9e1a | 3974 | return {}; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3975 | break; |
3976 | case 1: /* REGIMM */ | |
a385295e MR |
3977 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
3978 | || ((itype_rt (insn) & 0x1e) == 0 | |
3979 | && itype_rs (insn) == 0)); /* BPOSGE* */ | |
3d5f6d12 DJ |
3980 | break; |
3981 | case 2: /* J */ | |
3982 | case 3: /* JAL */ | |
a0ff9e1a | 3983 | return {}; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3984 | case 4: /* BEQ */ |
3985 | case 5: /* BNE */ | |
3986 | case 6: /* BLEZ */ | |
3987 | case 7: /* BGTZ */ | |
3988 | case 20: /* BEQL */ | |
3989 | case 21: /* BNEL */ | |
3990 | case 22: /* BLEZL */ | |
3991 | case 23: /* BGTTL */ | |
3992 | is_branch = 1; | |
3993 | break; | |
3994 | case 17: /* COP1 */ | |
a385295e MR |
3995 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
3996 | && (itype_rt (insn) & 0x2) == 0); | |
3997 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ | |
3998 | break; | |
d182e398 | 3999 | [[fallthrough]]; |
3d5f6d12 DJ |
4000 | case 18: /* COP2 */ |
4001 | case 19: /* COP3 */ | |
4002 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
4003 | break; | |
4004 | } | |
4005 | if (is_branch) | |
4006 | { | |
4007 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
4008 | if (last_breakpoint >= 1) | |
a0ff9e1a SM |
4009 | return {}; /* More than one branch found, fallback to the |
4010 | standard single-step code. */ | |
3d5f6d12 DJ |
4011 | breaks[1] = branch_bp; |
4012 | last_breakpoint++; | |
4013 | } | |
4014 | ||
4015 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
4016 | break; | |
4017 | } | |
4018 | ||
4019 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
4020 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
a0ff9e1a | 4021 | return {}; |
3d5f6d12 DJ |
4022 | |
4023 | loc += MIPS_INSN32_SIZE; | |
4024 | ||
4025 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
4026 | breaks[0] = loc; | |
4027 | ||
4028 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 4029 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
4030 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
4031 | last_breakpoint = 0; | |
4032 | ||
a0ff9e1a SM |
4033 | std::vector<CORE_ADDR> next_pcs; |
4034 | ||
3d5f6d12 DJ |
4035 | /* Effectively inserts the breakpoints. */ |
4036 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 4037 | next_pcs.push_back (breaks[index]); |
3d5f6d12 | 4038 | |
93f9a11f | 4039 | return next_pcs; |
3d5f6d12 DJ |
4040 | } |
4041 | ||
a0ff9e1a | 4042 | static std::vector<CORE_ADDR> |
4cc0665f | 4043 | micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
4cc0665f MR |
4044 | CORE_ADDR pc) |
4045 | { | |
4046 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
4047 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
70ab8ccd | 4048 | CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; |
4b844a38 AT |
4049 | CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's |
4050 | destination. */ | |
4cc0665f MR |
4051 | CORE_ADDR loc = pc; |
4052 | int sc_found = 0; | |
4053 | ULONGEST insn; | |
4054 | int insn_count; | |
4055 | int index; | |
4056 | ||
4057 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
4058 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4059 | if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ | |
a0ff9e1a | 4060 | return {}; |
4cc0665f MR |
4061 | loc += MIPS_INSN16_SIZE; |
4062 | insn <<= 16; | |
4063 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4064 | if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ | |
a0ff9e1a | 4065 | return {}; |
4cc0665f MR |
4066 | loc += MIPS_INSN16_SIZE; |
4067 | ||
4068 | /* Assume all atomic sequences end with an sc/scd instruction. Assume | |
4069 | that no atomic sequence is longer than "atomic_sequence_length" | |
4070 | instructions. */ | |
4071 | for (insn_count = 0; | |
4072 | !sc_found && insn_count < atomic_sequence_length; | |
4073 | ++insn_count) | |
4074 | { | |
4075 | int is_branch = 0; | |
4076 | ||
4077 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4078 | loc += MIPS_INSN16_SIZE; | |
4079 | ||
4080 | /* Assume that there is at most one conditional branch in the | |
dda83cd7 SM |
4081 | atomic sequence. If a branch is found, put a breakpoint in |
4082 | its destination address. */ | |
4cc0665f MR |
4083 | switch (mips_insn_size (ISA_MICROMIPS, insn)) |
4084 | { | |
4cc0665f MR |
4085 | /* 32-bit instructions. */ |
4086 | case 2 * MIPS_INSN16_SIZE: | |
4087 | switch (micromips_op (insn)) | |
4088 | { | |
4089 | case 0x10: /* POOL32I: bits 010000 */ | |
4090 | if ((b5s5_op (insn) & 0x18) != 0x0 | |
4091 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
4092 | /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ | |
4093 | && (b5s5_op (insn) & 0x1d) != 0x11 | |
4094 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
4095 | && ((b5s5_op (insn) & 0x1e) != 0x14 | |
4096 | || (insn & 0x3) != 0x0) | |
4097 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
4098 | && (b5s5_op (insn) & 0x1e) != 0x1a | |
4099 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
4100 | && ((b5s5_op (insn) & 0x1e) != 0x1c | |
4101 | || (insn & 0x3) != 0x0) | |
4102 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
4103 | && ((b5s5_op (insn) & 0x1c) != 0x1c | |
4104 | || (insn & 0x3) != 0x1)) | |
4105 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
4106 | break; | |
d182e398 | 4107 | [[fallthrough]]; |
4cc0665f MR |
4108 | |
4109 | case 0x25: /* BEQ: bits 100101 */ | |
4110 | case 0x2d: /* BNE: bits 101101 */ | |
4111 | insn <<= 16; | |
4112 | insn |= mips_fetch_instruction (gdbarch, | |
4113 | ISA_MICROMIPS, loc, NULL); | |
4114 | branch_bp = (loc + MIPS_INSN16_SIZE | |
4115 | + micromips_relative_offset16 (insn)); | |
4116 | is_branch = 1; | |
4117 | break; | |
4118 | ||
4119 | case 0x00: /* POOL32A: bits 000000 */ | |
4120 | insn <<= 16; | |
4121 | insn |= mips_fetch_instruction (gdbarch, | |
4122 | ISA_MICROMIPS, loc, NULL); | |
4123 | if (b0s6_op (insn) != 0x3c | |
4124 | /* POOL32Axf: bits 000000 ... 111100 */ | |
4125 | || (b6s10_ext (insn) & 0x2bf) != 0x3c) | |
4126 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
4127 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
4128 | break; | |
d182e398 | 4129 | [[fallthrough]]; |
4cc0665f MR |
4130 | |
4131 | case 0x1d: /* JALS: bits 011101 */ | |
4132 | case 0x35: /* J: bits 110101 */ | |
4133 | case 0x3d: /* JAL: bits 111101 */ | |
4134 | case 0x3c: /* JALX: bits 111100 */ | |
a0ff9e1a | 4135 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4136 | |
4137 | case 0x18: /* POOL32C: bits 011000 */ | |
4138 | if ((b12s4_op (insn) & 0xb) == 0xb) | |
4139 | /* SC, SCD: bits 011000 1x11 */ | |
4140 | sc_found = 1; | |
4141 | break; | |
4142 | } | |
4143 | loc += MIPS_INSN16_SIZE; | |
4144 | break; | |
4145 | ||
4146 | /* 16-bit instructions. */ | |
4147 | case MIPS_INSN16_SIZE: | |
4148 | switch (micromips_op (insn)) | |
4149 | { | |
4150 | case 0x23: /* BEQZ16: bits 100011 */ | |
4151 | case 0x2b: /* BNEZ16: bits 101011 */ | |
4152 | branch_bp = loc + micromips_relative_offset7 (insn); | |
4153 | is_branch = 1; | |
4154 | break; | |
4155 | ||
4156 | case 0x11: /* POOL16C: bits 010001 */ | |
4157 | if ((b5s5_op (insn) & 0x1c) != 0xc | |
4158 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
dda83cd7 | 4159 | && b5s5_op (insn) != 0x18) |
4cc0665f | 4160 | /* JRADDIUSP: bits 010001 11000 */ |
dda83cd7 | 4161 | break; |
a0ff9e1a | 4162 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4163 | |
4164 | case 0x33: /* B16: bits 110011 */ | |
a0ff9e1a | 4165 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4166 | } |
4167 | break; | |
4168 | } | |
4169 | if (is_branch) | |
4170 | { | |
4171 | if (last_breakpoint >= 1) | |
a0ff9e1a SM |
4172 | return {}; /* More than one branch found, fallback to the |
4173 | standard single-step code. */ | |
4cc0665f MR |
4174 | breaks[1] = branch_bp; |
4175 | last_breakpoint++; | |
4176 | } | |
4177 | } | |
4178 | if (!sc_found) | |
a0ff9e1a | 4179 | return {}; |
4cc0665f MR |
4180 | |
4181 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
4182 | breaks[0] = loc; | |
4183 | ||
4184 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
4185 | placed (branch instruction's destination) in the atomic sequence */ | |
4186 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
4187 | last_breakpoint = 0; | |
4188 | ||
a0ff9e1a SM |
4189 | std::vector<CORE_ADDR> next_pcs; |
4190 | ||
4cc0665f MR |
4191 | /* Effectively inserts the breakpoints. */ |
4192 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 4193 | next_pcs.push_back (breaks[index]); |
4cc0665f | 4194 | |
93f9a11f | 4195 | return next_pcs; |
4cc0665f MR |
4196 | } |
4197 | ||
a0ff9e1a | 4198 | static std::vector<CORE_ADDR> |
93f9a11f | 4199 | deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) |
4cc0665f MR |
4200 | { |
4201 | if (mips_pc_is_mips (pc)) | |
93f9a11f | 4202 | return mips_deal_with_atomic_sequence (gdbarch, pc); |
4cc0665f | 4203 | else if (mips_pc_is_micromips (gdbarch, pc)) |
93f9a11f | 4204 | return micromips_deal_with_atomic_sequence (gdbarch, pc); |
4cc0665f | 4205 | else |
a0ff9e1a | 4206 | return {}; |
4cc0665f MR |
4207 | } |
4208 | ||
29639122 JB |
4209 | /* mips_software_single_step() is called just before we want to resume |
4210 | the inferior, if we want to single-step it but there is no hardware | |
4211 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 4212 | the target of the coming instruction and breakpoint it. */ |
29639122 | 4213 | |
a0ff9e1a | 4214 | std::vector<CORE_ADDR> |
f5ea389a | 4215 | mips_software_single_step (struct regcache *regcache) |
c906108c | 4216 | { |
ac7936df | 4217 | struct gdbarch *gdbarch = regcache->arch (); |
8181d85f | 4218 | CORE_ADDR pc, next_pc; |
65596487 | 4219 | |
7113a196 | 4220 | pc = regcache_read_pc (regcache); |
a0ff9e1a SM |
4221 | std::vector<CORE_ADDR> next_pcs = deal_with_atomic_sequence (gdbarch, pc); |
4222 | ||
4223 | if (!next_pcs.empty ()) | |
93f9a11f | 4224 | return next_pcs; |
3d5f6d12 | 4225 | |
7113a196 | 4226 | next_pc = mips_next_pc (regcache, pc); |
e6590a1b | 4227 | |
a0ff9e1a | 4228 | return {next_pc}; |
29639122 | 4229 | } |
a65bbe44 | 4230 | |
29639122 | 4231 | /* Test whether the PC points to the return instruction at the |
025bb325 | 4232 | end of a function. */ |
65596487 | 4233 | |
29639122 | 4234 | static int |
e17a4113 | 4235 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 4236 | { |
6321c22a MR |
4237 | ULONGEST insn; |
4238 | ULONGEST hint; | |
4239 | ||
4240 | /* This used to check for MIPS16, but this piece of code is never | |
4cc0665f MR |
4241 | called for MIPS16 functions. And likewise microMIPS ones. */ |
4242 | gdb_assert (mips_pc_is_mips (pc)); | |
6321c22a | 4243 | |
4cc0665f | 4244 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
6321c22a MR |
4245 | hint = 0x7c0; |
4246 | return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ | |
29639122 | 4247 | } |
c906108c | 4248 | |
c906108c | 4249 | |
29639122 JB |
4250 | /* This fencepost looks highly suspicious to me. Removing it also |
4251 | seems suspicious as it could affect remote debugging across serial | |
4252 | lines. */ | |
c906108c | 4253 | |
29639122 | 4254 | static CORE_ADDR |
74ed0bb4 | 4255 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
4256 | { |
4257 | CORE_ADDR start_pc; | |
4258 | CORE_ADDR fence; | |
4259 | int instlen; | |
4260 | int seen_adjsp = 0; | |
d6b48e9c | 4261 | struct inferior *inf; |
65596487 | 4262 | |
74ed0bb4 | 4263 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
4264 | start_pc = pc; |
4265 | fence = start_pc - heuristic_fence_post; | |
4266 | if (start_pc == 0) | |
4267 | return 0; | |
65596487 | 4268 | |
44096aee | 4269 | if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS) |
29639122 | 4270 | fence = VM_MIN_ADDRESS; |
65596487 | 4271 | |
4cc0665f | 4272 | instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; |
98b4dd94 | 4273 | |
d6b48e9c PA |
4274 | inf = current_inferior (); |
4275 | ||
025bb325 | 4276 | /* Search back for previous return. */ |
29639122 JB |
4277 | for (start_pc -= instlen;; start_pc -= instlen) |
4278 | if (start_pc < fence) | |
4279 | { | |
4280 | /* It's not clear to me why we reach this point when | |
4281 | stop_soon, but with this test, at least we | |
4282 | don't print out warnings for every child forked (eg, on | |
4283 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 4284 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
4285 | { |
4286 | static int blurb_printed = 0; | |
98b4dd94 | 4287 | |
5af949e3 UW |
4288 | warning (_("GDB can't find the start of the function at %s."), |
4289 | paddress (gdbarch, pc)); | |
29639122 JB |
4290 | |
4291 | if (!blurb_printed) | |
4292 | { | |
4293 | /* This actually happens frequently in embedded | |
4294 | development, when you first connect to a board | |
4295 | and your stack pointer and pc are nowhere in | |
4296 | particular. This message needs to give people | |
4297 | in that situation enough information to | |
4298 | determine that it's no big deal. */ | |
6cb06a8c | 4299 | gdb_printf ("\n\ |
5af949e3 | 4300 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
4301 | and thus can't determine the size of that function's stack frame.\n\ |
4302 | This means that GDB may be unable to access that stack frame, or\n\ | |
4303 | the frames below it.\n\ | |
4304 | This problem is most likely caused by an invalid program counter or\n\ | |
4305 | stack pointer.\n\ | |
4306 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 4307 | from %s for code which looks like the beginning of a\n\ |
29639122 | 4308 | function, you can increase the range of the search using the `set\n\ |
5af949e3 | 4309 | heuristic-fence-post' command.\n", |
6cb06a8c | 4310 | paddress (gdbarch, pc), paddress (gdbarch, pc)); |
29639122 JB |
4311 | blurb_printed = 1; |
4312 | } | |
4313 | } | |
4314 | ||
4315 | return 0; | |
4316 | } | |
4cc0665f | 4317 | else if (mips_pc_is_mips16 (gdbarch, start_pc)) |
29639122 JB |
4318 | { |
4319 | unsigned short inst; | |
4320 | ||
4321 | /* On MIPS16, any one of the following is likely to be the | |
4322 | start of a function: | |
24b21115 | 4323 | extend save |
193774b3 | 4324 | save |
29639122 JB |
4325 | entry |
4326 | addiu sp,-n | |
4327 | daddiu sp,-n | |
025bb325 | 4328 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
4cc0665f | 4329 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); |
193774b3 MR |
4330 | if ((inst & 0xff80) == 0x6480) /* save */ |
4331 | { | |
4332 | if (start_pc - instlen >= fence) | |
4333 | { | |
4cc0665f MR |
4334 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, |
4335 | start_pc - instlen, NULL); | |
193774b3 MR |
4336 | if ((inst & 0xf800) == 0xf000) /* extend */ |
4337 | start_pc -= instlen; | |
4338 | } | |
4339 | break; | |
4340 | } | |
4341 | else if (((inst & 0xf81f) == 0xe809 | |
4342 | && (inst & 0x700) != 0x700) /* entry */ | |
4343 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
4344 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
4345 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
4346 | break; |
4347 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
4348 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
4349 | seen_adjsp = 1; | |
4350 | else | |
4351 | seen_adjsp = 0; | |
4352 | } | |
4cc0665f MR |
4353 | else if (mips_pc_is_micromips (gdbarch, start_pc)) |
4354 | { | |
4355 | ULONGEST insn; | |
4356 | int stop = 0; | |
4357 | long offset; | |
4358 | int dreg; | |
4359 | int sreg; | |
4360 | ||
4361 | /* On microMIPS, any one of the following is likely to be the | |
4362 | start of a function: | |
4363 | ADDIUSP -imm | |
4364 | (D)ADDIU $sp, -imm | |
4365 | LUI $gp, imm */ | |
4366 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
4367 | switch (micromips_op (insn)) | |
4368 | { | |
4369 | case 0xc: /* ADDIU: bits 001100 */ | |
4370 | case 0x17: /* DADDIU: bits 010111 */ | |
4371 | sreg = b0s5_reg (insn); | |
4372 | dreg = b5s5_reg (insn); | |
4373 | insn <<= 16; | |
4374 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, | |
4375 | pc + MIPS_INSN16_SIZE, NULL); | |
4376 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
4377 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
4378 | /* (D)ADDIU $sp, imm */ | |
4379 | && offset < 0) | |
4380 | stop = 1; | |
4381 | break; | |
4382 | ||
4383 | case 0x10: /* POOL32I: bits 010000 */ | |
4384 | if (b5s5_op (insn) == 0xd | |
4385 | /* LUI: bits 010000 001101 */ | |
4386 | && b0s5_reg (insn >> 16) == 28) | |
4387 | /* LUI $gp, imm */ | |
4388 | stop = 1; | |
4389 | break; | |
4390 | ||
4391 | case 0x13: /* POOL16D: bits 010011 */ | |
4392 | if ((insn & 0x1) == 0x1) | |
4393 | /* ADDIUSP: bits 010011 1 */ | |
4394 | { | |
4395 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
4396 | if (offset < 0) | |
4397 | /* ADDIUSP -imm */ | |
4398 | stop = 1; | |
4399 | } | |
4400 | else | |
4401 | /* ADDIUS5: bits 010011 0 */ | |
4402 | { | |
4403 | dreg = b5s5_reg (insn); | |
4404 | offset = (b1s4_imm (insn) ^ 8) - 8; | |
4405 | if (dreg == MIPS_SP_REGNUM && offset < 0) | |
4406 | /* ADDIUS5 $sp, -imm */ | |
4407 | stop = 1; | |
4408 | } | |
4409 | break; | |
4410 | } | |
4411 | if (stop) | |
4412 | break; | |
4413 | } | |
e17a4113 | 4414 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 4415 | { |
4c7d22cb | 4416 | /* Skip return and its delay slot. */ |
95ac2dcf | 4417 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
4418 | break; |
4419 | } | |
4420 | ||
4421 | return start_pc; | |
c906108c SS |
4422 | } |
4423 | ||
6c0d6680 DJ |
4424 | struct mips_objfile_private |
4425 | { | |
4426 | bfd_size_type size; | |
4427 | char *contents; | |
4428 | }; | |
4429 | ||
f09ded24 AC |
4430 | /* According to the current ABI, should the type be passed in a |
4431 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 4432 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 4433 | FP registers and, consequently this returns false - forces FP |
025bb325 | 4434 | arguments into integer registers. */ |
f09ded24 AC |
4435 | |
4436 | static int | |
74ed0bb4 MD |
4437 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
4438 | struct type *arg_type) | |
f09ded24 AC |
4439 | { |
4440 | return ((typecode == TYPE_CODE_FLT | |
345bd07c | 4441 | || (mips_eabi (gdbarch) |
6d82d43b AC |
4442 | && (typecode == TYPE_CODE_STRUCT |
4443 | || typecode == TYPE_CODE_UNION) | |
1f704f76 | 4444 | && arg_type->num_fields () == 1 |
940da03e | 4445 | && check_typedef (arg_type->field (0).type ())->code () |
b2d6f210 | 4446 | == TYPE_CODE_FLT)) |
345bd07c | 4447 | && mips_get_fpu_type (gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
4448 | } |
4449 | ||
49e790b0 | 4450 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 4451 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
4452 | |
4453 | static int | |
4454 | mips_type_needs_double_align (struct type *type) | |
4455 | { | |
78134374 | 4456 | enum type_code typecode = type->code (); |
361d1df0 | 4457 | |
df86565b | 4458 | if (typecode == TYPE_CODE_FLT && type->length () == 8) |
49e790b0 DJ |
4459 | return 1; |
4460 | else if (typecode == TYPE_CODE_STRUCT) | |
4461 | { | |
1f704f76 | 4462 | if (type->num_fields () < 1) |
49e790b0 | 4463 | return 0; |
940da03e | 4464 | return mips_type_needs_double_align (type->field (0).type ()); |
49e790b0 DJ |
4465 | } |
4466 | else if (typecode == TYPE_CODE_UNION) | |
4467 | { | |
361d1df0 | 4468 | int i, n; |
49e790b0 | 4469 | |
1f704f76 | 4470 | n = type->num_fields (); |
49e790b0 | 4471 | for (i = 0; i < n; i++) |
940da03e | 4472 | if (mips_type_needs_double_align (type->field (i).type ())) |
49e790b0 DJ |
4473 | return 1; |
4474 | return 0; | |
4475 | } | |
4476 | return 0; | |
4477 | } | |
4478 | ||
dc604539 AC |
4479 | /* Adjust the address downward (direction of stack growth) so that it |
4480 | is correctly aligned for a new stack frame. */ | |
4481 | static CORE_ADDR | |
4482 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
4483 | { | |
5b03f266 | 4484 | return align_down (addr, 16); |
dc604539 AC |
4485 | } |
4486 | ||
8ae38c14 | 4487 | /* Implement the "push_dummy_code" gdbarch method. */ |
2c76a0c7 JB |
4488 | |
4489 | static CORE_ADDR | |
4490 | mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
4491 | CORE_ADDR funaddr, struct value **args, | |
4492 | int nargs, struct type *value_type, | |
4493 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
4494 | struct regcache *regcache) | |
4495 | { | |
2c76a0c7 | 4496 | static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; |
2e81047f MR |
4497 | CORE_ADDR nop_addr; |
4498 | CORE_ADDR bp_slot; | |
2c76a0c7 JB |
4499 | |
4500 | /* Reserve enough room on the stack for our breakpoint instruction. */ | |
2e81047f MR |
4501 | bp_slot = sp - sizeof (nop_insn); |
4502 | ||
4503 | /* Return to microMIPS mode if calling microMIPS code to avoid | |
4504 | triggering an address error exception on processors that only | |
4505 | support microMIPS execution. */ | |
4506 | *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) | |
4507 | ? make_compact_addr (bp_slot) : bp_slot); | |
2c76a0c7 JB |
4508 | |
4509 | /* The breakpoint layer automatically adjusts the address of | |
4510 | breakpoints inserted in a branch delay slot. With enough | |
4511 | bad luck, the 4 bytes located just before our breakpoint | |
4512 | instruction could look like a branch instruction, and thus | |
4513 | trigger the adjustement, and break the function call entirely. | |
4514 | So, we reserve those 4 bytes and write a nop instruction | |
4515 | to prevent that from happening. */ | |
2e81047f | 4516 | nop_addr = bp_slot - sizeof (nop_insn); |
2c76a0c7 JB |
4517 | write_memory (nop_addr, nop_insn, sizeof (nop_insn)); |
4518 | sp = mips_frame_align (gdbarch, nop_addr); | |
4519 | ||
4520 | /* Inferior resumes at the function entry point. */ | |
4521 | *real_pc = funaddr; | |
4522 | ||
4523 | return sp; | |
4524 | } | |
4525 | ||
f7ab6ec6 | 4526 | static CORE_ADDR |
7d9b040b | 4527 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4528 | struct regcache *regcache, CORE_ADDR bp_addr, |
4529 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
4530 | function_call_return_method return_method, |
4531 | CORE_ADDR struct_addr) | |
c906108c SS |
4532 | { |
4533 | int argreg; | |
4534 | int float_argreg; | |
4535 | int argnum; | |
b926417a | 4536 | int arg_space = 0; |
c906108c | 4537 | int stack_offset = 0; |
e17a4113 | 4538 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4539 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
b3464d03 | 4540 | int abi_regsize = mips_abi_regsize (gdbarch); |
c906108c | 4541 | |
25ab4790 AC |
4542 | /* For shared libraries, "t9" needs to point at the function |
4543 | address. */ | |
4c7d22cb | 4544 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4545 | |
4546 | /* Set the return address register to point to the entry point of | |
4547 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4548 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4549 | |
c906108c | 4550 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
4551 | are properly aligned. The stack has to be at least 64-bit |
4552 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4553 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4554 | aligned, so we round to this widest known alignment. */ | |
4555 | ||
5b03f266 AC |
4556 | sp = align_down (sp, 16); |
4557 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 4558 | |
46e0f506 | 4559 | /* Now make space on the stack for the args. We allocate more |
c906108c | 4560 | than necessary for EABI, because the first few arguments are |
46e0f506 | 4561 | passed in registers, but that's OK. */ |
c906108c | 4562 | for (argnum = 0; argnum < nargs; argnum++) |
d0c97917 | 4563 | arg_space += align_up (args[argnum]->type ()->length (), |
df86565b | 4564 | abi_regsize); |
b926417a | 4565 | sp -= align_up (arg_space, 16); |
c906108c | 4566 | |
9ace0497 | 4567 | if (mips_debug) |
6cb06a8c TT |
4568 | gdb_printf (gdb_stdlog, |
4569 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", | |
4570 | paddress (gdbarch, sp), | |
4571 | (long) align_up (arg_space, 16)); | |
9ace0497 | 4572 | |
c906108c | 4573 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 4574 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4575 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 4576 | |
46e0f506 | 4577 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cf84fa6b | 4578 | if (return_method == return_method_struct) |
9ace0497 AC |
4579 | { |
4580 | if (mips_debug) | |
6cb06a8c TT |
4581 | gdb_printf (gdb_stdlog, |
4582 | "mips_eabi_push_dummy_call: " | |
4583 | "struct_return reg=%d %s\n", | |
4584 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 4585 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 4586 | } |
c906108c SS |
4587 | |
4588 | /* Now load as many as possible of the first arguments into | |
4589 | registers, and push the rest onto the stack. Loop thru args | |
4590 | from first to last. */ | |
4591 | for (argnum = 0; argnum < nargs; argnum++) | |
4592 | { | |
47a35522 | 4593 | const gdb_byte *val; |
b3464d03 PA |
4594 | /* This holds the address of structures that are passed by |
4595 | reference. */ | |
4596 | gdb_byte ref_valbuf[MAX_MIPS_ABI_REGSIZE]; | |
ea7c478f | 4597 | struct value *arg = args[argnum]; |
d0c97917 | 4598 | struct type *arg_type = check_typedef (arg->type ()); |
df86565b | 4599 | int len = arg_type->length (); |
78134374 | 4600 | enum type_code typecode = arg_type->code (); |
c906108c | 4601 | |
9ace0497 | 4602 | if (mips_debug) |
6cb06a8c TT |
4603 | gdb_printf (gdb_stdlog, |
4604 | "mips_eabi_push_dummy_call: %d len=%d type=%d", | |
4605 | argnum + 1, len, (int) typecode); | |
9ace0497 | 4606 | |
c906108c | 4607 | /* The EABI passes structures that do not fit in a register by |
dda83cd7 | 4608 | reference. */ |
b3464d03 | 4609 | if (len > abi_regsize |
9ace0497 | 4610 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 4611 | { |
b3464d03 PA |
4612 | gdb_assert (abi_regsize <= ARRAY_SIZE (ref_valbuf)); |
4613 | store_unsigned_integer (ref_valbuf, abi_regsize, byte_order, | |
9feb2d07 | 4614 | arg->address ()); |
c906108c | 4615 | typecode = TYPE_CODE_PTR; |
b3464d03 PA |
4616 | len = abi_regsize; |
4617 | val = ref_valbuf; | |
9ace0497 | 4618 | if (mips_debug) |
6cb06a8c | 4619 | gdb_printf (gdb_stdlog, " push"); |
c906108c SS |
4620 | } |
4621 | else | |
efaf1ae0 | 4622 | val = arg->contents ().data (); |
c906108c SS |
4623 | |
4624 | /* 32-bit ABIs always start floating point arguments in an | |
dda83cd7 SM |
4625 | even-numbered floating point register. Round the FP register |
4626 | up before the check to see if there are any FP registers | |
4627 | left. Non MIPS_EABI targets also pass the FP in the integer | |
4628 | registers so also round up normal registers. */ | |
b3464d03 | 4629 | if (abi_regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
4630 | { |
4631 | if ((float_argreg & 1)) | |
4632 | float_argreg++; | |
4633 | } | |
c906108c SS |
4634 | |
4635 | /* Floating point arguments passed in registers have to be | |
dda83cd7 SM |
4636 | treated specially. On 32-bit architectures, doubles |
4637 | are passed in register pairs; the even register gets | |
4638 | the low word, and the odd register gets the high word. | |
4639 | On non-EABI processors, the first two floating point arguments are | |
4640 | also copied to general registers, because MIPS16 functions | |
4641 | don't use float registers for arguments. This duplication of | |
4642 | arguments in general registers can't hurt non-MIPS16 functions | |
4643 | because those registers are normally skipped. */ | |
1012bd0e | 4644 | /* MIPS_EABI squeezes a struct that contains a single floating |
dda83cd7 SM |
4645 | point value into an FP register instead of pushing it onto the |
4646 | stack. */ | |
74ed0bb4 | 4647 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
345bd07c | 4648 | && float_argreg <= mips_last_fp_arg_regnum (gdbarch)) |
c906108c | 4649 | { |
6da397e0 KB |
4650 | /* EABI32 will pass doubles in consecutive registers, even on |
4651 | 64-bit cores. At one time, we used to check the size of | |
4652 | `float_argreg' to determine whether or not to pass doubles | |
4653 | in consecutive registers, but this is not sufficient for | |
4654 | making the ABI determination. */ | |
4655 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 4656 | { |
72a155b4 | 4657 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 4658 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 4659 | long regval; |
c906108c SS |
4660 | |
4661 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
4662 | regval = extract_signed_integer (val + low_offset, |
4663 | 4, byte_order); | |
9ace0497 | 4664 | if (mips_debug) |
6cb06a8c TT |
4665 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
4666 | float_argreg, phex (regval, 4)); | |
a8852dc5 | 4667 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4668 | |
4669 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
4670 | regval = extract_signed_integer (val + 4 - low_offset, |
4671 | 4, byte_order); | |
9ace0497 | 4672 | if (mips_debug) |
6cb06a8c TT |
4673 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
4674 | float_argreg, phex (regval, 4)); | |
a8852dc5 | 4675 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4676 | } |
4677 | else | |
4678 | { | |
4679 | /* This is a floating point value that fits entirely | |
dda83cd7 | 4680 | in a single register. */ |
53a5351d | 4681 | /* On 32 bit ABI's the float_argreg is further adjusted |
dda83cd7 | 4682 | above to ensure that it is even register aligned. */ |
a8852dc5 | 4683 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 4684 | if (mips_debug) |
6cb06a8c TT |
4685 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
4686 | float_argreg, phex (regval, len)); | |
a8852dc5 | 4687 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4688 | } |
4689 | } | |
4690 | else | |
4691 | { | |
4692 | /* Copy the argument to general registers or the stack in | |
4693 | register-sized pieces. Large arguments are split between | |
4694 | registers and stack. */ | |
b3464d03 | 4695 | /* Note: structs whose size is not a multiple of abi_regsize |
1a69e1e4 | 4696 | are treated specially: Irix cc passes |
d5ac5a39 AC |
4697 | them in registers where gcc sometimes puts them on the |
4698 | stack. For maximum compatibility, we will put them in | |
4699 | both places. */ | |
b3464d03 | 4700 | int odd_sized_struct = (len > abi_regsize && len % abi_regsize != 0); |
46e0f506 | 4701 | |
f09ded24 | 4702 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4703 | register are only written to memory. */ |
c906108c SS |
4704 | while (len > 0) |
4705 | { | |
ebafbe83 | 4706 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 4707 | int stack_used_p = 0; |
b3464d03 | 4708 | int partial_len = (len < abi_regsize ? len : abi_regsize); |
c906108c | 4709 | |
acdb74a0 | 4710 | if (mips_debug) |
6cb06a8c TT |
4711 | gdb_printf (gdb_stdlog, " -- partial=%d", |
4712 | partial_len); | |
acdb74a0 | 4713 | |
566f0f7a | 4714 | /* Write this portion of the argument to the stack. */ |
345bd07c | 4715 | if (argreg > mips_last_arg_regnum (gdbarch) |
f09ded24 | 4716 | || odd_sized_struct |
74ed0bb4 | 4717 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 4718 | { |
c906108c | 4719 | /* Should shorter than int integer values be |
025bb325 | 4720 | promoted to int before being stored? */ |
c906108c | 4721 | int longword_offset = 0; |
9ace0497 | 4722 | CORE_ADDR addr; |
566f0f7a | 4723 | stack_used_p = 1; |
72a155b4 | 4724 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 4725 | { |
b3464d03 | 4726 | if (abi_regsize == 8 |
480d3dd2 AC |
4727 | && (typecode == TYPE_CODE_INT |
4728 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4729 | || typecode == TYPE_CODE_FLT) && len <= 4) |
b3464d03 | 4730 | longword_offset = abi_regsize - len; |
480d3dd2 AC |
4731 | else if ((typecode == TYPE_CODE_STRUCT |
4732 | || typecode == TYPE_CODE_UNION) | |
df86565b | 4733 | && arg_type->length () < abi_regsize) |
b3464d03 | 4734 | longword_offset = abi_regsize - len; |
7a292a7a | 4735 | } |
c5aa993b | 4736 | |
9ace0497 AC |
4737 | if (mips_debug) |
4738 | { | |
6cb06a8c TT |
4739 | gdb_printf (gdb_stdlog, " - stack_offset=%s", |
4740 | paddress (gdbarch, stack_offset)); | |
4741 | gdb_printf (gdb_stdlog, " longword_offset=%s", | |
4742 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 4743 | } |
361d1df0 | 4744 | |
9ace0497 AC |
4745 | addr = sp + stack_offset + longword_offset; |
4746 | ||
4747 | if (mips_debug) | |
4748 | { | |
4749 | int i; | |
6cb06a8c TT |
4750 | gdb_printf (gdb_stdlog, " @%s ", |
4751 | paddress (gdbarch, addr)); | |
9ace0497 AC |
4752 | for (i = 0; i < partial_len; i++) |
4753 | { | |
6cb06a8c TT |
4754 | gdb_printf (gdb_stdlog, "%02x", |
4755 | val[i] & 0xff); | |
9ace0497 AC |
4756 | } |
4757 | } | |
4758 | write_memory (addr, val, partial_len); | |
c906108c SS |
4759 | } |
4760 | ||
f09ded24 | 4761 | /* Note!!! This is NOT an else clause. Odd sized |
dda83cd7 SM |
4762 | structs may go thru BOTH paths. Floating point |
4763 | arguments will not. */ | |
566f0f7a | 4764 | /* Write this portion of the argument to a general |
dda83cd7 | 4765 | purpose register. */ |
345bd07c | 4766 | if (argreg <= mips_last_arg_regnum (gdbarch) |
74ed0bb4 | 4767 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 4768 | { |
6d82d43b | 4769 | LONGEST regval = |
a8852dc5 | 4770 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 4771 | |
9ace0497 | 4772 | if (mips_debug) |
6cb06a8c TT |
4773 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
4774 | argreg, | |
4775 | phex (regval, abi_regsize)); | |
a8852dc5 | 4776 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 4777 | argreg++; |
c906108c | 4778 | } |
c5aa993b | 4779 | |
c906108c SS |
4780 | len -= partial_len; |
4781 | val += partial_len; | |
4782 | ||
b021a221 | 4783 | /* Compute the offset into the stack at which we will |
dda83cd7 | 4784 | copy the next parameter. |
566f0f7a | 4785 | |
dda83cd7 SM |
4786 | In the new EABI (and the NABI32), the stack_offset |
4787 | only needs to be adjusted when it has been used. */ | |
c906108c | 4788 | |
46e0f506 | 4789 | if (stack_used_p) |
b3464d03 | 4790 | stack_offset += align_up (partial_len, abi_regsize); |
c906108c SS |
4791 | } |
4792 | } | |
9ace0497 | 4793 | if (mips_debug) |
6cb06a8c | 4794 | gdb_printf (gdb_stdlog, "\n"); |
c906108c SS |
4795 | } |
4796 | ||
f10683bb | 4797 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4798 | |
0f71a2f6 JM |
4799 | /* Return adjusted stack pointer. */ |
4800 | return sp; | |
4801 | } | |
4802 | ||
a1f5b845 | 4803 | /* Determine the return value convention being used. */ |
6d82d43b | 4804 | |
9c8fdbfa | 4805 | static enum return_value_convention |
6a3a010b | 4806 | mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 4807 | struct type *type, struct regcache *regcache, |
47a35522 | 4808 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4809 | { |
08106042 | 4810 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
609ba780 JM |
4811 | int fp_return_type = 0; |
4812 | int offset, regnum, xfer; | |
4813 | ||
df86565b | 4814 | if (type->length () > 2 * mips_abi_regsize (gdbarch)) |
9c8fdbfa | 4815 | return RETURN_VALUE_STRUCT_CONVENTION; |
609ba780 JM |
4816 | |
4817 | /* Floating point type? */ | |
4818 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4819 | { | |
78134374 | 4820 | if (type->code () == TYPE_CODE_FLT) |
609ba780 JM |
4821 | fp_return_type = 1; |
4822 | /* Structs with a single field of float type | |
4823 | are returned in a floating point register. */ | |
78134374 SM |
4824 | if ((type->code () == TYPE_CODE_STRUCT |
4825 | || type->code () == TYPE_CODE_UNION) | |
1f704f76 | 4826 | && type->num_fields () == 1) |
609ba780 | 4827 | { |
940da03e | 4828 | struct type *fieldtype = type->field (0).type (); |
609ba780 | 4829 | |
78134374 | 4830 | if (check_typedef (fieldtype)->code () == TYPE_CODE_FLT) |
609ba780 JM |
4831 | fp_return_type = 1; |
4832 | } | |
4833 | } | |
4834 | ||
4835 | if (fp_return_type) | |
4836 | { | |
4837 | /* A floating-point value belongs in the least significant part | |
4838 | of FP0/FP1. */ | |
4839 | if (mips_debug) | |
6cb06a8c | 4840 | gdb_printf (gdb_stderr, "Return float in $fp0\n"); |
609ba780 JM |
4841 | regnum = mips_regnum (gdbarch)->fp0; |
4842 | } | |
4843 | else | |
4844 | { | |
4845 | /* An integer value goes in V0/V1. */ | |
4846 | if (mips_debug) | |
6cb06a8c | 4847 | gdb_printf (gdb_stderr, "Return scalar in $v0\n"); |
609ba780 JM |
4848 | regnum = MIPS_V0_REGNUM; |
4849 | } | |
4850 | for (offset = 0; | |
df86565b | 4851 | offset < type->length (); |
609ba780 JM |
4852 | offset += mips_abi_regsize (gdbarch), regnum++) |
4853 | { | |
4854 | xfer = mips_abi_regsize (gdbarch); | |
df86565b SM |
4855 | if (offset + xfer > type->length ()) |
4856 | xfer = type->length () - offset; | |
609ba780 JM |
4857 | mips_xfer_register (gdbarch, regcache, |
4858 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
4859 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
4860 | offset); | |
4861 | } | |
4862 | ||
9c8fdbfa | 4863 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
4864 | } |
4865 | ||
6d82d43b AC |
4866 | |
4867 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 4868 | |
8d26208a DJ |
4869 | /* Search for a naturally aligned double at OFFSET inside a struct |
4870 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
4871 | registers. */ | |
4872 | ||
4873 | static int | |
74ed0bb4 MD |
4874 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
4875 | int offset) | |
8d26208a DJ |
4876 | { |
4877 | int i; | |
4878 | ||
78134374 | 4879 | if (arg_type->code () != TYPE_CODE_STRUCT) |
8d26208a DJ |
4880 | return 0; |
4881 | ||
345bd07c | 4882 | if (mips_get_fpu_type (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
4883 | return 0; |
4884 | ||
df86565b | 4885 | if (arg_type->length () < offset + MIPS64_REGSIZE) |
8d26208a DJ |
4886 | return 0; |
4887 | ||
1f704f76 | 4888 | for (i = 0; i < arg_type->num_fields (); i++) |
8d26208a DJ |
4889 | { |
4890 | int pos; | |
4891 | struct type *field_type; | |
4892 | ||
4893 | /* We're only looking at normal fields. */ | |
c819a338 | 4894 | if (arg_type->field (i).is_static () |
b610c045 | 4895 | || (arg_type->field (i).loc_bitpos () % 8) != 0) |
8d26208a DJ |
4896 | continue; |
4897 | ||
4898 | /* If we have gone past the offset, there is no double to pass. */ | |
b610c045 | 4899 | pos = arg_type->field (i).loc_bitpos () / 8; |
8d26208a DJ |
4900 | if (pos > offset) |
4901 | return 0; | |
4902 | ||
940da03e | 4903 | field_type = check_typedef (arg_type->field (i).type ()); |
8d26208a DJ |
4904 | |
4905 | /* If this field is entirely before the requested offset, go | |
4906 | on to the next one. */ | |
df86565b | 4907 | if (pos + field_type->length () <= offset) |
8d26208a DJ |
4908 | continue; |
4909 | ||
4910 | /* If this is our special aligned double, we can stop. */ | |
78134374 | 4911 | if (field_type->code () == TYPE_CODE_FLT |
df86565b | 4912 | && field_type->length () == MIPS64_REGSIZE) |
8d26208a DJ |
4913 | return 1; |
4914 | ||
4915 | /* This field starts at or before the requested offset, and | |
4916 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 4917 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
4918 | } |
4919 | ||
4920 | return 0; | |
4921 | } | |
4922 | ||
f7ab6ec6 | 4923 | static CORE_ADDR |
7d9b040b | 4924 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4925 | struct regcache *regcache, CORE_ADDR bp_addr, |
4926 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
4927 | function_call_return_method return_method, |
4928 | CORE_ADDR struct_addr) | |
cb3d25d1 MS |
4929 | { |
4930 | int argreg; | |
4931 | int float_argreg; | |
4932 | int argnum; | |
b926417a | 4933 | int arg_space = 0; |
cb3d25d1 | 4934 | int stack_offset = 0; |
e17a4113 | 4935 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4936 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 4937 | |
25ab4790 AC |
4938 | /* For shared libraries, "t9" needs to point at the function |
4939 | address. */ | |
4c7d22cb | 4940 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4941 | |
4942 | /* Set the return address register to point to the entry point of | |
4943 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4944 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4945 | |
cb3d25d1 MS |
4946 | /* First ensure that the stack and structure return address (if any) |
4947 | are properly aligned. The stack has to be at least 64-bit | |
4948 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4949 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4950 | aligned, so we round to this widest known alignment. */ | |
4951 | ||
5b03f266 AC |
4952 | sp = align_down (sp, 16); |
4953 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
4954 | |
4955 | /* Now make space on the stack for the args. */ | |
4956 | for (argnum = 0; argnum < nargs; argnum++) | |
d0c97917 | 4957 | arg_space += align_up (args[argnum]->type ()->length (), |
df86565b | 4958 | MIPS64_REGSIZE); |
b926417a | 4959 | sp -= align_up (arg_space, 16); |
cb3d25d1 MS |
4960 | |
4961 | if (mips_debug) | |
6cb06a8c TT |
4962 | gdb_printf (gdb_stdlog, |
4963 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", | |
4964 | paddress (gdbarch, sp), | |
4965 | (long) align_up (arg_space, 16)); | |
cb3d25d1 MS |
4966 | |
4967 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4968 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4969 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 4970 | |
46e0f506 | 4971 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cf84fa6b | 4972 | if (return_method == return_method_struct) |
cb3d25d1 MS |
4973 | { |
4974 | if (mips_debug) | |
6cb06a8c TT |
4975 | gdb_printf (gdb_stdlog, |
4976 | "mips_n32n64_push_dummy_call: " | |
4977 | "struct_return reg=%d %s\n", | |
4978 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 4979 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
4980 | } |
4981 | ||
4982 | /* Now load as many as possible of the first arguments into | |
4983 | registers, and push the rest onto the stack. Loop thru args | |
4984 | from first to last. */ | |
4985 | for (argnum = 0; argnum < nargs; argnum++) | |
4986 | { | |
47a35522 | 4987 | const gdb_byte *val; |
cb3d25d1 | 4988 | struct value *arg = args[argnum]; |
d0c97917 | 4989 | struct type *arg_type = check_typedef (arg->type ()); |
df86565b | 4990 | int len = arg_type->length (); |
78134374 | 4991 | enum type_code typecode = arg_type->code (); |
cb3d25d1 MS |
4992 | |
4993 | if (mips_debug) | |
6cb06a8c TT |
4994 | gdb_printf (gdb_stdlog, |
4995 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", | |
4996 | argnum + 1, len, (int) typecode); | |
cb3d25d1 | 4997 | |
efaf1ae0 | 4998 | val = arg->contents ().data (); |
cb3d25d1 | 4999 | |
5b68030f JM |
5000 | /* A 128-bit long double value requires an even-odd pair of |
5001 | floating-point registers. */ | |
5002 | if (len == 16 | |
5003 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
5004 | && (float_argreg & 1)) | |
5005 | { | |
5006 | float_argreg++; | |
5007 | argreg++; | |
5008 | } | |
5009 | ||
74ed0bb4 | 5010 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
345bd07c | 5011 | && argreg <= mips_last_arg_regnum (gdbarch)) |
cb3d25d1 MS |
5012 | { |
5013 | /* This is a floating point value that fits entirely | |
5b68030f JM |
5014 | in a single register or a pair of registers. */ |
5015 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 5016 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 | 5017 | if (mips_debug) |
6cb06a8c TT |
5018 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
5019 | float_argreg, phex (regval, reglen)); | |
8d26208a | 5020 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
5021 | |
5022 | if (mips_debug) | |
6cb06a8c TT |
5023 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
5024 | argreg, phex (regval, reglen)); | |
9c9acae0 | 5025 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
5026 | float_argreg++; |
5027 | argreg++; | |
5b68030f JM |
5028 | if (len == 16) |
5029 | { | |
e17a4113 UW |
5030 | regval = extract_unsigned_integer (val + reglen, |
5031 | reglen, byte_order); | |
5b68030f | 5032 | if (mips_debug) |
6cb06a8c TT |
5033 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
5034 | float_argreg, phex (regval, reglen)); | |
5b68030f JM |
5035 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
5036 | ||
5037 | if (mips_debug) | |
6cb06a8c TT |
5038 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
5039 | argreg, phex (regval, reglen)); | |
5b68030f JM |
5040 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
5041 | float_argreg++; | |
5042 | argreg++; | |
5043 | } | |
cb3d25d1 MS |
5044 | } |
5045 | else | |
5046 | { | |
5047 | /* Copy the argument to general registers or the stack in | |
5048 | register-sized pieces. Large arguments are split between | |
5049 | registers and stack. */ | |
ab2e1992 MR |
5050 | /* For N32/N64, structs, unions, or other composite types are |
5051 | treated as a sequence of doublewords, and are passed in integer | |
5052 | or floating point registers as though they were simple scalar | |
5053 | parameters to the extent that they fit, with any excess on the | |
5054 | stack packed according to the normal memory layout of the | |
5055 | object. | |
5056 | The caller does not reserve space for the register arguments; | |
5057 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 5058 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 5059 | register are only written to memory. */ |
cb3d25d1 MS |
5060 | while (len > 0) |
5061 | { | |
ad018eee | 5062 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 5063 | int stack_used_p = 0; |
1a69e1e4 | 5064 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
5065 | |
5066 | if (mips_debug) | |
6cb06a8c TT |
5067 | gdb_printf (gdb_stdlog, " -- partial=%d", |
5068 | partial_len); | |
cb3d25d1 | 5069 | |
74ed0bb4 | 5070 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
345bd07c | 5071 | gdb_assert (argreg > mips_last_arg_regnum (gdbarch)); |
8d26208a | 5072 | |
cb3d25d1 | 5073 | /* Write this portion of the argument to the stack. */ |
345bd07c | 5074 | if (argreg > mips_last_arg_regnum (gdbarch)) |
cb3d25d1 MS |
5075 | { |
5076 | /* Should shorter than int integer values be | |
025bb325 | 5077 | promoted to int before being stored? */ |
cb3d25d1 MS |
5078 | int longword_offset = 0; |
5079 | CORE_ADDR addr; | |
5080 | stack_used_p = 1; | |
72a155b4 | 5081 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 5082 | { |
1a69e1e4 | 5083 | if ((typecode == TYPE_CODE_INT |
5b68030f | 5084 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
5085 | && len <= 4) |
5086 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
5087 | } |
5088 | ||
5089 | if (mips_debug) | |
5090 | { | |
6cb06a8c TT |
5091 | gdb_printf (gdb_stdlog, " - stack_offset=%s", |
5092 | paddress (gdbarch, stack_offset)); | |
5093 | gdb_printf (gdb_stdlog, " longword_offset=%s", | |
5094 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
5095 | } |
5096 | ||
5097 | addr = sp + stack_offset + longword_offset; | |
5098 | ||
5099 | if (mips_debug) | |
5100 | { | |
5101 | int i; | |
6cb06a8c TT |
5102 | gdb_printf (gdb_stdlog, " @%s ", |
5103 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
5104 | for (i = 0; i < partial_len; i++) |
5105 | { | |
6cb06a8c TT |
5106 | gdb_printf (gdb_stdlog, "%02x", |
5107 | val[i] & 0xff); | |
cb3d25d1 MS |
5108 | } |
5109 | } | |
5110 | write_memory (addr, val, partial_len); | |
5111 | } | |
5112 | ||
5113 | /* Note!!! This is NOT an else clause. Odd sized | |
dda83cd7 | 5114 | structs may go thru BOTH paths. */ |
cb3d25d1 | 5115 | /* Write this portion of the argument to a general |
dda83cd7 | 5116 | purpose register. */ |
345bd07c | 5117 | if (argreg <= mips_last_arg_regnum (gdbarch)) |
cb3d25d1 | 5118 | { |
5863b5d5 MR |
5119 | LONGEST regval; |
5120 | ||
5121 | /* Sign extend pointers, 32-bit integers and signed | |
5122 | 16-bit and 8-bit integers; everything else is taken | |
5123 | as is. */ | |
5124 | ||
5125 | if ((partial_len == 4 | |
5126 | && (typecode == TYPE_CODE_PTR | |
5127 | || typecode == TYPE_CODE_INT)) | |
5128 | || (partial_len < 4 | |
5129 | && typecode == TYPE_CODE_INT | |
c6d940a9 | 5130 | && !arg_type->is_unsigned ())) |
e17a4113 UW |
5131 | regval = extract_signed_integer (val, partial_len, |
5132 | byte_order); | |
5863b5d5 | 5133 | else |
e17a4113 UW |
5134 | regval = extract_unsigned_integer (val, partial_len, |
5135 | byte_order); | |
cb3d25d1 MS |
5136 | |
5137 | /* A non-floating-point argument being passed in a | |
5138 | general register. If a struct or union, and if | |
5139 | the remaining length is smaller than the register | |
5140 | size, we have to adjust the register value on | |
5141 | big endian targets. | |
5142 | ||
5143 | It does not seem to be necessary to do the | |
1a69e1e4 | 5144 | same for integral types. */ |
cb3d25d1 | 5145 | |
72a155b4 | 5146 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5147 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
5148 | && (typecode == TYPE_CODE_STRUCT |
5149 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5150 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 5151 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
5152 | |
5153 | if (mips_debug) | |
6cb06a8c TT |
5154 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
5155 | argreg, | |
5156 | phex (regval, MIPS64_REGSIZE)); | |
9c9acae0 | 5157 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 5158 | |
74ed0bb4 | 5159 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
df86565b | 5160 | arg_type->length () - len)) |
8d26208a DJ |
5161 | { |
5162 | if (mips_debug) | |
6cb06a8c TT |
5163 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
5164 | float_argreg, | |
5165 | phex (regval, MIPS64_REGSIZE)); | |
8d26208a DJ |
5166 | regcache_cooked_write_unsigned (regcache, float_argreg, |
5167 | regval); | |
5168 | } | |
5169 | ||
5170 | float_argreg++; | |
cb3d25d1 MS |
5171 | argreg++; |
5172 | } | |
5173 | ||
5174 | len -= partial_len; | |
5175 | val += partial_len; | |
5176 | ||
b021a221 | 5177 | /* Compute the offset into the stack at which we will |
dda83cd7 | 5178 | copy the next parameter. |
cb3d25d1 | 5179 | |
dda83cd7 SM |
5180 | In N32 (N64?), the stack_offset only needs to be |
5181 | adjusted when it has been used. */ | |
cb3d25d1 MS |
5182 | |
5183 | if (stack_used_p) | |
1a69e1e4 | 5184 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
5185 | } |
5186 | } | |
5187 | if (mips_debug) | |
6cb06a8c | 5188 | gdb_printf (gdb_stdlog, "\n"); |
cb3d25d1 MS |
5189 | } |
5190 | ||
f10683bb | 5191 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5192 | |
cb3d25d1 MS |
5193 | /* Return adjusted stack pointer. */ |
5194 | return sp; | |
5195 | } | |
5196 | ||
6d82d43b | 5197 | static enum return_value_convention |
6a3a010b | 5198 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, |
6d82d43b | 5199 | struct type *type, struct regcache *regcache, |
47a35522 | 5200 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 5201 | { |
08106042 | 5202 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
b18bb924 MR |
5203 | |
5204 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
5205 | ||
5206 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
5207 | if needed), as appropriate for the type. Composite results (struct, | |
5208 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
5209 | following rules: | |
5210 | ||
5211 | * A struct with only one or two floating point fields is returned in $f0 | |
5212 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
5213 | case. | |
5214 | ||
f08877ba | 5215 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
5216 | $2 (first 64 bits) and $3 (remainder, if necessary). |
5217 | ||
5218 | * Larger composite results are handled by converting the function to a | |
5219 | procedure with an implicit first parameter, which is a pointer to an area | |
5220 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
5221 | that all composite results be handled by conversion to implicit first | |
5222 | parameters. The MIPS/SGI Fortran implementation has always made a | |
5223 | specific exception to return COMPLEX results in the floating point | |
089169c0 YT |
5224 | registers.] |
5225 | ||
5226 | From MIPSpro Assembly Language Programmer's Guide, Document Number: | |
5227 | 007-2418-004 | |
5228 | ||
287de656 | 5229 | Software |
089169c0 YT |
5230 | Register Name(from |
5231 | Name fgregdef.h) Use and Linkage | |
5232 | ----------------------------------------------------------------- | |
5233 | $f0, $f2 fv0, fv1 Hold results of floating-point type function | |
287de656 SM |
5234 | ($f0) and complex type function ($f0 has the |
5235 | real part, $f2 has the imaginary part.) */ | |
b18bb924 | 5236 | |
df86565b | 5237 | if (type->length () > 2 * MIPS64_REGSIZE) |
6d82d43b | 5238 | return RETURN_VALUE_STRUCT_CONVENTION; |
089169c0 | 5239 | else if ((type->code () == TYPE_CODE_COMPLEX |
df86565b | 5240 | || (type->code () == TYPE_CODE_FLT && type->length () == 16)) |
d05f6826 DJ |
5241 | && tdep->mips_fpu_type != MIPS_FPU_NONE) |
5242 | { | |
089169c0 YT |
5243 | /* A complex value of up to 128 bits in width as well as a 128-bit |
5244 | floating-point value goes in both $f0 and $f2. A single complex | |
5245 | value is held in the lower halves only of the respective registers. | |
5246 | The two registers are used in the same as memory order, so the | |
5247 | bytes with the lower memory address are in $f0. */ | |
d05f6826 | 5248 | if (mips_debug) |
6cb06a8c | 5249 | gdb_printf (gdb_stderr, "Return float in $f0 and $f2\n"); |
ba32f989 | 5250 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5251 | (gdbarch_num_regs (gdbarch) |
5252 | + mips_regnum (gdbarch)->fp0), | |
df86565b | 5253 | type->length () / 2, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5254 | readbuf, writebuf, 0); |
ba32f989 | 5255 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5256 | (gdbarch_num_regs (gdbarch) |
5257 | + mips_regnum (gdbarch)->fp0 + 2), | |
df86565b SM |
5258 | type->length () / 2, gdbarch_byte_order (gdbarch), |
5259 | readbuf ? readbuf + type->length () / 2 : readbuf, | |
089169c0 | 5260 | (writebuf |
df86565b | 5261 | ? writebuf + type->length () / 2 : writebuf), 0); |
d05f6826 DJ |
5262 | return RETURN_VALUE_REGISTER_CONVENTION; |
5263 | } | |
78134374 | 5264 | else if (type->code () == TYPE_CODE_FLT |
6d82d43b AC |
5265 | && tdep->mips_fpu_type != MIPS_FPU_NONE) |
5266 | { | |
59aa1faa | 5267 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b | 5268 | if (mips_debug) |
6cb06a8c | 5269 | gdb_printf (gdb_stderr, "Return float in $fp0\n"); |
ba32f989 | 5270 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5271 | (gdbarch_num_regs (gdbarch) |
5272 | + mips_regnum (gdbarch)->fp0), | |
df86565b | 5273 | type->length (), |
72a155b4 | 5274 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5275 | readbuf, writebuf, 0); |
6d82d43b AC |
5276 | return RETURN_VALUE_REGISTER_CONVENTION; |
5277 | } | |
78134374 | 5278 | else if (type->code () == TYPE_CODE_STRUCT |
1f704f76 SM |
5279 | && type->num_fields () <= 2 |
5280 | && type->num_fields () >= 1 | |
5281 | && ((type->num_fields () == 1 | |
940da03e | 5282 | && (check_typedef (type->field (0).type ())->code () |
6d82d43b | 5283 | == TYPE_CODE_FLT)) |
1f704f76 | 5284 | || (type->num_fields () == 2 |
940da03e | 5285 | && (check_typedef (type->field (0).type ())->code () |
6d82d43b | 5286 | == TYPE_CODE_FLT) |
940da03e | 5287 | && (check_typedef (type->field (1).type ())->code () |
5b68030f | 5288 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
5289 | { |
5290 | /* A struct that contains one or two floats. Each value is part | |
dda83cd7 SM |
5291 | in the least significant part of their floating point |
5292 | register (or GPR, for soft float). */ | |
6d82d43b AC |
5293 | int regnum; |
5294 | int field; | |
5b68030f JM |
5295 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
5296 | ? mips_regnum (gdbarch)->fp0 | |
5297 | : MIPS_V0_REGNUM); | |
1f704f76 | 5298 | field < type->num_fields (); field++, regnum += 2) |
6d82d43b | 5299 | { |
3a543e21 | 5300 | int offset = type->field (field).loc_bitpos () / TARGET_CHAR_BIT; |
6d82d43b | 5301 | if (mips_debug) |
6cb06a8c TT |
5302 | gdb_printf (gdb_stderr, "Return float struct+%d\n", |
5303 | offset); | |
df86565b | 5304 | if (type->field (field).type ()->length () == 16) |
5b68030f JM |
5305 | { |
5306 | /* A 16-byte long double field goes in two consecutive | |
5307 | registers. */ | |
5308 | mips_xfer_register (gdbarch, regcache, | |
5309 | gdbarch_num_regs (gdbarch) + regnum, | |
5310 | 8, | |
5311 | gdbarch_byte_order (gdbarch), | |
5312 | readbuf, writebuf, offset); | |
5313 | mips_xfer_register (gdbarch, regcache, | |
5314 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
5315 | 8, | |
5316 | gdbarch_byte_order (gdbarch), | |
5317 | readbuf, writebuf, offset + 8); | |
5318 | } | |
5319 | else | |
5320 | mips_xfer_register (gdbarch, regcache, | |
5321 | gdbarch_num_regs (gdbarch) + regnum, | |
df86565b | 5322 | type->field (field).type ()->length (), |
5b68030f JM |
5323 | gdbarch_byte_order (gdbarch), |
5324 | readbuf, writebuf, offset); | |
6d82d43b AC |
5325 | } |
5326 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5327 | } | |
78134374 SM |
5328 | else if (type->code () == TYPE_CODE_STRUCT |
5329 | || type->code () == TYPE_CODE_UNION | |
5330 | || type->code () == TYPE_CODE_ARRAY) | |
6d82d43b | 5331 | { |
f08877ba | 5332 | /* A composite type. Extract the left justified value, |
dda83cd7 SM |
5333 | regardless of the byte order. I.e. DO NOT USE |
5334 | mips_xfer_lower. */ | |
6d82d43b AC |
5335 | int offset; |
5336 | int regnum; | |
4c7d22cb | 5337 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
df86565b | 5338 | offset < type->length (); |
72a155b4 | 5339 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5340 | { |
72a155b4 | 5341 | int xfer = register_size (gdbarch, regnum); |
df86565b SM |
5342 | if (offset + xfer > type->length ()) |
5343 | xfer = type->length () - offset; | |
6d82d43b | 5344 | if (mips_debug) |
6cb06a8c TT |
5345 | gdb_printf (gdb_stderr, "Return struct+%d:%d in $%d\n", |
5346 | offset, xfer, regnum); | |
ba32f989 DJ |
5347 | mips_xfer_register (gdbarch, regcache, |
5348 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
5349 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
5350 | offset); | |
6d82d43b AC |
5351 | } |
5352 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5353 | } | |
5354 | else | |
5355 | { | |
5356 | /* A scalar extract each part but least-significant-byte | |
dda83cd7 | 5357 | justified. */ |
6d82d43b AC |
5358 | int offset; |
5359 | int regnum; | |
4c7d22cb | 5360 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
df86565b | 5361 | offset < type->length (); |
72a155b4 | 5362 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5363 | { |
72a155b4 | 5364 | int xfer = register_size (gdbarch, regnum); |
df86565b SM |
5365 | if (offset + xfer > type->length ()) |
5366 | xfer = type->length () - offset; | |
6d82d43b | 5367 | if (mips_debug) |
6cb06a8c TT |
5368 | gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", |
5369 | offset, xfer, regnum); | |
ba32f989 DJ |
5370 | mips_xfer_register (gdbarch, regcache, |
5371 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5372 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5373 | readbuf, writebuf, offset); |
6d82d43b AC |
5374 | } |
5375 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5376 | } | |
5377 | } | |
5378 | ||
6a3a010b MR |
5379 | /* Which registers to use for passing floating-point values between |
5380 | function calls, one of floating-point, general and both kinds of | |
5381 | registers. O32 and O64 use different register kinds for standard | |
5382 | MIPS and MIPS16 code; to make the handling of cases where we may | |
5383 | not know what kind of code is being used (e.g. no debug information) | |
5384 | easier we sometimes use both kinds. */ | |
5385 | ||
5386 | enum mips_fval_reg | |
5387 | { | |
5388 | mips_fval_fpr, | |
5389 | mips_fval_gpr, | |
5390 | mips_fval_both | |
5391 | }; | |
5392 | ||
6d82d43b AC |
5393 | /* O32 ABI stuff. */ |
5394 | ||
5395 | static CORE_ADDR | |
7d9b040b | 5396 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5397 | struct regcache *regcache, CORE_ADDR bp_addr, |
5398 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
5399 | function_call_return_method return_method, |
5400 | CORE_ADDR struct_addr) | |
6d82d43b AC |
5401 | { |
5402 | int argreg; | |
5403 | int float_argreg; | |
5404 | int argnum; | |
b926417a | 5405 | int arg_space = 0; |
6d82d43b | 5406 | int stack_offset = 0; |
e17a4113 | 5407 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5408 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
5409 | |
5410 | /* For shared libraries, "t9" needs to point at the function | |
5411 | address. */ | |
4c7d22cb | 5412 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
5413 | |
5414 | /* Set the return address register to point to the entry point of | |
5415 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5416 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
5417 | |
5418 | /* First ensure that the stack and structure return address (if any) | |
5419 | are properly aligned. The stack has to be at least 64-bit | |
5420 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
5421 | aligned. For n32 and n64, stack frames need to be 128-bit |
5422 | aligned, so we round to this widest known alignment. */ | |
5423 | ||
5b03f266 AC |
5424 | sp = align_down (sp, 16); |
5425 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
5426 | |
5427 | /* Now make space on the stack for the args. */ | |
5428 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 | 5429 | { |
d0c97917 | 5430 | struct type *arg_type = check_typedef (args[argnum]->type ()); |
968b5391 MR |
5431 | |
5432 | /* Align to double-word if necessary. */ | |
2afd3f0a | 5433 | if (mips_type_needs_double_align (arg_type)) |
b926417a | 5434 | arg_space = align_up (arg_space, MIPS32_REGSIZE * 2); |
968b5391 | 5435 | /* Allocate space on the stack. */ |
df86565b | 5436 | arg_space += align_up (arg_type->length (), MIPS32_REGSIZE); |
968b5391 | 5437 | } |
b926417a | 5438 | sp -= align_up (arg_space, 16); |
ebafbe83 MS |
5439 | |
5440 | if (mips_debug) | |
6cb06a8c TT |
5441 | gdb_printf (gdb_stdlog, |
5442 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", | |
5443 | paddress (gdbarch, sp), | |
5444 | (long) align_up (arg_space, 16)); | |
ebafbe83 MS |
5445 | |
5446 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5447 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5448 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 5449 | |
bcb0cc15 | 5450 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cf84fa6b | 5451 | if (return_method == return_method_struct) |
ebafbe83 MS |
5452 | { |
5453 | if (mips_debug) | |
6cb06a8c TT |
5454 | gdb_printf (gdb_stdlog, |
5455 | "mips_o32_push_dummy_call: " | |
5456 | "struct_return reg=%d %s\n", | |
5457 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 5458 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5459 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
5460 | } |
5461 | ||
5462 | /* Now load as many as possible of the first arguments into | |
5463 | registers, and push the rest onto the stack. Loop thru args | |
5464 | from first to last. */ | |
5465 | for (argnum = 0; argnum < nargs; argnum++) | |
5466 | { | |
47a35522 | 5467 | const gdb_byte *val; |
ebafbe83 | 5468 | struct value *arg = args[argnum]; |
d0c97917 | 5469 | struct type *arg_type = check_typedef (arg->type ()); |
df86565b | 5470 | int len = arg_type->length (); |
78134374 | 5471 | enum type_code typecode = arg_type->code (); |
ebafbe83 MS |
5472 | |
5473 | if (mips_debug) | |
6cb06a8c TT |
5474 | gdb_printf (gdb_stdlog, |
5475 | "mips_o32_push_dummy_call: %d len=%d type=%d", | |
5476 | argnum + 1, len, (int) typecode); | |
46cac009 | 5477 | |
efaf1ae0 | 5478 | val = arg->contents ().data (); |
46cac009 AC |
5479 | |
5480 | /* 32-bit ABIs always start floating point arguments in an | |
dda83cd7 SM |
5481 | even-numbered floating point register. Round the FP register |
5482 | up before the check to see if there are any FP registers | |
5483 | left. O32 targets also pass the FP in the integer registers | |
5484 | so also round up normal registers. */ | |
74ed0bb4 | 5485 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
5486 | { |
5487 | if ((float_argreg & 1)) | |
5488 | float_argreg++; | |
5489 | } | |
5490 | ||
5491 | /* Floating point arguments passed in registers have to be | |
dda83cd7 SM |
5492 | treated specially. On 32-bit architectures, doubles are |
5493 | passed in register pairs; the even FP register gets the | |
5494 | low word, and the odd FP register gets the high word. | |
5495 | On O32, the first two floating point arguments are also | |
5496 | copied to general registers, following their memory order, | |
5497 | because MIPS16 functions don't use float registers for | |
5498 | arguments. This duplication of arguments in general | |
5499 | registers can't hurt non-MIPS16 functions, because those | |
5500 | registers are normally skipped. */ | |
46cac009 | 5501 | |
74ed0bb4 | 5502 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
345bd07c | 5503 | && float_argreg <= mips_last_fp_arg_regnum (gdbarch)) |
46cac009 | 5504 | { |
8b07f6d8 | 5505 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 5506 | { |
6a3a010b MR |
5507 | int freg_offset = gdbarch_byte_order (gdbarch) |
5508 | == BFD_ENDIAN_BIG ? 1 : 0; | |
46cac009 AC |
5509 | unsigned long regval; |
5510 | ||
6a3a010b MR |
5511 | /* First word. */ |
5512 | regval = extract_unsigned_integer (val, 4, byte_order); | |
46cac009 | 5513 | if (mips_debug) |
6cb06a8c TT |
5514 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
5515 | float_argreg + freg_offset, | |
5516 | phex (regval, 4)); | |
025bb325 | 5517 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5518 | float_argreg++ + freg_offset, |
5519 | regval); | |
46cac009 | 5520 | if (mips_debug) |
6cb06a8c TT |
5521 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
5522 | argreg, phex (regval, 4)); | |
9c9acae0 | 5523 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 | 5524 | |
6a3a010b MR |
5525 | /* Second word. */ |
5526 | regval = extract_unsigned_integer (val + 4, 4, byte_order); | |
46cac009 | 5527 | if (mips_debug) |
6cb06a8c TT |
5528 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
5529 | float_argreg - freg_offset, | |
5530 | phex (regval, 4)); | |
025bb325 | 5531 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5532 | float_argreg++ - freg_offset, |
5533 | regval); | |
46cac009 | 5534 | if (mips_debug) |
6cb06a8c TT |
5535 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
5536 | argreg, phex (regval, 4)); | |
9c9acae0 | 5537 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5538 | } |
5539 | else | |
5540 | { | |
5541 | /* This is a floating point value that fits entirely | |
dda83cd7 | 5542 | in a single register. */ |
46cac009 | 5543 | /* On 32 bit ABI's the float_argreg is further adjusted |
dda83cd7 | 5544 | above to ensure that it is even register aligned. */ |
e17a4113 | 5545 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 | 5546 | if (mips_debug) |
6cb06a8c TT |
5547 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
5548 | float_argreg, phex (regval, len)); | |
025bb325 MS |
5549 | regcache_cooked_write_unsigned (regcache, |
5550 | float_argreg++, regval); | |
5b68030f JM |
5551 | /* Although two FP registers are reserved for each |
5552 | argument, only one corresponding integer register is | |
5553 | reserved. */ | |
46cac009 | 5554 | if (mips_debug) |
6cb06a8c TT |
5555 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
5556 | argreg, phex (regval, len)); | |
5b68030f | 5557 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5558 | } |
5559 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 5560 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
5561 | } |
5562 | else | |
5563 | { | |
5564 | /* Copy the argument to general registers or the stack in | |
5565 | register-sized pieces. Large arguments are split between | |
5566 | registers and stack. */ | |
1a69e1e4 DJ |
5567 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
5568 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
5569 | them in registers where gcc sometimes puts them on the |
5570 | stack. For maximum compatibility, we will put them in | |
5571 | both places. */ | |
1a69e1e4 DJ |
5572 | int odd_sized_struct = (len > MIPS32_REGSIZE |
5573 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
5574 | /* Structures should be aligned to eight bytes (even arg registers) |
5575 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 5576 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
5577 | { |
5578 | if ((argreg & 1)) | |
968b5391 MR |
5579 | { |
5580 | argreg++; | |
1a69e1e4 | 5581 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 5582 | } |
46cac009 | 5583 | } |
46cac009 AC |
5584 | while (len > 0) |
5585 | { | |
1a69e1e4 | 5586 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
5587 | |
5588 | if (mips_debug) | |
6cb06a8c TT |
5589 | gdb_printf (gdb_stdlog, " -- partial=%d", |
5590 | partial_len); | |
46cac009 AC |
5591 | |
5592 | /* Write this portion of the argument to the stack. */ | |
345bd07c | 5593 | if (argreg > mips_last_arg_regnum (gdbarch) |
968b5391 | 5594 | || odd_sized_struct) |
46cac009 AC |
5595 | { |
5596 | /* Should shorter than int integer values be | |
025bb325 | 5597 | promoted to int before being stored? */ |
46cac009 AC |
5598 | int longword_offset = 0; |
5599 | CORE_ADDR addr; | |
46cac009 AC |
5600 | |
5601 | if (mips_debug) | |
5602 | { | |
6cb06a8c TT |
5603 | gdb_printf (gdb_stdlog, " - stack_offset=%s", |
5604 | paddress (gdbarch, stack_offset)); | |
5605 | gdb_printf (gdb_stdlog, " longword_offset=%s", | |
5606 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
5607 | } |
5608 | ||
5609 | addr = sp + stack_offset + longword_offset; | |
5610 | ||
5611 | if (mips_debug) | |
5612 | { | |
5613 | int i; | |
6cb06a8c TT |
5614 | gdb_printf (gdb_stdlog, " @%s ", |
5615 | paddress (gdbarch, addr)); | |
46cac009 AC |
5616 | for (i = 0; i < partial_len; i++) |
5617 | { | |
6cb06a8c TT |
5618 | gdb_printf (gdb_stdlog, "%02x", |
5619 | val[i] & 0xff); | |
46cac009 AC |
5620 | } |
5621 | } | |
5622 | write_memory (addr, val, partial_len); | |
5623 | } | |
5624 | ||
5625 | /* Note!!! This is NOT an else clause. Odd sized | |
dda83cd7 | 5626 | structs may go thru BOTH paths. */ |
46cac009 | 5627 | /* Write this portion of the argument to a general |
dda83cd7 | 5628 | purpose register. */ |
345bd07c | 5629 | if (argreg <= mips_last_arg_regnum (gdbarch)) |
46cac009 | 5630 | { |
e17a4113 UW |
5631 | LONGEST regval = extract_signed_integer (val, partial_len, |
5632 | byte_order); | |
4246e332 | 5633 | /* Value may need to be sign extended, because |
1b13c4f6 | 5634 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
5635 | |
5636 | /* A non-floating-point argument being passed in a | |
5637 | general register. If a struct or union, and if | |
5638 | the remaining length is smaller than the register | |
5639 | size, we have to adjust the register value on | |
5640 | big endian targets. | |
5641 | ||
5642 | It does not seem to be necessary to do the | |
5643 | same for integral types. | |
5644 | ||
5645 | Also don't do this adjustment on O64 binaries. | |
5646 | ||
5647 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
5648 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
5649 | mips_abi_regsize(), generates a left shift |
5650 | as part of storing the argument in a register | |
5651 | (the left shift isn't generated when | |
1b13c4f6 | 5652 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
5653 | it is quite possible that this is GCC |
5654 | contradicting the LE/O32 ABI, GDB has not been | |
5655 | adjusted to accommodate this. Either someone | |
5656 | needs to demonstrate that the LE/O32 ABI | |
5657 | specifies such a left shift OR this new ABI gets | |
5658 | identified as such and GDB gets tweaked | |
5659 | accordingly. */ | |
5660 | ||
72a155b4 | 5661 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5662 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
5663 | && (typecode == TYPE_CODE_STRUCT |
5664 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5665 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 5666 | * TARGET_CHAR_BIT); |
46cac009 AC |
5667 | |
5668 | if (mips_debug) | |
6cb06a8c TT |
5669 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
5670 | argreg, | |
5671 | phex (regval, MIPS32_REGSIZE)); | |
9c9acae0 | 5672 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
5673 | argreg++; |
5674 | ||
5675 | /* Prevent subsequent floating point arguments from | |
5676 | being passed in floating point registers. */ | |
345bd07c | 5677 | float_argreg = mips_last_fp_arg_regnum (gdbarch) + 1; |
46cac009 AC |
5678 | } |
5679 | ||
5680 | len -= partial_len; | |
5681 | val += partial_len; | |
5682 | ||
b021a221 | 5683 | /* Compute the offset into the stack at which we will |
dda83cd7 | 5684 | copy the next parameter. |
46cac009 | 5685 | |
dda83cd7 SM |
5686 | In older ABIs, the caller reserved space for |
5687 | registers that contained arguments. This was loosely | |
33b5899f | 5688 | referred to as their "home". Consequently, space is |
dda83cd7 | 5689 | always allocated. */ |
46cac009 | 5690 | |
1a69e1e4 | 5691 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
5692 | } |
5693 | } | |
5694 | if (mips_debug) | |
6cb06a8c | 5695 | gdb_printf (gdb_stdlog, "\n"); |
46cac009 AC |
5696 | } |
5697 | ||
f10683bb | 5698 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5699 | |
46cac009 AC |
5700 | /* Return adjusted stack pointer. */ |
5701 | return sp; | |
5702 | } | |
5703 | ||
6d82d43b | 5704 | static enum return_value_convention |
6a3a010b | 5705 | mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 5706 | struct type *type, struct regcache *regcache, |
47a35522 | 5707 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5708 | { |
6a3a010b | 5709 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5710 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
08106042 | 5711 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
6a3a010b | 5712 | enum mips_fval_reg fval_reg; |
6d82d43b | 5713 | |
6a3a010b | 5714 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
78134374 SM |
5715 | if (type->code () == TYPE_CODE_STRUCT |
5716 | || type->code () == TYPE_CODE_UNION | |
5717 | || type->code () == TYPE_CODE_ARRAY) | |
6d82d43b | 5718 | return RETURN_VALUE_STRUCT_CONVENTION; |
78134374 | 5719 | else if (type->code () == TYPE_CODE_FLT |
df86565b | 5720 | && type->length () == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) |
6d82d43b | 5721 | { |
6a3a010b | 5722 | /* A single-precision floating-point value. If reading in or copying, |
dda83cd7 SM |
5723 | then we get it from/put it to FP0 for standard MIPS code or GPR2 |
5724 | for MIPS16 code. If writing out only, then we put it to both FP0 | |
5725 | and GPR2. We do not support reading in with no function known, if | |
5726 | this safety check ever triggers, then we'll have to try harder. */ | |
6a3a010b | 5727 | gdb_assert (function || !readbuf); |
6d82d43b | 5728 | if (mips_debug) |
6a3a010b MR |
5729 | switch (fval_reg) |
5730 | { | |
5731 | case mips_fval_fpr: | |
6cb06a8c | 5732 | gdb_printf (gdb_stderr, "Return float in $fp0\n"); |
6a3a010b MR |
5733 | break; |
5734 | case mips_fval_gpr: | |
6cb06a8c | 5735 | gdb_printf (gdb_stderr, "Return float in $2\n"); |
6a3a010b MR |
5736 | break; |
5737 | case mips_fval_both: | |
6cb06a8c | 5738 | gdb_printf (gdb_stderr, "Return float in $fp0 and $2\n"); |
6a3a010b MR |
5739 | break; |
5740 | } | |
5741 | if (fval_reg != mips_fval_gpr) | |
5742 | mips_xfer_register (gdbarch, regcache, | |
5743 | (gdbarch_num_regs (gdbarch) | |
5744 | + mips_regnum (gdbarch)->fp0), | |
df86565b | 5745 | type->length (), |
6a3a010b MR |
5746 | gdbarch_byte_order (gdbarch), |
5747 | readbuf, writebuf, 0); | |
5748 | if (fval_reg != mips_fval_fpr) | |
5749 | mips_xfer_register (gdbarch, regcache, | |
5750 | gdbarch_num_regs (gdbarch) + 2, | |
df86565b | 5751 | type->length (), |
6a3a010b MR |
5752 | gdbarch_byte_order (gdbarch), |
5753 | readbuf, writebuf, 0); | |
6d82d43b AC |
5754 | return RETURN_VALUE_REGISTER_CONVENTION; |
5755 | } | |
78134374 | 5756 | else if (type->code () == TYPE_CODE_FLT |
df86565b | 5757 | && type->length () == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) |
6d82d43b | 5758 | { |
6a3a010b | 5759 | /* A double-precision floating-point value. If reading in or copying, |
dda83cd7 SM |
5760 | then we get it from/put it to FP1 and FP0 for standard MIPS code or |
5761 | GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it | |
5762 | to both FP1/FP0 and GPR2/GPR3. We do not support reading in with | |
5763 | no function known, if this safety check ever triggers, then we'll | |
5764 | have to try harder. */ | |
6a3a010b | 5765 | gdb_assert (function || !readbuf); |
6d82d43b | 5766 | if (mips_debug) |
6a3a010b MR |
5767 | switch (fval_reg) |
5768 | { | |
5769 | case mips_fval_fpr: | |
6cb06a8c | 5770 | gdb_printf (gdb_stderr, "Return float in $fp1/$fp0\n"); |
6a3a010b MR |
5771 | break; |
5772 | case mips_fval_gpr: | |
6cb06a8c | 5773 | gdb_printf (gdb_stderr, "Return float in $2/$3\n"); |
6a3a010b MR |
5774 | break; |
5775 | case mips_fval_both: | |
6cb06a8c TT |
5776 | gdb_printf (gdb_stderr, |
5777 | "Return float in $fp1/$fp0 and $2/$3\n"); | |
6a3a010b MR |
5778 | break; |
5779 | } | |
5780 | if (fval_reg != mips_fval_gpr) | |
6d82d43b | 5781 | { |
6a3a010b MR |
5782 | /* The most significant part goes in FP1, and the least significant |
5783 | in FP0. */ | |
5784 | switch (gdbarch_byte_order (gdbarch)) | |
5785 | { | |
5786 | case BFD_ENDIAN_LITTLE: | |
5787 | mips_xfer_register (gdbarch, regcache, | |
5788 | (gdbarch_num_regs (gdbarch) | |
5789 | + mips_regnum (gdbarch)->fp0 + 0), | |
5790 | 4, gdbarch_byte_order (gdbarch), | |
5791 | readbuf, writebuf, 0); | |
5792 | mips_xfer_register (gdbarch, regcache, | |
5793 | (gdbarch_num_regs (gdbarch) | |
5794 | + mips_regnum (gdbarch)->fp0 + 1), | |
5795 | 4, gdbarch_byte_order (gdbarch), | |
5796 | readbuf, writebuf, 4); | |
5797 | break; | |
5798 | case BFD_ENDIAN_BIG: | |
5799 | mips_xfer_register (gdbarch, regcache, | |
5800 | (gdbarch_num_regs (gdbarch) | |
5801 | + mips_regnum (gdbarch)->fp0 + 1), | |
5802 | 4, gdbarch_byte_order (gdbarch), | |
5803 | readbuf, writebuf, 0); | |
5804 | mips_xfer_register (gdbarch, regcache, | |
5805 | (gdbarch_num_regs (gdbarch) | |
5806 | + mips_regnum (gdbarch)->fp0 + 0), | |
5807 | 4, gdbarch_byte_order (gdbarch), | |
5808 | readbuf, writebuf, 4); | |
5809 | break; | |
5810 | default: | |
f34652de | 5811 | internal_error (_("bad switch")); |
6a3a010b MR |
5812 | } |
5813 | } | |
5814 | if (fval_reg != mips_fval_fpr) | |
5815 | { | |
5816 | /* The two 32-bit parts are always placed in GPR2 and GPR3 | |
5817 | following these registers' memory order. */ | |
ba32f989 | 5818 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5819 | gdbarch_num_regs (gdbarch) + 2, |
72a155b4 | 5820 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5821 | readbuf, writebuf, 0); |
ba32f989 | 5822 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5823 | gdbarch_num_regs (gdbarch) + 3, |
72a155b4 | 5824 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5825 | readbuf, writebuf, 4); |
6d82d43b AC |
5826 | } |
5827 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5828 | } | |
5829 | #if 0 | |
78134374 | 5830 | else if (type->code () == TYPE_CODE_STRUCT |
1f704f76 SM |
5831 | && type->num_fields () <= 2 |
5832 | && type->num_fields () >= 1 | |
5833 | && ((type->num_fields () == 1 | |
940da03e | 5834 | && (TYPE_CODE (type->field (0).type ()) |
6d82d43b | 5835 | == TYPE_CODE_FLT)) |
1f704f76 | 5836 | || (type->num_fields () == 2 |
940da03e | 5837 | && (TYPE_CODE (type->field (0).type ()) |
6d82d43b | 5838 | == TYPE_CODE_FLT) |
940da03e | 5839 | && (TYPE_CODE (type->field (1).type ()) |
6d82d43b AC |
5840 | == TYPE_CODE_FLT))) |
5841 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5842 | { | |
5843 | /* A struct that contains one or two floats. Each value is part | |
dda83cd7 SM |
5844 | in the least significant part of their floating point |
5845 | register.. */ | |
6d82d43b AC |
5846 | int regnum; |
5847 | int field; | |
72a155b4 | 5848 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
1f704f76 | 5849 | field < type->num_fields (); field++, regnum += 2) |
6d82d43b | 5850 | { |
3a543e21 | 5851 | int offset = (type->fields ()[field].loc_bitpos () / TARGET_CHAR_BIT); |
6d82d43b | 5852 | if (mips_debug) |
6cb06a8c TT |
5853 | gdb_printf (gdb_stderr, "Return float struct+%d\n", |
5854 | offset); | |
ba32f989 DJ |
5855 | mips_xfer_register (gdbarch, regcache, |
5856 | gdbarch_num_regs (gdbarch) + regnum, | |
940da03e | 5857 | TYPE_LENGTH (type->field (field).type ()), |
72a155b4 | 5858 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5859 | readbuf, writebuf, offset); |
6d82d43b AC |
5860 | } |
5861 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5862 | } | |
5863 | #endif | |
5864 | #if 0 | |
78134374 SM |
5865 | else if (type->code () == TYPE_CODE_STRUCT |
5866 | || type->code () == TYPE_CODE_UNION) | |
6d82d43b AC |
5867 | { |
5868 | /* A structure or union. Extract the left justified value, | |
dda83cd7 SM |
5869 | regardless of the byte order. I.e. DO NOT USE |
5870 | mips_xfer_lower. */ | |
6d82d43b AC |
5871 | int offset; |
5872 | int regnum; | |
4c7d22cb | 5873 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
df86565b | 5874 | offset < type->length (); |
72a155b4 | 5875 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5876 | { |
72a155b4 | 5877 | int xfer = register_size (gdbarch, regnum); |
df86565b SM |
5878 | if (offset + xfer > type->length ()) |
5879 | xfer = type->length () - offset; | |
6d82d43b | 5880 | if (mips_debug) |
6cb06a8c TT |
5881 | gdb_printf (gdb_stderr, "Return struct+%d:%d in $%d\n", |
5882 | offset, xfer, regnum); | |
ba32f989 DJ |
5883 | mips_xfer_register (gdbarch, regcache, |
5884 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
5885 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
5886 | } | |
5887 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5888 | } | |
5889 | #endif | |
5890 | else | |
5891 | { | |
5892 | /* A scalar extract each part but least-significant-byte | |
dda83cd7 SM |
5893 | justified. o32 thinks registers are 4 byte, regardless of |
5894 | the ISA. */ | |
6d82d43b AC |
5895 | int offset; |
5896 | int regnum; | |
4c7d22cb | 5897 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
df86565b | 5898 | offset < type->length (); |
1a69e1e4 | 5899 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 5900 | { |
1a69e1e4 | 5901 | int xfer = MIPS32_REGSIZE; |
df86565b SM |
5902 | if (offset + xfer > type->length ()) |
5903 | xfer = type->length () - offset; | |
6d82d43b | 5904 | if (mips_debug) |
6cb06a8c TT |
5905 | gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", |
5906 | offset, xfer, regnum); | |
ba32f989 DJ |
5907 | mips_xfer_register (gdbarch, regcache, |
5908 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 5909 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5910 | readbuf, writebuf, offset); |
6d82d43b AC |
5911 | } |
5912 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5913 | } | |
5914 | } | |
5915 | ||
5916 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
5917 | ABI. */ | |
46cac009 AC |
5918 | |
5919 | static CORE_ADDR | |
7d9b040b | 5920 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5921 | struct regcache *regcache, CORE_ADDR bp_addr, |
5922 | int nargs, | |
5923 | struct value **args, CORE_ADDR sp, | |
cf84fa6b | 5924 | function_call_return_method return_method, CORE_ADDR struct_addr) |
46cac009 AC |
5925 | { |
5926 | int argreg; | |
5927 | int float_argreg; | |
5928 | int argnum; | |
b926417a | 5929 | int arg_space = 0; |
46cac009 | 5930 | int stack_offset = 0; |
e17a4113 | 5931 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5932 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 5933 | |
25ab4790 AC |
5934 | /* For shared libraries, "t9" needs to point at the function |
5935 | address. */ | |
4c7d22cb | 5936 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
5937 | |
5938 | /* Set the return address register to point to the entry point of | |
5939 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5940 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 5941 | |
46cac009 AC |
5942 | /* First ensure that the stack and structure return address (if any) |
5943 | are properly aligned. The stack has to be at least 64-bit | |
5944 | aligned even on 32-bit machines, because doubles must be 64-bit | |
5945 | aligned. For n32 and n64, stack frames need to be 128-bit | |
5946 | aligned, so we round to this widest known alignment. */ | |
5947 | ||
5b03f266 AC |
5948 | sp = align_down (sp, 16); |
5949 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
5950 | |
5951 | /* Now make space on the stack for the args. */ | |
5952 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 | 5953 | { |
d0c97917 | 5954 | struct type *arg_type = check_typedef (args[argnum]->type ()); |
968b5391 | 5955 | |
968b5391 | 5956 | /* Allocate space on the stack. */ |
df86565b | 5957 | arg_space += align_up (arg_type->length (), MIPS64_REGSIZE); |
968b5391 | 5958 | } |
b926417a | 5959 | sp -= align_up (arg_space, 16); |
46cac009 AC |
5960 | |
5961 | if (mips_debug) | |
6cb06a8c TT |
5962 | gdb_printf (gdb_stdlog, |
5963 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", | |
5964 | paddress (gdbarch, sp), | |
5965 | (long) align_up (arg_space, 16)); | |
46cac009 AC |
5966 | |
5967 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5968 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5969 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
5970 | |
5971 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
cf84fa6b | 5972 | if (return_method == return_method_struct) |
46cac009 AC |
5973 | { |
5974 | if (mips_debug) | |
6cb06a8c TT |
5975 | gdb_printf (gdb_stdlog, |
5976 | "mips_o64_push_dummy_call: " | |
5977 | "struct_return reg=%d %s\n", | |
5978 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 5979 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5980 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
5981 | } |
5982 | ||
5983 | /* Now load as many as possible of the first arguments into | |
5984 | registers, and push the rest onto the stack. Loop thru args | |
5985 | from first to last. */ | |
5986 | for (argnum = 0; argnum < nargs; argnum++) | |
5987 | { | |
47a35522 | 5988 | const gdb_byte *val; |
46cac009 | 5989 | struct value *arg = args[argnum]; |
d0c97917 | 5990 | struct type *arg_type = check_typedef (arg->type ()); |
df86565b | 5991 | int len = arg_type->length (); |
78134374 | 5992 | enum type_code typecode = arg_type->code (); |
46cac009 AC |
5993 | |
5994 | if (mips_debug) | |
6cb06a8c TT |
5995 | gdb_printf (gdb_stdlog, |
5996 | "mips_o64_push_dummy_call: %d len=%d type=%d", | |
5997 | argnum + 1, len, (int) typecode); | |
ebafbe83 | 5998 | |
efaf1ae0 | 5999 | val = arg->contents ().data (); |
ebafbe83 | 6000 | |
ebafbe83 | 6001 | /* Floating point arguments passed in registers have to be |
dda83cd7 SM |
6002 | treated specially. On 32-bit architectures, doubles are |
6003 | passed in register pairs; the even FP register gets the | |
6004 | low word, and the odd FP register gets the high word. | |
6005 | On O64, the first two floating point arguments are also | |
6006 | copied to general registers, because MIPS16 functions | |
6007 | don't use float registers for arguments. This duplication | |
6008 | of arguments in general registers can't hurt non-MIPS16 | |
6009 | functions because those registers are normally skipped. */ | |
ebafbe83 | 6010 | |
74ed0bb4 | 6011 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
345bd07c | 6012 | && float_argreg <= mips_last_fp_arg_regnum (gdbarch)) |
ebafbe83 | 6013 | { |
e17a4113 | 6014 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a | 6015 | if (mips_debug) |
6cb06a8c TT |
6016 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
6017 | float_argreg, phex (regval, len)); | |
9c9acae0 | 6018 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a | 6019 | if (mips_debug) |
6cb06a8c TT |
6020 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
6021 | argreg, phex (regval, len)); | |
9c9acae0 | 6022 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 6023 | argreg++; |
ebafbe83 | 6024 | /* Reserve space for the FP register. */ |
1a69e1e4 | 6025 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
6026 | } |
6027 | else | |
6028 | { | |
6029 | /* Copy the argument to general registers or the stack in | |
6030 | register-sized pieces. Large arguments are split between | |
6031 | registers and stack. */ | |
1a69e1e4 | 6032 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
6033 | are treated specially: Irix cc passes them in registers |
6034 | where gcc sometimes puts them on the stack. For maximum | |
6035 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
6036 | int odd_sized_struct = (len > MIPS64_REGSIZE |
6037 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
6038 | while (len > 0) |
6039 | { | |
1a69e1e4 | 6040 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
6041 | |
6042 | if (mips_debug) | |
6cb06a8c TT |
6043 | gdb_printf (gdb_stdlog, " -- partial=%d", |
6044 | partial_len); | |
ebafbe83 MS |
6045 | |
6046 | /* Write this portion of the argument to the stack. */ | |
345bd07c | 6047 | if (argreg > mips_last_arg_regnum (gdbarch) |
968b5391 | 6048 | || odd_sized_struct) |
ebafbe83 MS |
6049 | { |
6050 | /* Should shorter than int integer values be | |
025bb325 | 6051 | promoted to int before being stored? */ |
ebafbe83 MS |
6052 | int longword_offset = 0; |
6053 | CORE_ADDR addr; | |
72a155b4 | 6054 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 6055 | { |
1a69e1e4 DJ |
6056 | if ((typecode == TYPE_CODE_INT |
6057 | || typecode == TYPE_CODE_PTR | |
6058 | || typecode == TYPE_CODE_FLT) | |
6059 | && len <= 4) | |
6060 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
6061 | } |
6062 | ||
6063 | if (mips_debug) | |
6064 | { | |
6cb06a8c TT |
6065 | gdb_printf (gdb_stdlog, " - stack_offset=%s", |
6066 | paddress (gdbarch, stack_offset)); | |
6067 | gdb_printf (gdb_stdlog, " longword_offset=%s", | |
6068 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
6069 | } |
6070 | ||
6071 | addr = sp + stack_offset + longword_offset; | |
6072 | ||
6073 | if (mips_debug) | |
6074 | { | |
6075 | int i; | |
6cb06a8c TT |
6076 | gdb_printf (gdb_stdlog, " @%s ", |
6077 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
6078 | for (i = 0; i < partial_len; i++) |
6079 | { | |
6cb06a8c TT |
6080 | gdb_printf (gdb_stdlog, "%02x", |
6081 | val[i] & 0xff); | |
ebafbe83 MS |
6082 | } |
6083 | } | |
6084 | write_memory (addr, val, partial_len); | |
6085 | } | |
6086 | ||
6087 | /* Note!!! This is NOT an else clause. Odd sized | |
dda83cd7 | 6088 | structs may go thru BOTH paths. */ |
ebafbe83 | 6089 | /* Write this portion of the argument to a general |
dda83cd7 | 6090 | purpose register. */ |
345bd07c | 6091 | if (argreg <= mips_last_arg_regnum (gdbarch)) |
ebafbe83 | 6092 | { |
e17a4113 UW |
6093 | LONGEST regval = extract_signed_integer (val, partial_len, |
6094 | byte_order); | |
4246e332 | 6095 | /* Value may need to be sign extended, because |
1b13c4f6 | 6096 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
6097 | |
6098 | /* A non-floating-point argument being passed in a | |
6099 | general register. If a struct or union, and if | |
6100 | the remaining length is smaller than the register | |
6101 | size, we have to adjust the register value on | |
6102 | big endian targets. | |
6103 | ||
6104 | It does not seem to be necessary to do the | |
025bb325 | 6105 | same for integral types. */ |
480d3dd2 | 6106 | |
72a155b4 | 6107 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 6108 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
6109 | && (typecode == TYPE_CODE_STRUCT |
6110 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 6111 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 6112 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
6113 | |
6114 | if (mips_debug) | |
6cb06a8c TT |
6115 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
6116 | argreg, | |
6117 | phex (regval, MIPS64_REGSIZE)); | |
9c9acae0 | 6118 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
6119 | argreg++; |
6120 | ||
6121 | /* Prevent subsequent floating point arguments from | |
6122 | being passed in floating point registers. */ | |
345bd07c | 6123 | float_argreg = mips_last_fp_arg_regnum (gdbarch) + 1; |
ebafbe83 MS |
6124 | } |
6125 | ||
6126 | len -= partial_len; | |
6127 | val += partial_len; | |
6128 | ||
b021a221 | 6129 | /* Compute the offset into the stack at which we will |
dda83cd7 | 6130 | copy the next parameter. |
ebafbe83 | 6131 | |
dda83cd7 SM |
6132 | In older ABIs, the caller reserved space for |
6133 | registers that contained arguments. This was loosely | |
33b5899f | 6134 | referred to as their "home". Consequently, space is |
dda83cd7 | 6135 | always allocated. */ |
ebafbe83 | 6136 | |
1a69e1e4 | 6137 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
6138 | } |
6139 | } | |
6140 | if (mips_debug) | |
6cb06a8c | 6141 | gdb_printf (gdb_stdlog, "\n"); |
ebafbe83 MS |
6142 | } |
6143 | ||
f10683bb | 6144 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 6145 | |
ebafbe83 MS |
6146 | /* Return adjusted stack pointer. */ |
6147 | return sp; | |
6148 | } | |
6149 | ||
9c8fdbfa | 6150 | static enum return_value_convention |
6a3a010b | 6151 | mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 6152 | struct type *type, struct regcache *regcache, |
47a35522 | 6153 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 6154 | { |
6a3a010b | 6155 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 6156 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
6a3a010b | 6157 | enum mips_fval_reg fval_reg; |
7a076fd2 | 6158 | |
6a3a010b | 6159 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
78134374 SM |
6160 | if (type->code () == TYPE_CODE_STRUCT |
6161 | || type->code () == TYPE_CODE_UNION | |
6162 | || type->code () == TYPE_CODE_ARRAY) | |
7a076fd2 | 6163 | return RETURN_VALUE_STRUCT_CONVENTION; |
78134374 | 6164 | else if (fp_register_arg_p (gdbarch, type->code (), type)) |
7a076fd2 | 6165 | { |
6a3a010b | 6166 | /* A floating-point value. If reading in or copying, then we get it |
dda83cd7 SM |
6167 | from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. |
6168 | If writing out only, then we put it to both FP0 and GPR2. We do | |
6169 | not support reading in with no function known, if this safety | |
6170 | check ever triggers, then we'll have to try harder. */ | |
6a3a010b | 6171 | gdb_assert (function || !readbuf); |
7a076fd2 | 6172 | if (mips_debug) |
6a3a010b MR |
6173 | switch (fval_reg) |
6174 | { | |
6175 | case mips_fval_fpr: | |
6cb06a8c | 6176 | gdb_printf (gdb_stderr, "Return float in $fp0\n"); |
6a3a010b MR |
6177 | break; |
6178 | case mips_fval_gpr: | |
6cb06a8c | 6179 | gdb_printf (gdb_stderr, "Return float in $2\n"); |
6a3a010b MR |
6180 | break; |
6181 | case mips_fval_both: | |
6cb06a8c | 6182 | gdb_printf (gdb_stderr, "Return float in $fp0 and $2\n"); |
6a3a010b MR |
6183 | break; |
6184 | } | |
6185 | if (fval_reg != mips_fval_gpr) | |
6186 | mips_xfer_register (gdbarch, regcache, | |
6187 | (gdbarch_num_regs (gdbarch) | |
6188 | + mips_regnum (gdbarch)->fp0), | |
df86565b | 6189 | type->length (), |
6a3a010b MR |
6190 | gdbarch_byte_order (gdbarch), |
6191 | readbuf, writebuf, 0); | |
6192 | if (fval_reg != mips_fval_fpr) | |
6193 | mips_xfer_register (gdbarch, regcache, | |
6194 | gdbarch_num_regs (gdbarch) + 2, | |
df86565b | 6195 | type->length (), |
6a3a010b MR |
6196 | gdbarch_byte_order (gdbarch), |
6197 | readbuf, writebuf, 0); | |
7a076fd2 FF |
6198 | return RETURN_VALUE_REGISTER_CONVENTION; |
6199 | } | |
6200 | else | |
6201 | { | |
6202 | /* A scalar extract each part but least-significant-byte | |
dda83cd7 | 6203 | justified. */ |
7a076fd2 FF |
6204 | int offset; |
6205 | int regnum; | |
6206 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
df86565b | 6207 | offset < type->length (); |
1a69e1e4 | 6208 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 6209 | { |
1a69e1e4 | 6210 | int xfer = MIPS64_REGSIZE; |
df86565b SM |
6211 | if (offset + xfer > type->length ()) |
6212 | xfer = type->length () - offset; | |
7a076fd2 | 6213 | if (mips_debug) |
6cb06a8c TT |
6214 | gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", |
6215 | offset, xfer, regnum); | |
ba32f989 DJ |
6216 | mips_xfer_register (gdbarch, regcache, |
6217 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 6218 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 6219 | readbuf, writebuf, offset); |
7a076fd2 FF |
6220 | } |
6221 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6222 | } | |
6d82d43b AC |
6223 | } |
6224 | ||
dd824b04 DJ |
6225 | /* Floating point register management. |
6226 | ||
6227 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
6228 | 64bit operations, these early MIPS cpus treat fp register pairs | |
6229 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
6230 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
6231 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
6232 | double precision floats into two 32-bit chunks and store them in | |
6233 | consecutive fp regs. To display 64-bit floats stored in this | |
6234 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
6235 | Throw in user-configurable endianness and you have a real mess. | |
6236 | ||
6237 | The way this works is: | |
6238 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
6239 | double-precision value will be split across two logical registers. | |
6240 | The lower-numbered logical register will hold the low-order bits, | |
6241 | regardless of the processor's endianness. | |
6242 | - If we are on a 64-bit processor, and we are looking for a | |
6243 | single-precision value, it will be in the low ordered bits | |
6244 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
6245 | save slot in memory. | |
6246 | - If we are in 64-bit mode, everything is straightforward. | |
6247 | ||
6248 | Note that this code only deals with "live" registers at the top of the | |
6249 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 6250 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
6251 | interface that can deal with dynamic saved register sizes -- fp |
6252 | regs could be 32 bits wide in one frame and 64 on the frame above | |
6253 | and below). */ | |
6254 | ||
6255 | /* Copy a 32-bit single-precision value from the current frame | |
6256 | into rare_buffer. */ | |
6257 | ||
6258 | static void | |
bd2b40ac | 6259 | mips_read_fp_register_single (frame_info_ptr frame, int regno, |
47a35522 | 6260 | gdb_byte *rare_buffer) |
dd824b04 | 6261 | { |
72a155b4 UW |
6262 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6263 | int raw_size = register_size (gdbarch, regno); | |
224c3ddb | 6264 | gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size); |
dd824b04 | 6265 | |
ca9d61b9 | 6266 | if (!deprecated_frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 6267 | error (_("can't read register %d (%s)"), |
72a155b4 | 6268 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6269 | if (raw_size == 8) |
6270 | { | |
6271 | /* We have a 64-bit value for this register. Find the low-order | |
dda83cd7 | 6272 | 32 bits. */ |
dd824b04 DJ |
6273 | int offset; |
6274 | ||
72a155b4 | 6275 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
6276 | offset = 4; |
6277 | else | |
6278 | offset = 0; | |
6279 | ||
6280 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
6281 | } | |
6282 | else | |
6283 | { | |
6284 | memcpy (rare_buffer, raw_buffer, 4); | |
6285 | } | |
6286 | } | |
6287 | ||
6288 | /* Copy a 64-bit double-precision value from the current frame into | |
6289 | rare_buffer. This may include getting half of it from the next | |
6290 | register. */ | |
6291 | ||
6292 | static void | |
bd2b40ac | 6293 | mips_read_fp_register_double (frame_info_ptr frame, int regno, |
47a35522 | 6294 | gdb_byte *rare_buffer) |
dd824b04 | 6295 | { |
72a155b4 UW |
6296 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6297 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 6298 | |
9c9acae0 | 6299 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
6300 | { |
6301 | /* We have a 64-bit value for this register, and we should use | |
dda83cd7 | 6302 | all 64 bits. */ |
ca9d61b9 | 6303 | if (!deprecated_frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 6304 | error (_("can't read register %d (%s)"), |
72a155b4 | 6305 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6306 | } |
6307 | else | |
6308 | { | |
72a155b4 | 6309 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 6310 | |
72a155b4 | 6311 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
f34652de | 6312 | internal_error (_("mips_read_fp_register_double: bad access to " |
e2e0b3e5 | 6313 | "odd-numbered FP register")); |
dd824b04 DJ |
6314 | |
6315 | /* mips_read_fp_register_single will find the correct 32 bits from | |
dda83cd7 | 6316 | each register. */ |
72a155b4 | 6317 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 6318 | { |
e11c53d2 AC |
6319 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
6320 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 6321 | } |
361d1df0 | 6322 | else |
dd824b04 | 6323 | { |
e11c53d2 AC |
6324 | mips_read_fp_register_single (frame, regno, rare_buffer); |
6325 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
6326 | } |
6327 | } | |
6328 | } | |
6329 | ||
c906108c | 6330 | static void |
bd2b40ac | 6331 | mips_print_fp_register (struct ui_file *file, frame_info_ptr frame, |
e11c53d2 | 6332 | int regnum) |
025bb325 | 6333 | { /* Do values for FP (float) regs. */ |
72a155b4 | 6334 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 6335 | gdb_byte *raw_buffer; |
8ba0dd51 UW |
6336 | std::string flt_str, dbl_str; |
6337 | ||
f69fdf9b UW |
6338 | const struct type *flt_type = builtin_type (gdbarch)->builtin_float; |
6339 | const struct type *dbl_type = builtin_type (gdbarch)->builtin_double; | |
c5aa993b | 6340 | |
224c3ddb SM |
6341 | raw_buffer |
6342 | = ((gdb_byte *) | |
6343 | alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0))); | |
c906108c | 6344 | |
6cb06a8c TT |
6345 | gdb_printf (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
6346 | gdb_printf (file, "%*s", | |
6347 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), | |
6348 | ""); | |
f0ef6b29 | 6349 | |
72a155b4 | 6350 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 6351 | { |
79a45b7d TT |
6352 | struct value_print_options opts; |
6353 | ||
f0ef6b29 | 6354 | /* 4-byte registers: Print hex and floating. Also print even |
dda83cd7 | 6355 | numbered registers as doubles. */ |
e11c53d2 | 6356 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
f69fdf9b | 6357 | flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g"); |
c5aa993b | 6358 | |
79a45b7d | 6359 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6360 | print_scalar_formatted (raw_buffer, |
6361 | builtin_type (gdbarch)->builtin_uint32, | |
6362 | &opts, 'w', file); | |
dd824b04 | 6363 | |
6cb06a8c | 6364 | gdb_printf (file, " flt: %s", flt_str.c_str ()); |
1adad886 | 6365 | |
72a155b4 | 6366 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 6367 | { |
e11c53d2 | 6368 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f69fdf9b | 6369 | dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g"); |
1adad886 | 6370 | |
6cb06a8c | 6371 | gdb_printf (file, " dbl: %s", dbl_str.c_str ()); |
f0ef6b29 | 6372 | } |
c906108c SS |
6373 | } |
6374 | else | |
dd824b04 | 6375 | { |
79a45b7d TT |
6376 | struct value_print_options opts; |
6377 | ||
f0ef6b29 | 6378 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 6379 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
f69fdf9b | 6380 | flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g"); |
c906108c | 6381 | |
e11c53d2 | 6382 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f69fdf9b | 6383 | dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g"); |
f0ef6b29 | 6384 | |
79a45b7d | 6385 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6386 | print_scalar_formatted (raw_buffer, |
6387 | builtin_type (gdbarch)->builtin_uint64, | |
6388 | &opts, 'g', file); | |
f0ef6b29 | 6389 | |
6cb06a8c TT |
6390 | gdb_printf (file, " flt: %s", flt_str.c_str ()); |
6391 | gdb_printf (file, " dbl: %s", dbl_str.c_str ()); | |
f0ef6b29 KB |
6392 | } |
6393 | } | |
6394 | ||
6395 | static void | |
bd2b40ac | 6396 | mips_print_register (struct ui_file *file, frame_info_ptr frame, |
0cc93a06 | 6397 | int regnum) |
f0ef6b29 | 6398 | { |
a4b8ebc8 | 6399 | struct gdbarch *gdbarch = get_frame_arch (frame); |
79a45b7d | 6400 | struct value_print_options opts; |
de15c4ab | 6401 | struct value *val; |
1adad886 | 6402 | |
004159a2 | 6403 | if (mips_float_register_p (gdbarch, regnum)) |
f0ef6b29 | 6404 | { |
e11c53d2 | 6405 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
6406 | return; |
6407 | } | |
6408 | ||
de15c4ab | 6409 | val = get_frame_register_value (frame, regnum); |
f0ef6b29 | 6410 | |
0426ad51 | 6411 | gdb_puts (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
6412 | |
6413 | /* The problem with printing numeric register names (r26, etc.) is that | |
6414 | the user can't use them on input. Probably the best solution is to | |
6415 | fix it so that either the numeric or the funky (a2, etc.) names | |
6416 | are accepted on input. */ | |
6417 | if (regnum < MIPS_NUMREGS) | |
6cb06a8c | 6418 | gdb_printf (file, "(r%d): ", regnum); |
f0ef6b29 | 6419 | else |
6cb06a8c | 6420 | gdb_printf (file, ": "); |
f0ef6b29 | 6421 | |
79a45b7d | 6422 | get_formatted_print_options (&opts, 'x'); |
4dba70ee | 6423 | value_print_scalar_formatted (val, &opts, 0, file); |
c906108c SS |
6424 | } |
6425 | ||
1bab7383 YQ |
6426 | /* Print IEEE exception condition bits in FLAGS. */ |
6427 | ||
6428 | static void | |
6429 | print_fpu_flags (struct ui_file *file, int flags) | |
6430 | { | |
6431 | if (flags & (1 << 0)) | |
0426ad51 | 6432 | gdb_puts (" inexact", file); |
1bab7383 | 6433 | if (flags & (1 << 1)) |
0426ad51 | 6434 | gdb_puts (" uflow", file); |
1bab7383 | 6435 | if (flags & (1 << 2)) |
0426ad51 | 6436 | gdb_puts (" oflow", file); |
1bab7383 | 6437 | if (flags & (1 << 3)) |
0426ad51 | 6438 | gdb_puts (" div0", file); |
1bab7383 | 6439 | if (flags & (1 << 4)) |
0426ad51 | 6440 | gdb_puts (" inval", file); |
1bab7383 | 6441 | if (flags & (1 << 5)) |
0426ad51 | 6442 | gdb_puts (" unimp", file); |
a11ac3b3 | 6443 | gdb_putc ('\n', file); |
1bab7383 YQ |
6444 | } |
6445 | ||
6446 | /* Print interesting information about the floating point processor | |
6447 | (if present) or emulator. */ | |
6448 | ||
6449 | static void | |
6450 | mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, | |
bd2b40ac | 6451 | frame_info_ptr frame, const char *args) |
1bab7383 YQ |
6452 | { |
6453 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
345bd07c | 6454 | enum mips_fpu_type type = mips_get_fpu_type (gdbarch); |
1bab7383 YQ |
6455 | ULONGEST fcs = 0; |
6456 | int i; | |
6457 | ||
6458 | if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs)) | |
6459 | type = MIPS_FPU_NONE; | |
6460 | ||
6cb06a8c TT |
6461 | gdb_printf (file, "fpu type: %s\n", |
6462 | type == MIPS_FPU_DOUBLE ? "double-precision" | |
6463 | : type == MIPS_FPU_SINGLE ? "single-precision" | |
6464 | : "none / unused"); | |
1bab7383 YQ |
6465 | |
6466 | if (type == MIPS_FPU_NONE) | |
6467 | return; | |
6468 | ||
6cb06a8c TT |
6469 | gdb_printf (file, "reg size: %d bits\n", |
6470 | register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8); | |
1bab7383 | 6471 | |
0426ad51 | 6472 | gdb_puts ("cond :", file); |
1bab7383 | 6473 | if (fcs & (1 << 23)) |
0426ad51 | 6474 | gdb_puts (" 0", file); |
1bab7383 YQ |
6475 | for (i = 1; i <= 7; i++) |
6476 | if (fcs & (1 << (24 + i))) | |
6cb06a8c | 6477 | gdb_printf (file, " %d", i); |
a11ac3b3 | 6478 | gdb_putc ('\n', file); |
1bab7383 | 6479 | |
0426ad51 | 6480 | gdb_puts ("cause :", file); |
1bab7383 YQ |
6481 | print_fpu_flags (file, (fcs >> 12) & 0x3f); |
6482 | fputs ("mask :", stdout); | |
6483 | print_fpu_flags (file, (fcs >> 7) & 0x1f); | |
6484 | fputs ("flags :", stdout); | |
6485 | print_fpu_flags (file, (fcs >> 2) & 0x1f); | |
6486 | ||
0426ad51 | 6487 | gdb_puts ("rounding: ", file); |
1bab7383 YQ |
6488 | switch (fcs & 3) |
6489 | { | |
0426ad51 TT |
6490 | case 0: gdb_puts ("nearest\n", file); break; |
6491 | case 1: gdb_puts ("zero\n", file); break; | |
6492 | case 2: gdb_puts ("+inf\n", file); break; | |
6493 | case 3: gdb_puts ("-inf\n", file); break; | |
1bab7383 YQ |
6494 | } |
6495 | ||
0426ad51 | 6496 | gdb_puts ("flush :", file); |
1bab7383 | 6497 | if (fcs & (1 << 21)) |
0426ad51 | 6498 | gdb_puts (" nearest", file); |
1bab7383 | 6499 | if (fcs & (1 << 22)) |
0426ad51 | 6500 | gdb_puts (" override", file); |
1bab7383 | 6501 | if (fcs & (1 << 24)) |
0426ad51 | 6502 | gdb_puts (" zero", file); |
1bab7383 | 6503 | if ((fcs & (0xb << 21)) == 0) |
0426ad51 | 6504 | gdb_puts (" no", file); |
a11ac3b3 | 6505 | gdb_putc ('\n', file); |
1bab7383 | 6506 | |
6cb06a8c TT |
6507 | gdb_printf (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no"); |
6508 | gdb_printf (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no"); | |
a11ac3b3 | 6509 | gdb_putc ('\n', file); |
1bab7383 YQ |
6510 | |
6511 | default_print_float_info (gdbarch, file, frame, args); | |
6512 | } | |
6513 | ||
f0ef6b29 KB |
6514 | /* Replacement for generic do_registers_info. |
6515 | Print regs in pretty columns. */ | |
6516 | ||
6517 | static int | |
bd2b40ac | 6518 | print_fp_register_row (struct ui_file *file, frame_info_ptr frame, |
e11c53d2 | 6519 | int regnum) |
f0ef6b29 | 6520 | { |
6cb06a8c | 6521 | gdb_printf (file, " "); |
e11c53d2 | 6522 | mips_print_fp_register (file, frame, regnum); |
6cb06a8c | 6523 | gdb_printf (file, "\n"); |
f0ef6b29 KB |
6524 | return regnum + 1; |
6525 | } | |
6526 | ||
6527 | ||
025bb325 | 6528 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
6529 | |
6530 | static int | |
bd2b40ac | 6531 | print_gp_register_row (struct ui_file *file, frame_info_ptr frame, |
a4b8ebc8 | 6532 | int start_regnum) |
c906108c | 6533 | { |
a4b8ebc8 | 6534 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 6535 | /* Do values for GP (int) regs. */ |
313c5961 AH |
6536 | const gdb_byte *raw_buffer; |
6537 | struct value *value; | |
025bb325 MS |
6538 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
6539 | per row. */ | |
c906108c | 6540 | int col, byte; |
a4b8ebc8 | 6541 | int regnum; |
c906108c | 6542 | |
025bb325 | 6543 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 6544 | for (col = 0, regnum = start_regnum; |
f6efe3f8 | 6545 | col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch); |
f57d151a | 6546 | regnum++) |
c906108c | 6547 | { |
72a155b4 | 6548 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6549 | continue; /* unused register */ |
004159a2 | 6550 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6551 | break; /* End the row: reached FP register. */ |
0cc93a06 | 6552 | /* Large registers are handled separately. */ |
72a155b4 | 6553 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6554 | { |
6555 | if (col > 0) | |
6556 | break; /* End the row before this register. */ | |
6557 | ||
6558 | /* Print this register on a row by itself. */ | |
6559 | mips_print_register (file, frame, regnum); | |
6cb06a8c | 6560 | gdb_printf (file, "\n"); |
0cc93a06 DJ |
6561 | return regnum + 1; |
6562 | } | |
d05f6826 | 6563 | if (col == 0) |
6cb06a8c TT |
6564 | gdb_printf (file, " "); |
6565 | gdb_printf (file, | |
6566 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", | |
6567 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
6568 | col++; |
6569 | } | |
d05f6826 DJ |
6570 | |
6571 | if (col == 0) | |
6572 | return regnum; | |
6573 | ||
025bb325 | 6574 | /* Print the R0 to R31 names. */ |
72a155b4 | 6575 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
6cb06a8c TT |
6576 | gdb_printf (file, "\n R%-4d", |
6577 | start_regnum % gdbarch_num_regs (gdbarch)); | |
20e6603c | 6578 | else |
6cb06a8c | 6579 | gdb_printf (file, "\n "); |
c906108c | 6580 | |
025bb325 | 6581 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 6582 | for (col = 0, regnum = start_regnum; |
f6efe3f8 | 6583 | col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch); |
f57d151a | 6584 | regnum++) |
c906108c | 6585 | { |
72a155b4 | 6586 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6587 | continue; /* unused register */ |
004159a2 | 6588 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6589 | break; /* End row: reached FP register. */ |
72a155b4 | 6590 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6591 | break; /* End row: large register. */ |
6592 | ||
c906108c | 6593 | /* OK: get the data in raw format. */ |
313c5961 | 6594 | value = get_frame_register_value (frame, regnum); |
d00664db TT |
6595 | if (value->optimized_out () |
6596 | || !value->entirely_available ()) | |
325c9fd4 | 6597 | { |
6cb06a8c TT |
6598 | gdb_printf (file, "%*s ", |
6599 | (int) mips_abi_regsize (gdbarch) * 2, | |
6600 | (mips_abi_regsize (gdbarch) == 4 ? "<unavl>" | |
6601 | : "<unavailable>")); | |
325c9fd4 JB |
6602 | col++; |
6603 | continue; | |
6604 | } | |
efaf1ae0 | 6605 | raw_buffer = value->contents_all ().data (); |
c906108c | 6606 | /* pad small registers */ |
4246e332 | 6607 | for (byte = 0; |
72a155b4 UW |
6608 | byte < (mips_abi_regsize (gdbarch) |
6609 | - register_size (gdbarch, regnum)); byte++) | |
6cb06a8c | 6610 | gdb_printf (file, " "); |
025bb325 | 6611 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 6612 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 6613 | for (byte = |
72a155b4 UW |
6614 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
6615 | byte < register_size (gdbarch, regnum); byte++) | |
6cb06a8c | 6616 | gdb_printf (file, "%02x", raw_buffer[byte]); |
c906108c | 6617 | else |
72a155b4 | 6618 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 6619 | byte >= 0; byte--) |
6cb06a8c TT |
6620 | gdb_printf (file, "%02x", raw_buffer[byte]); |
6621 | gdb_printf (file, " "); | |
c906108c SS |
6622 | col++; |
6623 | } | |
025bb325 | 6624 | if (col > 0) /* ie. if we actually printed anything... */ |
6cb06a8c | 6625 | gdb_printf (file, "\n"); |
c906108c SS |
6626 | |
6627 | return regnum; | |
6628 | } | |
6629 | ||
025bb325 | 6630 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 6631 | |
bf1f5b4c | 6632 | static void |
e11c53d2 | 6633 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
bd2b40ac | 6634 | frame_info_ptr frame, int regnum, int all) |
c906108c | 6635 | { |
025bb325 | 6636 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 6637 | { |
72a155b4 UW |
6638 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
6639 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 6640 | error (_("Not a valid register for the current processor type")); |
c906108c | 6641 | |
0cc93a06 | 6642 | mips_print_register (file, frame, regnum); |
6cb06a8c | 6643 | gdb_printf (file, "\n"); |
c906108c | 6644 | } |
c5aa993b | 6645 | else |
025bb325 | 6646 | /* Do all (or most) registers. */ |
c906108c | 6647 | { |
72a155b4 | 6648 | regnum = gdbarch_num_regs (gdbarch); |
f6efe3f8 | 6649 | while (regnum < gdbarch_num_cooked_regs (gdbarch)) |
c906108c | 6650 | { |
004159a2 | 6651 | if (mips_float_register_p (gdbarch, regnum)) |
e11c53d2 | 6652 | { |
025bb325 | 6653 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
6654 | regnum = print_fp_register_row (file, frame, regnum); |
6655 | else | |
025bb325 | 6656 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 6657 | } |
c906108c | 6658 | else |
e11c53d2 | 6659 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
6660 | } |
6661 | } | |
6662 | } | |
6663 | ||
63807e1d | 6664 | static int |
3352ef37 | 6665 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
bd2b40ac | 6666 | frame_info_ptr frame) |
c906108c | 6667 | { |
3352ef37 | 6668 | CORE_ADDR pc = get_frame_pc (frame); |
4cc0665f MR |
6669 | enum mips_isa isa; |
6670 | ULONGEST insn; | |
4cc0665f MR |
6671 | int size; |
6672 | ||
6673 | if ((mips_pc_is_mips (pc) | |
ab50adb6 | 6674 | && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc)) |
4cc0665f | 6675 | || (mips_pc_is_micromips (gdbarch, pc) |
ab50adb6 | 6676 | && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0)) |
4cc0665f | 6677 | || (mips_pc_is_mips16 (gdbarch, pc) |
ab50adb6 | 6678 | && !mips16_insn_at_pc_has_delay_slot (gdbarch, pc, 0))) |
06648491 MK |
6679 | return 0; |
6680 | ||
4cc0665f MR |
6681 | isa = mips_pc_isa (gdbarch, pc); |
6682 | /* _has_delay_slot above will have validated the read. */ | |
6683 | insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); | |
6684 | size = mips_insn_size (isa, insn); | |
8b86c959 YQ |
6685 | |
6686 | const address_space *aspace = get_frame_address_space (frame); | |
6687 | ||
4cc0665f | 6688 | return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; |
c906108c SS |
6689 | } |
6690 | ||
6d82d43b AC |
6691 | /* To skip prologues, I use this predicate. Returns either PC itself |
6692 | if the code at PC does not look like a function prologue; otherwise | |
6693 | returns an address that (if we're lucky) follows the prologue. If | |
6694 | LENIENT, then we must skip everything which is involved in setting | |
6695 | up the frame (it's OK to skip more, just so long as we don't skip | |
6696 | anything which might clobber the registers which are being saved. | |
6697 | We must skip more in the case where part of the prologue is in the | |
6698 | delay slot of a non-prologue instruction). */ | |
6699 | ||
6700 | static CORE_ADDR | |
6093d2eb | 6701 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 6702 | { |
8b622e6a AC |
6703 | CORE_ADDR limit_pc; |
6704 | CORE_ADDR func_addr; | |
6705 | ||
6d82d43b AC |
6706 | /* See if we can determine the end of the prologue via the symbol table. |
6707 | If so, then return either PC, or the PC after the prologue, whichever | |
6708 | is greater. */ | |
8b622e6a AC |
6709 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
6710 | { | |
d80b854b UW |
6711 | CORE_ADDR post_prologue_pc |
6712 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a | 6713 | if (post_prologue_pc != 0) |
325fac50 | 6714 | return std::max (pc, post_prologue_pc); |
8b622e6a | 6715 | } |
6d82d43b AC |
6716 | |
6717 | /* Can't determine prologue from the symbol table, need to examine | |
6718 | instructions. */ | |
6719 | ||
98b4dd94 JB |
6720 | /* Find an upper limit on the function prologue using the debug |
6721 | information. If the debug information could not be used to provide | |
6722 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 6723 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
6724 | if (limit_pc == 0) |
6725 | limit_pc = pc + 100; /* Magic. */ | |
6726 | ||
4cc0665f | 6727 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6728 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
4cc0665f MR |
6729 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6730 | return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); | |
6d82d43b | 6731 | else |
e17a4113 | 6732 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
6733 | } |
6734 | ||
c9cf6e20 MG |
6735 | /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version). |
6736 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
6737 | ||
97ab0fdd | 6738 | static int |
c9cf6e20 | 6739 | mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6740 | { |
6741 | CORE_ADDR func_addr = 0, func_end = 0; | |
6742 | ||
6743 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6744 | { | |
6745 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6746 | CORE_ADDR addr = func_end - 12; | |
6747 | ||
6748 | if (addr < func_addr + 4) | |
dda83cd7 | 6749 | addr = func_addr + 4; |
97ab0fdd | 6750 | if (pc < addr) |
dda83cd7 | 6751 | return 0; |
97ab0fdd MR |
6752 | |
6753 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
6754 | { | |
6755 | unsigned long high_word; | |
6756 | unsigned long inst; | |
6757 | ||
4cc0665f | 6758 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
97ab0fdd MR |
6759 | high_word = (inst >> 16) & 0xffff; |
6760 | ||
6761 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
6762 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
6763 | && inst != 0x03e00008 /* jr $ra */ | |
6764 | && inst != 0x00000000) /* nop */ | |
6765 | return 0; | |
6766 | } | |
6767 | ||
6768 | return 1; | |
6769 | } | |
6770 | ||
6771 | return 0; | |
6772 | } | |
6773 | ||
c9cf6e20 MG |
6774 | /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version). |
6775 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
4cc0665f MR |
6776 | |
6777 | static int | |
c9cf6e20 | 6778 | micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4cc0665f MR |
6779 | { |
6780 | CORE_ADDR func_addr = 0; | |
6781 | CORE_ADDR func_end = 0; | |
6782 | CORE_ADDR addr; | |
6783 | ULONGEST insn; | |
6784 | long offset; | |
6785 | int dreg; | |
6786 | int sreg; | |
6787 | int loc; | |
6788 | ||
6789 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6790 | return 0; | |
6791 | ||
6792 | /* The microMIPS epilogue is max. 12 bytes long. */ | |
6793 | addr = func_end - 12; | |
6794 | ||
6795 | if (addr < func_addr + 2) | |
6796 | addr = func_addr + 2; | |
6797 | if (pc < addr) | |
6798 | return 0; | |
6799 | ||
6800 | for (; pc < func_end; pc += loc) | |
6801 | { | |
6802 | loc = 0; | |
6803 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
6804 | loc += MIPS_INSN16_SIZE; | |
6805 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
6806 | { | |
4cc0665f MR |
6807 | /* 32-bit instructions. */ |
6808 | case 2 * MIPS_INSN16_SIZE: | |
6809 | insn <<= 16; | |
6810 | insn |= mips_fetch_instruction (gdbarch, | |
6811 | ISA_MICROMIPS, pc + loc, NULL); | |
6812 | loc += MIPS_INSN16_SIZE; | |
6813 | switch (micromips_op (insn >> 16)) | |
6814 | { | |
6815 | case 0xc: /* ADDIU: bits 001100 */ | |
6816 | case 0x17: /* DADDIU: bits 010111 */ | |
6817 | sreg = b0s5_reg (insn >> 16); | |
6818 | dreg = b5s5_reg (insn >> 16); | |
6819 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
6820 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
6821 | /* (D)ADDIU $sp, imm */ | |
6822 | && offset >= 0) | |
6823 | break; | |
6824 | return 0; | |
6825 | ||
6826 | default: | |
6827 | return 0; | |
6828 | } | |
6829 | break; | |
6830 | ||
6831 | /* 16-bit instructions. */ | |
6832 | case MIPS_INSN16_SIZE: | |
6833 | switch (micromips_op (insn)) | |
6834 | { | |
6835 | case 0x3: /* MOVE: bits 000011 */ | |
6836 | sreg = b0s5_reg (insn); | |
6837 | dreg = b5s5_reg (insn); | |
6838 | if (sreg == 0 && dreg == 0) | |
6839 | /* MOVE $zero, $zero aka NOP */ | |
6840 | break; | |
6841 | return 0; | |
6842 | ||
6843 | case 0x11: /* POOL16C: bits 010001 */ | |
6844 | if (b5s5_op (insn) == 0x18 | |
6845 | /* JRADDIUSP: bits 010011 11000 */ | |
6846 | || (b5s5_op (insn) == 0xd | |
6847 | /* JRC: bits 010011 01101 */ | |
6848 | && b0s5_reg (insn) == MIPS_RA_REGNUM)) | |
6849 | /* JRC $ra */ | |
6850 | break; | |
6851 | return 0; | |
6852 | ||
6853 | case 0x13: /* POOL16D: bits 010011 */ | |
6854 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
6855 | if ((insn & 0x1) == 0x1 | |
6856 | /* ADDIUSP: bits 010011 1 */ | |
6857 | && offset > 0) | |
6858 | break; | |
6859 | return 0; | |
6860 | ||
6861 | default: | |
6862 | return 0; | |
6863 | } | |
6864 | } | |
6865 | } | |
6866 | ||
6867 | return 1; | |
6868 | } | |
6869 | ||
c9cf6e20 MG |
6870 | /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version). |
6871 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
6872 | ||
97ab0fdd | 6873 | static int |
c9cf6e20 | 6874 | mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6875 | { |
6876 | CORE_ADDR func_addr = 0, func_end = 0; | |
6877 | ||
6878 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6879 | { | |
6880 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6881 | CORE_ADDR addr = func_end - 12; | |
6882 | ||
6883 | if (addr < func_addr + 4) | |
dda83cd7 | 6884 | addr = func_addr + 4; |
97ab0fdd | 6885 | if (pc < addr) |
dda83cd7 | 6886 | return 0; |
97ab0fdd MR |
6887 | |
6888 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
6889 | { | |
6890 | unsigned short inst; | |
6891 | ||
4cc0665f | 6892 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); |
97ab0fdd MR |
6893 | |
6894 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
6895 | continue; | |
6896 | ||
6897 | if (inst != 0x6300 /* addiu $sp,offset */ | |
6898 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
6899 | && inst != 0xe820 /* jr $ra */ | |
6900 | && inst != 0xe8a0 /* jrc $ra */ | |
6901 | && inst != 0x6500) /* nop */ | |
6902 | return 0; | |
6903 | } | |
6904 | ||
6905 | return 1; | |
6906 | } | |
6907 | ||
6908 | return 0; | |
6909 | } | |
6910 | ||
c9cf6e20 MG |
6911 | /* Implement the stack_frame_destroyed_p gdbarch method. |
6912 | ||
6913 | The epilogue is defined here as the area at the end of a function, | |
97ab0fdd | 6914 | after an instruction which destroys the function's stack frame. */ |
c9cf6e20 | 6915 | |
97ab0fdd | 6916 | static int |
c9cf6e20 | 6917 | mips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd | 6918 | { |
4cc0665f | 6919 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c9cf6e20 | 6920 | return mips16_stack_frame_destroyed_p (gdbarch, pc); |
4cc0665f | 6921 | else if (mips_pc_is_micromips (gdbarch, pc)) |
c9cf6e20 | 6922 | return micromips_stack_frame_destroyed_p (gdbarch, pc); |
97ab0fdd | 6923 | else |
c9cf6e20 | 6924 | return mips32_stack_frame_destroyed_p (gdbarch, pc); |
97ab0fdd MR |
6925 | } |
6926 | ||
c906108c SS |
6927 | /* Commands to show/set the MIPS FPU type. */ |
6928 | ||
c906108c | 6929 | static void |
bd4c9dfe | 6930 | show_mipsfpu_command (const char *args, int from_tty) |
c906108c | 6931 | { |
a121b7c1 | 6932 | const char *fpu; |
6ca0852e | 6933 | |
99d9c3b9 SM |
6934 | if (gdbarch_bfd_arch_info (current_inferior ()->arch ())->arch |
6935 | != bfd_arch_mips) | |
6ca0852e | 6936 | { |
6cb06a8c | 6937 | gdb_printf |
6ca0852e UW |
6938 | ("The MIPS floating-point coprocessor is unknown " |
6939 | "because the current architecture is not MIPS.\n"); | |
6940 | return; | |
6941 | } | |
6942 | ||
99d9c3b9 | 6943 | switch (mips_get_fpu_type (current_inferior ()->arch ())) |
c906108c SS |
6944 | { |
6945 | case MIPS_FPU_SINGLE: | |
6946 | fpu = "single-precision"; | |
6947 | break; | |
6948 | case MIPS_FPU_DOUBLE: | |
6949 | fpu = "double-precision"; | |
6950 | break; | |
6951 | case MIPS_FPU_NONE: | |
6952 | fpu = "absent (none)"; | |
6953 | break; | |
93d56215 | 6954 | default: |
f34652de | 6955 | internal_error (_("bad switch")); |
c906108c SS |
6956 | } |
6957 | if (mips_fpu_type_auto) | |
6cb06a8c TT |
6958 | gdb_printf ("The MIPS floating-point coprocessor " |
6959 | "is set automatically (currently %s)\n", | |
6960 | fpu); | |
c906108c | 6961 | else |
6cb06a8c | 6962 | gdb_printf |
6d82d43b | 6963 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); |
c906108c SS |
6964 | } |
6965 | ||
6966 | ||
c906108c | 6967 | static void |
bd4c9dfe | 6968 | set_mipsfpu_single_command (const char *args, int from_tty) |
c906108c | 6969 | { |
8d5838b5 | 6970 | struct gdbarch_info info; |
c906108c SS |
6971 | mips_fpu_type = MIPS_FPU_SINGLE; |
6972 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6973 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6974 | instead of relying on globals. Doing that would let generic code | |
6975 | handle the search for this specific architecture. */ | |
6976 | if (!gdbarch_update_p (info)) | |
f34652de | 6977 | internal_error (_("set mipsfpu failed")); |
c906108c SS |
6978 | } |
6979 | ||
c906108c | 6980 | static void |
bd4c9dfe | 6981 | set_mipsfpu_double_command (const char *args, int from_tty) |
c906108c | 6982 | { |
8d5838b5 | 6983 | struct gdbarch_info info; |
c906108c SS |
6984 | mips_fpu_type = MIPS_FPU_DOUBLE; |
6985 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6986 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6987 | instead of relying on globals. Doing that would let generic code | |
6988 | handle the search for this specific architecture. */ | |
6989 | if (!gdbarch_update_p (info)) | |
f34652de | 6990 | internal_error (_("set mipsfpu failed")); |
c906108c SS |
6991 | } |
6992 | ||
c906108c | 6993 | static void |
bd4c9dfe | 6994 | set_mipsfpu_none_command (const char *args, int from_tty) |
c906108c | 6995 | { |
8d5838b5 | 6996 | struct gdbarch_info info; |
c906108c SS |
6997 | mips_fpu_type = MIPS_FPU_NONE; |
6998 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6999 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
7000 | instead of relying on globals. Doing that would let generic code | |
7001 | handle the search for this specific architecture. */ | |
7002 | if (!gdbarch_update_p (info)) | |
f34652de | 7003 | internal_error (_("set mipsfpu failed")); |
c906108c SS |
7004 | } |
7005 | ||
c906108c | 7006 | static void |
bd4c9dfe | 7007 | set_mipsfpu_auto_command (const char *args, int from_tty) |
c906108c SS |
7008 | { |
7009 | mips_fpu_type_auto = 1; | |
7010 | } | |
7011 | ||
c906108c SS |
7012 | /* Just like reinit_frame_cache, but with the right arguments to be |
7013 | callable as an sfunc. */ | |
7014 | ||
7015 | static void | |
eb4c3f4a | 7016 | reinit_frame_cache_sfunc (const char *args, int from_tty, |
acdb74a0 | 7017 | struct cmd_list_element *c) |
c906108c SS |
7018 | { |
7019 | reinit_frame_cache (); | |
7020 | } | |
7021 | ||
a89aa300 AC |
7022 | static int |
7023 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 7024 | { |
f0c2e3e0 AB |
7025 | gdb_disassemble_info *di |
7026 | = static_cast<gdb_disassemble_info *> (info->application_data); | |
e47ad6c0 | 7027 | struct gdbarch *gdbarch = di->arch (); |
4cc0665f | 7028 | |
d31431ed AC |
7029 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
7030 | disassembler needs to be able to locally determine the ISA, and | |
7031 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
7032 | work. */ | |
4cc0665f | 7033 | if (mips_pc_is_mips16 (gdbarch, memaddr)) |
ec4045ea | 7034 | info->mach = bfd_mach_mips16; |
4cc0665f MR |
7035 | else if (mips_pc_is_micromips (gdbarch, memaddr)) |
7036 | info->mach = bfd_mach_mips_micromips; | |
c906108c SS |
7037 | |
7038 | /* Round down the instruction address to the appropriate boundary. */ | |
4cc0665f MR |
7039 | memaddr &= (info->mach == bfd_mach_mips16 |
7040 | || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; | |
c5aa993b | 7041 | |
6394c606 | 7042 | return default_print_insn (memaddr, info); |
c906108c SS |
7043 | } |
7044 | ||
cd6c3b4f YQ |
7045 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
7046 | ||
d19280ad YQ |
7047 | static int |
7048 | mips_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
c906108c | 7049 | { |
4cc0665f MR |
7050 | CORE_ADDR pc = *pcptr; |
7051 | ||
d19280ad | 7052 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 7053 | { |
d19280ad YQ |
7054 | *pcptr = unmake_compact_addr (pc); |
7055 | return MIPS_BP_KIND_MIPS16; | |
7056 | } | |
7057 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
7058 | { | |
7059 | ULONGEST insn; | |
7060 | int status; | |
c906108c | 7061 | |
d19280ad YQ |
7062 | *pcptr = unmake_compact_addr (pc); |
7063 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
7064 | if (status || (mips_insn_size (ISA_MICROMIPS, insn) == 2)) | |
7065 | return MIPS_BP_KIND_MICROMIPS16; | |
7066 | else | |
7067 | return MIPS_BP_KIND_MICROMIPS32; | |
c906108c SS |
7068 | } |
7069 | else | |
d19280ad YQ |
7070 | return MIPS_BP_KIND_MIPS32; |
7071 | } | |
7072 | ||
cd6c3b4f YQ |
7073 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
7074 | ||
d19280ad YQ |
7075 | static const gdb_byte * |
7076 | mips_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
7077 | { | |
7078 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
7079 | ||
7080 | switch (kind) | |
c906108c | 7081 | { |
d19280ad YQ |
7082 | case MIPS_BP_KIND_MIPS16: |
7083 | { | |
7084 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; | |
7085 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; | |
7086 | ||
7087 | *size = 2; | |
7088 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7089 | return mips16_big_breakpoint; | |
7090 | else | |
c906108c | 7091 | return mips16_little_breakpoint; |
d19280ad YQ |
7092 | } |
7093 | case MIPS_BP_KIND_MICROMIPS16: | |
7094 | { | |
7095 | static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; | |
7096 | static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; | |
7097 | ||
7098 | *size = 2; | |
7099 | ||
7100 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7101 | return micromips16_big_breakpoint; | |
7102 | else | |
7103 | return micromips16_little_breakpoint; | |
7104 | } | |
7105 | case MIPS_BP_KIND_MICROMIPS32: | |
7106 | { | |
7107 | static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; | |
7108 | static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; | |
7109 | ||
7110 | *size = 4; | |
7111 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7112 | return micromips32_big_breakpoint; | |
7113 | else | |
7114 | return micromips32_little_breakpoint; | |
7115 | } | |
7116 | case MIPS_BP_KIND_MIPS32: | |
7117 | { | |
7118 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; | |
7119 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; | |
c906108c | 7120 | |
d19280ad YQ |
7121 | *size = 4; |
7122 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7123 | return big_breakpoint; | |
7124 | else | |
7e3d947d | 7125 | return little_breakpoint; |
d19280ad YQ |
7126 | } |
7127 | default: | |
7128 | gdb_assert_not_reached ("unexpected mips breakpoint kind"); | |
7129 | }; | |
c906108c SS |
7130 | } |
7131 | ||
ab50adb6 MR |
7132 | /* Return non-zero if the standard MIPS instruction INST has a branch |
7133 | delay slot (i.e. it is a jump or branch instruction). This function | |
7134 | is based on mips32_next_pc. */ | |
c8cef75f MR |
7135 | |
7136 | static int | |
ab50adb6 | 7137 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst) |
c8cef75f | 7138 | { |
c8cef75f | 7139 | int op; |
a385295e MR |
7140 | int rs; |
7141 | int rt; | |
c8cef75f | 7142 | |
c8cef75f MR |
7143 | op = itype_op (inst); |
7144 | if ((inst & 0xe0000000) != 0) | |
a385295e MR |
7145 | { |
7146 | rs = itype_rs (inst); | |
7147 | rt = itype_rt (inst); | |
f94363d7 AP |
7148 | return (is_octeon_bbit_op (op, gdbarch) |
7149 | || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
a385295e MR |
7150 | || op == 29 /* JALX: bits 011101 */ |
7151 | || (op == 17 | |
7152 | && (rs == 8 | |
c8cef75f | 7153 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
7154 | || (rs == 9 && (rt & 0x2) == 0) |
7155 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ | |
7156 | || (rs == 10 && (rt & 0x2) == 0)))); | |
7157 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ | |
7158 | } | |
c8cef75f MR |
7159 | else |
7160 | switch (op & 0x07) /* extract bits 28,27,26 */ | |
7161 | { | |
7162 | case 0: /* SPECIAL */ | |
7163 | op = rtype_funct (inst); | |
7164 | return (op == 8 /* JR */ | |
7165 | || op == 9); /* JALR */ | |
7166 | break; /* end SPECIAL */ | |
7167 | case 1: /* REGIMM */ | |
a385295e MR |
7168 | rs = itype_rs (inst); |
7169 | rt = itype_rt (inst); /* branch condition */ | |
7170 | return ((rt & 0xc) == 0 | |
c8cef75f MR |
7171 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
7172 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ | |
a385295e MR |
7173 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
7174 | /* BPOSGE32, BPOSGE64: bits 1110x */ | |
c8cef75f MR |
7175 | break; /* end REGIMM */ |
7176 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ | |
7177 | return 1; | |
7178 | break; | |
7179 | } | |
7180 | } | |
7181 | ||
ab50adb6 MR |
7182 | /* Return non-zero if a standard MIPS instruction at ADDR has a branch |
7183 | delay slot (i.e. it is a jump or branch instruction). */ | |
c8cef75f | 7184 | |
4cc0665f | 7185 | static int |
ab50adb6 | 7186 | mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) |
4cc0665f MR |
7187 | { |
7188 | ULONGEST insn; | |
7189 | int status; | |
7190 | ||
ab50adb6 | 7191 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); |
4cc0665f MR |
7192 | if (status) |
7193 | return 0; | |
7194 | ||
ab50adb6 MR |
7195 | return mips32_instruction_has_delay_slot (gdbarch, insn); |
7196 | } | |
4cc0665f | 7197 | |
ab50adb6 MR |
7198 | /* Return non-zero if the microMIPS instruction INSN, comprising the |
7199 | 16-bit major opcode word in the high 16 bits and any second word | |
7200 | in the low 16 bits, has a branch delay slot (i.e. it is a non-compact | |
7201 | jump or branch instruction). The instruction must be 32-bit if | |
7202 | MUSTBE32 is set or can be any instruction otherwise. */ | |
7203 | ||
7204 | static int | |
7205 | micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32) | |
7206 | { | |
7207 | ULONGEST major = insn >> 16; | |
4cc0665f | 7208 | |
ab50adb6 MR |
7209 | switch (micromips_op (major)) |
7210 | { | |
7211 | /* 16-bit instructions. */ | |
7212 | case 0x33: /* B16: bits 110011 */ | |
7213 | case 0x2b: /* BNEZ16: bits 101011 */ | |
7214 | case 0x23: /* BEQZ16: bits 100011 */ | |
7215 | return !mustbe32; | |
7216 | case 0x11: /* POOL16C: bits 010001 */ | |
7217 | return (!mustbe32 | |
7218 | && ((b5s5_op (major) == 0xc | |
7219 | /* JR16: bits 010001 01100 */ | |
7220 | || (b5s5_op (major) & 0x1e) == 0xe))); | |
7221 | /* JALR16, JALRS16: bits 010001 0111x */ | |
7222 | /* 32-bit instructions. */ | |
7223 | case 0x3d: /* JAL: bits 111101 */ | |
7224 | case 0x3c: /* JALX: bits 111100 */ | |
7225 | case 0x35: /* J: bits 110101 */ | |
7226 | case 0x2d: /* BNE: bits 101101 */ | |
7227 | case 0x25: /* BEQ: bits 100101 */ | |
7228 | case 0x1d: /* JALS: bits 011101 */ | |
7229 | return 1; | |
7230 | case 0x10: /* POOL32I: bits 010000 */ | |
7231 | return ((b5s5_op (major) & 0x1c) == 0x0 | |
4cc0665f | 7232 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ |
ab50adb6 | 7233 | || (b5s5_op (major) & 0x1d) == 0x4 |
4cc0665f | 7234 | /* BLEZ, BGTZ: bits 010000 001x0 */ |
ab50adb6 | 7235 | || (b5s5_op (major) & 0x1d) == 0x11 |
4cc0665f | 7236 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ |
ab50adb6 MR |
7237 | || ((b5s5_op (major) & 0x1e) == 0x14 |
7238 | && (major & 0x3) == 0x0) | |
4cc0665f | 7239 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ |
ab50adb6 | 7240 | || (b5s5_op (major) & 0x1e) == 0x1a |
4cc0665f | 7241 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ |
ab50adb6 MR |
7242 | || ((b5s5_op (major) & 0x1e) == 0x1c |
7243 | && (major & 0x3) == 0x0) | |
4cc0665f | 7244 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ |
ab50adb6 MR |
7245 | || ((b5s5_op (major) & 0x1c) == 0x1c |
7246 | && (major & 0x3) == 0x1)); | |
4cc0665f | 7247 | /* BC1ANY*: bits 010000 111xx xxx01 */ |
ab50adb6 MR |
7248 | case 0x0: /* POOL32A: bits 000000 */ |
7249 | return (b0s6_op (insn) == 0x3c | |
7250 | /* POOL32Axf: bits 000000 ... 111100 */ | |
7251 | && (b6s10_ext (insn) & 0x2bf) == 0x3c); | |
7252 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
7253 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
7254 | default: | |
7255 | return 0; | |
7256 | } | |
4cc0665f MR |
7257 | } |
7258 | ||
ab50adb6 | 7259 | /* Return non-zero if a microMIPS instruction at ADDR has a branch delay |
ae790652 MR |
7260 | slot (i.e. it is a non-compact jump instruction). The instruction |
7261 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ | |
7262 | ||
c8cef75f | 7263 | static int |
ab50adb6 MR |
7264 | micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, |
7265 | CORE_ADDR addr, int mustbe32) | |
c8cef75f | 7266 | { |
ab50adb6 | 7267 | ULONGEST insn; |
c8cef75f | 7268 | int status; |
3f7f3650 | 7269 | int size; |
c8cef75f | 7270 | |
ab50adb6 | 7271 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); |
c8cef75f MR |
7272 | if (status) |
7273 | return 0; | |
3f7f3650 | 7274 | size = mips_insn_size (ISA_MICROMIPS, insn); |
ab50adb6 | 7275 | insn <<= 16; |
3f7f3650 | 7276 | if (size == 2 * MIPS_INSN16_SIZE) |
ab50adb6 MR |
7277 | { |
7278 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
7279 | if (status) | |
7280 | return 0; | |
7281 | } | |
7282 | ||
7283 | return micromips_instruction_has_delay_slot (insn, mustbe32); | |
7284 | } | |
c8cef75f | 7285 | |
ab50adb6 MR |
7286 | /* Return non-zero if the MIPS16 instruction INST, which must be |
7287 | a 32-bit instruction if MUSTBE32 is set or can be any instruction | |
7288 | otherwise, has a branch delay slot (i.e. it is a non-compact jump | |
7289 | instruction). This function is based on mips16_next_pc. */ | |
7290 | ||
7291 | static int | |
7292 | mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32) | |
7293 | { | |
ae790652 MR |
7294 | if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */ |
7295 | return !mustbe32; | |
c8cef75f MR |
7296 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ |
7297 | } | |
7298 | ||
ab50adb6 MR |
7299 | /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay |
7300 | slot (i.e. it is a non-compact jump instruction). The instruction | |
7301 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ | |
7302 | ||
7303 | static int | |
7304 | mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
7305 | CORE_ADDR addr, int mustbe32) | |
7306 | { | |
7307 | unsigned short insn; | |
7308 | int status; | |
7309 | ||
7310 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); | |
7311 | if (status) | |
7312 | return 0; | |
7313 | ||
7314 | return mips16_instruction_has_delay_slot (insn, mustbe32); | |
7315 | } | |
7316 | ||
c8cef75f MR |
7317 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. |
7318 | This assumes KSSEG exists. */ | |
7319 | ||
7320 | static CORE_ADDR | |
7321 | mips_segment_boundary (CORE_ADDR bpaddr) | |
7322 | { | |
7323 | CORE_ADDR mask = CORE_ADDR_MAX; | |
7324 | int segsize; | |
7325 | ||
7326 | if (sizeof (CORE_ADDR) == 8) | |
7327 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid | |
7328 | a compiler warning produced where CORE_ADDR is a 32-bit type even | |
7329 | though in that case this is dead code). */ | |
7330 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) | |
7331 | { | |
7332 | case 3: | |
7333 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) | |
7334 | segsize = 29; /* 32-bit compatibility segment */ | |
7335 | else | |
7336 | segsize = 62; /* xkseg */ | |
7337 | break; | |
7338 | case 2: /* xkphys */ | |
7339 | segsize = 59; | |
7340 | break; | |
7341 | default: /* xksseg (1), xkuseg/kuseg (0) */ | |
7342 | segsize = 62; | |
7343 | break; | |
7344 | } | |
7345 | else if (bpaddr & 0x80000000) /* kernel segment */ | |
7346 | segsize = 29; | |
7347 | else | |
7348 | segsize = 31; /* user segment */ | |
7349 | mask <<= segsize; | |
7350 | return bpaddr & mask; | |
7351 | } | |
7352 | ||
7353 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting | |
7354 | it backwards if necessary. Return the address of the new location. */ | |
7355 | ||
7356 | static CORE_ADDR | |
7357 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
7358 | { | |
22e048c9 | 7359 | CORE_ADDR prev_addr; |
c8cef75f MR |
7360 | CORE_ADDR boundary; |
7361 | CORE_ADDR func_addr; | |
7362 | ||
7363 | /* If a breakpoint is set on the instruction in a branch delay slot, | |
7364 | GDB gets confused. When the breakpoint is hit, the PC isn't on | |
7365 | the instruction in the branch delay slot, the PC will point to | |
7366 | the branch instruction. Since the PC doesn't match any known | |
7367 | breakpoints, GDB reports a trap exception. | |
7368 | ||
7369 | There are two possible fixes for this problem. | |
7370 | ||
7371 | 1) When the breakpoint gets hit, see if the BD bit is set in the | |
7372 | Cause register (which indicates the last exception occurred in a | |
7373 | branch delay slot). If the BD bit is set, fix the PC to point to | |
7374 | the instruction in the branch delay slot. | |
7375 | ||
7376 | 2) When the user sets the breakpoint, don't allow him to set the | |
7377 | breakpoint on the instruction in the branch delay slot. Instead | |
7378 | move the breakpoint to the branch instruction (which will have | |
7379 | the same result). | |
7380 | ||
7381 | The problem with the first solution is that if the user then | |
7382 | single-steps the processor, the branch instruction will get | |
7383 | skipped (since GDB thinks the PC is on the instruction in the | |
7384 | branch delay slot). | |
7385 | ||
7386 | So, we'll use the second solution. To do this we need to know if | |
7387 | the instruction we're trying to set the breakpoint on is in the | |
7388 | branch delay slot. */ | |
7389 | ||
7390 | boundary = mips_segment_boundary (bpaddr); | |
7391 | ||
7392 | /* Make sure we don't scan back before the beginning of the current | |
7393 | function, since we may fetch constant data or insns that look like | |
7394 | a jump. Of course we might do that anyway if the compiler has | |
7395 | moved constants inline. :-( */ | |
7396 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) | |
7397 | && func_addr > boundary && func_addr <= bpaddr) | |
7398 | boundary = func_addr; | |
7399 | ||
4cc0665f | 7400 | if (mips_pc_is_mips (bpaddr)) |
c8cef75f MR |
7401 | { |
7402 | if (bpaddr == boundary) | |
7403 | return bpaddr; | |
7404 | ||
7405 | /* If the previous instruction has a branch delay slot, we have | |
dda83cd7 | 7406 | to move the breakpoint to the branch instruction. */ |
c8cef75f | 7407 | prev_addr = bpaddr - 4; |
ab50adb6 | 7408 | if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr)) |
c8cef75f MR |
7409 | bpaddr = prev_addr; |
7410 | } | |
7411 | else | |
7412 | { | |
ab50adb6 | 7413 | int (*insn_at_pc_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); |
c8cef75f MR |
7414 | CORE_ADDR addr, jmpaddr; |
7415 | int i; | |
7416 | ||
4cc0665f | 7417 | boundary = unmake_compact_addr (boundary); |
c8cef75f MR |
7418 | |
7419 | /* The only MIPS16 instructions with delay slots are JAL, JALX, | |
dda83cd7 SM |
7420 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, |
7421 | so try for that first, then try the 2 byte JALR/JR. | |
7422 | The microMIPS ASE has a whole range of jumps and branches | |
7423 | with delay slots, some of which take 4 bytes and some take | |
7424 | 2 bytes, so the idea is the same. | |
7425 | FIXME: We have to assume that bpaddr is not the second half | |
7426 | of an extended instruction. */ | |
ab50adb6 MR |
7427 | insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) |
7428 | ? micromips_insn_at_pc_has_delay_slot | |
7429 | : mips16_insn_at_pc_has_delay_slot); | |
c8cef75f MR |
7430 | |
7431 | jmpaddr = 0; | |
7432 | addr = bpaddr; | |
7433 | for (i = 1; i < 4; i++) | |
7434 | { | |
4cc0665f | 7435 | if (unmake_compact_addr (addr) == boundary) |
c8cef75f | 7436 | break; |
4cc0665f | 7437 | addr -= MIPS_INSN16_SIZE; |
ab50adb6 | 7438 | if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0)) |
c8cef75f MR |
7439 | /* Looks like a JR/JALR at [target-1], but it could be |
7440 | the second word of a previous JAL/JALX, so record it | |
7441 | and check back one more. */ | |
7442 | jmpaddr = addr; | |
ab50adb6 | 7443 | else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1)) |
c8cef75f MR |
7444 | { |
7445 | if (i == 2) | |
7446 | /* Looks like a JAL/JALX at [target-2], but it could also | |
7447 | be the second word of a previous JAL/JALX, record it, | |
7448 | and check back one more. */ | |
7449 | jmpaddr = addr; | |
7450 | else | |
7451 | /* Looks like a JAL/JALX at [target-3], so any previously | |
7452 | recorded JAL/JALX or JR/JALR must be wrong, because: | |
7453 | ||
7454 | >-3: JAL | |
7455 | -2: JAL-ext (can't be JAL/JALX) | |
7456 | -1: bdslot (can't be JR/JALR) | |
7457 | 0: target insn | |
7458 | ||
7459 | Of course it could be another JAL-ext which looks | |
7460 | like a JAL, but in that case we'd have broken out | |
7461 | of this loop at [target-2]: | |
7462 | ||
7463 | -4: JAL | |
7464 | >-3: JAL-ext | |
7465 | -2: bdslot (can't be jmp) | |
7466 | -1: JR/JALR | |
7467 | 0: target insn */ | |
7468 | jmpaddr = 0; | |
7469 | } | |
7470 | else | |
7471 | { | |
7472 | /* Not a jump instruction: if we're at [target-1] this | |
dda83cd7 SM |
7473 | could be the second word of a JAL/JALX, so continue; |
7474 | otherwise we're done. */ | |
c8cef75f MR |
7475 | if (i > 1) |
7476 | break; | |
7477 | } | |
7478 | } | |
7479 | ||
7480 | if (jmpaddr) | |
7481 | bpaddr = jmpaddr; | |
7482 | } | |
7483 | ||
7484 | return bpaddr; | |
7485 | } | |
7486 | ||
14132e89 MR |
7487 | /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 |
7488 | call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ | |
7489 | ||
7490 | static int | |
7491 | mips_is_stub_suffix (const char *suffix, int zero) | |
7492 | { | |
7493 | switch (suffix[0]) | |
7494 | { | |
7495 | case '0': | |
7496 | return zero && suffix[1] == '\0'; | |
7497 | case '1': | |
7498 | return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); | |
7499 | case '2': | |
7500 | case '5': | |
7501 | case '6': | |
7502 | case '9': | |
7503 | return suffix[1] == '\0'; | |
7504 | default: | |
7505 | return 0; | |
7506 | } | |
7507 | } | |
7508 | ||
7509 | /* Return non-zero if MODE is one of the mode infixes used for MIPS16 | |
7510 | call stubs, one of sf, df, sc, or dc. */ | |
7511 | ||
7512 | static int | |
7513 | mips_is_stub_mode (const char *mode) | |
7514 | { | |
7515 | return ((mode[0] == 's' || mode[0] == 'd') | |
7516 | && (mode[1] == 'f' || mode[1] == 'c')); | |
7517 | } | |
7518 | ||
7519 | /* Code at PC is a compiler-generated stub. Such a stub for a function | |
7520 | bar might have a name like __fn_stub_bar, and might look like this: | |
7521 | ||
7522 | mfc1 $4, $f13 | |
7523 | mfc1 $5, $f12 | |
7524 | mfc1 $6, $f15 | |
7525 | mfc1 $7, $f14 | |
7526 | ||
7527 | followed by (or interspersed with): | |
7528 | ||
7529 | j bar | |
7530 | ||
7531 | or: | |
7532 | ||
7533 | lui $25, %hi(bar) | |
7534 | addiu $25, $25, %lo(bar) | |
7535 | jr $25 | |
7536 | ||
7537 | ($1 may be used in old code; for robustness we accept any register) | |
7538 | or, in PIC code: | |
7539 | ||
7540 | lui $28, %hi(_gp_disp) | |
7541 | addiu $28, $28, %lo(_gp_disp) | |
7542 | addu $28, $28, $25 | |
7543 | lw $25, %got(bar) | |
7544 | addiu $25, $25, %lo(bar) | |
7545 | jr $25 | |
7546 | ||
7547 | In the case of a __call_stub_bar stub, the sequence to set up | |
7548 | arguments might look like this: | |
7549 | ||
7550 | mtc1 $4, $f13 | |
7551 | mtc1 $5, $f12 | |
7552 | mtc1 $6, $f15 | |
7553 | mtc1 $7, $f14 | |
7554 | ||
7555 | followed by (or interspersed with) one of the jump sequences above. | |
7556 | ||
7557 | In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead | |
7558 | of J or JR, respectively, followed by: | |
7559 | ||
7560 | mfc1 $2, $f0 | |
7561 | mfc1 $3, $f1 | |
7562 | jr $18 | |
7563 | ||
7564 | We are at the beginning of the stub here, and scan down and extract | |
7565 | the target address from the jump immediate instruction or, if a jump | |
7566 | register instruction is used, from the register referred. Return | |
7567 | the value of PC calculated or 0 if inconclusive. | |
7568 | ||
7569 | The limit on the search is arbitrarily set to 20 instructions. FIXME. */ | |
7570 | ||
7571 | static CORE_ADDR | |
bd2b40ac | 7572 | mips_get_mips16_fn_stub_pc (frame_info_ptr frame, CORE_ADDR pc) |
14132e89 MR |
7573 | { |
7574 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
7575 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7576 | int addrreg = MIPS_ZERO_REGNUM; | |
7577 | CORE_ADDR start_pc = pc; | |
7578 | CORE_ADDR target_pc = 0; | |
7579 | CORE_ADDR addr = 0; | |
7580 | CORE_ADDR gp = 0; | |
7581 | int status = 0; | |
7582 | int i; | |
7583 | ||
7584 | for (i = 0; | |
7585 | status == 0 && target_pc == 0 && i < 20; | |
7586 | i++, pc += MIPS_INSN32_SIZE) | |
7587 | { | |
4cc0665f | 7588 | ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
14132e89 MR |
7589 | CORE_ADDR imm; |
7590 | int rt; | |
7591 | int rs; | |
7592 | int rd; | |
7593 | ||
7594 | switch (itype_op (inst)) | |
7595 | { | |
7596 | case 0: /* SPECIAL */ | |
7597 | switch (rtype_funct (inst)) | |
7598 | { | |
7599 | case 8: /* JR */ | |
7600 | case 9: /* JALR */ | |
7601 | rs = rtype_rs (inst); | |
7602 | if (rs == MIPS_GP_REGNUM) | |
7603 | target_pc = gp; /* Hmm... */ | |
7604 | else if (rs == addrreg) | |
7605 | target_pc = addr; | |
7606 | break; | |
7607 | ||
7608 | case 0x21: /* ADDU */ | |
7609 | rt = rtype_rt (inst); | |
7610 | rs = rtype_rs (inst); | |
7611 | rd = rtype_rd (inst); | |
7612 | if (rd == MIPS_GP_REGNUM | |
7613 | && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) | |
7614 | || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) | |
7615 | gp += start_pc; | |
7616 | break; | |
7617 | } | |
7618 | break; | |
7619 | ||
7620 | case 2: /* J */ | |
7621 | case 3: /* JAL */ | |
7622 | target_pc = jtype_target (inst) << 2; | |
7623 | target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); | |
7624 | break; | |
7625 | ||
7626 | case 9: /* ADDIU */ | |
7627 | rt = itype_rt (inst); | |
7628 | rs = itype_rs (inst); | |
7629 | if (rt == rs) | |
7630 | { | |
7631 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7632 | if (rt == MIPS_GP_REGNUM) | |
7633 | gp += imm; | |
7634 | else if (rt == addrreg) | |
7635 | addr += imm; | |
7636 | } | |
7637 | break; | |
7638 | ||
7639 | case 0xf: /* LUI */ | |
7640 | rt = itype_rt (inst); | |
7641 | imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; | |
7642 | if (rt == MIPS_GP_REGNUM) | |
7643 | gp = imm; | |
7644 | else if (rt != MIPS_ZERO_REGNUM) | |
7645 | { | |
7646 | addrreg = rt; | |
7647 | addr = imm; | |
7648 | } | |
7649 | break; | |
7650 | ||
7651 | case 0x23: /* LW */ | |
7652 | rt = itype_rt (inst); | |
7653 | rs = itype_rs (inst); | |
7654 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7655 | if (gp != 0 && rs == MIPS_GP_REGNUM) | |
7656 | { | |
7657 | gdb_byte buf[4]; | |
7658 | ||
7659 | memset (buf, 0, sizeof (buf)); | |
7660 | status = target_read_memory (gp + imm, buf, sizeof (buf)); | |
7661 | addrreg = rt; | |
7662 | addr = extract_signed_integer (buf, sizeof (buf), byte_order); | |
7663 | } | |
7664 | break; | |
7665 | } | |
7666 | } | |
7667 | ||
7668 | return target_pc; | |
7669 | } | |
7670 | ||
7671 | /* If PC is in a MIPS16 call or return stub, return the address of the | |
7672 | target PC, which is either the callee or the caller. There are several | |
c906108c SS |
7673 | cases which must be handled: |
7674 | ||
14132e89 MR |
7675 | * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7676 | and the target PC is in $31 ($ra). | |
c906108c | 7677 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
14132e89 MR |
7678 | and the target PC is in $2. |
7679 | * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, | |
7680 | i.e. before the JALR instruction, this is effectively a call stub | |
7681 | and the target PC is in $2. Otherwise this is effectively | |
7682 | a return stub and the target PC is in $18. | |
7683 | * If the PC is at the start of __call_stub_fp_*, i.e. before the | |
7684 | JAL or JALR instruction, this is effectively a call stub and the | |
7685 | target PC is buried in the instruction stream. Otherwise this | |
7686 | is effectively a return stub and the target PC is in $18. | |
7687 | * If the PC is in __call_stub_* or in __fn_stub_*, this is a call | |
7688 | stub and the target PC is buried in the instruction stream. | |
7689 | ||
7690 | See the source code for the stubs in gcc/config/mips/mips16.S, or the | |
7691 | stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the | |
e7d6a6d2 | 7692 | gory details. */ |
c906108c | 7693 | |
757a7cc6 | 7694 | static CORE_ADDR |
bd2b40ac | 7695 | mips_skip_mips16_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) |
c906108c | 7696 | { |
e17a4113 | 7697 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 7698 | CORE_ADDR start_addr; |
14132e89 MR |
7699 | const char *name; |
7700 | size_t prefixlen; | |
c906108c SS |
7701 | |
7702 | /* Find the starting address and name of the function containing the PC. */ | |
7703 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
7704 | return 0; | |
7705 | ||
14132e89 MR |
7706 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7707 | and the target PC is in $31 ($ra). */ | |
7708 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7709 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7710 | && mips_is_stub_mode (name + prefixlen) | |
7711 | && name[prefixlen + 2] == '\0') | |
7712 | return get_frame_register_signed | |
7713 | (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
7714 | ||
7715 | /* If the PC is in __mips16_call_stub_*, this is one of the call | |
7716 | call/return stubs. */ | |
7717 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7718 | if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) | |
c906108c SS |
7719 | { |
7720 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
dda83cd7 | 7721 | and the target PC is in $2. */ |
14132e89 MR |
7722 | if (mips_is_stub_suffix (name + prefixlen, 0)) |
7723 | return get_frame_register_signed | |
7724 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c | 7725 | |
14132e89 | 7726 | /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
dda83cd7 SM |
7727 | i.e. before the JALR instruction, this is effectively a call stub |
7728 | and the target PC is in $2. Otherwise this is effectively | |
7729 | a return stub and the target PC is in $18. */ | |
14132e89 MR |
7730 | else if (mips_is_stub_mode (name + prefixlen) |
7731 | && name[prefixlen + 2] == '_' | |
7732 | && mips_is_stub_suffix (name + prefixlen + 3, 0)) | |
c906108c SS |
7733 | { |
7734 | if (pc == start_addr) | |
14132e89 MR |
7735 | /* This is the 'call' part of a call stub. The return |
7736 | address is in $2. */ | |
7737 | return get_frame_register_signed | |
7738 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c SS |
7739 | else |
7740 | /* This is the 'return' part of a call stub. The return | |
14132e89 MR |
7741 | address is in $18. */ |
7742 | return get_frame_register_signed | |
7743 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7744 | } |
14132e89 MR |
7745 | else |
7746 | return 0; /* Not a stub. */ | |
7747 | } | |
7748 | ||
7749 | /* If the PC is in __call_stub_* or __fn_stub*, this is one of the | |
7750 | compiler-generated call or call/return stubs. */ | |
61012eef GB |
7751 | if (startswith (name, mips_str_fn_stub) |
7752 | || startswith (name, mips_str_call_stub)) | |
14132e89 MR |
7753 | { |
7754 | if (pc == start_addr) | |
7755 | /* This is the 'call' part of a call stub. Call this helper | |
7756 | to scan through this code for interesting instructions | |
7757 | and determine the final PC. */ | |
7758 | return mips_get_mips16_fn_stub_pc (frame, pc); | |
7759 | else | |
7760 | /* This is the 'return' part of a call stub. The return address | |
7761 | is in $18. */ | |
7762 | return get_frame_register_signed | |
7763 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7764 | } |
14132e89 MR |
7765 | |
7766 | return 0; /* Not a stub. */ | |
7767 | } | |
7768 | ||
7769 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
7770 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
7771 | ||
7772 | static int | |
7773 | mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) | |
7774 | { | |
7775 | CORE_ADDR start_addr; | |
7776 | size_t prefixlen; | |
7777 | ||
7778 | /* Find the starting address of the function containing the PC. */ | |
7779 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
7780 | return 0; | |
7781 | ||
7782 | /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at | |
7783 | the start, i.e. after the JALR instruction, this is effectively | |
7784 | a return stub. */ | |
7785 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7786 | if (pc != start_addr | |
7787 | && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 | |
7788 | && mips_is_stub_mode (name + prefixlen) | |
7789 | && name[prefixlen + 2] == '_' | |
7790 | && mips_is_stub_suffix (name + prefixlen + 3, 1)) | |
7791 | return 1; | |
7792 | ||
7793 | /* If the PC is in __call_stub_fp_* but not at the start, i.e. after | |
7794 | the JAL or JALR instruction, this is effectively a return stub. */ | |
7795 | prefixlen = strlen (mips_str_call_fp_stub); | |
7796 | if (pc != start_addr | |
7797 | && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) | |
7798 | return 1; | |
7799 | ||
7800 | /* Consume the .pic. prefix of any PIC stub, this function must return | |
7801 | true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub | |
7802 | or the call stub path will trigger in handle_inferior_event causing | |
7803 | it to go astray. */ | |
7804 | prefixlen = strlen (mips_str_pic); | |
7805 | if (strncmp (name, mips_str_pic, prefixlen) == 0) | |
7806 | name += prefixlen; | |
7807 | ||
7808 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ | |
7809 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7810 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7811 | && mips_is_stub_mode (name + prefixlen) | |
7812 | && name[prefixlen + 2] == '\0') | |
7813 | return 1; | |
7814 | ||
7815 | return 0; /* Not a stub. */ | |
c906108c SS |
7816 | } |
7817 | ||
db5f024e DJ |
7818 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
7819 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
7820 | so that $t9 has the correct value at function entry. */ | |
7821 | ||
7822 | static CORE_ADDR | |
bd2b40ac | 7823 | mips_skip_pic_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) |
db5f024e | 7824 | { |
e17a4113 UW |
7825 | struct gdbarch *gdbarch = get_frame_arch (frame); |
7826 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7cbd4a93 | 7827 | struct bound_minimal_symbol msym; |
db5f024e DJ |
7828 | int i; |
7829 | gdb_byte stub_code[16]; | |
7830 | int32_t stub_words[4]; | |
7831 | ||
7832 | /* The stub for foo is named ".pic.foo", and is either two | |
7833 | instructions inserted before foo or a three instruction sequence | |
7834 | which jumps to foo. */ | |
7835 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 7836 | if (msym.minsym == NULL |
4aeddc50 | 7837 | || msym.value_address () != pc |
c9d95fa3 CB |
7838 | || msym.minsym->linkage_name () == NULL |
7839 | || !startswith (msym.minsym->linkage_name (), ".pic.")) | |
db5f024e DJ |
7840 | return 0; |
7841 | ||
7842 | /* A two-instruction header. */ | |
5bbfd12d | 7843 | if (msym.minsym->size () == 8) |
db5f024e DJ |
7844 | return pc + 8; |
7845 | ||
7846 | /* A three-instruction (plus delay slot) trampoline. */ | |
5bbfd12d | 7847 | if (msym.minsym->size () == 16) |
db5f024e DJ |
7848 | { |
7849 | if (target_read_memory (pc, stub_code, 16) != 0) | |
7850 | return 0; | |
7851 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
7852 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
7853 | 4, byte_order); | |
db5f024e DJ |
7854 | |
7855 | /* A stub contains these instructions: | |
7856 | lui t9, %hi(target) | |
7857 | j target | |
7858 | addiu t9, t9, %lo(target) | |
7859 | nop | |
7860 | ||
7861 | This works even for N64, since stubs are only generated with | |
7862 | -msym32. */ | |
7863 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
7864 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
7865 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
7866 | && stub_words[3] == 0x00000000) | |
34b192ce MR |
7867 | return ((((stub_words[0] & 0x0000ffff) << 16) |
7868 | + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; | |
db5f024e DJ |
7869 | } |
7870 | ||
7871 | /* Not a recognized stub. */ | |
7872 | return 0; | |
7873 | } | |
7874 | ||
7875 | static CORE_ADDR | |
bd2b40ac | 7876 | mips_skip_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) |
db5f024e | 7877 | { |
14132e89 | 7878 | CORE_ADDR requested_pc = pc; |
db5f024e | 7879 | CORE_ADDR target_pc; |
14132e89 MR |
7880 | CORE_ADDR new_pc; |
7881 | ||
7882 | do | |
7883 | { | |
7884 | target_pc = pc; | |
db5f024e | 7885 | |
14132e89 MR |
7886 | new_pc = mips_skip_mips16_trampoline_code (frame, pc); |
7887 | if (new_pc) | |
3e29f34a | 7888 | pc = new_pc; |
db5f024e | 7889 | |
14132e89 MR |
7890 | new_pc = find_solib_trampoline_target (frame, pc); |
7891 | if (new_pc) | |
3e29f34a | 7892 | pc = new_pc; |
db5f024e | 7893 | |
14132e89 MR |
7894 | new_pc = mips_skip_pic_trampoline_code (frame, pc); |
7895 | if (new_pc) | |
3e29f34a | 7896 | pc = new_pc; |
14132e89 MR |
7897 | } |
7898 | while (pc != target_pc); | |
db5f024e | 7899 | |
14132e89 | 7900 | return pc != requested_pc ? pc : 0; |
db5f024e DJ |
7901 | } |
7902 | ||
a4b8ebc8 | 7903 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 7904 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7905 | |
7906 | static int | |
d3f73121 | 7907 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7908 | { |
a4b8ebc8 | 7909 | int regnum; |
2f38ef89 | 7910 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7911 | regnum = num; |
2f38ef89 | 7912 | else if (num >= 38 && num < 70) |
d3f73121 | 7913 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 7914 | else if (num == 70) |
d3f73121 | 7915 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7916 | else if (num == 71) |
d3f73121 | 7917 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7918 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
7919 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; | |
2f38ef89 | 7920 | else |
0fde2c53 | 7921 | return -1; |
d3f73121 | 7922 | return gdbarch_num_regs (gdbarch) + regnum; |
88c72b7d AC |
7923 | } |
7924 | ||
2f38ef89 | 7925 | |
a4b8ebc8 | 7926 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 7927 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7928 | |
7929 | static int | |
d3f73121 | 7930 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7931 | { |
a4b8ebc8 | 7932 | int regnum; |
2f38ef89 | 7933 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7934 | regnum = num; |
2f38ef89 | 7935 | else if (num >= 32 && num < 64) |
d3f73121 | 7936 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 7937 | else if (num == 64) |
d3f73121 | 7938 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7939 | else if (num == 65) |
d3f73121 | 7940 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7941 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
7942 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; | |
2f38ef89 | 7943 | else |
0fde2c53 | 7944 | return -1; |
d3f73121 | 7945 | return gdbarch_num_regs (gdbarch) + regnum; |
a4b8ebc8 AC |
7946 | } |
7947 | ||
7948 | static int | |
e7faf938 | 7949 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
7950 | { |
7951 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 7952 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
7953 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
7954 | decide if it is valid. Should instead define a standard sim/gdb | |
7955 | register numbering scheme. */ | |
e7faf938 | 7956 | if (gdbarch_register_name (gdbarch, |
637b2f86 | 7957 | gdbarch_num_regs (gdbarch) + regnum)[0] != '\0') |
a4b8ebc8 AC |
7958 | return regnum; |
7959 | else | |
6d82d43b | 7960 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
7961 | } |
7962 | ||
2f38ef89 | 7963 | |
4844f454 CV |
7964 | /* Convert an integer into an address. Extracting the value signed |
7965 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
7966 | |
7967 | static CORE_ADDR | |
79dd2d24 | 7968 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 7969 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 7970 | { |
e17a4113 | 7971 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
df86565b | 7972 | return extract_signed_integer (buf, type->length (), byte_order); |
fc0c74b1 AC |
7973 | } |
7974 | ||
82e91389 DJ |
7975 | /* Dummy virtual frame pointer method. This is no more or less accurate |
7976 | than most other architectures; we just need to be explicit about it, | |
7977 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
7978 | an assertion failure. */ | |
7979 | ||
7980 | static void | |
a54fba4c MD |
7981 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
7982 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
7983 | { |
7984 | *reg = MIPS_SP_REGNUM; | |
7985 | *offset = 0; | |
7986 | } | |
7987 | ||
caaa3122 DJ |
7988 | static void |
7989 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
7990 | { | |
7991 | enum mips_abi *abip = (enum mips_abi *) obj; | |
fd361982 | 7992 | const char *name = bfd_section_name (sect); |
caaa3122 DJ |
7993 | |
7994 | if (*abip != MIPS_ABI_UNKNOWN) | |
7995 | return; | |
7996 | ||
61012eef | 7997 | if (!startswith (name, ".mdebug.")) |
caaa3122 DJ |
7998 | return; |
7999 | ||
8000 | if (strcmp (name, ".mdebug.abi32") == 0) | |
8001 | *abip = MIPS_ABI_O32; | |
8002 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
8003 | *abip = MIPS_ABI_N32; | |
62a49b2c | 8004 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 8005 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
8006 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
8007 | *abip = MIPS_ABI_O64; | |
8008 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
8009 | *abip = MIPS_ABI_EABI32; | |
8010 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
8011 | *abip = MIPS_ABI_EABI64; | |
8012 | else | |
8a3fe4f8 | 8013 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
8014 | } |
8015 | ||
22e47e37 FF |
8016 | static void |
8017 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
8018 | { | |
8019 | int *lbp = (int *) obj; | |
fd361982 | 8020 | const char *name = bfd_section_name (sect); |
22e47e37 | 8021 | |
61012eef | 8022 | if (startswith (name, ".gcc_compiled_long32")) |
22e47e37 | 8023 | *lbp = 32; |
61012eef | 8024 | else if (startswith (name, ".gcc_compiled_long64")) |
22e47e37 | 8025 | *lbp = 64; |
61012eef | 8026 | else if (startswith (name, ".gcc_compiled_long")) |
22e47e37 FF |
8027 | warning (_("unrecognized .gcc_compiled_longXX")); |
8028 | } | |
8029 | ||
2e4ebe70 DJ |
8030 | static enum mips_abi |
8031 | global_mips_abi (void) | |
8032 | { | |
8033 | int i; | |
8034 | ||
8035 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
8036 | if (mips_abi_strings[i] == mips_abi_string) | |
8037 | return (enum mips_abi) i; | |
8038 | ||
f34652de | 8039 | internal_error (_("unknown ABI string")); |
2e4ebe70 DJ |
8040 | } |
8041 | ||
4cc0665f MR |
8042 | /* Return the default compressed instruction set, either of MIPS16 |
8043 | or microMIPS, selected when none could have been determined from | |
8044 | the ELF header of the binary being executed (or no binary has been | |
8045 | selected. */ | |
8046 | ||
8047 | static enum mips_isa | |
8048 | global_mips_compression (void) | |
8049 | { | |
8050 | int i; | |
8051 | ||
8052 | for (i = 0; mips_compression_strings[i] != NULL; i++) | |
8053 | if (mips_compression_strings[i] == mips_compression_string) | |
8054 | return (enum mips_isa) i; | |
8055 | ||
f34652de | 8056 | internal_error (_("unknown compressed ISA string")); |
4cc0665f MR |
8057 | } |
8058 | ||
29709017 DJ |
8059 | static void |
8060 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
8061 | { | |
29709017 DJ |
8062 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
8063 | assume that's what we've got. */ | |
4eb0ad19 DJ |
8064 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
8065 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
8066 | |
8067 | /* If the size matches the full set of registers GDB traditionally | |
8068 | knows about, including floating point, for either 32-bit or | |
8069 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
8070 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
8071 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
8072 | |
8073 | /* Otherwise we don't have a useful guess. */ | |
8074 | } | |
8075 | ||
f8b73d13 | 8076 | static struct value * |
bd2b40ac | 8077 | value_of_mips_user_reg (frame_info_ptr frame, const void *baton) |
f8b73d13 | 8078 | { |
19ba03f4 | 8079 | const int *reg_p = (const int *) baton; |
a7952927 | 8080 | return value_of_register (*reg_p, get_next_frame_sentinel_okay (frame)); |
f8b73d13 DJ |
8081 | } |
8082 | ||
c2d11a7d | 8083 | static struct gdbarch * |
6d82d43b | 8084 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 8085 | { |
c2d11a7d | 8086 | int elf_flags; |
2e4ebe70 | 8087 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 8088 | int i, num_regs; |
8d5838b5 | 8089 | enum mips_fpu_type fpu_type; |
c1e1314d | 8090 | tdesc_arch_data_up tdesc_data; |
d929bc19 | 8091 | int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY; |
27087b7f | 8092 | const char * const *reg_names; |
1faeff08 | 8093 | struct mips_regnum mips_regnum, *regnum; |
4cc0665f | 8094 | enum mips_isa mips_isa; |
1faeff08 MR |
8095 | int dspacc; |
8096 | int dspctl; | |
8097 | ||
ec03c1ac AC |
8098 | /* First of all, extract the elf_flags, if available. */ |
8099 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8100 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 | 8101 | else if (arches != NULL) |
345bd07c SM |
8102 | { |
8103 | mips_gdbarch_tdep *tdep | |
08106042 | 8104 | = gdbarch_tdep<mips_gdbarch_tdep> (arches->gdbarch); |
345bd07c SM |
8105 | elf_flags = tdep->elf_flags; |
8106 | } | |
ec03c1ac AC |
8107 | else |
8108 | elf_flags = 0; | |
8109 | if (gdbarch_debug) | |
6cb06a8c TT |
8110 | gdb_printf (gdb_stdlog, |
8111 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); | |
c2d11a7d | 8112 | |
102182a9 | 8113 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
8114 | switch ((elf_flags & EF_MIPS_ABI)) |
8115 | { | |
66cf4294 | 8116 | case EF_MIPS_ABI_O32: |
ec03c1ac | 8117 | found_abi = MIPS_ABI_O32; |
0dadbba0 | 8118 | break; |
66cf4294 | 8119 | case EF_MIPS_ABI_O64: |
ec03c1ac | 8120 | found_abi = MIPS_ABI_O64; |
0dadbba0 | 8121 | break; |
66cf4294 | 8122 | case EF_MIPS_ABI_EABI32: |
ec03c1ac | 8123 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 | 8124 | break; |
66cf4294 | 8125 | case EF_MIPS_ABI_EABI64: |
ec03c1ac | 8126 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
8127 | break; |
8128 | default: | |
acdb74a0 | 8129 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 8130 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 8131 | else |
ec03c1ac | 8132 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
8133 | break; |
8134 | } | |
acdb74a0 | 8135 | |
caaa3122 | 8136 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
8137 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
8138 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 8139 | |
dc305454 | 8140 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
8141 | MIPS architecture (if there is one). */ |
8142 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
345bd07c SM |
8143 | { |
8144 | mips_gdbarch_tdep *tdep | |
08106042 | 8145 | = gdbarch_tdep<mips_gdbarch_tdep> (arches->gdbarch); |
345bd07c SM |
8146 | found_abi = tdep->found_abi; |
8147 | } | |
2e4ebe70 | 8148 | |
32a6503c | 8149 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 8150 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
8151 | && info.bfd_arch_info != NULL |
8152 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8153 | { | |
8154 | switch (info.bfd_arch_info->mach) | |
8155 | { | |
8156 | case bfd_mach_mips3900: | |
ec03c1ac | 8157 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
8158 | break; |
8159 | case bfd_mach_mips4100: | |
8160 | case bfd_mach_mips5000: | |
ec03c1ac | 8161 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 8162 | break; |
1d06468c EZ |
8163 | case bfd_mach_mips8000: |
8164 | case bfd_mach_mips10000: | |
32a6503c KB |
8165 | /* On Irix, ELF64 executables use the N64 ABI. The |
8166 | pseudo-sections which describe the ABI aren't present | |
8167 | on IRIX. (Even for executables created by gcc.) */ | |
e6c2f47b PA |
8168 | if (info.abfd != NULL |
8169 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
28d169de | 8170 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) |
ec03c1ac | 8171 | found_abi = MIPS_ABI_N64; |
28d169de | 8172 | else |
ec03c1ac | 8173 | found_abi = MIPS_ABI_N32; |
1d06468c | 8174 | break; |
bf64bfd6 AC |
8175 | } |
8176 | } | |
2e4ebe70 | 8177 | |
26c53e50 DJ |
8178 | /* Default 64-bit objects to N64 instead of O32. */ |
8179 | if (found_abi == MIPS_ABI_UNKNOWN | |
8180 | && info.abfd != NULL | |
8181 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
8182 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
8183 | found_abi = MIPS_ABI_N64; | |
8184 | ||
ec03c1ac | 8185 | if (gdbarch_debug) |
6cb06a8c TT |
8186 | gdb_printf (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", |
8187 | found_abi); | |
ec03c1ac AC |
8188 | |
8189 | /* What has the user specified from the command line? */ | |
8190 | wanted_abi = global_mips_abi (); | |
8191 | if (gdbarch_debug) | |
6cb06a8c TT |
8192 | gdb_printf (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", |
8193 | wanted_abi); | |
2e4ebe70 DJ |
8194 | |
8195 | /* Now that we have found what the ABI for this binary would be, | |
8196 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
8197 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
8198 | mips_abi = wanted_abi; | |
ec03c1ac AC |
8199 | else if (found_abi != MIPS_ABI_UNKNOWN) |
8200 | mips_abi = found_abi; | |
8201 | else | |
8202 | mips_abi = MIPS_ABI_O32; | |
8203 | if (gdbarch_debug) | |
6cb06a8c TT |
8204 | gdb_printf (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", |
8205 | mips_abi); | |
2e4ebe70 | 8206 | |
c5196c92 MR |
8207 | /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */ |
8208 | if (mips_abi != MIPS_ABI_EABI32 | |
8209 | && mips_abi != MIPS_ABI_O32 | |
8210 | && info.bfd_arch_info != NULL | |
8211 | && info.bfd_arch_info->arch == bfd_arch_mips | |
8212 | && info.bfd_arch_info->bits_per_word < 64) | |
8213 | info.bfd_arch_info = bfd_lookup_arch (bfd_arch_mips, bfd_mach_mips4000); | |
8214 | ||
4cc0665f MR |
8215 | /* Determine the default compressed ISA. */ |
8216 | if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 | |
8217 | && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) | |
8218 | mips_isa = ISA_MICROMIPS; | |
8219 | else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 | |
8220 | && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) | |
8221 | mips_isa = ISA_MIPS16; | |
8222 | else | |
8223 | mips_isa = global_mips_compression (); | |
8224 | mips_compression_string = mips_compression_strings[mips_isa]; | |
8225 | ||
ec03c1ac | 8226 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 8227 | if (gdbarch_debug) |
6cb06a8c TT |
8228 | gdb_printf (gdb_stdlog, |
8229 | "mips_gdbarch_init: " | |
8230 | "mips64_transfers_32bit_regs_p = %d\n", | |
8231 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 8232 | |
8d5838b5 | 8233 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
8234 | #ifdef HAVE_ELF |
8235 | if (info.abfd | |
8236 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8237 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
8238 | Tag_GNU_MIPS_ABI_FP); | |
8239 | #endif /* HAVE_ELF */ | |
8240 | ||
8d5838b5 AC |
8241 | if (!mips_fpu_type_auto) |
8242 | fpu_type = mips_fpu_type; | |
d929bc19 | 8243 | else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY) |
609ca2b9 DJ |
8244 | { |
8245 | switch (elf_fpu_type) | |
8246 | { | |
d929bc19 | 8247 | case Val_GNU_MIPS_ABI_FP_DOUBLE: |
609ca2b9 DJ |
8248 | fpu_type = MIPS_FPU_DOUBLE; |
8249 | break; | |
d929bc19 | 8250 | case Val_GNU_MIPS_ABI_FP_SINGLE: |
609ca2b9 DJ |
8251 | fpu_type = MIPS_FPU_SINGLE; |
8252 | break; | |
d929bc19 | 8253 | case Val_GNU_MIPS_ABI_FP_SOFT: |
609ca2b9 DJ |
8254 | default: |
8255 | /* Soft float or unknown. */ | |
8256 | fpu_type = MIPS_FPU_NONE; | |
8257 | break; | |
8258 | } | |
8259 | } | |
8d5838b5 AC |
8260 | else if (info.bfd_arch_info != NULL |
8261 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8262 | switch (info.bfd_arch_info->mach) | |
8263 | { | |
8264 | case bfd_mach_mips3900: | |
8265 | case bfd_mach_mips4100: | |
8266 | case bfd_mach_mips4111: | |
a9d61c86 | 8267 | case bfd_mach_mips4120: |
8d5838b5 AC |
8268 | fpu_type = MIPS_FPU_NONE; |
8269 | break; | |
8270 | case bfd_mach_mips4650: | |
8271 | fpu_type = MIPS_FPU_SINGLE; | |
8272 | break; | |
8273 | default: | |
8274 | fpu_type = MIPS_FPU_DOUBLE; | |
8275 | break; | |
8276 | } | |
8277 | else if (arches != NULL) | |
345bd07c | 8278 | fpu_type = mips_get_fpu_type (arches->gdbarch); |
8d5838b5 AC |
8279 | else |
8280 | fpu_type = MIPS_FPU_DOUBLE; | |
8281 | if (gdbarch_debug) | |
6cb06a8c TT |
8282 | gdb_printf (gdb_stdlog, |
8283 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); | |
8d5838b5 | 8284 | |
29709017 DJ |
8285 | /* Check for blatant incompatibilities. */ |
8286 | ||
8287 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
8288 | ABI. */ | |
8289 | if (info.target_desc | |
8290 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
8291 | && mips_abi != MIPS_ABI_EABI32 | |
8292 | && mips_abi != MIPS_ABI_O32) | |
37c33887 MR |
8293 | return NULL; |
8294 | ||
8295 | /* Fill in the OS dependent register numbers and names. */ | |
8296 | if (info.osabi == GDB_OSABI_LINUX) | |
f8b73d13 | 8297 | { |
37c33887 MR |
8298 | mips_regnum.fp0 = 38; |
8299 | mips_regnum.pc = 37; | |
8300 | mips_regnum.cause = 36; | |
8301 | mips_regnum.badvaddr = 35; | |
8302 | mips_regnum.hi = 34; | |
8303 | mips_regnum.lo = 33; | |
8304 | mips_regnum.fp_control_status = 70; | |
8305 | mips_regnum.fp_implementation_revision = 71; | |
8306 | mips_regnum.dspacc = -1; | |
8307 | mips_regnum.dspctl = -1; | |
8308 | dspacc = 72; | |
8309 | dspctl = 78; | |
8310 | num_regs = 90; | |
8311 | reg_names = mips_linux_reg_names; | |
8312 | } | |
8313 | else | |
8314 | { | |
8315 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; | |
8316 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; | |
8317 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
8318 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; | |
8319 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; | |
8320 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; | |
8321 | mips_regnum.fp_control_status = 70; | |
8322 | mips_regnum.fp_implementation_revision = 71; | |
8323 | mips_regnum.dspacc = dspacc = -1; | |
8324 | mips_regnum.dspctl = dspctl = -1; | |
8325 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
8326 | if (info.bfd_arch_info != NULL | |
dda83cd7 SM |
8327 | && info.bfd_arch_info->mach == bfd_mach_mips3900) |
8328 | reg_names = mips_tx39_reg_names; | |
37c33887 | 8329 | else |
dda83cd7 | 8330 | reg_names = mips_generic_reg_names; |
37c33887 MR |
8331 | } |
8332 | ||
8333 | /* Check any target description for validity. */ | |
8334 | if (tdesc_has_registers (info.target_desc)) | |
8335 | { | |
8336 | static const char *const mips_gprs[] = { | |
8337 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
8338 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
8339 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
8340 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
8341 | }; | |
8342 | static const char *const mips_fprs[] = { | |
8343 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
8344 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
8345 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
8346 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
8347 | }; | |
8348 | ||
8349 | const struct tdesc_feature *feature; | |
8350 | int valid_p; | |
8351 | ||
8352 | feature = tdesc_find_feature (info.target_desc, | |
8353 | "org.gnu.gdb.mips.cpu"); | |
8354 | if (feature == NULL) | |
8355 | return NULL; | |
8356 | ||
8357 | tdesc_data = tdesc_data_alloc (); | |
8358 | ||
8359 | valid_p = 1; | |
8360 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
c1e1314d | 8361 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
37c33887 MR |
8362 | mips_gprs[i]); |
8363 | ||
8364 | ||
c1e1314d | 8365 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8366 | mips_regnum.lo, "lo"); |
c1e1314d | 8367 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8368 | mips_regnum.hi, "hi"); |
c1e1314d | 8369 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8370 | mips_regnum.pc, "pc"); |
8371 | ||
8372 | if (!valid_p) | |
c1e1314d | 8373 | return NULL; |
37c33887 MR |
8374 | |
8375 | feature = tdesc_find_feature (info.target_desc, | |
8376 | "org.gnu.gdb.mips.cp0"); | |
8377 | if (feature == NULL) | |
c1e1314d | 8378 | return NULL; |
37c33887 MR |
8379 | |
8380 | valid_p = 1; | |
c1e1314d | 8381 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8382 | mips_regnum.badvaddr, "badvaddr"); |
c1e1314d | 8383 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8384 | MIPS_PS_REGNUM, "status"); |
c1e1314d | 8385 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8386 | mips_regnum.cause, "cause"); |
8387 | ||
8388 | if (!valid_p) | |
c1e1314d | 8389 | return NULL; |
37c33887 MR |
8390 | |
8391 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
8392 | backend is not prepared for that, though. */ | |
8393 | feature = tdesc_find_feature (info.target_desc, | |
8394 | "org.gnu.gdb.mips.fpu"); | |
8395 | if (feature == NULL) | |
c1e1314d | 8396 | return NULL; |
37c33887 MR |
8397 | |
8398 | valid_p = 1; | |
8399 | for (i = 0; i < 32; i++) | |
c1e1314d | 8400 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8401 | i + mips_regnum.fp0, mips_fprs[i]); |
8402 | ||
c1e1314d | 8403 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8404 | mips_regnum.fp_control_status, |
8405 | "fcsr"); | |
8406 | valid_p | |
c1e1314d | 8407 | &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8408 | mips_regnum.fp_implementation_revision, |
8409 | "fir"); | |
8410 | ||
8411 | if (!valid_p) | |
c1e1314d | 8412 | return NULL; |
37c33887 MR |
8413 | |
8414 | num_regs = mips_regnum.fp_implementation_revision + 1; | |
8415 | ||
8416 | if (dspacc >= 0) | |
8417 | { | |
8418 | feature = tdesc_find_feature (info.target_desc, | |
8419 | "org.gnu.gdb.mips.dsp"); | |
8420 | /* The DSP registers are optional; it's OK if they are absent. */ | |
8421 | if (feature != NULL) | |
8422 | { | |
8423 | i = 0; | |
8424 | valid_p = 1; | |
c1e1314d | 8425 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8426 | dspacc + i++, "hi1"); |
c1e1314d | 8427 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8428 | dspacc + i++, "lo1"); |
c1e1314d | 8429 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8430 | dspacc + i++, "hi2"); |
c1e1314d | 8431 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8432 | dspacc + i++, "lo2"); |
c1e1314d | 8433 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8434 | dspacc + i++, "hi3"); |
c1e1314d | 8435 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8436 | dspacc + i++, "lo3"); |
8437 | ||
c1e1314d | 8438 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8439 | dspctl, "dspctl"); |
8440 | ||
8441 | if (!valid_p) | |
c1e1314d | 8442 | return NULL; |
37c33887 MR |
8443 | |
8444 | mips_regnum.dspacc = dspacc; | |
8445 | mips_regnum.dspctl = dspctl; | |
8446 | ||
8447 | num_regs = mips_regnum.dspctl + 1; | |
8448 | } | |
8449 | } | |
8450 | ||
8451 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
8452 | when only 32-bit registers are provided. */ | |
8453 | reg_names = NULL; | |
f8b73d13 | 8454 | } |
29709017 | 8455 | |
025bb325 | 8456 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
8457 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
8458 | arches != NULL; | |
8459 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
8460 | { | |
345bd07c | 8461 | mips_gdbarch_tdep *tdep |
08106042 | 8462 | = gdbarch_tdep<mips_gdbarch_tdep> (arches->gdbarch); |
345bd07c | 8463 | |
d54398a7 | 8464 | /* MIPS needs to be pedantic about which ABI and the compressed |
dda83cd7 | 8465 | ISA variation the object is using. */ |
345bd07c | 8466 | if (tdep->elf_flags != elf_flags) |
c2d11a7d | 8467 | continue; |
345bd07c | 8468 | if (tdep->mips_abi != mips_abi) |
0dadbba0 | 8469 | continue; |
345bd07c | 8470 | if (tdep->mips_isa != mips_isa) |
d54398a7 | 8471 | continue; |
719ec221 | 8472 | /* Need to be pedantic about which register virtual size is |
dda83cd7 | 8473 | used. */ |
345bd07c | 8474 | if (tdep->mips64_transfers_32bit_regs_p |
719ec221 AC |
8475 | != mips64_transfers_32bit_regs_p) |
8476 | continue; | |
8d5838b5 | 8477 | /* Be pedantic about which FPU is selected. */ |
345bd07c | 8478 | if (mips_get_fpu_type (arches->gdbarch) != fpu_type) |
8d5838b5 | 8479 | continue; |
f8b73d13 | 8480 | |
4be87837 | 8481 | return arches->gdbarch; |
c2d11a7d JM |
8482 | } |
8483 | ||
102182a9 | 8484 | /* Need a new architecture. Fill in a target specific vector. */ |
2b16913c SM |
8485 | gdbarch *gdbarch |
8486 | = gdbarch_alloc (&info, gdbarch_tdep_up (new mips_gdbarch_tdep)); | |
8487 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); | |
8488 | ||
c2d11a7d | 8489 | tdep->elf_flags = elf_flags; |
719ec221 | 8490 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
8491 | tdep->found_abi = found_abi; |
8492 | tdep->mips_abi = mips_abi; | |
4cc0665f | 8493 | tdep->mips_isa = mips_isa; |
8d5838b5 | 8494 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
8495 | tdep->register_size_valid_p = 0; |
8496 | tdep->register_size = 0; | |
8497 | ||
8498 | if (info.target_desc) | |
8499 | { | |
8500 | /* Some useful properties can be inferred from the target. */ | |
8501 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
8502 | { | |
8503 | tdep->register_size_valid_p = 1; | |
8504 | tdep->register_size = 4; | |
8505 | } | |
8506 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
8507 | { | |
8508 | tdep->register_size_valid_p = 1; | |
8509 | tdep->register_size = 8; | |
8510 | } | |
8511 | } | |
c2d11a7d | 8512 | |
102182a9 | 8513 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
8514 | set_gdbarch_short_bit (gdbarch, 16); |
8515 | set_gdbarch_int_bit (gdbarch, 32); | |
8516 | set_gdbarch_float_bit (gdbarch, 32); | |
8517 | set_gdbarch_double_bit (gdbarch, 64); | |
8518 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
8519 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
8520 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
7f0f3b0f SM |
8521 | set_gdbarch_deprecated_pseudo_register_write (gdbarch, |
8522 | mips_pseudo_register_write); | |
1d06468c | 8523 | |
175ff332 HZ |
8524 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8525 | mips_ax_pseudo_register_collect); | |
8526 | set_gdbarch_ax_pseudo_register_push_stack | |
8527 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
8528 | ||
6d82d43b | 8529 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 | 8530 | mips_elf_make_msymbol_special); |
3e29f34a MR |
8531 | set_gdbarch_make_symbol_special (gdbarch, mips_make_symbol_special); |
8532 | set_gdbarch_adjust_dwarf2_addr (gdbarch, mips_adjust_dwarf2_addr); | |
8533 | set_gdbarch_adjust_dwarf2_line (gdbarch, mips_adjust_dwarf2_line); | |
f7ab6ec6 | 8534 | |
1faeff08 MR |
8535 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
8536 | *regnum = mips_regnum; | |
1faeff08 MR |
8537 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
8538 | set_gdbarch_num_regs (gdbarch, num_regs); | |
8539 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8540 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
8541 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
8542 | tdep->mips_processor_reg_names = reg_names; | |
8543 | tdep->regnum = regnum; | |
fe29b929 | 8544 | |
0dadbba0 | 8545 | switch (mips_abi) |
c2d11a7d | 8546 | { |
0dadbba0 | 8547 | case MIPS_ABI_O32: |
25ab4790 | 8548 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 8549 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 8550 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8551 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 8552 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8553 | set_gdbarch_long_bit (gdbarch, 32); |
8554 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8555 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8556 | break; | |
0dadbba0 | 8557 | case MIPS_ABI_O64: |
25ab4790 | 8558 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 8559 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 8560 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8561 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 8562 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8563 | set_gdbarch_long_bit (gdbarch, 32); |
8564 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8565 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8566 | break; | |
0dadbba0 | 8567 | case MIPS_ABI_EABI32: |
25ab4790 | 8568 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8569 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8570 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8571 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8572 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8573 | set_gdbarch_long_bit (gdbarch, 32); |
8574 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8575 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8576 | break; | |
0dadbba0 | 8577 | case MIPS_ABI_EABI64: |
25ab4790 | 8578 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8579 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8580 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8581 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8582 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8583 | set_gdbarch_long_bit (gdbarch, 64); |
8584 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8585 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8586 | break; | |
0dadbba0 | 8587 | case MIPS_ABI_N32: |
25ab4790 | 8588 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8589 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8590 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8591 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8592 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
8593 | set_gdbarch_long_bit (gdbarch, 32); |
8594 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8595 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8596 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8597 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
8598 | break; |
8599 | case MIPS_ABI_N64: | |
25ab4790 | 8600 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8601 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8602 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8603 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
8604 | tdep->default_mask_address_p = 0; |
8605 | set_gdbarch_long_bit (gdbarch, 64); | |
8606 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8607 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8608 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8609 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 8610 | break; |
c2d11a7d | 8611 | default: |
f34652de | 8612 | internal_error (_("unknown ABI in switch")); |
c2d11a7d JM |
8613 | } |
8614 | ||
22e47e37 FF |
8615 | /* GCC creates a pseudo-section whose name specifies the size of |
8616 | longs, since -mlong32 or -mlong64 may be used independent of | |
8617 | other options. How those options affect pointer sizes is ABI and | |
8618 | architecture dependent, so use them to override the default sizes | |
8619 | set by the ABI. This table shows the relationship between ABI, | |
8620 | -mlongXX, and size of pointers: | |
8621 | ||
8622 | ABI -mlongXX ptr bits | |
8623 | --- -------- -------- | |
8624 | o32 32 32 | |
8625 | o32 64 32 | |
8626 | n32 32 32 | |
8627 | n32 64 64 | |
8628 | o64 32 32 | |
8629 | o64 64 64 | |
8630 | n64 32 32 | |
8631 | n64 64 64 | |
8632 | eabi32 32 32 | |
8633 | eabi32 64 32 | |
8634 | eabi64 32 32 | |
8635 | eabi64 64 64 | |
8636 | ||
8637 | Note that for o32 and eabi32, pointers are always 32 bits | |
8638 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 8639 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
8640 | |
8641 | if (info.abfd != NULL) | |
8642 | { | |
8643 | int long_bit = 0; | |
8644 | ||
8645 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
8646 | if (long_bit) | |
8647 | { | |
8648 | set_gdbarch_long_bit (gdbarch, long_bit); | |
8649 | switch (mips_abi) | |
8650 | { | |
8651 | case MIPS_ABI_O32: | |
8652 | case MIPS_ABI_EABI32: | |
8653 | break; | |
8654 | case MIPS_ABI_N32: | |
8655 | case MIPS_ABI_O64: | |
8656 | case MIPS_ABI_N64: | |
8657 | case MIPS_ABI_EABI64: | |
8658 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
8659 | break; | |
8660 | default: | |
f34652de | 8661 | internal_error (_("unknown ABI in switch")); |
22e47e37 FF |
8662 | } |
8663 | } | |
8664 | } | |
8665 | ||
a5ea2558 AC |
8666 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
8667 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
8668 | comment: | |
8669 | ||
8670 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
8671 | flag in object files because to do so would make it impossible to | |
102182a9 | 8672 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 8673 | unnecessarily restrictive. |
361d1df0 | 8674 | |
a5ea2558 AC |
8675 | We could solve this problem by adding "-gp32" multilibs to gcc, |
8676 | but to set this flag before gcc is built with such multilibs will | |
8677 | break too many systems.'' | |
8678 | ||
8679 | But even more unhelpfully, the default linker output target for | |
8680 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
8681 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 8682 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
8683 | this flag to detect 32-bit mode would do the wrong thing given |
8684 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 8685 | as 32-bit programs by default. */ |
a5ea2558 | 8686 | |
6c997a34 | 8687 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 8688 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 8689 | |
102182a9 MS |
8690 | /* Add/remove bits from an address. The MIPS needs be careful to |
8691 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
8692 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
8693 | ||
58dfe9ff AC |
8694 | /* Unwind the frame. */ |
8695 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 8696 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 8697 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 8698 | |
102182a9 | 8699 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 8700 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
8701 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
8702 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
8703 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
8704 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 8705 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 8706 | |
025bb325 | 8707 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 8708 | |
2c76a0c7 JB |
8709 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8710 | set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); | |
dc604539 | 8711 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 8712 | |
1bab7383 YQ |
8713 | set_gdbarch_print_float_info (gdbarch, mips_print_float_info); |
8714 | ||
87783b8b AC |
8715 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
8716 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
8717 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
8718 | ||
f7b9e9fc | 8719 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
04180708 YQ |
8720 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, mips_breakpoint_kind_from_pc); |
8721 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, mips_sw_breakpoint_from_kind); | |
c8cef75f MR |
8722 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
8723 | mips_adjust_breakpoint_address); | |
f7b9e9fc AC |
8724 | |
8725 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 8726 | |
c9cf6e20 | 8727 | set_gdbarch_stack_frame_destroyed_p (gdbarch, mips_stack_frame_destroyed_p); |
97ab0fdd | 8728 | |
fc0c74b1 AC |
8729 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
8730 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
8731 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 8732 | |
a4b8ebc8 | 8733 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 8734 | |
e11c53d2 | 8735 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 8736 | |
471b9d15 MR |
8737 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
8738 | if (mips_abi == MIPS_ABI_N64) | |
8739 | set_gdbarch_disassembler_options_implicit | |
8740 | (gdbarch, (const char *) mips_disassembler_options_n64); | |
8741 | else if (mips_abi == MIPS_ABI_N32) | |
8742 | set_gdbarch_disassembler_options_implicit | |
8743 | (gdbarch, (const char *) mips_disassembler_options_n32); | |
9dae60cc | 8744 | else |
471b9d15 MR |
8745 | set_gdbarch_disassembler_options_implicit |
8746 | (gdbarch, (const char *) mips_disassembler_options_o32); | |
8747 | set_gdbarch_disassembler_options (gdbarch, &mips_disassembler_options); | |
8748 | set_gdbarch_valid_disassembler_options (gdbarch, | |
8749 | disassembler_options_mips ()); | |
e5ab0dce | 8750 | |
d92524f1 PM |
8751 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
8752 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 8753 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
8754 | being used as guards for target_stopped_by_watchpoint, why not have |
8755 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
8756 | is sitting on? */ |
8757 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
8758 | ||
e7d6a6d2 | 8759 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 8760 | |
14132e89 MR |
8761 | /* NOTE drow/2012-04-25: We overload the core solib trampoline code |
8762 | to support MIPS16. This is a bad thing. Make sure not to do it | |
8763 | if we have an OS ABI that actually supports shared libraries, since | |
8764 | shared library support is more important. If we have an OS someday | |
8765 | that supports both shared libraries and MIPS16, we'll have to find | |
8766 | a better place for these. | |
8767 | macro/2012-04-25: But that applies to return trampolines only and | |
8768 | currently no MIPS OS ABI uses shared libraries that have them. */ | |
8769 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
8770 | ||
025bb325 MS |
8771 | set_gdbarch_single_step_through_delay (gdbarch, |
8772 | mips_single_step_through_delay); | |
3352ef37 | 8773 | |
0d5de010 DJ |
8774 | /* Virtual tables. */ |
8775 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
8776 | ||
29709017 DJ |
8777 | mips_register_g_packet_guesses (gdbarch); |
8778 | ||
6de918a6 | 8779 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
c1e1314d | 8780 | info.tdesc_data = tdesc_data.get (); |
6de918a6 | 8781 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 8782 | |
9aac7884 MR |
8783 | /* The hook may have adjusted num_regs, fetch the final value and |
8784 | set pc_regnum and sp_regnum now that it has been fixed. */ | |
9aac7884 MR |
8785 | num_regs = gdbarch_num_regs (gdbarch); |
8786 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
8787 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8788 | ||
5792a79b | 8789 | /* Unwind the frame. */ |
b8a22b94 DJ |
8790 | dwarf2_append_unwinders (gdbarch); |
8791 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
8792 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
4cc0665f | 8793 | frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); |
b8a22b94 | 8794 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); |
2bd0c3d7 | 8795 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 8796 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 | 8797 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
4cc0665f | 8798 | frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); |
45c9dd44 | 8799 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); |
5792a79b | 8800 | |
c1e1314d | 8801 | if (tdesc_data != nullptr) |
f8b73d13 DJ |
8802 | { |
8803 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
c1e1314d | 8804 | tdesc_use_registers (gdbarch, info.target_desc, std::move (tdesc_data)); |
f8b73d13 DJ |
8805 | |
8806 | /* Override the normal target description methods to handle our | |
8807 | dual real and pseudo registers. */ | |
8808 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
8809 | set_gdbarch_register_reggroup_p (gdbarch, |
8810 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
8811 | |
8812 | num_regs = gdbarch_num_regs (gdbarch); | |
8813 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8814 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
8815 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8816 | } | |
8817 | ||
8818 | /* Add ABI-specific aliases for the registers. */ | |
8819 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
8820 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
8821 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
8822 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
8823 | else | |
8824 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
8825 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
8826 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
8827 | ||
8828 | /* Add some other standard aliases. */ | |
8829 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
8830 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
8831 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
8832 | ||
865093a3 AR |
8833 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
8834 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
8835 | value_of_mips_user_reg, | |
8836 | &mips_numeric_register_aliases[i].regnum); | |
8837 | ||
4b9b3959 AC |
8838 | return gdbarch; |
8839 | } | |
8840 | ||
2e4ebe70 | 8841 | static void |
eb4c3f4a TT |
8842 | mips_abi_update (const char *ignore_args, |
8843 | int from_tty, struct cmd_list_element *c) | |
2e4ebe70 DJ |
8844 | { |
8845 | struct gdbarch_info info; | |
8846 | ||
8847 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
8848 | mips_gdbarch_init will take care of the rest. */ | |
2e4ebe70 DJ |
8849 | gdbarch_update_p (info); |
8850 | } | |
8851 | ||
ad188201 KB |
8852 | /* Print out which MIPS ABI is in use. */ |
8853 | ||
8854 | static void | |
1f8ca57c JB |
8855 | show_mips_abi (struct ui_file *file, |
8856 | int from_tty, | |
8857 | struct cmd_list_element *ignored_cmd, | |
8858 | const char *ignored_value) | |
ad188201 | 8859 | { |
99d9c3b9 SM |
8860 | if (gdbarch_bfd_arch_info (current_inferior ()->arch ())->arch |
8861 | != bfd_arch_mips) | |
6cb06a8c | 8862 | gdb_printf |
1f8ca57c JB |
8863 | (file, |
8864 | "The MIPS ABI is unknown because the current architecture " | |
8865 | "is not MIPS.\n"); | |
ad188201 KB |
8866 | else |
8867 | { | |
8868 | enum mips_abi global_abi = global_mips_abi (); | |
99d9c3b9 | 8869 | enum mips_abi actual_abi = mips_abi (current_inferior ()->arch ()); |
ad188201 KB |
8870 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
8871 | ||
8872 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6cb06a8c | 8873 | gdb_printf |
1f8ca57c JB |
8874 | (file, |
8875 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 8876 | actual_abi_str); |
ad188201 | 8877 | else if (global_abi == actual_abi) |
6cb06a8c | 8878 | gdb_printf |
1f8ca57c JB |
8879 | (file, |
8880 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 8881 | actual_abi_str); |
ad188201 KB |
8882 | else |
8883 | { | |
8884 | /* Probably shouldn't happen... */ | |
6cb06a8c TT |
8885 | gdb_printf (file, |
8886 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
8887 | "even though the user setting was \"%s\".\n", | |
8888 | actual_abi_str, mips_abi_strings[global_abi]); | |
ad188201 KB |
8889 | } |
8890 | } | |
8891 | } | |
8892 | ||
4cc0665f MR |
8893 | /* Print out which MIPS compressed ISA encoding is used. */ |
8894 | ||
8895 | static void | |
8896 | show_mips_compression (struct ui_file *file, int from_tty, | |
8897 | struct cmd_list_element *c, const char *value) | |
8898 | { | |
6cb06a8c TT |
8899 | gdb_printf (file, _("The compressed ISA encoding used is %s.\n"), |
8900 | value); | |
4cc0665f MR |
8901 | } |
8902 | ||
a4f320fd MR |
8903 | /* Return a textual name for MIPS FPU type FPU_TYPE. */ |
8904 | ||
8905 | static const char * | |
8906 | mips_fpu_type_str (enum mips_fpu_type fpu_type) | |
8907 | { | |
8908 | switch (fpu_type) | |
8909 | { | |
8910 | case MIPS_FPU_NONE: | |
8911 | return "none"; | |
8912 | case MIPS_FPU_SINGLE: | |
8913 | return "single"; | |
8914 | case MIPS_FPU_DOUBLE: | |
8915 | return "double"; | |
8916 | default: | |
8917 | return "???"; | |
8918 | } | |
8919 | } | |
8920 | ||
4b9b3959 | 8921 | static void |
72a155b4 | 8922 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 8923 | { |
08106042 | 8924 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
4b9b3959 | 8925 | if (tdep != NULL) |
c2d11a7d | 8926 | { |
acdb74a0 AC |
8927 | int ef_mips_arch; |
8928 | int ef_mips_32bitmode; | |
f49e4e6d | 8929 | /* Determine the ISA. */ |
acdb74a0 AC |
8930 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
8931 | { | |
66cf4294 | 8932 | case EF_MIPS_ARCH_1: |
acdb74a0 AC |
8933 | ef_mips_arch = 1; |
8934 | break; | |
66cf4294 | 8935 | case EF_MIPS_ARCH_2: |
acdb74a0 AC |
8936 | ef_mips_arch = 2; |
8937 | break; | |
66cf4294 | 8938 | case EF_MIPS_ARCH_3: |
acdb74a0 AC |
8939 | ef_mips_arch = 3; |
8940 | break; | |
66cf4294 | 8941 | case EF_MIPS_ARCH_4: |
93d56215 | 8942 | ef_mips_arch = 4; |
acdb74a0 AC |
8943 | break; |
8944 | default: | |
93d56215 | 8945 | ef_mips_arch = 0; |
acdb74a0 AC |
8946 | break; |
8947 | } | |
f49e4e6d | 8948 | /* Determine the size of a pointer. */ |
acdb74a0 | 8949 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
6cb06a8c TT |
8950 | gdb_printf (file, |
8951 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
8952 | tdep->elf_flags); | |
8953 | gdb_printf (file, | |
8954 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", | |
8955 | ef_mips_32bitmode); | |
8956 | gdb_printf (file, | |
8957 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
8958 | ef_mips_arch); | |
8959 | gdb_printf (file, | |
8960 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
8961 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); | |
8962 | gdb_printf (file, | |
8963 | "mips_dump_tdep: " | |
8964 | "mips_mask_address_p() %d (default %d)\n", | |
8965 | mips_mask_address_p (tdep), | |
8966 | tdep->default_mask_address_p); | |
c2d11a7d | 8967 | } |
6cb06a8c TT |
8968 | gdb_printf (file, |
8969 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
8970 | MIPS_DEFAULT_FPU_TYPE, | |
8971 | mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE)); | |
8972 | gdb_printf (file, "mips_dump_tdep: MIPS_EABI = %d\n", | |
8973 | mips_eabi (gdbarch)); | |
8974 | gdb_printf (file, | |
8975 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
8976 | mips_get_fpu_type (gdbarch), | |
8977 | mips_fpu_type_str (mips_get_fpu_type (gdbarch))); | |
c2d11a7d JM |
8978 | } |
8979 | ||
6c265988 | 8980 | void _initialize_mips_tdep (); |
c906108c | 8981 | void |
6c265988 | 8982 | _initialize_mips_tdep () |
c906108c SS |
8983 | { |
8984 | static struct cmd_list_element *mipsfpulist = NULL; | |
c906108c | 8985 | |
6d82d43b | 8986 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
8987 | if (MIPS_ABI_LAST + 1 |
8988 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
f34652de | 8989 | internal_error (_("mips_abi_strings out of sync")); |
2e4ebe70 | 8990 | |
4b9b3959 | 8991 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 8992 | |
4eb0ad19 DJ |
8993 | /* Create feature sets with the appropriate properties. The values |
8994 | are not important. */ | |
51a948fd | 8995 | mips_tdesc_gp32 = allocate_target_description ().release (); |
4eb0ad19 DJ |
8996 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); |
8997 | ||
51a948fd | 8998 | mips_tdesc_gp64 = allocate_target_description ().release (); |
4eb0ad19 DJ |
8999 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); |
9000 | ||
025bb325 | 9001 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
f54bdb6d SM |
9002 | add_setshow_prefix_cmd ("mips", no_class, |
9003 | _("Various MIPS specific commands."), | |
9004 | _("Various MIPS specific commands."), | |
9005 | &setmipscmdlist, &showmipscmdlist, | |
9006 | &setlist, &showlist); | |
a5ea2558 | 9007 | |
025bb325 | 9008 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
9009 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
9010 | &mips_abi_string, _("\ | |
9011 | Set the MIPS ABI used by this program."), _("\ | |
9012 | Show the MIPS ABI used by this program."), _("\ | |
9013 | This option can be set to one of:\n\ | |
9014 | auto - the default ABI associated with the current binary\n\ | |
9015 | o32\n\ | |
9016 | o64\n\ | |
9017 | n32\n\ | |
9018 | n64\n\ | |
9019 | eabi32\n\ | |
9020 | eabi64"), | |
9021 | mips_abi_update, | |
9022 | show_mips_abi, | |
9023 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 9024 | |
4cc0665f MR |
9025 | /* Allow the user to set the ISA to assume for compressed code if ELF |
9026 | file flags don't tell or there is no program file selected. This | |
9027 | setting is updated whenever unambiguous ELF file flags are interpreted, | |
9028 | and carried over to subsequent sessions. */ | |
9029 | add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, | |
9030 | &mips_compression_string, _("\ | |
9031 | Set the compressed ISA encoding used by MIPS code."), _("\ | |
9032 | Show the compressed ISA encoding used by MIPS code."), _("\ | |
9033 | Select the compressed ISA encoding used in functions that have no symbol\n\ | |
9034 | information available. The encoding can be set to either of:\n\ | |
9035 | mips16\n\ | |
9036 | micromips\n\ | |
9037 | and is updated automatically from ELF file flags if available."), | |
9038 | mips_abi_update, | |
9039 | show_mips_compression, | |
9040 | &setmipscmdlist, &showmipscmdlist); | |
9041 | ||
c906108c SS |
9042 | /* Let the user turn off floating point and set the fence post for |
9043 | heuristic_proc_start. */ | |
9044 | ||
3b6acaee TT |
9045 | add_basic_prefix_cmd ("mipsfpu", class_support, |
9046 | _("Set use of MIPS floating-point coprocessor."), | |
2f822da5 | 9047 | &mipsfpulist, 0, &setlist); |
c906108c | 9048 | add_cmd ("single", class_support, set_mipsfpu_single_command, |
1a966eab | 9049 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c | 9050 | &mipsfpulist); |
5e84b7ee SM |
9051 | cmd_list_element *set_mipsfpu_double_cmd |
9052 | = add_cmd ("double", class_support, set_mipsfpu_double_command, | |
9053 | _("Select double-precision MIPS floating-point coprocessor."), | |
9054 | &mipsfpulist); | |
9055 | add_alias_cmd ("on", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist); | |
9056 | add_alias_cmd ("yes", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist); | |
9057 | add_alias_cmd ("1", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist); | |
9058 | ||
9059 | cmd_list_element *set_mipsfpu_none_cmd | |
9060 | = add_cmd ("none", class_support, set_mipsfpu_none_command, | |
9061 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); | |
9062 | add_alias_cmd ("off", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist); | |
9063 | add_alias_cmd ("no", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist); | |
9064 | add_alias_cmd ("0", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist); | |
c906108c | 9065 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, |
1a966eab | 9066 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
9067 | &mipsfpulist); |
9068 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 9069 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
9070 | &showlist); |
9071 | ||
c906108c SS |
9072 | /* We really would like to have both "0" and "unlimited" work, but |
9073 | command.c doesn't deal with that. So make it a var_zinteger | |
9074 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 9075 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
9076 | &heuristic_fence_post, _("\ |
9077 | Set the distance searched for the start of a function."), _("\ | |
9078 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
9079 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
9080 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 9081 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 9082 | reinit_frame_cache_sfunc, |
025bb325 MS |
9083 | NULL, /* FIXME: i18n: The distance searched for |
9084 | the start of a function is %s. */ | |
6bcadd06 | 9085 | &setlist, &showlist); |
c906108c SS |
9086 | |
9087 | /* Allow the user to control whether the upper bits of 64-bit | |
9088 | addresses should be zeroed. */ | |
7915a72c AC |
9089 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
9090 | &mask_address_var, _("\ | |
9091 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
9092 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 9093 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 9094 | allow GDB to determine the correct value."), |
08546159 AC |
9095 | NULL, show_mask_address, |
9096 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
9097 | |
9098 | /* Allow the user to control the size of 32 bit registers within the | |
9099 | raw remote packet. */ | |
b3f42336 | 9100 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
9101 | &mips64_transfers_32bit_regs_p, _("\ |
9102 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
9103 | _("\ | |
9104 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
9105 | _("\ | |
719ec221 AC |
9106 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
9107 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 9108 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 9109 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
9110 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
9111 | MIPS target that transfers 32-bit | |
9112 | quantities is %s. */ | |
7915a72c | 9113 | &setlist, &showlist); |
9ace0497 | 9114 | |
025bb325 | 9115 | /* Debug this files internals. */ |
ccce17b0 YQ |
9116 | add_setshow_zuinteger_cmd ("mips", class_maintenance, |
9117 | &mips_debug, _("\ | |
7915a72c AC |
9118 | Set mips debugging."), _("\ |
9119 | Show mips debugging."), _("\ | |
9120 | When non-zero, mips specific debugging is enabled."), | |
ccce17b0 YQ |
9121 | NULL, |
9122 | NULL, /* FIXME: i18n: Mips debugging is | |
9123 | currently %s. */ | |
9124 | &setdebuglist, &showdebuglist); | |
c906108c | 9125 | } |