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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
47a35522 | 5 | Free Software Foundation, Inc. |
bf64bfd6 | 6 | |
c906108c SS |
7 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
8 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
9 | ||
c5aa993b | 10 | This file is part of GDB. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is free software; you can redistribute it and/or modify |
13 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 14 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 15 | (at your option) any later version. |
c906108c | 16 | |
c5aa993b JM |
17 | This program is distributed in the hope that it will be useful, |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
c906108c | 21 | |
c5aa993b | 22 | You should have received a copy of the GNU General Public License |
a9762ec7 | 23 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
24 | |
25 | #include "defs.h" | |
26 | #include "gdb_string.h" | |
5e2e9765 | 27 | #include "gdb_assert.h" |
c906108c SS |
28 | #include "frame.h" |
29 | #include "inferior.h" | |
30 | #include "symtab.h" | |
31 | #include "value.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "language.h" | |
34 | #include "gdbcore.h" | |
35 | #include "symfile.h" | |
36 | #include "objfiles.h" | |
37 | #include "gdbtypes.h" | |
38 | #include "target.h" | |
28d069e6 | 39 | #include "arch-utils.h" |
4e052eda | 40 | #include "regcache.h" |
70f80edf | 41 | #include "osabi.h" |
d1973055 | 42 | #include "mips-tdep.h" |
fe898f56 | 43 | #include "block.h" |
a4b8ebc8 | 44 | #include "reggroups.h" |
c906108c | 45 | #include "opcode/mips.h" |
c2d11a7d JM |
46 | #include "elf/mips.h" |
47 | #include "elf-bfd.h" | |
2475bac3 | 48 | #include "symcat.h" |
a4b8ebc8 | 49 | #include "sim-regno.h" |
a89aa300 | 50 | #include "dis-asm.h" |
edfae063 AC |
51 | #include "frame-unwind.h" |
52 | #include "frame-base.h" | |
53 | #include "trad-frame.h" | |
7d9b040b | 54 | #include "infcall.h" |
fed7ba43 | 55 | #include "floatformat.h" |
29709017 DJ |
56 | #include "remote.h" |
57 | #include "target-descriptions.h" | |
2bd0c3d7 | 58 | #include "dwarf2-frame.h" |
f8b73d13 | 59 | #include "user-regs.h" |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
24e05951 | 65 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
66 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
67 | #define ST0_FR (1 << 26) | |
68 | ||
b0069a17 AC |
69 | /* The sizes of floating point registers. */ |
70 | ||
71 | enum | |
72 | { | |
73 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
74 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
75 | }; | |
76 | ||
1a69e1e4 DJ |
77 | enum |
78 | { | |
79 | MIPS32_REGSIZE = 4, | |
80 | MIPS64_REGSIZE = 8 | |
81 | }; | |
0dadbba0 | 82 | |
2e4ebe70 DJ |
83 | static const char *mips_abi_string; |
84 | ||
85 | static const char *mips_abi_strings[] = { | |
86 | "auto", | |
87 | "n32", | |
88 | "o32", | |
28d169de | 89 | "n64", |
2e4ebe70 DJ |
90 | "o64", |
91 | "eabi32", | |
92 | "eabi64", | |
93 | NULL | |
94 | }; | |
95 | ||
f8b73d13 DJ |
96 | /* The standard register names, and all the valid aliases for them. */ |
97 | struct register_alias | |
98 | { | |
99 | const char *name; | |
100 | int regnum; | |
101 | }; | |
102 | ||
103 | /* Aliases for o32 and most other ABIs. */ | |
104 | const struct register_alias mips_o32_aliases[] = { | |
105 | { "ta0", 12 }, | |
106 | { "ta1", 13 }, | |
107 | { "ta2", 14 }, | |
108 | { "ta3", 15 } | |
109 | }; | |
110 | ||
111 | /* Aliases for n32 and n64. */ | |
112 | const struct register_alias mips_n32_n64_aliases[] = { | |
113 | { "ta0", 8 }, | |
114 | { "ta1", 9 }, | |
115 | { "ta2", 10 }, | |
116 | { "ta3", 11 } | |
117 | }; | |
118 | ||
119 | /* Aliases for ABI-independent registers. */ | |
120 | const struct register_alias mips_register_aliases[] = { | |
121 | /* The architecture manuals specify these ABI-independent names for | |
122 | the GPRs. */ | |
123 | #define R(n) { "r" #n, n } | |
124 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
125 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
126 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
127 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
128 | #undef R | |
129 | ||
130 | /* k0 and k1 are sometimes called these instead (for "kernel | |
131 | temp"). */ | |
132 | { "kt0", 26 }, | |
133 | { "kt1", 27 }, | |
134 | ||
135 | /* This is the traditional GDB name for the CP0 status register. */ | |
136 | { "sr", MIPS_PS_REGNUM }, | |
137 | ||
138 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
139 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
140 | ||
141 | /* This is the traditional GDB name for the FCSR. */ | |
142 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
143 | }; | |
144 | ||
7a292a7a | 145 | /* Some MIPS boards don't support floating point while others only |
ceae6e75 | 146 | support single-precision floating-point operations. */ |
c906108c SS |
147 | |
148 | enum mips_fpu_type | |
6d82d43b AC |
149 | { |
150 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
151 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
152 | MIPS_FPU_NONE /* No floating point. */ | |
153 | }; | |
c906108c SS |
154 | |
155 | #ifndef MIPS_DEFAULT_FPU_TYPE | |
156 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
157 | #endif | |
158 | static int mips_fpu_type_auto = 1; | |
159 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 160 | |
9ace0497 | 161 | static int mips_debug = 0; |
7a292a7a | 162 | |
29709017 DJ |
163 | /* Properties (for struct target_desc) describing the g/G packet |
164 | layout. */ | |
165 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
166 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
167 | ||
4eb0ad19 DJ |
168 | struct target_desc *mips_tdesc_gp32; |
169 | struct target_desc *mips_tdesc_gp64; | |
170 | ||
c2d11a7d JM |
171 | /* MIPS specific per-architecture information */ |
172 | struct gdbarch_tdep | |
6d82d43b AC |
173 | { |
174 | /* from the elf header */ | |
175 | int elf_flags; | |
176 | ||
177 | /* mips options */ | |
178 | enum mips_abi mips_abi; | |
179 | enum mips_abi found_abi; | |
180 | enum mips_fpu_type mips_fpu_type; | |
181 | int mips_last_arg_regnum; | |
182 | int mips_last_fp_arg_regnum; | |
6d82d43b AC |
183 | int default_mask_address_p; |
184 | /* Is the target using 64-bit raw integer registers but only | |
185 | storing a left-aligned 32-bit value in each? */ | |
186 | int mips64_transfers_32bit_regs_p; | |
187 | /* Indexes for various registers. IRIX and embedded have | |
188 | different values. This contains the "public" fields. Don't | |
189 | add any that do not need to be public. */ | |
190 | const struct mips_regnum *regnum; | |
191 | /* Register names table for the current register set. */ | |
192 | const char **mips_processor_reg_names; | |
29709017 DJ |
193 | |
194 | /* The size of register data available from the target, if known. | |
195 | This doesn't quite obsolete the manual | |
196 | mips64_transfers_32bit_regs_p, since that is documented to force | |
197 | left alignment even for big endian (very strange). */ | |
198 | int register_size_valid_p; | |
199 | int register_size; | |
6d82d43b | 200 | }; |
c2d11a7d | 201 | |
fed7ba43 JB |
202 | static int |
203 | n32n64_floatformat_always_valid (const struct floatformat *fmt, | |
2244f671 | 204 | const void *from) |
fed7ba43 JB |
205 | { |
206 | return 1; | |
207 | } | |
208 | ||
209 | /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long. | |
210 | They are implemented as a pair of 64bit doubles where the high | |
211 | part holds the result of the operation rounded to double, and | |
212 | the low double holds the difference between the exact result and | |
213 | the rounded result. So "high" + "low" contains the result with | |
214 | added precision. Unfortunately, the floatformat structure used | |
215 | by GDB is not powerful enough to describe this format. As a temporary | |
216 | measure, we define a 128bit floatformat that only uses the high part. | |
217 | We lose a bit of precision but that's probably the best we can do | |
218 | for now with the current infrastructure. */ | |
219 | ||
220 | static const struct floatformat floatformat_n32n64_long_double_big = | |
221 | { | |
222 | floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52, | |
223 | floatformat_intbit_no, | |
8da61cc4 | 224 | "floatformat_n32n64_long_double_big", |
fed7ba43 JB |
225 | n32n64_floatformat_always_valid |
226 | }; | |
227 | ||
8da61cc4 DJ |
228 | static const struct floatformat *floatformats_n32n64_long[BFD_ENDIAN_UNKNOWN] = |
229 | { | |
230 | &floatformat_n32n64_long_double_big, | |
231 | &floatformat_n32n64_long_double_big | |
232 | }; | |
233 | ||
56cea623 AC |
234 | const struct mips_regnum * |
235 | mips_regnum (struct gdbarch *gdbarch) | |
236 | { | |
237 | return gdbarch_tdep (gdbarch)->regnum; | |
238 | } | |
239 | ||
240 | static int | |
241 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
242 | { | |
243 | return mips_regnum (gdbarch)->fp0 + 12; | |
244 | } | |
245 | ||
0dadbba0 | 246 | #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \ |
216a600b | 247 | || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64) |
c2d11a7d | 248 | |
c2d11a7d | 249 | #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum) |
c2d11a7d | 250 | |
c2d11a7d | 251 | #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum) |
c2d11a7d | 252 | |
c2d11a7d | 253 | #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type) |
c2d11a7d | 254 | |
95404a3e AC |
255 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
256 | functions to test, set, or clear bit 0 of addresses. */ | |
257 | ||
258 | static CORE_ADDR | |
259 | is_mips16_addr (CORE_ADDR addr) | |
260 | { | |
261 | return ((addr) & 1); | |
262 | } | |
263 | ||
95404a3e AC |
264 | static CORE_ADDR |
265 | unmake_mips16_addr (CORE_ADDR addr) | |
266 | { | |
5b652102 | 267 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
268 | } |
269 | ||
d1973055 KB |
270 | /* Return the MIPS ABI associated with GDBARCH. */ |
271 | enum mips_abi | |
272 | mips_abi (struct gdbarch *gdbarch) | |
273 | { | |
274 | return gdbarch_tdep (gdbarch)->mips_abi; | |
275 | } | |
276 | ||
4246e332 | 277 | int |
1b13c4f6 | 278 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 279 | { |
29709017 DJ |
280 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
281 | ||
282 | /* If we know how big the registers are, use that size. */ | |
283 | if (tdep->register_size_valid_p) | |
284 | return tdep->register_size; | |
285 | ||
286 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
287 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
288 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
289 | } | |
290 | ||
480d3dd2 AC |
291 | /* Return the currently configured (or set) saved register size. */ |
292 | ||
e6bc2e8a | 293 | unsigned int |
13326b4e | 294 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 295 | { |
1a69e1e4 DJ |
296 | switch (mips_abi (gdbarch)) |
297 | { | |
298 | case MIPS_ABI_EABI32: | |
299 | case MIPS_ABI_O32: | |
300 | return 4; | |
301 | case MIPS_ABI_N32: | |
302 | case MIPS_ABI_N64: | |
303 | case MIPS_ABI_O64: | |
304 | case MIPS_ABI_EABI64: | |
305 | return 8; | |
306 | case MIPS_ABI_UNKNOWN: | |
307 | case MIPS_ABI_LAST: | |
308 | default: | |
309 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
310 | } | |
d929b26f AC |
311 | } |
312 | ||
71b8ef93 | 313 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 314 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 315 | "info" field is used for this purpose. |
5a89d8aa | 316 | |
95f1da47 | 317 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
318 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
319 | minimal symbol to mark it as a 16-bit function | |
320 | ||
f594e5e9 | 321 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 322 | |
5a89d8aa | 323 | static void |
6d82d43b AC |
324 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
325 | { | |
326 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
327 | { | |
328 | MSYMBOL_INFO (msym) = (char *) | |
329 | (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
330 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
331 | } | |
5a89d8aa MS |
332 | } |
333 | ||
71b8ef93 MS |
334 | static int |
335 | msymbol_is_special (struct minimal_symbol *msym) | |
336 | { | |
337 | return (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0); | |
338 | } | |
339 | ||
88658117 AC |
340 | /* XFER a value from the big/little/left end of the register. |
341 | Depending on the size of the value it might occupy the entire | |
342 | register or just part of it. Make an allowance for this, aligning | |
343 | things accordingly. */ | |
344 | ||
345 | static void | |
346 | mips_xfer_register (struct regcache *regcache, int reg_num, int length, | |
870cd05e MK |
347 | enum bfd_endian endian, gdb_byte *in, |
348 | const gdb_byte *out, int buf_offset) | |
88658117 | 349 | { |
88658117 | 350 | int reg_offset = 0; |
f57d151a | 351 | gdb_assert (reg_num >= gdbarch_num_regs (current_gdbarch)); |
cb1d2653 AC |
352 | /* Need to transfer the left or right part of the register, based on |
353 | the targets byte order. */ | |
88658117 AC |
354 | switch (endian) |
355 | { | |
356 | case BFD_ENDIAN_BIG: | |
719ec221 | 357 | reg_offset = register_size (current_gdbarch, reg_num) - length; |
88658117 AC |
358 | break; |
359 | case BFD_ENDIAN_LITTLE: | |
360 | reg_offset = 0; | |
361 | break; | |
6d82d43b | 362 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
363 | reg_offset = 0; |
364 | break; | |
365 | default: | |
e2e0b3e5 | 366 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
367 | } |
368 | if (mips_debug) | |
cb1d2653 AC |
369 | fprintf_unfiltered (gdb_stderr, |
370 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
371 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
372 | if (mips_debug && out != NULL) |
373 | { | |
374 | int i; | |
cb1d2653 | 375 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 376 | for (i = 0; i < length; i++) |
cb1d2653 | 377 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
378 | } |
379 | if (in != NULL) | |
6d82d43b AC |
380 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
381 | in + buf_offset); | |
88658117 | 382 | if (out != NULL) |
6d82d43b AC |
383 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
384 | out + buf_offset); | |
88658117 AC |
385 | if (mips_debug && in != NULL) |
386 | { | |
387 | int i; | |
cb1d2653 | 388 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 389 | for (i = 0; i < length; i++) |
cb1d2653 | 390 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
391 | } |
392 | if (mips_debug) | |
393 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
394 | } | |
395 | ||
dd824b04 DJ |
396 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
397 | compatiblity mode. A return value of 1 means that we have | |
398 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
399 | ||
400 | static int | |
9c9acae0 | 401 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 DJ |
402 | { |
403 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not | |
404 | meaningful. */ | |
6d82d43b AC |
405 | if (register_size (current_gdbarch, mips_regnum (current_gdbarch)->fp0) == |
406 | 4) | |
dd824b04 DJ |
407 | return 0; |
408 | ||
409 | #if 0 | |
410 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
411 | in all the places we deal with FP registers. PR gdb/413. */ | |
412 | /* Otherwise check the FR bit in the status register - it controls | |
413 | the FP compatiblity mode. If it is clear we are in compatibility | |
414 | mode. */ | |
9c9acae0 | 415 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
416 | return 1; |
417 | #endif | |
361d1df0 | 418 | |
dd824b04 DJ |
419 | return 0; |
420 | } | |
421 | ||
7a292a7a | 422 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 423 | |
a14ed312 | 424 | static CORE_ADDR heuristic_proc_start (CORE_ADDR); |
c906108c | 425 | |
a14ed312 | 426 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 427 | |
67b2c998 DJ |
428 | static struct type *mips_float_register_type (void); |
429 | static struct type *mips_double_register_type (void); | |
430 | ||
acdb74a0 AC |
431 | /* The list of available "set mips " and "show mips " commands */ |
432 | ||
433 | static struct cmd_list_element *setmipscmdlist = NULL; | |
434 | static struct cmd_list_element *showmipscmdlist = NULL; | |
435 | ||
5e2e9765 KB |
436 | /* Integer registers 0 thru 31 are handled explicitly by |
437 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 438 | are listed in the following tables. */ |
691c0433 | 439 | |
6d82d43b AC |
440 | enum |
441 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
442 | |
443 | /* Generic MIPS. */ | |
444 | ||
445 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
446 | "sr", "lo", "hi", "bad", "cause", "pc", |
447 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
448 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
449 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
450 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
451 | "fsr", "fir", "" /*"fp" */ , "", | |
452 | "", "", "", "", "", "", "", "", | |
453 | "", "", "", "", "", "", "", "", | |
691c0433 AC |
454 | }; |
455 | ||
456 | /* Names of IDT R3041 registers. */ | |
457 | ||
458 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
459 | "sr", "lo", "hi", "bad", "cause", "pc", |
460 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
461 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
462 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
463 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
464 | "fsr", "fir", "", /*"fp" */ "", | |
465 | "", "", "bus", "ccfg", "", "", "", "", | |
466 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
467 | }; |
468 | ||
469 | /* Names of tx39 registers. */ | |
470 | ||
471 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
472 | "sr", "lo", "hi", "bad", "cause", "pc", |
473 | "", "", "", "", "", "", "", "", | |
474 | "", "", "", "", "", "", "", "", | |
475 | "", "", "", "", "", "", "", "", | |
476 | "", "", "", "", "", "", "", "", | |
477 | "", "", "", "", | |
478 | "", "", "", "", "", "", "", "", | |
479 | "", "", "config", "cache", "debug", "depc", "epc", "" | |
691c0433 AC |
480 | }; |
481 | ||
482 | /* Names of IRIX registers. */ | |
483 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
484 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
485 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
486 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
487 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
488 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
489 | }; |
490 | ||
cce74817 | 491 | |
5e2e9765 | 492 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 493 | static const char * |
5e2e9765 | 494 | mips_register_name (int regno) |
cce74817 | 495 | { |
691c0433 | 496 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
5e2e9765 KB |
497 | /* GPR names for all ABIs other than n32/n64. */ |
498 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
499 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
500 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
501 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
502 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
503 | }; |
504 | ||
505 | /* GPR names for n32 and n64 ABIs. */ | |
506 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
507 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
508 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
509 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
510 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
511 | }; |
512 | ||
513 | enum mips_abi abi = mips_abi (current_gdbarch); | |
514 | ||
f57d151a UW |
515 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
516 | but then don't make the raw register names visible. */ | |
517 | int rawnum = regno % gdbarch_num_regs (current_gdbarch); | |
518 | if (regno < gdbarch_num_regs (current_gdbarch)) | |
a4b8ebc8 AC |
519 | return ""; |
520 | ||
5e2e9765 KB |
521 | /* The MIPS integer registers are always mapped from 0 to 31. The |
522 | names of the registers (which reflects the conventions regarding | |
523 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 524 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
525 | { |
526 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 527 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 528 | else |
a4b8ebc8 | 529 | return mips_gpr_names[rawnum]; |
5e2e9765 | 530 | } |
f8b73d13 DJ |
531 | else if (tdesc_has_registers (gdbarch_target_desc (current_gdbarch))) |
532 | return tdesc_register_name (rawnum); | |
f57d151a | 533 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (current_gdbarch)) |
691c0433 AC |
534 | { |
535 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
536 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
537 | } | |
5e2e9765 KB |
538 | else |
539 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 540 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 541 | } |
5e2e9765 | 542 | |
a4b8ebc8 | 543 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 544 | |
a4b8ebc8 AC |
545 | static int |
546 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
547 | struct reggroup *reggroup) | |
548 | { | |
549 | int vector_p; | |
550 | int float_p; | |
551 | int raw_p; | |
f57d151a UW |
552 | int rawnum = regnum % gdbarch_num_regs (current_gdbarch); |
553 | int pseudo = regnum / gdbarch_num_regs (current_gdbarch); | |
a4b8ebc8 AC |
554 | if (reggroup == all_reggroup) |
555 | return pseudo; | |
556 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
557 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
558 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
559 | (gdbarch), as not all architectures are multi-arch. */ | |
f57d151a | 560 | raw_p = rawnum < gdbarch_num_regs (current_gdbarch); |
c9f4d572 UW |
561 | if (gdbarch_register_name (current_gdbarch, regnum) == NULL |
562 | || gdbarch_register_name (current_gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
563 | return 0; |
564 | if (reggroup == float_reggroup) | |
565 | return float_p && pseudo; | |
566 | if (reggroup == vector_reggroup) | |
567 | return vector_p && pseudo; | |
568 | if (reggroup == general_reggroup) | |
569 | return (!vector_p && !float_p) && pseudo; | |
570 | /* Save the pseudo registers. Need to make certain that any code | |
571 | extracting register values from a saved register cache also uses | |
572 | pseudo registers. */ | |
573 | if (reggroup == save_reggroup) | |
574 | return raw_p && pseudo; | |
575 | /* Restore the same pseudo register. */ | |
576 | if (reggroup == restore_reggroup) | |
577 | return raw_p && pseudo; | |
6d82d43b | 578 | return 0; |
a4b8ebc8 AC |
579 | } |
580 | ||
f8b73d13 DJ |
581 | /* Return the groups that a MIPS register can be categorised into. |
582 | This version is only used if we have a target description which | |
583 | describes real registers (and their groups). */ | |
584 | ||
585 | static int | |
586 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
587 | struct reggroup *reggroup) | |
588 | { | |
589 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
590 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
591 | int ret; | |
592 | ||
593 | /* Only save, restore, and display the pseudo registers. Need to | |
594 | make certain that any code extracting register values from a | |
595 | saved register cache also uses pseudo registers. | |
596 | ||
597 | Note: saving and restoring the pseudo registers is slightly | |
598 | strange; if we have 64 bits, we should save and restore all | |
599 | 64 bits. But this is hard and has little benefit. */ | |
600 | if (!pseudo) | |
601 | return 0; | |
602 | ||
603 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
604 | if (ret != -1) | |
605 | return ret; | |
606 | ||
607 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
608 | } | |
609 | ||
a4b8ebc8 | 610 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 611 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 612 | registers. Take care of alignment and size problems. */ |
c5aa993b | 613 | |
a4b8ebc8 AC |
614 | static void |
615 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
47a35522 | 616 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 617 | { |
f57d151a UW |
618 | int rawnum = cookednum % gdbarch_num_regs (current_gdbarch); |
619 | gdb_assert (cookednum >= gdbarch_num_regs (current_gdbarch) | |
620 | && cookednum < 2 * gdbarch_num_regs (current_gdbarch)); | |
47ebcfbe | 621 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 622 | regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
623 | else if (register_size (gdbarch, rawnum) > |
624 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
625 | { |
626 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
4c6b5505 | 627 | || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
628 | regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
629 | else | |
630 | regcache_raw_read_part (regcache, rawnum, 4, 4, buf); | |
631 | } | |
632 | else | |
e2e0b3e5 | 633 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
634 | } |
635 | ||
636 | static void | |
6d82d43b AC |
637 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
638 | struct regcache *regcache, int cookednum, | |
47a35522 | 639 | const gdb_byte *buf) |
a4b8ebc8 | 640 | { |
f57d151a UW |
641 | int rawnum = cookednum % gdbarch_num_regs (current_gdbarch); |
642 | gdb_assert (cookednum >= gdbarch_num_regs (current_gdbarch) | |
643 | && cookednum < 2 * gdbarch_num_regs (current_gdbarch)); | |
47ebcfbe | 644 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 645 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
646 | else if (register_size (gdbarch, rawnum) > |
647 | register_size (gdbarch, cookednum)) | |
47ebcfbe AC |
648 | { |
649 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
4c6b5505 | 650 | || gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
47ebcfbe AC |
651 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
652 | else | |
653 | regcache_raw_write_part (regcache, rawnum, 4, 4, buf); | |
654 | } | |
655 | else | |
e2e0b3e5 | 656 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 657 | } |
c5aa993b | 658 | |
c906108c | 659 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 660 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
661 | |
662 | /* Heuristic_proc_start may hunt through the text section for a long | |
663 | time across a 2400 baud serial line. Allows the user to limit this | |
664 | search. */ | |
665 | ||
666 | static unsigned int heuristic_fence_post = 0; | |
667 | ||
46cd78fb | 668 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
669 | register N. NOTE: This defines the pseudo register type so need to |
670 | rebuild the architecture vector. */ | |
43e526b9 JM |
671 | |
672 | static int mips64_transfers_32bit_regs_p = 0; | |
673 | ||
719ec221 AC |
674 | static void |
675 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
676 | struct cmd_list_element *c) | |
43e526b9 | 677 | { |
719ec221 AC |
678 | struct gdbarch_info info; |
679 | gdbarch_info_init (&info); | |
680 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
681 | instead of relying on globals. Doing that would let generic code | |
682 | handle the search for this specific architecture. */ | |
683 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 684 | { |
719ec221 | 685 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 686 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 687 | } |
a4b8ebc8 AC |
688 | } |
689 | ||
47ebcfbe | 690 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 691 | |
ff2e87ac AC |
692 | static int |
693 | mips_convert_register_p (int regnum, struct type *type) | |
694 | { | |
4c6b5505 | 695 | return (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
719ec221 | 696 | && register_size (current_gdbarch, regnum) == 4 |
f57d151a UW |
697 | && (regnum % gdbarch_num_regs (current_gdbarch)) |
698 | >= mips_regnum (current_gdbarch)->fp0 | |
699 | && (regnum % gdbarch_num_regs (current_gdbarch)) | |
700 | < mips_regnum (current_gdbarch)->fp0 + 32 | |
6d82d43b | 701 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
702 | } |
703 | ||
42c466d7 | 704 | static void |
ff2e87ac | 705 | mips_register_to_value (struct frame_info *frame, int regnum, |
47a35522 | 706 | struct type *type, gdb_byte *to) |
102182a9 | 707 | { |
47a35522 MK |
708 | get_frame_register (frame, regnum + 0, to + 4); |
709 | get_frame_register (frame, regnum + 1, to + 0); | |
102182a9 MS |
710 | } |
711 | ||
42c466d7 | 712 | static void |
ff2e87ac | 713 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 714 | struct type *type, const gdb_byte *from) |
102182a9 | 715 | { |
47a35522 MK |
716 | put_frame_register (frame, regnum + 0, from + 4); |
717 | put_frame_register (frame, regnum + 1, from + 0); | |
102182a9 MS |
718 | } |
719 | ||
a4b8ebc8 AC |
720 | /* Return the GDB type object for the "standard" data type of data in |
721 | register REG. */ | |
78fde5f8 KB |
722 | |
723 | static struct type * | |
a4b8ebc8 AC |
724 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
725 | { | |
f57d151a UW |
726 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (current_gdbarch)); |
727 | if ((regnum % gdbarch_num_regs (current_gdbarch)) | |
728 | >= mips_regnum (current_gdbarch)->fp0 | |
729 | && (regnum % gdbarch_num_regs (current_gdbarch)) | |
730 | < mips_regnum (current_gdbarch)->fp0 + 32) | |
a6425924 | 731 | { |
5ef80fb0 | 732 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 733 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 DJ |
734 | if (mips_isa_regsize (gdbarch) == 4) |
735 | return builtin_type_ieee_single; | |
736 | else | |
737 | return builtin_type_ieee_double; | |
a6425924 | 738 | } |
f57d151a | 739 | else if (regnum < gdbarch_num_regs (current_gdbarch)) |
d5ac5a39 AC |
740 | { |
741 | /* The raw or ISA registers. These are all sized according to | |
742 | the ISA regsize. */ | |
743 | if (mips_isa_regsize (gdbarch) == 4) | |
744 | return builtin_type_int32; | |
745 | else | |
746 | return builtin_type_int64; | |
747 | } | |
78fde5f8 | 748 | else |
d5ac5a39 AC |
749 | { |
750 | /* The cooked or ABI registers. These are sized according to | |
751 | the ABI (with a few complications). */ | |
f57d151a | 752 | if (regnum >= (gdbarch_num_regs (current_gdbarch) |
d5ac5a39 | 753 | + mips_regnum (current_gdbarch)->fp_control_status) |
f57d151a UW |
754 | && regnum <= gdbarch_num_regs (current_gdbarch) |
755 | + MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
756 | /* The pseudo/cooked view of the embedded registers is always |
757 | 32-bit. The raw view is handled below. */ | |
758 | return builtin_type_int32; | |
759 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | |
760 | /* The target, while possibly using a 64-bit register buffer, | |
761 | is only transfering 32-bits of each integer register. | |
762 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
763 | return builtin_type_int32; | |
764 | else if (mips_abi_regsize (gdbarch) == 4) | |
765 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
766 | 32- or 64-bit). */ | |
767 | return builtin_type_int32; | |
768 | else | |
769 | /* 64-bit ABI. */ | |
770 | return builtin_type_int64; | |
771 | } | |
78fde5f8 KB |
772 | } |
773 | ||
f8b73d13 DJ |
774 | /* Return the GDB type for the pseudo register REGNUM, which is the |
775 | ABI-level view. This function is only called if there is a target | |
776 | description which includes registers, so we know precisely the | |
777 | types of hardware registers. */ | |
778 | ||
779 | static struct type * | |
780 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
781 | { | |
782 | const int num_regs = gdbarch_num_regs (gdbarch); | |
783 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
784 | int rawnum = regnum % num_regs; | |
785 | struct type *rawtype; | |
786 | ||
787 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
788 | ||
789 | /* Absent registers are still absent. */ | |
790 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
791 | if (TYPE_LENGTH (rawtype) == 0) | |
792 | return rawtype; | |
793 | ||
794 | if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | |
795 | /* Present the floating point registers however the hardware did; | |
796 | do not try to convert between FPU layouts. */ | |
797 | return rawtype; | |
798 | ||
799 | if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
800 | { | |
801 | /* The pseudo/cooked view of embedded registers is always | |
802 | 32-bit, even if the target transfers 64-bit values for them. | |
803 | New targets relying on XML descriptions should only transfer | |
804 | the necessary 32 bits, but older versions of GDB expected 64, | |
805 | so allow the target to provide 64 bits without interfering | |
806 | with the displayed type. */ | |
807 | return builtin_type_int32; | |
808 | } | |
809 | ||
810 | /* Use pointer types for registers if we can. For n32 we can not, | |
811 | since we do not have a 64-bit pointer type. */ | |
812 | if (mips_abi_regsize (gdbarch) == TYPE_LENGTH (builtin_type_void_data_ptr)) | |
813 | { | |
814 | if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
815 | return builtin_type_void_data_ptr; | |
816 | else if (rawnum == MIPS_EMBED_PC_REGNUM) | |
817 | return builtin_type_void_func_ptr; | |
818 | } | |
819 | ||
820 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
821 | && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
822 | return builtin_type_int32; | |
823 | ||
824 | /* For all other registers, pass through the hardware type. */ | |
825 | return rawtype; | |
826 | } | |
bcb0cc15 | 827 | |
c906108c | 828 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 829 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
830 | |
831 | static int | |
480d3dd2 | 832 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
833 | { |
834 | switch (mask_address_var) | |
835 | { | |
7f19b9a2 | 836 | case AUTO_BOOLEAN_TRUE: |
4014092b | 837 | return 1; |
7f19b9a2 | 838 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
839 | return 0; |
840 | break; | |
7f19b9a2 | 841 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 842 | return tdep->default_mask_address_p; |
4014092b | 843 | default: |
e2e0b3e5 | 844 | internal_error (__FILE__, __LINE__, _("mips_mask_address_p: bad switch")); |
4014092b | 845 | return -1; |
361d1df0 | 846 | } |
4014092b AC |
847 | } |
848 | ||
849 | static void | |
08546159 AC |
850 | show_mask_address (struct ui_file *file, int from_tty, |
851 | struct cmd_list_element *c, const char *value) | |
4014092b | 852 | { |
480d3dd2 | 853 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
08546159 AC |
854 | |
855 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
856 | switch (mask_address_var) |
857 | { | |
7f19b9a2 | 858 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
859 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
860 | break; | |
7f19b9a2 | 861 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
862 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
863 | break; | |
7f19b9a2 | 864 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
865 | printf_filtered |
866 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
867 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
868 | break; |
869 | default: | |
e2e0b3e5 | 870 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 871 | break; |
361d1df0 | 872 | } |
4014092b | 873 | } |
c906108c | 874 | |
c906108c SS |
875 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
876 | ||
0fe7e7c8 AC |
877 | int |
878 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
879 | { |
880 | struct minimal_symbol *sym; | |
881 | ||
882 | /* If bit 0 of the address is set, assume this is a MIPS16 address. */ | |
95404a3e | 883 | if (is_mips16_addr (memaddr)) |
c906108c SS |
884 | return 1; |
885 | ||
886 | /* A flag indicating that this is a MIPS16 function is stored by elfread.c in | |
887 | the high bit of the info field. Use this to decide if the function is | |
888 | MIPS16 or normal MIPS. */ | |
889 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
890 | if (sym) | |
71b8ef93 | 891 | return msymbol_is_special (sym); |
c906108c SS |
892 | else |
893 | return 0; | |
894 | } | |
895 | ||
b2fa5097 | 896 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
6c997a34 AC |
897 | all registers should be sign extended for simplicity? */ |
898 | ||
899 | static CORE_ADDR | |
61a1198a | 900 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 901 | { |
61a1198a UW |
902 | ULONGEST pc; |
903 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
904 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
905 | return pc; | |
b6cb9035 AC |
906 | } |
907 | ||
58dfe9ff AC |
908 | static CORE_ADDR |
909 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
910 | { | |
edfae063 | 911 | return frame_unwind_register_signed (next_frame, |
f57d151a UW |
912 | gdbarch_num_regs (current_gdbarch) |
913 | + mips_regnum (gdbarch)->pc); | |
edfae063 AC |
914 | } |
915 | ||
30244cd8 UW |
916 | static CORE_ADDR |
917 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
918 | { | |
f57d151a UW |
919 | return frame_unwind_register_signed (next_frame, |
920 | gdbarch_num_regs (current_gdbarch) | |
921 | + MIPS_SP_REGNUM); | |
30244cd8 UW |
922 | } |
923 | ||
edfae063 AC |
924 | /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that |
925 | dummy frame. The frame ID's base needs to match the TOS value | |
926 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
927 | breakpoint. */ | |
928 | ||
929 | static struct frame_id | |
930 | mips_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
931 | { | |
f57d151a UW |
932 | return frame_id_build |
933 | (frame_unwind_register_signed (next_frame, | |
934 | gdbarch_num_regs (current_gdbarch) | |
935 | + MIPS_SP_REGNUM), | |
936 | frame_pc_unwind (next_frame)); | |
58dfe9ff AC |
937 | } |
938 | ||
b6cb9035 | 939 | static void |
61a1198a | 940 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 941 | { |
61a1198a UW |
942 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
943 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 944 | } |
c906108c | 945 | |
c906108c SS |
946 | /* Fetch and return instruction from the specified location. If the PC |
947 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
948 | ||
d37cca3d | 949 | static ULONGEST |
acdb74a0 | 950 | mips_fetch_instruction (CORE_ADDR addr) |
c906108c | 951 | { |
47a35522 | 952 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
953 | int instlen; |
954 | int status; | |
955 | ||
0fe7e7c8 | 956 | if (mips_pc_is_mips16 (addr)) |
c906108c | 957 | { |
95ac2dcf | 958 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 959 | addr = unmake_mips16_addr (addr); |
c906108c SS |
960 | } |
961 | else | |
95ac2dcf | 962 | instlen = MIPS_INSN32_SIZE; |
359a9262 | 963 | status = read_memory_nobpt (addr, buf, instlen); |
c906108c SS |
964 | if (status) |
965 | memory_error (status, addr); | |
966 | return extract_unsigned_integer (buf, instlen); | |
967 | } | |
968 | ||
c906108c | 969 | /* These the fields of 32 bit mips instructions */ |
e135b889 DJ |
970 | #define mips32_op(x) (x >> 26) |
971 | #define itype_op(x) (x >> 26) | |
972 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 973 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 974 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 975 | |
e135b889 DJ |
976 | #define jtype_op(x) (x >> 26) |
977 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 978 | |
e135b889 DJ |
979 | #define rtype_op(x) (x >> 26) |
980 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
981 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
982 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
983 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
984 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 985 | |
06987e64 MK |
986 | static LONGEST |
987 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 988 | { |
06987e64 | 989 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
990 | } |
991 | ||
f49e4e6d MS |
992 | /* Determine where to set a single step breakpoint while considering |
993 | branch prediction. */ | |
5a89d8aa | 994 | static CORE_ADDR |
0b1b3e42 | 995 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b JM |
996 | { |
997 | unsigned long inst; | |
998 | int op; | |
999 | inst = mips_fetch_instruction (pc); | |
e135b889 | 1000 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction */ |
c5aa993b | 1001 | { |
e135b889 | 1002 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1003 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1004 | { |
e135b889 | 1005 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1006 | switch (op) |
1007 | { | |
e135b889 DJ |
1008 | case 0: /* BEQL */ |
1009 | goto equal_branch; | |
1010 | case 1: /* BNEL */ | |
1011 | goto neq_branch; | |
1012 | case 2: /* BLEZL */ | |
1013 | goto less_branch; | |
313628cc | 1014 | case 3: /* BGTZL */ |
e135b889 | 1015 | goto greater_branch; |
c5aa993b JM |
1016 | default: |
1017 | pc += 4; | |
c906108c SS |
1018 | } |
1019 | } | |
e135b889 | 1020 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1021 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
e135b889 DJ |
1022 | { |
1023 | int tf = itype_rt (inst) & 0x01; | |
1024 | int cnum = itype_rt (inst) >> 2; | |
6d82d43b | 1025 | int fcrcs = |
0b1b3e42 UW |
1026 | get_frame_register_signed (frame, mips_regnum (current_gdbarch)-> |
1027 | fp_control_status); | |
e135b889 DJ |
1028 | int cond = ((fcrcs >> 24) & 0x0e) | ((fcrcs >> 23) & 0x01); |
1029 | ||
1030 | if (((cond >> cnum) & 0x01) == tf) | |
1031 | pc += mips32_relative_offset (inst) + 4; | |
1032 | else | |
1033 | pc += 8; | |
1034 | } | |
c5aa993b JM |
1035 | else |
1036 | pc += 4; /* Not a branch, next instruction is easy */ | |
c906108c SS |
1037 | } |
1038 | else | |
c5aa993b JM |
1039 | { /* This gets way messy */ |
1040 | ||
c906108c | 1041 | /* Further subdivide into SPECIAL, REGIMM and other */ |
e135b889 | 1042 | switch (op = itype_op (inst) & 0x07) /* extract bits 28,27,26 */ |
c906108c | 1043 | { |
c5aa993b JM |
1044 | case 0: /* SPECIAL */ |
1045 | op = rtype_funct (inst); | |
1046 | switch (op) | |
1047 | { | |
1048 | case 8: /* JR */ | |
1049 | case 9: /* JALR */ | |
6c997a34 | 1050 | /* Set PC to that address */ |
0b1b3e42 | 1051 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b JM |
1052 | break; |
1053 | default: | |
1054 | pc += 4; | |
1055 | } | |
1056 | ||
6d82d43b | 1057 | break; /* end SPECIAL */ |
c5aa993b | 1058 | case 1: /* REGIMM */ |
c906108c | 1059 | { |
e135b889 DJ |
1060 | op = itype_rt (inst); /* branch condition */ |
1061 | switch (op) | |
c906108c | 1062 | { |
c5aa993b | 1063 | case 0: /* BLTZ */ |
e135b889 DJ |
1064 | case 2: /* BLTZL */ |
1065 | case 16: /* BLTZAL */ | |
c5aa993b | 1066 | case 18: /* BLTZALL */ |
c906108c | 1067 | less_branch: |
0b1b3e42 | 1068 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1069 | pc += mips32_relative_offset (inst) + 4; |
1070 | else | |
1071 | pc += 8; /* after the delay slot */ | |
1072 | break; | |
e135b889 | 1073 | case 1: /* BGEZ */ |
c5aa993b JM |
1074 | case 3: /* BGEZL */ |
1075 | case 17: /* BGEZAL */ | |
1076 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1077 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1078 | pc += mips32_relative_offset (inst) + 4; |
1079 | else | |
1080 | pc += 8; /* after the delay slot */ | |
1081 | break; | |
e135b889 | 1082 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1083 | default: |
1084 | pc += 4; | |
c906108c SS |
1085 | } |
1086 | } | |
6d82d43b | 1087 | break; /* end REGIMM */ |
c5aa993b JM |
1088 | case 2: /* J */ |
1089 | case 3: /* JAL */ | |
1090 | { | |
1091 | unsigned long reg; | |
1092 | reg = jtype_target (inst) << 2; | |
e135b889 | 1093 | /* Upper four bits get never changed... */ |
5b652102 | 1094 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1095 | } |
c5aa993b JM |
1096 | break; |
1097 | /* FIXME case JALX : */ | |
1098 | { | |
1099 | unsigned long reg; | |
1100 | reg = jtype_target (inst) << 2; | |
5b652102 | 1101 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1102 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1103 | } | |
c5aa993b | 1104 | break; /* The new PC will be alternate mode */ |
e135b889 | 1105 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1106 | equal_branch: |
0b1b3e42 UW |
1107 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1108 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1109 | pc += mips32_relative_offset (inst) + 4; |
1110 | else | |
1111 | pc += 8; | |
1112 | break; | |
e135b889 | 1113 | case 5: /* BNE, BNEL */ |
c5aa993b | 1114 | neq_branch: |
0b1b3e42 UW |
1115 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1116 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1117 | pc += mips32_relative_offset (inst) + 4; |
1118 | else | |
1119 | pc += 8; | |
1120 | break; | |
e135b889 | 1121 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1122 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1123 | pc += mips32_relative_offset (inst) + 4; |
1124 | else | |
1125 | pc += 8; | |
1126 | break; | |
1127 | case 7: | |
e135b889 DJ |
1128 | default: |
1129 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1130 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1131 | pc += mips32_relative_offset (inst) + 4; |
1132 | else | |
1133 | pc += 8; | |
1134 | break; | |
c5aa993b JM |
1135 | } /* switch */ |
1136 | } /* else */ | |
1137 | return pc; | |
1138 | } /* mips32_next_pc */ | |
c906108c SS |
1139 | |
1140 | /* Decoding the next place to set a breakpoint is irregular for the | |
e26cc349 | 1141 | mips 16 variant, but fortunately, there fewer instructions. We have to cope |
c906108c SS |
1142 | ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. |
1143 | We dont want to set a single step instruction on the extend instruction | |
1144 | either. | |
c5aa993b | 1145 | */ |
c906108c SS |
1146 | |
1147 | /* Lots of mips16 instruction formats */ | |
1148 | /* Predicting jumps requires itype,ritype,i8type | |
1149 | and their extensions extItype,extritype,extI8type | |
c5aa993b | 1150 | */ |
c906108c SS |
1151 | enum mips16_inst_fmts |
1152 | { | |
c5aa993b JM |
1153 | itype, /* 0 immediate 5,10 */ |
1154 | ritype, /* 1 5,3,8 */ | |
1155 | rrtype, /* 2 5,3,3,5 */ | |
1156 | rritype, /* 3 5,3,3,5 */ | |
1157 | rrrtype, /* 4 5,3,3,3,2 */ | |
1158 | rriatype, /* 5 5,3,3,1,4 */ | |
1159 | shifttype, /* 6 5,3,3,3,2 */ | |
1160 | i8type, /* 7 5,3,8 */ | |
1161 | i8movtype, /* 8 5,3,3,5 */ | |
1162 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1163 | i64type, /* 10 5,3,8 */ | |
1164 | ri64type, /* 11 5,3,3,5 */ | |
1165 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1166 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1167 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1168 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1169 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1170 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1171 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1172 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1173 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1174 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1175 | }; | |
12f02c2a AC |
1176 | /* I am heaping all the fields of the formats into one structure and |
1177 | then, only the fields which are involved in instruction extension */ | |
c906108c | 1178 | struct upk_mips16 |
6d82d43b AC |
1179 | { |
1180 | CORE_ADDR offset; | |
1181 | unsigned int regx; /* Function in i8 type */ | |
1182 | unsigned int regy; | |
1183 | }; | |
c906108c SS |
1184 | |
1185 | ||
12f02c2a AC |
1186 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
1187 | for the bits which make up the immediatate extension. */ | |
c906108c | 1188 | |
12f02c2a AC |
1189 | static CORE_ADDR |
1190 | extended_offset (unsigned int extension) | |
c906108c | 1191 | { |
12f02c2a | 1192 | CORE_ADDR value; |
c5aa993b JM |
1193 | value = (extension >> 21) & 0x3f; /* * extract 15:11 */ |
1194 | value = value << 6; | |
1195 | value |= (extension >> 16) & 0x1f; /* extrace 10:5 */ | |
1196 | value = value << 5; | |
1197 | value |= extension & 0x01f; /* extract 4:0 */ | |
1198 | return value; | |
c906108c SS |
1199 | } |
1200 | ||
1201 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1202 | instruction. It won't malfunction, but why make excess remote memory |
1203 | references? If the immediate operands get sign extended or something, | |
1204 | do it after the extension is performed. */ | |
c906108c | 1205 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1206 | when the offset is to be used in relative addressing. */ |
c906108c | 1207 | |
12f02c2a | 1208 | static unsigned int |
c5aa993b | 1209 | fetch_mips_16 (CORE_ADDR pc) |
c906108c | 1210 | { |
47a35522 | 1211 | gdb_byte buf[8]; |
c5aa993b JM |
1212 | pc &= 0xfffffffe; /* clear the low order bit */ |
1213 | target_read_memory (pc, buf, 2); | |
1214 | return extract_unsigned_integer (buf, 2); | |
c906108c SS |
1215 | } |
1216 | ||
1217 | static void | |
c5aa993b | 1218 | unpack_mips16 (CORE_ADDR pc, |
12f02c2a AC |
1219 | unsigned int extension, |
1220 | unsigned int inst, | |
6d82d43b | 1221 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1222 | { |
12f02c2a AC |
1223 | CORE_ADDR offset; |
1224 | int regx; | |
1225 | int regy; | |
1226 | switch (insn_format) | |
c906108c | 1227 | { |
c5aa993b | 1228 | case itype: |
c906108c | 1229 | { |
12f02c2a AC |
1230 | CORE_ADDR value; |
1231 | if (extension) | |
c5aa993b JM |
1232 | { |
1233 | value = extended_offset (extension); | |
1234 | value = value << 11; /* rom for the original value */ | |
6d82d43b | 1235 | value |= inst & 0x7ff; /* eleven bits from instruction */ |
c906108c SS |
1236 | } |
1237 | else | |
c5aa993b | 1238 | { |
12f02c2a | 1239 | value = inst & 0x7ff; |
c5aa993b | 1240 | /* FIXME : Consider sign extension */ |
c906108c | 1241 | } |
12f02c2a AC |
1242 | offset = value; |
1243 | regx = -1; | |
1244 | regy = -1; | |
c906108c | 1245 | } |
c5aa993b JM |
1246 | break; |
1247 | case ritype: | |
1248 | case i8type: | |
1249 | { /* A register identifier and an offset */ | |
c906108c SS |
1250 | /* Most of the fields are the same as I type but the |
1251 | immediate value is of a different length */ | |
12f02c2a AC |
1252 | CORE_ADDR value; |
1253 | if (extension) | |
c906108c | 1254 | { |
c5aa993b JM |
1255 | value = extended_offset (extension); |
1256 | value = value << 8; /* from the original instruction */ | |
12f02c2a AC |
1257 | value |= inst & 0xff; /* eleven bits from instruction */ |
1258 | regx = (extension >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1259 | if (value & 0x4000) /* test the sign bit , bit 26 */ |
1260 | { | |
1261 | value &= ~0x3fff; /* remove the sign bit */ | |
1262 | value = -value; | |
c906108c SS |
1263 | } |
1264 | } | |
c5aa993b JM |
1265 | else |
1266 | { | |
12f02c2a AC |
1267 | value = inst & 0xff; /* 8 bits */ |
1268 | regx = (inst >> 8) & 0x07; /* or i8 funct */ | |
c5aa993b JM |
1269 | /* FIXME: Do sign extension , this format needs it */ |
1270 | if (value & 0x80) /* THIS CONFUSES ME */ | |
1271 | { | |
1272 | value &= 0xef; /* remove the sign bit */ | |
1273 | value = -value; | |
1274 | } | |
c5aa993b | 1275 | } |
12f02c2a AC |
1276 | offset = value; |
1277 | regy = -1; | |
c5aa993b | 1278 | break; |
c906108c | 1279 | } |
c5aa993b | 1280 | case jalxtype: |
c906108c | 1281 | { |
c5aa993b | 1282 | unsigned long value; |
12f02c2a AC |
1283 | unsigned int nexthalf; |
1284 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b JM |
1285 | value = value << 16; |
1286 | nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */ | |
1287 | value |= nexthalf; | |
12f02c2a AC |
1288 | offset = value; |
1289 | regx = -1; | |
1290 | regy = -1; | |
c5aa993b | 1291 | break; |
c906108c SS |
1292 | } |
1293 | default: | |
e2e0b3e5 | 1294 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1295 | } |
12f02c2a AC |
1296 | upk->offset = offset; |
1297 | upk->regx = regx; | |
1298 | upk->regy = regy; | |
c906108c SS |
1299 | } |
1300 | ||
1301 | ||
c5aa993b JM |
1302 | static CORE_ADDR |
1303 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1304 | { |
5b652102 | 1305 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1306 | } |
1307 | ||
12f02c2a | 1308 | static CORE_ADDR |
0b1b3e42 | 1309 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1310 | unsigned int extension, unsigned int insn) |
c906108c | 1311 | { |
12f02c2a AC |
1312 | int op = (insn >> 11); |
1313 | switch (op) | |
c906108c | 1314 | { |
6d82d43b | 1315 | case 2: /* Branch */ |
12f02c2a AC |
1316 | { |
1317 | CORE_ADDR offset; | |
1318 | struct upk_mips16 upk; | |
1319 | unpack_mips16 (pc, extension, insn, itype, &upk); | |
1320 | offset = upk.offset; | |
1321 | if (offset & 0x800) | |
1322 | { | |
1323 | offset &= 0xeff; | |
1324 | offset = -offset; | |
1325 | } | |
1326 | pc += (offset << 1) + 2; | |
1327 | break; | |
1328 | } | |
6d82d43b | 1329 | case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */ |
12f02c2a AC |
1330 | { |
1331 | struct upk_mips16 upk; | |
1332 | unpack_mips16 (pc, extension, insn, jalxtype, &upk); | |
1333 | pc = add_offset_16 (pc, upk.offset); | |
1334 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
1335 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */ | |
1336 | else | |
1337 | pc |= 0x01; | |
1338 | break; | |
1339 | } | |
6d82d43b | 1340 | case 4: /* beqz */ |
12f02c2a AC |
1341 | { |
1342 | struct upk_mips16 upk; | |
1343 | int reg; | |
1344 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1345 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1346 | if (reg == 0) |
1347 | pc += (upk.offset << 1) + 2; | |
1348 | else | |
1349 | pc += 2; | |
1350 | break; | |
1351 | } | |
6d82d43b | 1352 | case 5: /* bnez */ |
12f02c2a AC |
1353 | { |
1354 | struct upk_mips16 upk; | |
1355 | int reg; | |
1356 | unpack_mips16 (pc, extension, insn, ritype, &upk); | |
0b1b3e42 | 1357 | reg = get_frame_register_signed (frame, upk.regx); |
12f02c2a AC |
1358 | if (reg != 0) |
1359 | pc += (upk.offset << 1) + 2; | |
1360 | else | |
1361 | pc += 2; | |
1362 | break; | |
1363 | } | |
6d82d43b | 1364 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1365 | { |
1366 | struct upk_mips16 upk; | |
1367 | int reg; | |
1368 | unpack_mips16 (pc, extension, insn, i8type, &upk); | |
1369 | /* upk.regx contains the opcode */ | |
0b1b3e42 | 1370 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1371 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1372 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1373 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1374 | pc += (upk.offset << 1) + 2; | |
1375 | else | |
1376 | pc += 2; | |
1377 | break; | |
1378 | } | |
6d82d43b | 1379 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1380 | { |
1381 | struct upk_mips16 upk; | |
1382 | /* upk.fmt = rrtype; */ | |
1383 | op = insn & 0x1f; | |
1384 | if (op == 0) | |
c5aa993b | 1385 | { |
12f02c2a AC |
1386 | int reg; |
1387 | upk.regx = (insn >> 8) & 0x07; | |
1388 | upk.regy = (insn >> 5) & 0x07; | |
1389 | switch (upk.regy) | |
c5aa993b | 1390 | { |
12f02c2a AC |
1391 | case 0: |
1392 | reg = upk.regx; | |
1393 | break; | |
1394 | case 1: | |
1395 | reg = 31; | |
6d82d43b | 1396 | break; /* Function return instruction */ |
12f02c2a AC |
1397 | case 2: |
1398 | reg = upk.regx; | |
1399 | break; | |
1400 | default: | |
1401 | reg = 31; | |
6d82d43b | 1402 | break; /* BOGUS Guess */ |
c906108c | 1403 | } |
0b1b3e42 | 1404 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1405 | } |
12f02c2a | 1406 | else |
c5aa993b | 1407 | pc += 2; |
12f02c2a AC |
1408 | break; |
1409 | } | |
1410 | case 30: | |
1411 | /* This is an instruction extension. Fetch the real instruction | |
1412 | (which follows the extension) and decode things based on | |
1413 | that. */ | |
1414 | { | |
1415 | pc += 2; | |
0b1b3e42 | 1416 | pc = extended_mips16_next_pc (frame, pc, insn, fetch_mips_16 (pc)); |
12f02c2a AC |
1417 | break; |
1418 | } | |
1419 | default: | |
1420 | { | |
1421 | pc += 2; | |
1422 | break; | |
1423 | } | |
c906108c | 1424 | } |
c5aa993b | 1425 | return pc; |
12f02c2a | 1426 | } |
c906108c | 1427 | |
5a89d8aa | 1428 | static CORE_ADDR |
0b1b3e42 | 1429 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a AC |
1430 | { |
1431 | unsigned int insn = fetch_mips_16 (pc); | |
0b1b3e42 | 1432 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1433 | } |
1434 | ||
1435 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1436 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a AC |
1437 | It works by decoding the current instruction and predicting where a |
1438 | branch will go. This isnt hard because all the data is available. | |
ce1f96de | 1439 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1440 | static CORE_ADDR |
0b1b3e42 | 1441 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1442 | { |
ce1f96de | 1443 | if (is_mips16_addr (pc)) |
0b1b3e42 | 1444 | return mips16_next_pc (frame, pc); |
c5aa993b | 1445 | else |
0b1b3e42 | 1446 | return mips32_next_pc (frame, pc); |
12f02c2a | 1447 | } |
c906108c | 1448 | |
edfae063 AC |
1449 | struct mips_frame_cache |
1450 | { | |
1451 | CORE_ADDR base; | |
1452 | struct trad_frame_saved_reg *saved_regs; | |
1453 | }; | |
1454 | ||
29639122 JB |
1455 | /* Set a register's saved stack address in temp_saved_regs. If an |
1456 | address has already been set for this register, do nothing; this | |
1457 | way we will only recognize the first save of a given register in a | |
1458 | function prologue. | |
eec63939 | 1459 | |
f57d151a UW |
1460 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1461 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1462 | Strictly speaking, only the second range is used as it is only second | |
1463 | range (the ABI instead of ISA registers) that comes into play when finding | |
1464 | saved registers in a frame. */ | |
eec63939 AC |
1465 | |
1466 | static void | |
29639122 JB |
1467 | set_reg_offset (struct mips_frame_cache *this_cache, int regnum, |
1468 | CORE_ADDR offset) | |
eec63939 | 1469 | { |
29639122 JB |
1470 | if (this_cache != NULL |
1471 | && this_cache->saved_regs[regnum].addr == -1) | |
1472 | { | |
f57d151a UW |
1473 | this_cache->saved_regs[regnum |
1474 | + 0 * gdbarch_num_regs (current_gdbarch)].addr | |
1475 | = offset; | |
1476 | this_cache->saved_regs[regnum | |
1477 | + 1 * gdbarch_num_regs (current_gdbarch)].addr | |
1478 | = offset; | |
29639122 | 1479 | } |
eec63939 AC |
1480 | } |
1481 | ||
eec63939 | 1482 | |
29639122 JB |
1483 | /* Fetch the immediate value from a MIPS16 instruction. |
1484 | If the previous instruction was an EXTEND, use it to extend | |
1485 | the upper bits of the immediate value. This is a helper function | |
1486 | for mips16_scan_prologue. */ | |
eec63939 | 1487 | |
29639122 JB |
1488 | static int |
1489 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1490 | unsigned short inst, /* current instruction */ | |
1491 | int nbits, /* number of bits in imm field */ | |
1492 | int scale, /* scale factor to be applied to imm */ | |
1493 | int is_signed) /* is the imm field signed? */ | |
eec63939 | 1494 | { |
29639122 | 1495 | int offset; |
eec63939 | 1496 | |
29639122 JB |
1497 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1498 | { | |
1499 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1500 | if (offset & 0x8000) /* check for negative extend */ | |
1501 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1502 | return offset | (inst & 0x1f); | |
1503 | } | |
eec63939 | 1504 | else |
29639122 JB |
1505 | { |
1506 | int max_imm = 1 << nbits; | |
1507 | int mask = max_imm - 1; | |
1508 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1509 | |
29639122 JB |
1510 | offset = inst & mask; |
1511 | if (is_signed && (offset & sign_bit)) | |
1512 | offset = 0 - (max_imm - offset); | |
1513 | return offset * scale; | |
1514 | } | |
1515 | } | |
eec63939 | 1516 | |
65596487 | 1517 | |
29639122 JB |
1518 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1519 | the associated FRAME_CACHE if not null. | |
1520 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1521 | |
29639122 JB |
1522 | static CORE_ADDR |
1523 | mips16_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
1524 | struct frame_info *next_frame, | |
1525 | struct mips_frame_cache *this_cache) | |
1526 | { | |
1527 | CORE_ADDR cur_pc; | |
1528 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer */ | |
1529 | CORE_ADDR sp; | |
1530 | long frame_offset = 0; /* Size of stack frame. */ | |
1531 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1532 | int frame_reg = MIPS_SP_REGNUM; | |
1533 | unsigned short prev_inst = 0; /* saved copy of previous instruction */ | |
1534 | unsigned inst = 0; /* current instruction */ | |
1535 | unsigned entry_inst = 0; /* the entry instruction */ | |
1536 | int reg, offset; | |
a343eb3c | 1537 | |
29639122 JB |
1538 | int extend_bytes = 0; |
1539 | int prev_extend_bytes; | |
1540 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1541 | |
29639122 JB |
1542 | /* Can be called when there's no process, and hence when there's no |
1543 | NEXT_FRAME. */ | |
1544 | if (next_frame != NULL) | |
d2ca4222 UW |
1545 | sp = frame_unwind_register_signed (next_frame, |
1546 | gdbarch_num_regs (current_gdbarch) | |
1547 | + MIPS_SP_REGNUM); | |
29639122 JB |
1548 | else |
1549 | sp = 0; | |
eec63939 | 1550 | |
29639122 JB |
1551 | if (limit_pc > start_pc + 200) |
1552 | limit_pc = start_pc + 200; | |
eec63939 | 1553 | |
95ac2dcf | 1554 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1555 | { |
1556 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1557 | the immediate offset extension from it in mips16_get_imm. */ | |
1558 | prev_inst = inst; | |
eec63939 | 1559 | |
29639122 JB |
1560 | /* Fetch and decode the instruction. */ |
1561 | inst = (unsigned short) mips_fetch_instruction (cur_pc); | |
eec63939 | 1562 | |
29639122 JB |
1563 | /* Normally we ignore extend instructions. However, if it is |
1564 | not followed by a valid prologue instruction, then this | |
1565 | instruction is not part of the prologue either. We must | |
1566 | remember in this case to adjust the end_prologue_addr back | |
1567 | over the extend. */ | |
1568 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1569 | { | |
95ac2dcf | 1570 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1571 | continue; |
1572 | } | |
eec63939 | 1573 | |
29639122 JB |
1574 | prev_extend_bytes = extend_bytes; |
1575 | extend_bytes = 0; | |
eec63939 | 1576 | |
29639122 JB |
1577 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1578 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1579 | { | |
1580 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
1581 | if (offset < 0) /* negative stack adjustment? */ | |
1582 | frame_offset -= offset; | |
1583 | else | |
1584 | /* Exit loop if a positive stack adjustment is found, which | |
1585 | usually means that the stack cleanup code in the function | |
1586 | epilogue is reached. */ | |
1587 | break; | |
1588 | } | |
1589 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1590 | { | |
1591 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1592 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
1593 | set_reg_offset (this_cache, reg, sp + offset); | |
1594 | } | |
1595 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1596 | { | |
1597 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1598 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1599 | set_reg_offset (this_cache, reg, sp + offset); | |
1600 | } | |
1601 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1602 | { | |
1603 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4c7d22cb | 1604 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1605 | } |
1606 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1607 | { | |
1608 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
4c7d22cb | 1609 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1610 | } |
1611 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1612 | { | |
1613 | frame_addr = sp; | |
1614 | frame_reg = 17; | |
1615 | } | |
1616 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1617 | { | |
1618 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1619 | frame_addr = sp + offset; | |
1620 | frame_reg = 17; | |
1621 | frame_adjust = offset; | |
1622 | } | |
1623 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1624 | { | |
1625 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1626 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1627 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1628 | } | |
1629 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1630 | { | |
1631 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1632 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
1633 | set_reg_offset (this_cache, reg, frame_addr + offset); | |
1634 | } | |
1635 | else if ((inst & 0xf81f) == 0xe809 | |
1636 | && (inst & 0x700) != 0x700) /* entry */ | |
1637 | entry_inst = inst; /* save for later processing */ | |
1638 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ | |
95ac2dcf | 1639 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1640 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1641 | { | |
1642 | /* This instruction is part of the prologue, but we don't | |
1643 | need to do anything special to handle it. */ | |
1644 | } | |
1645 | else | |
1646 | { | |
1647 | /* This instruction is not an instruction typically found | |
1648 | in a prologue, so we must have reached the end of the | |
1649 | prologue. */ | |
1650 | if (end_prologue_addr == 0) | |
1651 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1652 | } | |
1653 | } | |
eec63939 | 1654 | |
29639122 JB |
1655 | /* The entry instruction is typically the first instruction in a function, |
1656 | and it stores registers at offsets relative to the value of the old SP | |
1657 | (before the prologue). But the value of the sp parameter to this | |
1658 | function is the new SP (after the prologue has been executed). So we | |
1659 | can't calculate those offsets until we've seen the entire prologue, | |
1660 | and can calculate what the old SP must have been. */ | |
1661 | if (entry_inst != 0) | |
1662 | { | |
1663 | int areg_count = (entry_inst >> 8) & 7; | |
1664 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1665 | |
29639122 JB |
1666 | /* The entry instruction always subtracts 32 from the SP. */ |
1667 | frame_offset += 32; | |
1668 | ||
1669 | /* Now we can calculate what the SP must have been at the | |
1670 | start of the function prologue. */ | |
1671 | sp += frame_offset; | |
1672 | ||
1673 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1674 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1675 | { | |
1676 | set_reg_offset (this_cache, reg, sp + offset); | |
1677 | offset += mips_abi_regsize (current_gdbarch); | |
1678 | } | |
1679 | ||
1680 | /* Check if the ra register was pushed on the stack. */ | |
1681 | offset = -4; | |
1682 | if (entry_inst & 0x20) | |
1683 | { | |
4c7d22cb | 1684 | set_reg_offset (this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1685 | offset -= mips_abi_regsize (current_gdbarch); |
1686 | } | |
1687 | ||
1688 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1689 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1690 | { | |
1691 | set_reg_offset (this_cache, reg, sp + offset); | |
1692 | offset -= mips_abi_regsize (current_gdbarch); | |
1693 | } | |
1694 | } | |
1695 | ||
1696 | if (this_cache != NULL) | |
1697 | { | |
1698 | this_cache->base = | |
f57d151a UW |
1699 | (frame_unwind_register_signed (next_frame, |
1700 | gdbarch_num_regs (current_gdbarch) | |
1701 | + frame_reg) | |
29639122 JB |
1702 | + frame_offset - frame_adjust); |
1703 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
1704 | be able to get rid of the assignment below, evetually. But it's | |
1705 | still needed for now. */ | |
f57d151a UW |
1706 | this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) |
1707 | + mips_regnum (current_gdbarch)->pc] | |
1708 | = this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) | |
1709 | + MIPS_RA_REGNUM]; | |
29639122 JB |
1710 | } |
1711 | ||
1712 | /* If we didn't reach the end of the prologue when scanning the function | |
1713 | instructions, then set end_prologue_addr to the address of the | |
1714 | instruction immediately after the last one we scanned. */ | |
1715 | if (end_prologue_addr == 0) | |
1716 | end_prologue_addr = cur_pc; | |
1717 | ||
1718 | return end_prologue_addr; | |
eec63939 AC |
1719 | } |
1720 | ||
29639122 JB |
1721 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1722 | Procedures that use the 32-bit instruction set are handled by the | |
1723 | mips_insn32 unwinder. */ | |
1724 | ||
1725 | static struct mips_frame_cache * | |
1726 | mips_insn16_frame_cache (struct frame_info *next_frame, void **this_cache) | |
eec63939 | 1727 | { |
29639122 | 1728 | struct mips_frame_cache *cache; |
eec63939 AC |
1729 | |
1730 | if ((*this_cache) != NULL) | |
1731 | return (*this_cache); | |
29639122 JB |
1732 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
1733 | (*this_cache) = cache; | |
1734 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
eec63939 | 1735 | |
29639122 JB |
1736 | /* Analyze the function prologue. */ |
1737 | { | |
6de5b849 JB |
1738 | const CORE_ADDR pc = |
1739 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 1740 | CORE_ADDR start_addr; |
eec63939 | 1741 | |
29639122 JB |
1742 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
1743 | if (start_addr == 0) | |
1744 | start_addr = heuristic_proc_start (pc); | |
1745 | /* We can't analyze the prologue if we couldn't find the begining | |
1746 | of the function. */ | |
1747 | if (start_addr == 0) | |
1748 | return cache; | |
eec63939 | 1749 | |
29639122 JB |
1750 | mips16_scan_prologue (start_addr, pc, next_frame, *this_cache); |
1751 | } | |
1752 | ||
3e8c568d | 1753 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a UW |
1754 | trad_frame_set_value (cache->saved_regs, gdbarch_num_regs (current_gdbarch) |
1755 | + MIPS_SP_REGNUM, cache->base); | |
eec63939 | 1756 | |
29639122 | 1757 | return (*this_cache); |
eec63939 AC |
1758 | } |
1759 | ||
1760 | static void | |
29639122 JB |
1761 | mips_insn16_frame_this_id (struct frame_info *next_frame, void **this_cache, |
1762 | struct frame_id *this_id) | |
eec63939 | 1763 | { |
29639122 JB |
1764 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1765 | this_cache); | |
93d42b30 DJ |
1766 | (*this_id) = frame_id_build (info->base, |
1767 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
eec63939 AC |
1768 | } |
1769 | ||
1770 | static void | |
29639122 | 1771 | mips_insn16_frame_prev_register (struct frame_info *next_frame, |
eec63939 AC |
1772 | void **this_cache, |
1773 | int regnum, int *optimizedp, | |
1774 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 1775 | int *realnump, gdb_byte *valuep) |
eec63939 | 1776 | { |
29639122 JB |
1777 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1778 | this_cache); | |
1779 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
1780 | optimizedp, lvalp, addrp, realnump, valuep); | |
eec63939 AC |
1781 | } |
1782 | ||
29639122 | 1783 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
1784 | { |
1785 | NORMAL_FRAME, | |
29639122 JB |
1786 | mips_insn16_frame_this_id, |
1787 | mips_insn16_frame_prev_register | |
eec63939 AC |
1788 | }; |
1789 | ||
1790 | static const struct frame_unwind * | |
29639122 | 1791 | mips_insn16_frame_sniffer (struct frame_info *next_frame) |
eec63939 | 1792 | { |
6de5b849 | 1793 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 1794 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
1795 | return &mips_insn16_frame_unwind; |
1796 | return NULL; | |
eec63939 AC |
1797 | } |
1798 | ||
1799 | static CORE_ADDR | |
29639122 JB |
1800 | mips_insn16_frame_base_address (struct frame_info *next_frame, |
1801 | void **this_cache) | |
eec63939 | 1802 | { |
29639122 JB |
1803 | struct mips_frame_cache *info = mips_insn16_frame_cache (next_frame, |
1804 | this_cache); | |
1805 | return info->base; | |
eec63939 AC |
1806 | } |
1807 | ||
29639122 | 1808 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 1809 | { |
29639122 JB |
1810 | &mips_insn16_frame_unwind, |
1811 | mips_insn16_frame_base_address, | |
1812 | mips_insn16_frame_base_address, | |
1813 | mips_insn16_frame_base_address | |
eec63939 AC |
1814 | }; |
1815 | ||
1816 | static const struct frame_base * | |
29639122 | 1817 | mips_insn16_frame_base_sniffer (struct frame_info *next_frame) |
eec63939 | 1818 | { |
29639122 JB |
1819 | if (mips_insn16_frame_sniffer (next_frame) != NULL) |
1820 | return &mips_insn16_frame_base; | |
eec63939 AC |
1821 | else |
1822 | return NULL; | |
edfae063 AC |
1823 | } |
1824 | ||
29639122 JB |
1825 | /* Mark all the registers as unset in the saved_regs array |
1826 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
1827 | ||
1828 | void | |
1829 | reset_saved_regs (struct mips_frame_cache *this_cache) | |
c906108c | 1830 | { |
29639122 JB |
1831 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
1832 | return; | |
1833 | ||
1834 | { | |
f57d151a | 1835 | const int num_regs = gdbarch_num_regs (current_gdbarch); |
29639122 | 1836 | int i; |
64159455 | 1837 | |
29639122 JB |
1838 | for (i = 0; i < num_regs; i++) |
1839 | { | |
1840 | this_cache->saved_regs[i].addr = -1; | |
1841 | } | |
1842 | } | |
c906108c SS |
1843 | } |
1844 | ||
29639122 JB |
1845 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1846 | the associated FRAME_CACHE if not null. | |
1847 | Return the address of the first instruction past the prologue. */ | |
c906108c | 1848 | |
875e1767 | 1849 | static CORE_ADDR |
29639122 JB |
1850 | mips32_scan_prologue (CORE_ADDR start_pc, CORE_ADDR limit_pc, |
1851 | struct frame_info *next_frame, | |
1852 | struct mips_frame_cache *this_cache) | |
c906108c | 1853 | { |
29639122 JB |
1854 | CORE_ADDR cur_pc; |
1855 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for frame-pointer */ | |
1856 | CORE_ADDR sp; | |
1857 | long frame_offset; | |
1858 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 1859 | |
29639122 JB |
1860 | CORE_ADDR end_prologue_addr = 0; |
1861 | int seen_sp_adjust = 0; | |
1862 | int load_immediate_bytes = 0; | |
8fa9cfa1 | 1863 | |
29639122 JB |
1864 | /* Can be called when there's no process, and hence when there's no |
1865 | NEXT_FRAME. */ | |
1866 | if (next_frame != NULL) | |
d2ca4222 UW |
1867 | sp = frame_unwind_register_signed (next_frame, |
1868 | gdbarch_num_regs (current_gdbarch) | |
1869 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 1870 | else |
29639122 | 1871 | sp = 0; |
9022177c | 1872 | |
29639122 JB |
1873 | if (limit_pc > start_pc + 200) |
1874 | limit_pc = start_pc + 200; | |
9022177c | 1875 | |
29639122 | 1876 | restart: |
9022177c | 1877 | |
29639122 | 1878 | frame_offset = 0; |
95ac2dcf | 1879 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 1880 | { |
29639122 JB |
1881 | unsigned long inst, high_word, low_word; |
1882 | int reg; | |
9022177c | 1883 | |
29639122 JB |
1884 | /* Fetch the instruction. */ |
1885 | inst = (unsigned long) mips_fetch_instruction (cur_pc); | |
9022177c | 1886 | |
29639122 JB |
1887 | /* Save some code by pre-extracting some useful fields. */ |
1888 | high_word = (inst >> 16) & 0xffff; | |
1889 | low_word = inst & 0xffff; | |
1890 | reg = high_word & 0x1f; | |
fe29b929 | 1891 | |
29639122 JB |
1892 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
1893 | || high_word == 0x23bd /* addi $sp,$sp,-i */ | |
1894 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
1895 | { | |
1896 | if (low_word & 0x8000) /* negative stack adjustment? */ | |
1897 | frame_offset += 0x10000 - low_word; | |
1898 | else | |
1899 | /* Exit loop if a positive stack adjustment is found, which | |
1900 | usually means that the stack cleanup code in the function | |
1901 | epilogue is reached. */ | |
1902 | break; | |
1903 | seen_sp_adjust = 1; | |
1904 | } | |
1905 | else if ((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ | |
1906 | { | |
1907 | set_reg_offset (this_cache, reg, sp + low_word); | |
1908 | } | |
1909 | else if ((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ | |
1910 | { | |
1911 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
1912 | set_reg_offset (this_cache, reg, sp + low_word); | |
1913 | } | |
1914 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
1915 | { | |
1916 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
1917 | if ((long) low_word != frame_offset) | |
1918 | frame_addr = sp + low_word; | |
d2ca4222 | 1919 | else if (next_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1920 | { |
1921 | unsigned alloca_adjust; | |
a4b8ebc8 | 1922 | |
29639122 | 1923 | frame_reg = 30; |
d2ca4222 UW |
1924 | frame_addr = frame_unwind_register_signed |
1925 | (next_frame, | |
1926 | gdbarch_num_regs (current_gdbarch) + 30); | |
1927 | ||
29639122 JB |
1928 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
1929 | if (alloca_adjust > 0) | |
1930 | { | |
1931 | /* FP > SP + frame_size. This may be because of | |
1932 | an alloca or somethings similar. Fix sp to | |
1933 | "pre-alloca" value, and try again. */ | |
1934 | sp += alloca_adjust; | |
1935 | /* Need to reset the status of all registers. Otherwise, | |
1936 | we will hit a guard that prevents the new address | |
1937 | for each register to be recomputed during the second | |
1938 | pass. */ | |
1939 | reset_saved_regs (this_cache); | |
1940 | goto restart; | |
1941 | } | |
1942 | } | |
1943 | } | |
1944 | /* move $30,$sp. With different versions of gas this will be either | |
1945 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
1946 | Accept any one of these. */ | |
1947 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
1948 | { | |
1949 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
d2ca4222 | 1950 | if (next_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
1951 | { |
1952 | unsigned alloca_adjust; | |
c906108c | 1953 | |
29639122 | 1954 | frame_reg = 30; |
d2ca4222 UW |
1955 | frame_addr = frame_unwind_register_signed |
1956 | (next_frame, | |
1957 | gdbarch_num_regs (current_gdbarch) + 30); | |
1958 | ||
29639122 JB |
1959 | alloca_adjust = (unsigned) (frame_addr - sp); |
1960 | if (alloca_adjust > 0) | |
1961 | { | |
1962 | /* FP > SP + frame_size. This may be because of | |
1963 | an alloca or somethings similar. Fix sp to | |
1964 | "pre-alloca" value, and try again. */ | |
1965 | sp = frame_addr; | |
1966 | /* Need to reset the status of all registers. Otherwise, | |
1967 | we will hit a guard that prevents the new address | |
1968 | for each register to be recomputed during the second | |
1969 | pass. */ | |
1970 | reset_saved_regs (this_cache); | |
1971 | goto restart; | |
1972 | } | |
1973 | } | |
1974 | } | |
1975 | else if ((high_word & 0xFFE0) == 0xafc0) /* sw reg,offset($30) */ | |
1976 | { | |
1977 | set_reg_offset (this_cache, reg, frame_addr + low_word); | |
1978 | } | |
1979 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
1980 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
1981 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
1982 | || high_word == 0x3c1c /* lui $gp,n */ | |
1983 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
1984 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
1985 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
1986 | ) | |
1987 | { | |
1988 | /* These instructions are part of the prologue, but we don't | |
1989 | need to do anything special to handle them. */ | |
1990 | } | |
1991 | /* The instructions below load $at or $t0 with an immediate | |
1992 | value in preparation for a stack adjustment via | |
1993 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
1994 | initialize a local variable, so we accept them only before | |
1995 | a stack adjustment instruction was seen. */ | |
1996 | else if (!seen_sp_adjust | |
1997 | && (high_word == 0x3c01 /* lui $at,n */ | |
1998 | || high_word == 0x3c08 /* lui $t0,n */ | |
1999 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2000 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2001 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2002 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2003 | )) | |
2004 | { | |
95ac2dcf | 2005 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
29639122 JB |
2006 | } |
2007 | else | |
2008 | { | |
2009 | /* This instruction is not an instruction typically found | |
2010 | in a prologue, so we must have reached the end of the | |
2011 | prologue. */ | |
2012 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2013 | loop now? Why would we need to continue scanning the function | |
2014 | instructions? */ | |
2015 | if (end_prologue_addr == 0) | |
2016 | end_prologue_addr = cur_pc; | |
2017 | } | |
a4b8ebc8 | 2018 | } |
c906108c | 2019 | |
29639122 JB |
2020 | if (this_cache != NULL) |
2021 | { | |
2022 | this_cache->base = | |
f57d151a UW |
2023 | (frame_unwind_register_signed (next_frame, |
2024 | gdbarch_num_regs (current_gdbarch) | |
2025 | + frame_reg) | |
29639122 JB |
2026 | + frame_offset); |
2027 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2028 | this assignment below, eventually. But it's still needed | |
2029 | for now. */ | |
f57d151a UW |
2030 | this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) |
2031 | + mips_regnum (current_gdbarch)->pc] | |
2032 | = this_cache->saved_regs[gdbarch_num_regs (current_gdbarch) | |
2033 | + MIPS_RA_REGNUM]; | |
29639122 | 2034 | } |
c906108c | 2035 | |
29639122 JB |
2036 | /* If we didn't reach the end of the prologue when scanning the function |
2037 | instructions, then set end_prologue_addr to the address of the | |
2038 | instruction immediately after the last one we scanned. */ | |
2039 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2040 | we may as well be careful and do our best if we have a null | |
2041 | end_prologue_addr. */ | |
2042 | if (end_prologue_addr == 0) | |
2043 | end_prologue_addr = cur_pc; | |
2044 | ||
2045 | /* In a frameless function, we might have incorrectly | |
2046 | skipped some load immediate instructions. Undo the skipping | |
2047 | if the load immediate was not followed by a stack adjustment. */ | |
2048 | if (load_immediate_bytes && !seen_sp_adjust) | |
2049 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2050 | |
29639122 | 2051 | return end_prologue_addr; |
c906108c SS |
2052 | } |
2053 | ||
29639122 JB |
2054 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2055 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2056 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2057 | unwinder. */ | |
c906108c | 2058 | |
29639122 JB |
2059 | static struct mips_frame_cache * |
2060 | mips_insn32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 2061 | { |
29639122 | 2062 | struct mips_frame_cache *cache; |
c906108c | 2063 | |
29639122 JB |
2064 | if ((*this_cache) != NULL) |
2065 | return (*this_cache); | |
c5aa993b | 2066 | |
29639122 JB |
2067 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2068 | (*this_cache) = cache; | |
2069 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
c5aa993b | 2070 | |
29639122 JB |
2071 | /* Analyze the function prologue. */ |
2072 | { | |
6de5b849 JB |
2073 | const CORE_ADDR pc = |
2074 | frame_unwind_address_in_block (next_frame, NORMAL_FRAME); | |
29639122 | 2075 | CORE_ADDR start_addr; |
c906108c | 2076 | |
29639122 JB |
2077 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2078 | if (start_addr == 0) | |
2079 | start_addr = heuristic_proc_start (pc); | |
2080 | /* We can't analyze the prologue if we couldn't find the begining | |
2081 | of the function. */ | |
2082 | if (start_addr == 0) | |
2083 | return cache; | |
c5aa993b | 2084 | |
29639122 JB |
2085 | mips32_scan_prologue (start_addr, pc, next_frame, *this_cache); |
2086 | } | |
2087 | ||
3e8c568d | 2088 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a UW |
2089 | trad_frame_set_value (cache->saved_regs, |
2090 | gdbarch_num_regs (current_gdbarch) + MIPS_SP_REGNUM, | |
2091 | cache->base); | |
c5aa993b | 2092 | |
29639122 | 2093 | return (*this_cache); |
c906108c SS |
2094 | } |
2095 | ||
29639122 JB |
2096 | static void |
2097 | mips_insn32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2098 | struct frame_id *this_id) | |
c906108c | 2099 | { |
29639122 JB |
2100 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2101 | this_cache); | |
93d42b30 DJ |
2102 | (*this_id) = frame_id_build (info->base, |
2103 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
29639122 | 2104 | } |
c906108c | 2105 | |
29639122 JB |
2106 | static void |
2107 | mips_insn32_frame_prev_register (struct frame_info *next_frame, | |
2108 | void **this_cache, | |
2109 | int regnum, int *optimizedp, | |
2110 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2111 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2112 | { |
2113 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, | |
2114 | this_cache); | |
2115 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, | |
2116 | optimizedp, lvalp, addrp, realnump, valuep); | |
c906108c SS |
2117 | } |
2118 | ||
29639122 JB |
2119 | static const struct frame_unwind mips_insn32_frame_unwind = |
2120 | { | |
2121 | NORMAL_FRAME, | |
2122 | mips_insn32_frame_this_id, | |
2123 | mips_insn32_frame_prev_register | |
2124 | }; | |
c906108c | 2125 | |
29639122 JB |
2126 | static const struct frame_unwind * |
2127 | mips_insn32_frame_sniffer (struct frame_info *next_frame) | |
2128 | { | |
6de5b849 | 2129 | CORE_ADDR pc = frame_pc_unwind (next_frame); |
0fe7e7c8 | 2130 | if (! mips_pc_is_mips16 (pc)) |
29639122 JB |
2131 | return &mips_insn32_frame_unwind; |
2132 | return NULL; | |
2133 | } | |
c906108c | 2134 | |
1c645fec | 2135 | static CORE_ADDR |
29639122 JB |
2136 | mips_insn32_frame_base_address (struct frame_info *next_frame, |
2137 | void **this_cache) | |
c906108c | 2138 | { |
29639122 JB |
2139 | struct mips_frame_cache *info = mips_insn32_frame_cache (next_frame, |
2140 | this_cache); | |
2141 | return info->base; | |
2142 | } | |
c906108c | 2143 | |
29639122 JB |
2144 | static const struct frame_base mips_insn32_frame_base = |
2145 | { | |
2146 | &mips_insn32_frame_unwind, | |
2147 | mips_insn32_frame_base_address, | |
2148 | mips_insn32_frame_base_address, | |
2149 | mips_insn32_frame_base_address | |
2150 | }; | |
1c645fec | 2151 | |
29639122 JB |
2152 | static const struct frame_base * |
2153 | mips_insn32_frame_base_sniffer (struct frame_info *next_frame) | |
2154 | { | |
2155 | if (mips_insn32_frame_sniffer (next_frame) != NULL) | |
2156 | return &mips_insn32_frame_base; | |
a65bbe44 | 2157 | else |
29639122 JB |
2158 | return NULL; |
2159 | } | |
a65bbe44 | 2160 | |
29639122 JB |
2161 | static struct trad_frame_cache * |
2162 | mips_stub_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2163 | { | |
2164 | CORE_ADDR pc; | |
2165 | CORE_ADDR start_addr; | |
2166 | CORE_ADDR stack_addr; | |
2167 | struct trad_frame_cache *this_trad_cache; | |
c906108c | 2168 | |
29639122 JB |
2169 | if ((*this_cache) != NULL) |
2170 | return (*this_cache); | |
2171 | this_trad_cache = trad_frame_cache_zalloc (next_frame); | |
2172 | (*this_cache) = this_trad_cache; | |
1c645fec | 2173 | |
29639122 | 2174 | /* The return address is in the link register. */ |
3e8c568d UW |
2175 | trad_frame_set_reg_realreg (this_trad_cache, |
2176 | gdbarch_pc_regnum (current_gdbarch), | |
aa6c981f DJ |
2177 | (gdbarch_num_regs (current_gdbarch) |
2178 | + MIPS_RA_REGNUM)); | |
1c645fec | 2179 | |
29639122 JB |
2180 | /* Frame ID, since it's a frameless / stackless function, no stack |
2181 | space is allocated and SP on entry is the current SP. */ | |
2182 | pc = frame_pc_unwind (next_frame); | |
2183 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
4c7d22cb | 2184 | stack_addr = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM); |
aa6c981f | 2185 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2186 | |
29639122 JB |
2187 | /* Assume that the frame's base is the same as the |
2188 | stack-pointer. */ | |
2189 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2190 | |
29639122 JB |
2191 | return this_trad_cache; |
2192 | } | |
c906108c | 2193 | |
29639122 JB |
2194 | static void |
2195 | mips_stub_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2196 | struct frame_id *this_id) | |
2197 | { | |
2198 | struct trad_frame_cache *this_trad_cache | |
2199 | = mips_stub_frame_cache (next_frame, this_cache); | |
2200 | trad_frame_get_id (this_trad_cache, this_id); | |
2201 | } | |
c906108c | 2202 | |
29639122 JB |
2203 | static void |
2204 | mips_stub_frame_prev_register (struct frame_info *next_frame, | |
2205 | void **this_cache, | |
2206 | int regnum, int *optimizedp, | |
2207 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
a8a0fc4c | 2208 | int *realnump, gdb_byte *valuep) |
29639122 JB |
2209 | { |
2210 | struct trad_frame_cache *this_trad_cache | |
2211 | = mips_stub_frame_cache (next_frame, this_cache); | |
2212 | trad_frame_get_register (this_trad_cache, next_frame, regnum, optimizedp, | |
2213 | lvalp, addrp, realnump, valuep); | |
2214 | } | |
c906108c | 2215 | |
29639122 JB |
2216 | static const struct frame_unwind mips_stub_frame_unwind = |
2217 | { | |
2218 | NORMAL_FRAME, | |
2219 | mips_stub_frame_this_id, | |
2220 | mips_stub_frame_prev_register | |
2221 | }; | |
c906108c | 2222 | |
29639122 JB |
2223 | static const struct frame_unwind * |
2224 | mips_stub_frame_sniffer (struct frame_info *next_frame) | |
2225 | { | |
aa6c981f | 2226 | gdb_byte dummy[4]; |
979b38e0 | 2227 | struct obj_section *s; |
93d42b30 | 2228 | CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME); |
979b38e0 | 2229 | |
aa6c981f DJ |
2230 | /* Use the stub unwinder for unreadable code. */ |
2231 | if (target_read_memory (frame_pc_unwind (next_frame), dummy, 4) != 0) | |
2232 | return &mips_stub_frame_unwind; | |
2233 | ||
29639122 JB |
2234 | if (in_plt_section (pc, NULL)) |
2235 | return &mips_stub_frame_unwind; | |
979b38e0 DJ |
2236 | |
2237 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2238 | s = find_pc_section (pc); | |
2239 | ||
2240 | if (s != NULL | |
2241 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2242 | ".MIPS.stubs") == 0) | |
2243 | return &mips_stub_frame_unwind; | |
2244 | ||
2245 | return NULL; | |
29639122 | 2246 | } |
c906108c | 2247 | |
29639122 JB |
2248 | static CORE_ADDR |
2249 | mips_stub_frame_base_address (struct frame_info *next_frame, | |
2250 | void **this_cache) | |
2251 | { | |
2252 | struct trad_frame_cache *this_trad_cache | |
2253 | = mips_stub_frame_cache (next_frame, this_cache); | |
2254 | return trad_frame_get_this_base (this_trad_cache); | |
2255 | } | |
0fce0821 | 2256 | |
29639122 JB |
2257 | static const struct frame_base mips_stub_frame_base = |
2258 | { | |
2259 | &mips_stub_frame_unwind, | |
2260 | mips_stub_frame_base_address, | |
2261 | mips_stub_frame_base_address, | |
2262 | mips_stub_frame_base_address | |
2263 | }; | |
2264 | ||
2265 | static const struct frame_base * | |
2266 | mips_stub_frame_base_sniffer (struct frame_info *next_frame) | |
2267 | { | |
2268 | if (mips_stub_frame_sniffer (next_frame) != NULL) | |
2269 | return &mips_stub_frame_base; | |
2270 | else | |
2271 | return NULL; | |
2272 | } | |
2273 | ||
29639122 | 2274 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2275 | |
29639122 JB |
2276 | static CORE_ADDR |
2277 | mips_addr_bits_remove (CORE_ADDR addr) | |
65596487 | 2278 | { |
29639122 JB |
2279 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2280 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | |
2281 | /* This hack is a work-around for existing boards using PMON, the | |
2282 | simulator, and any other 64-bit targets that doesn't have true | |
2283 | 64-bit addressing. On these targets, the upper 32 bits of | |
2284 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2285 | likely to have been sign extended to all 1s by instruction | |
2286 | sequences that load 32-bit addresses. For example, a typical | |
2287 | piece of code that loads an address is this: | |
65596487 | 2288 | |
29639122 JB |
2289 | lui $r2, <upper 16 bits> |
2290 | ori $r2, <lower 16 bits> | |
65596487 | 2291 | |
29639122 JB |
2292 | But the lui sign-extends the value such that the upper 32 bits |
2293 | may be all 1s. The workaround is simply to mask off these | |
2294 | bits. In the future, gcc may be changed to support true 64-bit | |
2295 | addressing, and this masking will have to be disabled. */ | |
2296 | return addr &= 0xffffffffUL; | |
2297 | else | |
2298 | return addr; | |
65596487 JB |
2299 | } |
2300 | ||
29639122 JB |
2301 | /* mips_software_single_step() is called just before we want to resume |
2302 | the inferior, if we want to single-step it but there is no hardware | |
2303 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2304 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2305 | |
e6590a1b | 2306 | int |
0b1b3e42 | 2307 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2308 | { |
8181d85f | 2309 | CORE_ADDR pc, next_pc; |
65596487 | 2310 | |
0b1b3e42 UW |
2311 | pc = get_frame_pc (frame); |
2312 | next_pc = mips_next_pc (frame, pc); | |
e6590a1b | 2313 | |
e0cd558a | 2314 | insert_single_step_breakpoint (next_pc); |
e6590a1b | 2315 | return 1; |
29639122 | 2316 | } |
a65bbe44 | 2317 | |
29639122 JB |
2318 | /* Test whether the PC points to the return instruction at the |
2319 | end of a function. */ | |
65596487 | 2320 | |
29639122 JB |
2321 | static int |
2322 | mips_about_to_return (CORE_ADDR pc) | |
2323 | { | |
0fe7e7c8 | 2324 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2325 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2326 | generates a "jr $ra"; other times it generates code to load | |
2327 | the return address from the stack to an accessible register (such | |
2328 | as $a3), then a "jr" using that register. This second case | |
2329 | is almost impossible to distinguish from an indirect jump | |
2330 | used for switch statements, so we don't even try. */ | |
2331 | return mips_fetch_instruction (pc) == 0xe820; /* jr $ra */ | |
2332 | else | |
2333 | return mips_fetch_instruction (pc) == 0x3e00008; /* jr $ra */ | |
2334 | } | |
c906108c | 2335 | |
c906108c | 2336 | |
29639122 JB |
2337 | /* This fencepost looks highly suspicious to me. Removing it also |
2338 | seems suspicious as it could affect remote debugging across serial | |
2339 | lines. */ | |
c906108c | 2340 | |
29639122 JB |
2341 | static CORE_ADDR |
2342 | heuristic_proc_start (CORE_ADDR pc) | |
2343 | { | |
2344 | CORE_ADDR start_pc; | |
2345 | CORE_ADDR fence; | |
2346 | int instlen; | |
2347 | int seen_adjsp = 0; | |
65596487 | 2348 | |
bf6ae464 | 2349 | pc = gdbarch_addr_bits_remove (current_gdbarch, pc); |
29639122 JB |
2350 | start_pc = pc; |
2351 | fence = start_pc - heuristic_fence_post; | |
2352 | if (start_pc == 0) | |
2353 | return 0; | |
65596487 | 2354 | |
29639122 JB |
2355 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2356 | fence = VM_MIN_ADDRESS; | |
65596487 | 2357 | |
95ac2dcf | 2358 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2359 | |
29639122 JB |
2360 | /* search back for previous return */ |
2361 | for (start_pc -= instlen;; start_pc -= instlen) | |
2362 | if (start_pc < fence) | |
2363 | { | |
2364 | /* It's not clear to me why we reach this point when | |
2365 | stop_soon, but with this test, at least we | |
2366 | don't print out warnings for every child forked (eg, on | |
2367 | decstation). 22apr93 rich@cygnus.com. */ | |
2368 | if (stop_soon == NO_STOP_QUIETLY) | |
2369 | { | |
2370 | static int blurb_printed = 0; | |
98b4dd94 | 2371 | |
8a3fe4f8 | 2372 | warning (_("GDB can't find the start of the function at 0x%s."), |
29639122 JB |
2373 | paddr_nz (pc)); |
2374 | ||
2375 | if (!blurb_printed) | |
2376 | { | |
2377 | /* This actually happens frequently in embedded | |
2378 | development, when you first connect to a board | |
2379 | and your stack pointer and pc are nowhere in | |
2380 | particular. This message needs to give people | |
2381 | in that situation enough information to | |
2382 | determine that it's no big deal. */ | |
2383 | printf_filtered ("\n\ | |
2384 | GDB is unable to find the start of the function at 0x%s\n\ | |
2385 | and thus can't determine the size of that function's stack frame.\n\ | |
2386 | This means that GDB may be unable to access that stack frame, or\n\ | |
2387 | the frames below it.\n\ | |
2388 | This problem is most likely caused by an invalid program counter or\n\ | |
2389 | stack pointer.\n\ | |
2390 | However, if you think GDB should simply search farther back\n\ | |
2391 | from 0x%s for code which looks like the beginning of a\n\ | |
2392 | function, you can increase the range of the search using the `set\n\ | |
2393 | heuristic-fence-post' command.\n", paddr_nz (pc), paddr_nz (pc)); | |
2394 | blurb_printed = 1; | |
2395 | } | |
2396 | } | |
2397 | ||
2398 | return 0; | |
2399 | } | |
0fe7e7c8 | 2400 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2401 | { |
2402 | unsigned short inst; | |
2403 | ||
2404 | /* On MIPS16, any one of the following is likely to be the | |
2405 | start of a function: | |
193774b3 MR |
2406 | extend save |
2407 | save | |
29639122 JB |
2408 | entry |
2409 | addiu sp,-n | |
2410 | daddiu sp,-n | |
2411 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */ | |
2412 | inst = mips_fetch_instruction (start_pc); | |
193774b3 MR |
2413 | if ((inst & 0xff80) == 0x6480) /* save */ |
2414 | { | |
2415 | if (start_pc - instlen >= fence) | |
2416 | { | |
2417 | inst = mips_fetch_instruction (start_pc - instlen); | |
2418 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
2419 | start_pc -= instlen; | |
2420 | } | |
2421 | break; | |
2422 | } | |
2423 | else if (((inst & 0xf81f) == 0xe809 | |
2424 | && (inst & 0x700) != 0x700) /* entry */ | |
2425 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2426 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2427 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2428 | break; |
2429 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2430 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2431 | seen_adjsp = 1; | |
2432 | else | |
2433 | seen_adjsp = 0; | |
2434 | } | |
2435 | else if (mips_about_to_return (start_pc)) | |
2436 | { | |
4c7d22cb | 2437 | /* Skip return and its delay slot. */ |
95ac2dcf | 2438 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2439 | break; |
2440 | } | |
2441 | ||
2442 | return start_pc; | |
c906108c SS |
2443 | } |
2444 | ||
6c0d6680 DJ |
2445 | struct mips_objfile_private |
2446 | { | |
2447 | bfd_size_type size; | |
2448 | char *contents; | |
2449 | }; | |
2450 | ||
f09ded24 AC |
2451 | /* According to the current ABI, should the type be passed in a |
2452 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2453 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 AC |
2454 | FP registers and, consequently this returns false - forces FP |
2455 | arguments into integer registers. */ | |
2456 | ||
2457 | static int | |
2458 | fp_register_arg_p (enum type_code typecode, struct type *arg_type) | |
2459 | { | |
2460 | return ((typecode == TYPE_CODE_FLT | |
2461 | || (MIPS_EABI | |
6d82d43b AC |
2462 | && (typecode == TYPE_CODE_STRUCT |
2463 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2464 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2465 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2466 | == TYPE_CODE_FLT)) | |
c86b5b38 | 2467 | && MIPS_FPU_TYPE != MIPS_FPU_NONE); |
f09ded24 AC |
2468 | } |
2469 | ||
49e790b0 DJ |
2470 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
2471 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ | |
2472 | ||
2473 | static int | |
2474 | mips_type_needs_double_align (struct type *type) | |
2475 | { | |
2476 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2477 | |
49e790b0 DJ |
2478 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2479 | return 1; | |
2480 | else if (typecode == TYPE_CODE_STRUCT) | |
2481 | { | |
2482 | if (TYPE_NFIELDS (type) < 1) | |
2483 | return 0; | |
2484 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2485 | } | |
2486 | else if (typecode == TYPE_CODE_UNION) | |
2487 | { | |
361d1df0 | 2488 | int i, n; |
49e790b0 DJ |
2489 | |
2490 | n = TYPE_NFIELDS (type); | |
2491 | for (i = 0; i < n; i++) | |
2492 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2493 | return 1; | |
2494 | return 0; | |
2495 | } | |
2496 | return 0; | |
2497 | } | |
2498 | ||
dc604539 AC |
2499 | /* Adjust the address downward (direction of stack growth) so that it |
2500 | is correctly aligned for a new stack frame. */ | |
2501 | static CORE_ADDR | |
2502 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2503 | { | |
5b03f266 | 2504 | return align_down (addr, 16); |
dc604539 AC |
2505 | } |
2506 | ||
f7ab6ec6 | 2507 | static CORE_ADDR |
7d9b040b | 2508 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2509 | struct regcache *regcache, CORE_ADDR bp_addr, |
2510 | int nargs, struct value **args, CORE_ADDR sp, | |
2511 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2512 | { |
2513 | int argreg; | |
2514 | int float_argreg; | |
2515 | int argnum; | |
2516 | int len = 0; | |
2517 | int stack_offset = 0; | |
480d3dd2 | 2518 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2519 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2520 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2521 | |
25ab4790 AC |
2522 | /* For shared libraries, "t9" needs to point at the function |
2523 | address. */ | |
4c7d22cb | 2524 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2525 | |
2526 | /* Set the return address register to point to the entry point of | |
2527 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2528 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2529 | |
c906108c | 2530 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2531 | are properly aligned. The stack has to be at least 64-bit |
2532 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2533 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2534 | aligned, so we round to this widest known alignment. */ | |
2535 | ||
5b03f266 AC |
2536 | sp = align_down (sp, 16); |
2537 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2538 | |
46e0f506 | 2539 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2540 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2541 | passed in registers, but that's OK. */ |
c906108c | 2542 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2543 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2544 | sp -= align_up (len, 16); |
c906108c | 2545 | |
9ace0497 | 2546 | if (mips_debug) |
6d82d43b | 2547 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2548 | "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n", |
2549 | paddr_nz (sp), (long) align_up (len, 16)); | |
9ace0497 | 2550 | |
c906108c | 2551 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2552 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2553 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
c906108c | 2554 | |
46e0f506 | 2555 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2556 | if (struct_return) |
9ace0497 AC |
2557 | { |
2558 | if (mips_debug) | |
2559 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2560 | "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2561 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 2562 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 2563 | } |
c906108c SS |
2564 | |
2565 | /* Now load as many as possible of the first arguments into | |
2566 | registers, and push the rest onto the stack. Loop thru args | |
2567 | from first to last. */ | |
2568 | for (argnum = 0; argnum < nargs; argnum++) | |
2569 | { | |
47a35522 MK |
2570 | const gdb_byte *val; |
2571 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 2572 | struct value *arg = args[argnum]; |
4991999e | 2573 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
2574 | int len = TYPE_LENGTH (arg_type); |
2575 | enum type_code typecode = TYPE_CODE (arg_type); | |
2576 | ||
9ace0497 AC |
2577 | if (mips_debug) |
2578 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2579 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 2580 | argnum + 1, len, (int) typecode); |
9ace0497 | 2581 | |
c906108c | 2582 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 2583 | reference. */ |
1a69e1e4 | 2584 | if (len > regsize |
9ace0497 | 2585 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 2586 | { |
1a69e1e4 | 2587 | store_unsigned_integer (valbuf, regsize, VALUE_ADDRESS (arg)); |
c906108c | 2588 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 2589 | len = regsize; |
c906108c | 2590 | val = valbuf; |
9ace0497 AC |
2591 | if (mips_debug) |
2592 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
2593 | } |
2594 | else | |
47a35522 | 2595 | val = value_contents (arg); |
c906108c SS |
2596 | |
2597 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
2598 | even-numbered floating point register. Round the FP register |
2599 | up before the check to see if there are any FP registers | |
46e0f506 MS |
2600 | left. Non MIPS_EABI targets also pass the FP in the integer |
2601 | registers so also round up normal registers. */ | |
1a69e1e4 | 2602 | if (regsize < 8 && fp_register_arg_p (typecode, arg_type)) |
acdb74a0 AC |
2603 | { |
2604 | if ((float_argreg & 1)) | |
2605 | float_argreg++; | |
2606 | } | |
c906108c SS |
2607 | |
2608 | /* Floating point arguments passed in registers have to be | |
2609 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
2610 | are passed in register pairs; the even register gets |
2611 | the low word, and the odd register gets the high word. | |
2612 | On non-EABI processors, the first two floating point arguments are | |
2613 | also copied to general registers, because MIPS16 functions | |
2614 | don't use float registers for arguments. This duplication of | |
2615 | arguments in general registers can't hurt non-MIPS16 functions | |
2616 | because those registers are normally skipped. */ | |
1012bd0e EZ |
2617 | /* MIPS_EABI squeezes a struct that contains a single floating |
2618 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 2619 | stack. */ |
f09ded24 AC |
2620 | if (fp_register_arg_p (typecode, arg_type) |
2621 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
c906108c | 2622 | { |
6da397e0 KB |
2623 | /* EABI32 will pass doubles in consecutive registers, even on |
2624 | 64-bit cores. At one time, we used to check the size of | |
2625 | `float_argreg' to determine whether or not to pass doubles | |
2626 | in consecutive registers, but this is not sufficient for | |
2627 | making the ABI determination. */ | |
2628 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 2629 | { |
4c6b5505 UW |
2630 | int low_offset = gdbarch_byte_order (current_gdbarch) |
2631 | == BFD_ENDIAN_BIG ? 4 : 0; | |
c906108c SS |
2632 | unsigned long regval; |
2633 | ||
2634 | /* Write the low word of the double to the even register(s). */ | |
c5aa993b | 2635 | regval = extract_unsigned_integer (val + low_offset, 4); |
9ace0497 | 2636 | if (mips_debug) |
acdb74a0 | 2637 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2638 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2639 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2640 | |
2641 | /* Write the high word of the double to the odd register(s). */ | |
c5aa993b | 2642 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); |
9ace0497 | 2643 | if (mips_debug) |
acdb74a0 | 2644 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2645 | float_argreg, phex (regval, 4)); |
9c9acae0 | 2646 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2647 | } |
2648 | else | |
2649 | { | |
2650 | /* This is a floating point value that fits entirely | |
2651 | in a single register. */ | |
53a5351d | 2652 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 2653 | above to ensure that it is even register aligned. */ |
9ace0497 AC |
2654 | LONGEST regval = extract_unsigned_integer (val, len); |
2655 | if (mips_debug) | |
acdb74a0 | 2656 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 2657 | float_argreg, phex (regval, len)); |
9c9acae0 | 2658 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
c906108c SS |
2659 | } |
2660 | } | |
2661 | else | |
2662 | { | |
2663 | /* Copy the argument to general registers or the stack in | |
2664 | register-sized pieces. Large arguments are split between | |
2665 | registers and stack. */ | |
1a69e1e4 DJ |
2666 | /* Note: structs whose size is not a multiple of regsize |
2667 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
2668 | them in registers where gcc sometimes puts them on the |
2669 | stack. For maximum compatibility, we will put them in | |
2670 | both places. */ | |
1a69e1e4 | 2671 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 2672 | |
f09ded24 | 2673 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2674 | register are only written to memory. */ |
c906108c SS |
2675 | while (len > 0) |
2676 | { | |
ebafbe83 | 2677 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 2678 | int stack_used_p = 0; |
1a69e1e4 | 2679 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 2680 | |
acdb74a0 AC |
2681 | if (mips_debug) |
2682 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2683 | partial_len); | |
2684 | ||
566f0f7a | 2685 | /* Write this portion of the argument to the stack. */ |
f09ded24 AC |
2686 | if (argreg > MIPS_LAST_ARG_REGNUM |
2687 | || odd_sized_struct | |
2688 | || fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2689 | { |
c906108c SS |
2690 | /* Should shorter than int integer values be |
2691 | promoted to int before being stored? */ | |
c906108c | 2692 | int longword_offset = 0; |
9ace0497 | 2693 | CORE_ADDR addr; |
566f0f7a | 2694 | stack_used_p = 1; |
4c6b5505 | 2695 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 2696 | { |
1a69e1e4 | 2697 | if (regsize == 8 |
480d3dd2 AC |
2698 | && (typecode == TYPE_CODE_INT |
2699 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 2700 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 2701 | longword_offset = regsize - len; |
480d3dd2 AC |
2702 | else if ((typecode == TYPE_CODE_STRUCT |
2703 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
2704 | && TYPE_LENGTH (arg_type) < regsize) |
2705 | longword_offset = regsize - len; | |
7a292a7a | 2706 | } |
c5aa993b | 2707 | |
9ace0497 AC |
2708 | if (mips_debug) |
2709 | { | |
cb3d25d1 MS |
2710 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", |
2711 | paddr_nz (stack_offset)); | |
2712 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2713 | paddr_nz (longword_offset)); | |
9ace0497 | 2714 | } |
361d1df0 | 2715 | |
9ace0497 AC |
2716 | addr = sp + stack_offset + longword_offset; |
2717 | ||
2718 | if (mips_debug) | |
2719 | { | |
2720 | int i; | |
6d82d43b | 2721 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 | 2722 | paddr_nz (addr)); |
9ace0497 AC |
2723 | for (i = 0; i < partial_len; i++) |
2724 | { | |
6d82d43b | 2725 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 2726 | val[i] & 0xff); |
9ace0497 AC |
2727 | } |
2728 | } | |
2729 | write_memory (addr, val, partial_len); | |
c906108c SS |
2730 | } |
2731 | ||
f09ded24 AC |
2732 | /* Note!!! This is NOT an else clause. Odd sized |
2733 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 2734 | arguments will not. */ |
566f0f7a | 2735 | /* Write this portion of the argument to a general |
6d82d43b | 2736 | purpose register. */ |
f09ded24 AC |
2737 | if (argreg <= MIPS_LAST_ARG_REGNUM |
2738 | && !fp_register_arg_p (typecode, arg_type)) | |
c906108c | 2739 | { |
6d82d43b AC |
2740 | LONGEST regval = |
2741 | extract_unsigned_integer (val, partial_len); | |
c906108c | 2742 | |
9ace0497 | 2743 | if (mips_debug) |
acdb74a0 | 2744 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 2745 | argreg, |
1a69e1e4 | 2746 | phex (regval, regsize)); |
9c9acae0 | 2747 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
c906108c | 2748 | argreg++; |
c906108c | 2749 | } |
c5aa993b | 2750 | |
c906108c SS |
2751 | len -= partial_len; |
2752 | val += partial_len; | |
2753 | ||
566f0f7a | 2754 | /* Compute the the offset into the stack at which we |
6d82d43b | 2755 | will copy the next parameter. |
566f0f7a | 2756 | |
566f0f7a | 2757 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 2758 | only needs to be adjusted when it has been used. */ |
c906108c | 2759 | |
46e0f506 | 2760 | if (stack_used_p) |
1a69e1e4 | 2761 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
2762 | } |
2763 | } | |
9ace0497 AC |
2764 | if (mips_debug) |
2765 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
2766 | } |
2767 | ||
f10683bb | 2768 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 2769 | |
0f71a2f6 JM |
2770 | /* Return adjusted stack pointer. */ |
2771 | return sp; | |
2772 | } | |
2773 | ||
a1f5b845 | 2774 | /* Determine the return value convention being used. */ |
6d82d43b | 2775 | |
9c8fdbfa AC |
2776 | static enum return_value_convention |
2777 | mips_eabi_return_value (struct gdbarch *gdbarch, | |
2778 | struct type *type, struct regcache *regcache, | |
47a35522 | 2779 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 2780 | { |
9c8fdbfa AC |
2781 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
2782 | return RETURN_VALUE_STRUCT_CONVENTION; | |
2783 | if (readbuf) | |
2784 | memset (readbuf, 0, TYPE_LENGTH (type)); | |
2785 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6d82d43b AC |
2786 | } |
2787 | ||
6d82d43b AC |
2788 | |
2789 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 2790 | |
8d26208a DJ |
2791 | /* Search for a naturally aligned double at OFFSET inside a struct |
2792 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
2793 | registers. */ | |
2794 | ||
2795 | static int | |
2796 | mips_n32n64_fp_arg_chunk_p (struct type *arg_type, int offset) | |
2797 | { | |
2798 | int i; | |
2799 | ||
2800 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
2801 | return 0; | |
2802 | ||
2803 | if (MIPS_FPU_TYPE != MIPS_FPU_DOUBLE) | |
2804 | return 0; | |
2805 | ||
2806 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
2807 | return 0; | |
2808 | ||
2809 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
2810 | { | |
2811 | int pos; | |
2812 | struct type *field_type; | |
2813 | ||
2814 | /* We're only looking at normal fields. */ | |
2815 | if (TYPE_FIELD_STATIC (arg_type, i) | |
2816 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) | |
2817 | continue; | |
2818 | ||
2819 | /* If we have gone past the offset, there is no double to pass. */ | |
2820 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
2821 | if (pos > offset) | |
2822 | return 0; | |
2823 | ||
2824 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
2825 | ||
2826 | /* If this field is entirely before the requested offset, go | |
2827 | on to the next one. */ | |
2828 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
2829 | continue; | |
2830 | ||
2831 | /* If this is our special aligned double, we can stop. */ | |
2832 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
2833 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
2834 | return 1; | |
2835 | ||
2836 | /* This field starts at or before the requested offset, and | |
2837 | overlaps it. If it is a structure, recurse inwards. */ | |
2838 | return mips_n32n64_fp_arg_chunk_p (field_type, offset - pos); | |
2839 | } | |
2840 | ||
2841 | return 0; | |
2842 | } | |
2843 | ||
f7ab6ec6 | 2844 | static CORE_ADDR |
7d9b040b | 2845 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2846 | struct regcache *regcache, CORE_ADDR bp_addr, |
2847 | int nargs, struct value **args, CORE_ADDR sp, | |
2848 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
2849 | { |
2850 | int argreg; | |
2851 | int float_argreg; | |
2852 | int argnum; | |
2853 | int len = 0; | |
2854 | int stack_offset = 0; | |
480d3dd2 | 2855 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 2856 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 2857 | |
25ab4790 AC |
2858 | /* For shared libraries, "t9" needs to point at the function |
2859 | address. */ | |
4c7d22cb | 2860 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2861 | |
2862 | /* Set the return address register to point to the entry point of | |
2863 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2864 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2865 | |
cb3d25d1 MS |
2866 | /* First ensure that the stack and structure return address (if any) |
2867 | are properly aligned. The stack has to be at least 64-bit | |
2868 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2869 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2870 | aligned, so we round to this widest known alignment. */ | |
2871 | ||
5b03f266 AC |
2872 | sp = align_down (sp, 16); |
2873 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
2874 | |
2875 | /* Now make space on the stack for the args. */ | |
2876 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 2877 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 2878 | sp -= align_up (len, 16); |
cb3d25d1 MS |
2879 | |
2880 | if (mips_debug) | |
6d82d43b | 2881 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
2882 | "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n", |
2883 | paddr_nz (sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
2884 | |
2885 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 2886 | argreg = MIPS_A0_REGNUM; |
56cea623 | 2887 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
cb3d25d1 | 2888 | |
46e0f506 | 2889 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
2890 | if (struct_return) |
2891 | { | |
2892 | if (mips_debug) | |
2893 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2894 | "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n", |
cb3d25d1 | 2895 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 2896 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
2897 | } |
2898 | ||
2899 | /* Now load as many as possible of the first arguments into | |
2900 | registers, and push the rest onto the stack. Loop thru args | |
2901 | from first to last. */ | |
2902 | for (argnum = 0; argnum < nargs; argnum++) | |
2903 | { | |
47a35522 | 2904 | const gdb_byte *val; |
cb3d25d1 | 2905 | struct value *arg = args[argnum]; |
4991999e | 2906 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
2907 | int len = TYPE_LENGTH (arg_type); |
2908 | enum type_code typecode = TYPE_CODE (arg_type); | |
2909 | ||
2910 | if (mips_debug) | |
2911 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 2912 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
2913 | argnum + 1, len, (int) typecode); |
2914 | ||
47a35522 | 2915 | val = value_contents (arg); |
cb3d25d1 MS |
2916 | |
2917 | if (fp_register_arg_p (typecode, arg_type) | |
8d26208a | 2918 | && argreg <= MIPS_LAST_ARG_REGNUM) |
cb3d25d1 MS |
2919 | { |
2920 | /* This is a floating point value that fits entirely | |
2921 | in a single register. */ | |
cb3d25d1 MS |
2922 | LONGEST regval = extract_unsigned_integer (val, len); |
2923 | if (mips_debug) | |
2924 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
2925 | float_argreg, phex (regval, len)); | |
8d26208a | 2926 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
2927 | |
2928 | if (mips_debug) | |
2929 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
2930 | argreg, phex (regval, len)); | |
9c9acae0 | 2931 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
2932 | float_argreg++; |
2933 | argreg++; | |
cb3d25d1 MS |
2934 | } |
2935 | else | |
2936 | { | |
2937 | /* Copy the argument to general registers or the stack in | |
2938 | register-sized pieces. Large arguments are split between | |
2939 | registers and stack. */ | |
ab2e1992 MR |
2940 | /* For N32/N64, structs, unions, or other composite types are |
2941 | treated as a sequence of doublewords, and are passed in integer | |
2942 | or floating point registers as though they were simple scalar | |
2943 | parameters to the extent that they fit, with any excess on the | |
2944 | stack packed according to the normal memory layout of the | |
2945 | object. | |
2946 | The caller does not reserve space for the register arguments; | |
2947 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 2948 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 2949 | register are only written to memory. */ |
cb3d25d1 MS |
2950 | while (len > 0) |
2951 | { | |
ad018eee | 2952 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 2953 | int stack_used_p = 0; |
1a69e1e4 | 2954 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
2955 | |
2956 | if (mips_debug) | |
2957 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
2958 | partial_len); | |
2959 | ||
8d26208a DJ |
2960 | if (fp_register_arg_p (typecode, arg_type)) |
2961 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM); | |
2962 | ||
cb3d25d1 | 2963 | /* Write this portion of the argument to the stack. */ |
ab2e1992 | 2964 | if (argreg > MIPS_LAST_ARG_REGNUM) |
cb3d25d1 MS |
2965 | { |
2966 | /* Should shorter than int integer values be | |
2967 | promoted to int before being stored? */ | |
2968 | int longword_offset = 0; | |
2969 | CORE_ADDR addr; | |
2970 | stack_used_p = 1; | |
4c6b5505 | 2971 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 2972 | { |
1a69e1e4 DJ |
2973 | if ((typecode == TYPE_CODE_INT |
2974 | || typecode == TYPE_CODE_PTR | |
2975 | || typecode == TYPE_CODE_FLT) | |
2976 | && len <= 4) | |
2977 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
2978 | } |
2979 | ||
2980 | if (mips_debug) | |
2981 | { | |
2982 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
2983 | paddr_nz (stack_offset)); | |
2984 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
2985 | paddr_nz (longword_offset)); | |
2986 | } | |
2987 | ||
2988 | addr = sp + stack_offset + longword_offset; | |
2989 | ||
2990 | if (mips_debug) | |
2991 | { | |
2992 | int i; | |
6d82d43b | 2993 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
cb3d25d1 MS |
2994 | paddr_nz (addr)); |
2995 | for (i = 0; i < partial_len; i++) | |
2996 | { | |
6d82d43b | 2997 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
2998 | val[i] & 0xff); |
2999 | } | |
3000 | } | |
3001 | write_memory (addr, val, partial_len); | |
3002 | } | |
3003 | ||
3004 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3005 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3006 | /* Write this portion of the argument to a general |
6d82d43b | 3007 | purpose register. */ |
8d26208a | 3008 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
cb3d25d1 | 3009 | { |
6d82d43b AC |
3010 | LONGEST regval = |
3011 | extract_unsigned_integer (val, partial_len); | |
cb3d25d1 MS |
3012 | |
3013 | /* A non-floating-point argument being passed in a | |
3014 | general register. If a struct or union, and if | |
3015 | the remaining length is smaller than the register | |
3016 | size, we have to adjust the register value on | |
3017 | big endian targets. | |
3018 | ||
3019 | It does not seem to be necessary to do the | |
1a69e1e4 | 3020 | same for integral types. */ |
cb3d25d1 | 3021 | |
4c6b5505 | 3022 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3023 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3024 | && (typecode == TYPE_CODE_STRUCT |
3025 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3026 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3027 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3028 | |
3029 | if (mips_debug) | |
3030 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3031 | argreg, | |
1a69e1e4 | 3032 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3033 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3034 | |
3035 | if (mips_n32n64_fp_arg_chunk_p (arg_type, | |
3036 | TYPE_LENGTH (arg_type) - len)) | |
3037 | { | |
3038 | if (mips_debug) | |
3039 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3040 | float_argreg, | |
3041 | phex (regval, MIPS64_REGSIZE)); | |
3042 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3043 | regval); | |
3044 | } | |
3045 | ||
3046 | float_argreg++; | |
cb3d25d1 MS |
3047 | argreg++; |
3048 | } | |
3049 | ||
3050 | len -= partial_len; | |
3051 | val += partial_len; | |
3052 | ||
3053 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3054 | will copy the next parameter. |
cb3d25d1 MS |
3055 | |
3056 | In N32 (N64?), the stack_offset only needs to be | |
3057 | adjusted when it has been used. */ | |
3058 | ||
3059 | if (stack_used_p) | |
1a69e1e4 | 3060 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3061 | } |
3062 | } | |
3063 | if (mips_debug) | |
3064 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3065 | } | |
3066 | ||
f10683bb | 3067 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3068 | |
cb3d25d1 MS |
3069 | /* Return adjusted stack pointer. */ |
3070 | return sp; | |
3071 | } | |
3072 | ||
6d82d43b AC |
3073 | static enum return_value_convention |
3074 | mips_n32n64_return_value (struct gdbarch *gdbarch, | |
3075 | struct type *type, struct regcache *regcache, | |
47a35522 | 3076 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3077 | { |
6d82d43b | 3078 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
b18bb924 MR |
3079 | |
3080 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3081 | ||
3082 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3083 | if needed), as appropriate for the type. Composite results (struct, | |
3084 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3085 | following rules: | |
3086 | ||
3087 | * A struct with only one or two floating point fields is returned in $f0 | |
3088 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3089 | case. | |
3090 | ||
3091 | * Any other struct or union results of at most 128 bits are returned in | |
3092 | $2 (first 64 bits) and $3 (remainder, if necessary). | |
3093 | ||
3094 | * Larger composite results are handled by converting the function to a | |
3095 | procedure with an implicit first parameter, which is a pointer to an area | |
3096 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3097 | that all composite results be handled by conversion to implicit first | |
3098 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3099 | specific exception to return COMPLEX results in the floating point | |
3100 | registers.] */ | |
3101 | ||
3102 | if (TYPE_CODE (type) == TYPE_CODE_ARRAY | |
1a69e1e4 | 3103 | || TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3104 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3105 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3106 | && TYPE_LENGTH (type) == 16 | |
3107 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3108 | { | |
3109 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3110 | two registers are used in the same as memory order, so the | |
3111 | eight bytes with the lower memory address are in $f0. */ | |
3112 | if (mips_debug) | |
3113 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
3114 | mips_xfer_register (regcache, | |
f57d151a UW |
3115 | gdbarch_num_regs (current_gdbarch) |
3116 | + mips_regnum (current_gdbarch)->fp0, | |
4c6b5505 UW |
3117 | 8, gdbarch_byte_order (current_gdbarch), |
3118 | readbuf, writebuf, 0); | |
d05f6826 | 3119 | mips_xfer_register (regcache, |
f57d151a UW |
3120 | gdbarch_num_regs (current_gdbarch) |
3121 | + mips_regnum (current_gdbarch)->fp0 + 2, | |
4c6b5505 UW |
3122 | 8, gdbarch_byte_order (current_gdbarch), |
3123 | readbuf ? readbuf + 8 : readbuf, | |
d05f6826 DJ |
3124 | writebuf ? writebuf + 8 : writebuf, 0); |
3125 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3126 | } | |
6d82d43b AC |
3127 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3128 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3129 | { | |
59aa1faa | 3130 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3131 | if (mips_debug) |
3132 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3133 | mips_xfer_register (regcache, | |
f57d151a UW |
3134 | gdbarch_num_regs (current_gdbarch) |
3135 | + mips_regnum (current_gdbarch)->fp0, | |
6d82d43b | 3136 | TYPE_LENGTH (type), |
4c6b5505 UW |
3137 | gdbarch_byte_order (current_gdbarch), |
3138 | readbuf, writebuf, 0); | |
6d82d43b AC |
3139 | return RETURN_VALUE_REGISTER_CONVENTION; |
3140 | } | |
3141 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3142 | && TYPE_NFIELDS (type) <= 2 | |
3143 | && TYPE_NFIELDS (type) >= 1 | |
3144 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3145 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3146 | == TYPE_CODE_FLT)) |
3147 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3148 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3149 | == TYPE_CODE_FLT) |
b18bb924 | 3150 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
6d82d43b AC |
3151 | == TYPE_CODE_FLT))) |
3152 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3153 | { | |
3154 | /* A struct that contains one or two floats. Each value is part | |
3155 | in the least significant part of their floating point | |
3156 | register.. */ | |
6d82d43b AC |
3157 | int regnum; |
3158 | int field; | |
3159 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3160 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3161 | { | |
3162 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3163 | / TARGET_CHAR_BIT); | |
3164 | if (mips_debug) | |
3165 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3166 | offset); | |
f57d151a UW |
3167 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3168 | + regnum, | |
6d82d43b | 3169 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
4c6b5505 UW |
3170 | gdbarch_byte_order (current_gdbarch), |
3171 | readbuf, writebuf, offset); | |
6d82d43b AC |
3172 | } |
3173 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3174 | } | |
3175 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3176 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3177 | { | |
3178 | /* A structure or union. Extract the left justified value, | |
3179 | regardless of the byte order. I.e. DO NOT USE | |
3180 | mips_xfer_lower. */ | |
3181 | int offset; | |
3182 | int regnum; | |
4c7d22cb | 3183 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3184 | offset < TYPE_LENGTH (type); |
3185 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3186 | { | |
3187 | int xfer = register_size (current_gdbarch, regnum); | |
3188 | if (offset + xfer > TYPE_LENGTH (type)) | |
3189 | xfer = TYPE_LENGTH (type) - offset; | |
3190 | if (mips_debug) | |
3191 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3192 | offset, xfer, regnum); | |
f57d151a UW |
3193 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3194 | + regnum, xfer, | |
6d82d43b AC |
3195 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3196 | } | |
3197 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3198 | } | |
3199 | else | |
3200 | { | |
3201 | /* A scalar extract each part but least-significant-byte | |
3202 | justified. */ | |
3203 | int offset; | |
3204 | int regnum; | |
4c7d22cb | 3205 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3206 | offset < TYPE_LENGTH (type); |
3207 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3208 | { | |
3209 | int xfer = register_size (current_gdbarch, regnum); | |
6d82d43b AC |
3210 | if (offset + xfer > TYPE_LENGTH (type)) |
3211 | xfer = TYPE_LENGTH (type) - offset; | |
3212 | if (mips_debug) | |
3213 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3214 | offset, xfer, regnum); | |
f57d151a UW |
3215 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3216 | + regnum, xfer, | |
4c6b5505 UW |
3217 | gdbarch_byte_order (current_gdbarch), |
3218 | readbuf, writebuf, offset); | |
6d82d43b AC |
3219 | } |
3220 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3221 | } | |
3222 | } | |
3223 | ||
3224 | /* O32 ABI stuff. */ | |
3225 | ||
3226 | static CORE_ADDR | |
7d9b040b | 3227 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3228 | struct regcache *regcache, CORE_ADDR bp_addr, |
3229 | int nargs, struct value **args, CORE_ADDR sp, | |
3230 | int struct_return, CORE_ADDR struct_addr) | |
3231 | { | |
3232 | int argreg; | |
3233 | int float_argreg; | |
3234 | int argnum; | |
3235 | int len = 0; | |
3236 | int stack_offset = 0; | |
3237 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
7d9b040b | 3238 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3239 | |
3240 | /* For shared libraries, "t9" needs to point at the function | |
3241 | address. */ | |
4c7d22cb | 3242 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3243 | |
3244 | /* Set the return address register to point to the entry point of | |
3245 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3246 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3247 | |
3248 | /* First ensure that the stack and structure return address (if any) | |
3249 | are properly aligned. The stack has to be at least 64-bit | |
3250 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3251 | aligned. For n32 and n64, stack frames need to be 128-bit |
3252 | aligned, so we round to this widest known alignment. */ | |
3253 | ||
5b03f266 AC |
3254 | sp = align_down (sp, 16); |
3255 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3256 | |
3257 | /* Now make space on the stack for the args. */ | |
3258 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3259 | { |
3260 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3261 | int arglen = TYPE_LENGTH (arg_type); | |
3262 | ||
3263 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3264 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3265 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3266 | /* Allocate space on the stack. */ |
1a69e1e4 | 3267 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3268 | } |
5b03f266 | 3269 | sp -= align_up (len, 16); |
ebafbe83 MS |
3270 | |
3271 | if (mips_debug) | |
6d82d43b | 3272 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3273 | "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n", |
3274 | paddr_nz (sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3275 | |
3276 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3277 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3278 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
ebafbe83 | 3279 | |
bcb0cc15 | 3280 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3281 | if (struct_return) |
3282 | { | |
3283 | if (mips_debug) | |
3284 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3285 | "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n", |
ebafbe83 | 3286 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3287 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3288 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3289 | } |
3290 | ||
3291 | /* Now load as many as possible of the first arguments into | |
3292 | registers, and push the rest onto the stack. Loop thru args | |
3293 | from first to last. */ | |
3294 | for (argnum = 0; argnum < nargs; argnum++) | |
3295 | { | |
47a35522 | 3296 | const gdb_byte *val; |
ebafbe83 | 3297 | struct value *arg = args[argnum]; |
4991999e | 3298 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3299 | int len = TYPE_LENGTH (arg_type); |
3300 | enum type_code typecode = TYPE_CODE (arg_type); | |
3301 | ||
3302 | if (mips_debug) | |
3303 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3304 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3305 | argnum + 1, len, (int) typecode); |
3306 | ||
47a35522 | 3307 | val = value_contents (arg); |
46cac009 AC |
3308 | |
3309 | /* 32-bit ABIs always start floating point arguments in an | |
3310 | even-numbered floating point register. Round the FP register | |
3311 | up before the check to see if there are any FP registers | |
3312 | left. O32/O64 targets also pass the FP in the integer | |
3313 | registers so also round up normal registers. */ | |
2afd3f0a | 3314 | if (fp_register_arg_p (typecode, arg_type)) |
46cac009 AC |
3315 | { |
3316 | if ((float_argreg & 1)) | |
3317 | float_argreg++; | |
3318 | } | |
3319 | ||
3320 | /* Floating point arguments passed in registers have to be | |
3321 | treated specially. On 32-bit architectures, doubles | |
3322 | are passed in register pairs; the even register gets | |
3323 | the low word, and the odd register gets the high word. | |
3324 | On O32/O64, the first two floating point arguments are | |
3325 | also copied to general registers, because MIPS16 functions | |
3326 | don't use float registers for arguments. This duplication of | |
3327 | arguments in general registers can't hurt non-MIPS16 functions | |
3328 | because those registers are normally skipped. */ | |
3329 | ||
3330 | if (fp_register_arg_p (typecode, arg_type) | |
3331 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3332 | { | |
8b07f6d8 | 3333 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3334 | { |
4c6b5505 UW |
3335 | int low_offset = gdbarch_byte_order (current_gdbarch) |
3336 | == BFD_ENDIAN_BIG ? 4 : 0; | |
46cac009 AC |
3337 | unsigned long regval; |
3338 | ||
3339 | /* Write the low word of the double to the even register(s). */ | |
3340 | regval = extract_unsigned_integer (val + low_offset, 4); | |
3341 | if (mips_debug) | |
3342 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3343 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3344 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3345 | if (mips_debug) |
3346 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3347 | argreg, phex (regval, 4)); | |
9c9acae0 | 3348 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3349 | |
3350 | /* Write the high word of the double to the odd register(s). */ | |
3351 | regval = extract_unsigned_integer (val + 4 - low_offset, 4); | |
3352 | if (mips_debug) | |
3353 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3354 | float_argreg, phex (regval, 4)); | |
9c9acae0 | 3355 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 AC |
3356 | |
3357 | if (mips_debug) | |
3358 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3359 | argreg, phex (regval, 4)); | |
9c9acae0 | 3360 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3361 | } |
3362 | else | |
3363 | { | |
3364 | /* This is a floating point value that fits entirely | |
3365 | in a single register. */ | |
3366 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3367 | above to ensure that it is even register aligned. */ |
46cac009 AC |
3368 | LONGEST regval = extract_unsigned_integer (val, len); |
3369 | if (mips_debug) | |
3370 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3371 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3372 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
46cac009 | 3373 | /* CAGNEY: 32 bit MIPS ABI's always reserve two FP |
6d82d43b AC |
3374 | registers for each argument. The below is (my |
3375 | guess) to ensure that the corresponding integer | |
3376 | register has reserved the same space. */ | |
46cac009 AC |
3377 | if (mips_debug) |
3378 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3379 | argreg, phex (regval, len)); | |
9c9acae0 | 3380 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 3381 | argreg += 2; |
46cac009 AC |
3382 | } |
3383 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3384 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3385 | } |
3386 | else | |
3387 | { | |
3388 | /* Copy the argument to general registers or the stack in | |
3389 | register-sized pieces. Large arguments are split between | |
3390 | registers and stack. */ | |
1a69e1e4 DJ |
3391 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3392 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3393 | them in registers where gcc sometimes puts them on the |
3394 | stack. For maximum compatibility, we will put them in | |
3395 | both places. */ | |
1a69e1e4 DJ |
3396 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3397 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3398 | /* Structures should be aligned to eight bytes (even arg registers) |
3399 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3400 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3401 | { |
3402 | if ((argreg & 1)) | |
968b5391 MR |
3403 | { |
3404 | argreg++; | |
1a69e1e4 | 3405 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3406 | } |
46cac009 | 3407 | } |
46cac009 AC |
3408 | while (len > 0) |
3409 | { | |
3410 | /* Remember if the argument was written to the stack. */ | |
3411 | int stack_used_p = 0; | |
1a69e1e4 | 3412 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3413 | |
3414 | if (mips_debug) | |
3415 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3416 | partial_len); | |
3417 | ||
3418 | /* Write this portion of the argument to the stack. */ | |
3419 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3420 | || odd_sized_struct) |
46cac009 AC |
3421 | { |
3422 | /* Should shorter than int integer values be | |
3423 | promoted to int before being stored? */ | |
3424 | int longword_offset = 0; | |
3425 | CORE_ADDR addr; | |
3426 | stack_used_p = 1; | |
46cac009 AC |
3427 | |
3428 | if (mips_debug) | |
3429 | { | |
3430 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3431 | paddr_nz (stack_offset)); | |
3432 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3433 | paddr_nz (longword_offset)); | |
3434 | } | |
3435 | ||
3436 | addr = sp + stack_offset + longword_offset; | |
3437 | ||
3438 | if (mips_debug) | |
3439 | { | |
3440 | int i; | |
6d82d43b | 3441 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
46cac009 AC |
3442 | paddr_nz (addr)); |
3443 | for (i = 0; i < partial_len; i++) | |
3444 | { | |
6d82d43b | 3445 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
3446 | val[i] & 0xff); |
3447 | } | |
3448 | } | |
3449 | write_memory (addr, val, partial_len); | |
3450 | } | |
3451 | ||
3452 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3453 | structs may go thru BOTH paths. */ |
46cac009 | 3454 | /* Write this portion of the argument to a general |
6d82d43b | 3455 | purpose register. */ |
968b5391 | 3456 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
46cac009 AC |
3457 | { |
3458 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3459 | /* Value may need to be sign extended, because |
1b13c4f6 | 3460 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
3461 | |
3462 | /* A non-floating-point argument being passed in a | |
3463 | general register. If a struct or union, and if | |
3464 | the remaining length is smaller than the register | |
3465 | size, we have to adjust the register value on | |
3466 | big endian targets. | |
3467 | ||
3468 | It does not seem to be necessary to do the | |
3469 | same for integral types. | |
3470 | ||
3471 | Also don't do this adjustment on O64 binaries. | |
3472 | ||
3473 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
3474 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
3475 | mips_abi_regsize(), generates a left shift |
3476 | as part of storing the argument in a register | |
3477 | (the left shift isn't generated when | |
1b13c4f6 | 3478 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
3479 | it is quite possible that this is GCC |
3480 | contradicting the LE/O32 ABI, GDB has not been | |
3481 | adjusted to accommodate this. Either someone | |
3482 | needs to demonstrate that the LE/O32 ABI | |
3483 | specifies such a left shift OR this new ABI gets | |
3484 | identified as such and GDB gets tweaked | |
3485 | accordingly. */ | |
3486 | ||
4c6b5505 | 3487 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3488 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
3489 | && (typecode == TYPE_CODE_STRUCT |
3490 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3491 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 3492 | * TARGET_CHAR_BIT); |
46cac009 AC |
3493 | |
3494 | if (mips_debug) | |
3495 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3496 | argreg, | |
1a69e1e4 | 3497 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 3498 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
3499 | argreg++; |
3500 | ||
3501 | /* Prevent subsequent floating point arguments from | |
3502 | being passed in floating point registers. */ | |
3503 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3504 | } | |
3505 | ||
3506 | len -= partial_len; | |
3507 | val += partial_len; | |
3508 | ||
3509 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3510 | will copy the next parameter. |
46cac009 | 3511 | |
6d82d43b AC |
3512 | In older ABIs, the caller reserved space for |
3513 | registers that contained arguments. This was loosely | |
3514 | refered to as their "home". Consequently, space is | |
3515 | always allocated. */ | |
46cac009 | 3516 | |
1a69e1e4 | 3517 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
3518 | } |
3519 | } | |
3520 | if (mips_debug) | |
3521 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3522 | } | |
3523 | ||
f10683bb | 3524 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3525 | |
46cac009 AC |
3526 | /* Return adjusted stack pointer. */ |
3527 | return sp; | |
3528 | } | |
3529 | ||
6d82d43b AC |
3530 | static enum return_value_convention |
3531 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *type, | |
3532 | struct regcache *regcache, | |
47a35522 | 3533 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b AC |
3534 | { |
3535 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3536 | ||
3537 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3538 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3539 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3540 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3541 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3542 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3543 | { | |
3544 | /* A single-precision floating-point value. It fits in the | |
3545 | least significant part of FP0. */ | |
3546 | if (mips_debug) | |
3547 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3548 | mips_xfer_register (regcache, | |
f57d151a UW |
3549 | gdbarch_num_regs (current_gdbarch) |
3550 | + mips_regnum (current_gdbarch)->fp0, | |
6d82d43b | 3551 | TYPE_LENGTH (type), |
4c6b5505 UW |
3552 | gdbarch_byte_order (current_gdbarch), |
3553 | readbuf, writebuf, 0); | |
6d82d43b AC |
3554 | return RETURN_VALUE_REGISTER_CONVENTION; |
3555 | } | |
3556 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
3557 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3558 | { | |
3559 | /* A double-precision floating-point value. The most | |
3560 | significant part goes in FP1, and the least significant in | |
3561 | FP0. */ | |
3562 | if (mips_debug) | |
3563 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
4c6b5505 | 3564 | switch (gdbarch_byte_order (current_gdbarch)) |
6d82d43b AC |
3565 | { |
3566 | case BFD_ENDIAN_LITTLE: | |
3567 | mips_xfer_register (regcache, | |
f57d151a UW |
3568 | gdbarch_num_regs (current_gdbarch) |
3569 | + mips_regnum (current_gdbarch)->fp0 + | |
4c6b5505 UW |
3570 | 0, 4, gdbarch_byte_order (current_gdbarch), |
3571 | readbuf, writebuf, 0); | |
6d82d43b | 3572 | mips_xfer_register (regcache, |
f57d151a UW |
3573 | gdbarch_num_regs (current_gdbarch) |
3574 | + mips_regnum (current_gdbarch)->fp0 + 1, | |
4c6b5505 UW |
3575 | 4, gdbarch_byte_order (current_gdbarch), |
3576 | readbuf, writebuf, 4); | |
6d82d43b AC |
3577 | break; |
3578 | case BFD_ENDIAN_BIG: | |
3579 | mips_xfer_register (regcache, | |
f57d151a UW |
3580 | gdbarch_num_regs (current_gdbarch) |
3581 | + mips_regnum (current_gdbarch)->fp0 + 1, | |
4c6b5505 UW |
3582 | 4, gdbarch_byte_order (current_gdbarch), |
3583 | readbuf, writebuf, 0); | |
6d82d43b | 3584 | mips_xfer_register (regcache, |
f57d151a UW |
3585 | gdbarch_num_regs (current_gdbarch) |
3586 | + mips_regnum (current_gdbarch)->fp0 + 0, | |
4c6b5505 UW |
3587 | 4, gdbarch_byte_order (current_gdbarch), |
3588 | readbuf, writebuf, 4); | |
6d82d43b AC |
3589 | break; |
3590 | default: | |
e2e0b3e5 | 3591 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
3592 | } |
3593 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3594 | } | |
3595 | #if 0 | |
3596 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3597 | && TYPE_NFIELDS (type) <= 2 | |
3598 | && TYPE_NFIELDS (type) >= 1 | |
3599 | && ((TYPE_NFIELDS (type) == 1 | |
3600 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3601 | == TYPE_CODE_FLT)) | |
3602 | || (TYPE_NFIELDS (type) == 2 | |
3603 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
3604 | == TYPE_CODE_FLT) | |
3605 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
3606 | == TYPE_CODE_FLT))) | |
3607 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3608 | { | |
3609 | /* A struct that contains one or two floats. Each value is part | |
3610 | in the least significant part of their floating point | |
3611 | register.. */ | |
870cd05e | 3612 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
3613 | int regnum; |
3614 | int field; | |
3615 | for (field = 0, regnum = mips_regnum (current_gdbarch)->fp0; | |
3616 | field < TYPE_NFIELDS (type); field++, regnum += 2) | |
3617 | { | |
3618 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3619 | / TARGET_CHAR_BIT); | |
3620 | if (mips_debug) | |
3621 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3622 | offset); | |
f57d151a UW |
3623 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3624 | + regnum, | |
6d82d43b | 3625 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
4c6b5505 UW |
3626 | gdbarch_byte_order (current_gdbarch), |
3627 | readbuf, writebuf, offset); | |
6d82d43b AC |
3628 | } |
3629 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3630 | } | |
3631 | #endif | |
3632 | #if 0 | |
3633 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3634 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3635 | { | |
3636 | /* A structure or union. Extract the left justified value, | |
3637 | regardless of the byte order. I.e. DO NOT USE | |
3638 | mips_xfer_lower. */ | |
3639 | int offset; | |
3640 | int regnum; | |
4c7d22cb | 3641 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b AC |
3642 | offset < TYPE_LENGTH (type); |
3643 | offset += register_size (current_gdbarch, regnum), regnum++) | |
3644 | { | |
3645 | int xfer = register_size (current_gdbarch, regnum); | |
3646 | if (offset + xfer > TYPE_LENGTH (type)) | |
3647 | xfer = TYPE_LENGTH (type) - offset; | |
3648 | if (mips_debug) | |
3649 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3650 | offset, xfer, regnum); | |
f57d151a UW |
3651 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3652 | + regnum, xfer, | |
6d82d43b AC |
3653 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
3654 | } | |
3655 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3656 | } | |
3657 | #endif | |
3658 | else | |
3659 | { | |
3660 | /* A scalar extract each part but least-significant-byte | |
3661 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 3662 | the ISA. */ |
6d82d43b AC |
3663 | int offset; |
3664 | int regnum; | |
4c7d22cb | 3665 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3666 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 3667 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 3668 | { |
1a69e1e4 | 3669 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
3670 | if (offset + xfer > TYPE_LENGTH (type)) |
3671 | xfer = TYPE_LENGTH (type) - offset; | |
3672 | if (mips_debug) | |
3673 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3674 | offset, xfer, regnum); | |
f57d151a UW |
3675 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3676 | + regnum, xfer, | |
4c6b5505 UW |
3677 | gdbarch_byte_order (current_gdbarch), |
3678 | readbuf, writebuf, offset); | |
6d82d43b AC |
3679 | } |
3680 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3681 | } | |
3682 | } | |
3683 | ||
3684 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
3685 | ABI. */ | |
46cac009 AC |
3686 | |
3687 | static CORE_ADDR | |
7d9b040b | 3688 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3689 | struct regcache *regcache, CORE_ADDR bp_addr, |
3690 | int nargs, | |
3691 | struct value **args, CORE_ADDR sp, | |
3692 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
3693 | { |
3694 | int argreg; | |
3695 | int float_argreg; | |
3696 | int argnum; | |
3697 | int len = 0; | |
3698 | int stack_offset = 0; | |
480d3dd2 | 3699 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7d9b040b | 3700 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 3701 | |
25ab4790 AC |
3702 | /* For shared libraries, "t9" needs to point at the function |
3703 | address. */ | |
4c7d22cb | 3704 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3705 | |
3706 | /* Set the return address register to point to the entry point of | |
3707 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3708 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3709 | |
46cac009 AC |
3710 | /* First ensure that the stack and structure return address (if any) |
3711 | are properly aligned. The stack has to be at least 64-bit | |
3712 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3713 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3714 | aligned, so we round to this widest known alignment. */ | |
3715 | ||
5b03f266 AC |
3716 | sp = align_down (sp, 16); |
3717 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
3718 | |
3719 | /* Now make space on the stack for the args. */ | |
3720 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3721 | { |
3722 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3723 | int arglen = TYPE_LENGTH (arg_type); | |
3724 | ||
968b5391 | 3725 | /* Allocate space on the stack. */ |
1a69e1e4 | 3726 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 3727 | } |
5b03f266 | 3728 | sp -= align_up (len, 16); |
46cac009 AC |
3729 | |
3730 | if (mips_debug) | |
6d82d43b | 3731 | fprintf_unfiltered (gdb_stdlog, |
5b03f266 AC |
3732 | "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n", |
3733 | paddr_nz (sp), (long) align_up (len, 16)); | |
46cac009 AC |
3734 | |
3735 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3736 | argreg = MIPS_A0_REGNUM; |
56cea623 | 3737 | float_argreg = mips_fpa0_regnum (current_gdbarch); |
46cac009 AC |
3738 | |
3739 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
3740 | if (struct_return) | |
3741 | { | |
3742 | if (mips_debug) | |
3743 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3744 | "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n", |
46cac009 | 3745 | argreg, paddr_nz (struct_addr)); |
9c9acae0 | 3746 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3747 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
3748 | } |
3749 | ||
3750 | /* Now load as many as possible of the first arguments into | |
3751 | registers, and push the rest onto the stack. Loop thru args | |
3752 | from first to last. */ | |
3753 | for (argnum = 0; argnum < nargs; argnum++) | |
3754 | { | |
47a35522 | 3755 | const gdb_byte *val; |
46cac009 | 3756 | struct value *arg = args[argnum]; |
4991999e | 3757 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
3758 | int len = TYPE_LENGTH (arg_type); |
3759 | enum type_code typecode = TYPE_CODE (arg_type); | |
3760 | ||
3761 | if (mips_debug) | |
3762 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3763 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
3764 | argnum + 1, len, (int) typecode); |
3765 | ||
47a35522 | 3766 | val = value_contents (arg); |
ebafbe83 | 3767 | |
ebafbe83 MS |
3768 | /* Floating point arguments passed in registers have to be |
3769 | treated specially. On 32-bit architectures, doubles | |
3770 | are passed in register pairs; the even register gets | |
3771 | the low word, and the odd register gets the high word. | |
3772 | On O32/O64, the first two floating point arguments are | |
3773 | also copied to general registers, because MIPS16 functions | |
3774 | don't use float registers for arguments. This duplication of | |
3775 | arguments in general registers can't hurt non-MIPS16 functions | |
3776 | because those registers are normally skipped. */ | |
3777 | ||
3778 | if (fp_register_arg_p (typecode, arg_type) | |
3779 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM) | |
3780 | { | |
2afd3f0a MR |
3781 | LONGEST regval = extract_unsigned_integer (val, len); |
3782 | if (mips_debug) | |
3783 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3784 | float_argreg, phex (regval, len)); | |
9c9acae0 | 3785 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
3786 | if (mips_debug) |
3787 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3788 | argreg, phex (regval, len)); | |
9c9acae0 | 3789 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 3790 | argreg++; |
ebafbe83 | 3791 | /* Reserve space for the FP register. */ |
1a69e1e4 | 3792 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
3793 | } |
3794 | else | |
3795 | { | |
3796 | /* Copy the argument to general registers or the stack in | |
3797 | register-sized pieces. Large arguments are split between | |
3798 | registers and stack. */ | |
1a69e1e4 | 3799 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
3800 | are treated specially: Irix cc passes them in registers |
3801 | where gcc sometimes puts them on the stack. For maximum | |
3802 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
3803 | int odd_sized_struct = (len > MIPS64_REGSIZE |
3804 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
3805 | while (len > 0) |
3806 | { | |
3807 | /* Remember if the argument was written to the stack. */ | |
3808 | int stack_used_p = 0; | |
1a69e1e4 | 3809 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
3810 | |
3811 | if (mips_debug) | |
3812 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3813 | partial_len); | |
3814 | ||
3815 | /* Write this portion of the argument to the stack. */ | |
3816 | if (argreg > MIPS_LAST_ARG_REGNUM | |
968b5391 | 3817 | || odd_sized_struct) |
ebafbe83 MS |
3818 | { |
3819 | /* Should shorter than int integer values be | |
3820 | promoted to int before being stored? */ | |
3821 | int longword_offset = 0; | |
3822 | CORE_ADDR addr; | |
3823 | stack_used_p = 1; | |
4c6b5505 | 3824 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 3825 | { |
1a69e1e4 DJ |
3826 | if ((typecode == TYPE_CODE_INT |
3827 | || typecode == TYPE_CODE_PTR | |
3828 | || typecode == TYPE_CODE_FLT) | |
3829 | && len <= 4) | |
3830 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
3831 | } |
3832 | ||
3833 | if (mips_debug) | |
3834 | { | |
3835 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=0x%s", | |
3836 | paddr_nz (stack_offset)); | |
3837 | fprintf_unfiltered (gdb_stdlog, " longword_offset=0x%s", | |
3838 | paddr_nz (longword_offset)); | |
3839 | } | |
3840 | ||
3841 | addr = sp + stack_offset + longword_offset; | |
3842 | ||
3843 | if (mips_debug) | |
3844 | { | |
3845 | int i; | |
6d82d43b | 3846 | fprintf_unfiltered (gdb_stdlog, " @0x%s ", |
ebafbe83 MS |
3847 | paddr_nz (addr)); |
3848 | for (i = 0; i < partial_len; i++) | |
3849 | { | |
6d82d43b | 3850 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
3851 | val[i] & 0xff); |
3852 | } | |
3853 | } | |
3854 | write_memory (addr, val, partial_len); | |
3855 | } | |
3856 | ||
3857 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 3858 | structs may go thru BOTH paths. */ |
ebafbe83 | 3859 | /* Write this portion of the argument to a general |
6d82d43b | 3860 | purpose register. */ |
968b5391 | 3861 | if (argreg <= MIPS_LAST_ARG_REGNUM) |
ebafbe83 MS |
3862 | { |
3863 | LONGEST regval = extract_signed_integer (val, partial_len); | |
4246e332 | 3864 | /* Value may need to be sign extended, because |
1b13c4f6 | 3865 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
3866 | |
3867 | /* A non-floating-point argument being passed in a | |
3868 | general register. If a struct or union, and if | |
3869 | the remaining length is smaller than the register | |
3870 | size, we have to adjust the register value on | |
3871 | big endian targets. | |
3872 | ||
3873 | It does not seem to be necessary to do the | |
401835eb | 3874 | same for integral types. */ |
480d3dd2 | 3875 | |
4c6b5505 | 3876 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3877 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3878 | && (typecode == TYPE_CODE_STRUCT |
3879 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3880 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3881 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
3882 | |
3883 | if (mips_debug) | |
3884 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3885 | argreg, | |
1a69e1e4 | 3886 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3887 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
3888 | argreg++; |
3889 | ||
3890 | /* Prevent subsequent floating point arguments from | |
3891 | being passed in floating point registers. */ | |
3892 | float_argreg = MIPS_LAST_FP_ARG_REGNUM + 1; | |
3893 | } | |
3894 | ||
3895 | len -= partial_len; | |
3896 | val += partial_len; | |
3897 | ||
3898 | /* Compute the the offset into the stack at which we | |
6d82d43b | 3899 | will copy the next parameter. |
ebafbe83 | 3900 | |
6d82d43b AC |
3901 | In older ABIs, the caller reserved space for |
3902 | registers that contained arguments. This was loosely | |
3903 | refered to as their "home". Consequently, space is | |
3904 | always allocated. */ | |
ebafbe83 | 3905 | |
1a69e1e4 | 3906 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
3907 | } |
3908 | } | |
3909 | if (mips_debug) | |
3910 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3911 | } | |
3912 | ||
f10683bb | 3913 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3914 | |
ebafbe83 MS |
3915 | /* Return adjusted stack pointer. */ |
3916 | return sp; | |
3917 | } | |
3918 | ||
9c8fdbfa AC |
3919 | static enum return_value_convention |
3920 | mips_o64_return_value (struct gdbarch *gdbarch, | |
3921 | struct type *type, struct regcache *regcache, | |
47a35522 | 3922 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3923 | { |
7a076fd2 FF |
3924 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3925 | ||
3926 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3927 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
3928 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
3929 | return RETURN_VALUE_STRUCT_CONVENTION; | |
3930 | else if (fp_register_arg_p (TYPE_CODE (type), type)) | |
3931 | { | |
3932 | /* A floating-point value. It fits in the least significant | |
3933 | part of FP0. */ | |
3934 | if (mips_debug) | |
3935 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3936 | mips_xfer_register (regcache, | |
f57d151a UW |
3937 | gdbarch_num_regs (current_gdbarch) |
3938 | + mips_regnum (current_gdbarch)->fp0, | |
7a076fd2 | 3939 | TYPE_LENGTH (type), |
4c6b5505 UW |
3940 | gdbarch_byte_order (current_gdbarch), |
3941 | readbuf, writebuf, 0); | |
7a076fd2 FF |
3942 | return RETURN_VALUE_REGISTER_CONVENTION; |
3943 | } | |
3944 | else | |
3945 | { | |
3946 | /* A scalar extract each part but least-significant-byte | |
3947 | justified. */ | |
3948 | int offset; | |
3949 | int regnum; | |
3950 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
3951 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 3952 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 3953 | { |
1a69e1e4 | 3954 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
3955 | if (offset + xfer > TYPE_LENGTH (type)) |
3956 | xfer = TYPE_LENGTH (type) - offset; | |
3957 | if (mips_debug) | |
3958 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3959 | offset, xfer, regnum); | |
f57d151a UW |
3960 | mips_xfer_register (regcache, gdbarch_num_regs (current_gdbarch) |
3961 | + regnum, xfer, | |
4c6b5505 UW |
3962 | gdbarch_byte_order (current_gdbarch), |
3963 | readbuf, writebuf, offset); | |
7a076fd2 FF |
3964 | } |
3965 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3966 | } | |
6d82d43b AC |
3967 | } |
3968 | ||
dd824b04 DJ |
3969 | /* Floating point register management. |
3970 | ||
3971 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
3972 | 64bit operations, these early MIPS cpus treat fp register pairs | |
3973 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
3974 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
3975 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
3976 | double precision floats into two 32-bit chunks and store them in | |
3977 | consecutive fp regs. To display 64-bit floats stored in this | |
3978 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
3979 | Throw in user-configurable endianness and you have a real mess. | |
3980 | ||
3981 | The way this works is: | |
3982 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
3983 | double-precision value will be split across two logical registers. | |
3984 | The lower-numbered logical register will hold the low-order bits, | |
3985 | regardless of the processor's endianness. | |
3986 | - If we are on a 64-bit processor, and we are looking for a | |
3987 | single-precision value, it will be in the low ordered bits | |
3988 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
3989 | save slot in memory. | |
3990 | - If we are in 64-bit mode, everything is straightforward. | |
3991 | ||
3992 | Note that this code only deals with "live" registers at the top of the | |
3993 | stack. We will attempt to deal with saved registers later, when | |
3994 | the raw/cooked register interface is in place. (We need a general | |
3995 | interface that can deal with dynamic saved register sizes -- fp | |
3996 | regs could be 32 bits wide in one frame and 64 on the frame above | |
3997 | and below). */ | |
3998 | ||
67b2c998 DJ |
3999 | static struct type * |
4000 | mips_float_register_type (void) | |
4001 | { | |
8da61cc4 | 4002 | return builtin_type_ieee_single; |
67b2c998 DJ |
4003 | } |
4004 | ||
4005 | static struct type * | |
4006 | mips_double_register_type (void) | |
4007 | { | |
8da61cc4 | 4008 | return builtin_type_ieee_double; |
67b2c998 DJ |
4009 | } |
4010 | ||
dd824b04 DJ |
4011 | /* Copy a 32-bit single-precision value from the current frame |
4012 | into rare_buffer. */ | |
4013 | ||
4014 | static void | |
e11c53d2 | 4015 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4016 | gdb_byte *rare_buffer) |
dd824b04 | 4017 | { |
719ec221 | 4018 | int raw_size = register_size (current_gdbarch, regno); |
47a35522 | 4019 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4020 | |
e11c53d2 | 4021 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 UW |
4022 | error (_("can't read register %d (%s)"), |
4023 | regno, gdbarch_register_name (current_gdbarch, regno)); | |
dd824b04 DJ |
4024 | if (raw_size == 8) |
4025 | { | |
4026 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4027 | 32 bits. */ |
dd824b04 DJ |
4028 | int offset; |
4029 | ||
4c6b5505 | 4030 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4031 | offset = 4; |
4032 | else | |
4033 | offset = 0; | |
4034 | ||
4035 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4036 | } | |
4037 | else | |
4038 | { | |
4039 | memcpy (rare_buffer, raw_buffer, 4); | |
4040 | } | |
4041 | } | |
4042 | ||
4043 | /* Copy a 64-bit double-precision value from the current frame into | |
4044 | rare_buffer. This may include getting half of it from the next | |
4045 | register. */ | |
4046 | ||
4047 | static void | |
e11c53d2 | 4048 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4049 | gdb_byte *rare_buffer) |
dd824b04 | 4050 | { |
719ec221 | 4051 | int raw_size = register_size (current_gdbarch, regno); |
dd824b04 | 4052 | |
9c9acae0 | 4053 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4054 | { |
4055 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4056 | all 64 bits. */ |
e11c53d2 | 4057 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 UW |
4058 | error (_("can't read register %d (%s)"), |
4059 | regno, gdbarch_register_name (current_gdbarch, regno)); | |
dd824b04 DJ |
4060 | } |
4061 | else | |
4062 | { | |
82e91389 DJ |
4063 | int rawnum = regno % gdbarch_num_regs (current_gdbarch); |
4064 | ||
4065 | if ((rawnum - mips_regnum (current_gdbarch)->fp0) & 1) | |
dd824b04 | 4066 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4067 | _("mips_read_fp_register_double: bad access to " |
4068 | "odd-numbered FP register")); | |
dd824b04 DJ |
4069 | |
4070 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4071 | each register. */ |
4c6b5505 | 4072 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4073 | { |
e11c53d2 AC |
4074 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4075 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4076 | } |
361d1df0 | 4077 | else |
dd824b04 | 4078 | { |
e11c53d2 AC |
4079 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4080 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4081 | } |
4082 | } | |
4083 | } | |
4084 | ||
c906108c | 4085 | static void |
e11c53d2 AC |
4086 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4087 | int regnum) | |
c5aa993b | 4088 | { /* do values for FP (float) regs */ |
47a35522 | 4089 | gdb_byte *raw_buffer; |
3903d437 AC |
4090 | double doub, flt1; /* doubles extracted from raw hex data */ |
4091 | int inv1, inv2; | |
c5aa993b | 4092 | |
47a35522 MK |
4093 | raw_buffer = alloca (2 * register_size (current_gdbarch, |
4094 | mips_regnum (current_gdbarch)->fp0)); | |
c906108c | 4095 | |
c9f4d572 UW |
4096 | fprintf_filtered (file, "%s:", |
4097 | gdbarch_register_name (current_gdbarch, regnum)); | |
4098 | fprintf_filtered (file, "%*s", | |
4099 | 4 - (int) strlen (gdbarch_register_name | |
4100 | (current_gdbarch, regnum)), | |
e11c53d2 | 4101 | ""); |
f0ef6b29 | 4102 | |
9c9acae0 | 4103 | if (register_size (current_gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4104 | { |
f0ef6b29 KB |
4105 | /* 4-byte registers: Print hex and floating. Also print even |
4106 | numbered registers as doubles. */ | |
e11c53d2 | 4107 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
67b2c998 | 4108 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c5aa993b | 4109 | |
6d82d43b AC |
4110 | print_scalar_formatted (raw_buffer, builtin_type_uint32, 'x', 'w', |
4111 | file); | |
dd824b04 | 4112 | |
e11c53d2 | 4113 | fprintf_filtered (file, " flt: "); |
1adad886 | 4114 | if (inv1) |
e11c53d2 | 4115 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4116 | else |
e11c53d2 | 4117 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4118 | |
82e91389 | 4119 | if ((regnum - gdbarch_num_regs (current_gdbarch)) % 2 == 0) |
f0ef6b29 | 4120 | { |
e11c53d2 | 4121 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 | 4122 | doub = unpack_double (mips_double_register_type (), raw_buffer, |
6d82d43b | 4123 | &inv2); |
1adad886 | 4124 | |
e11c53d2 | 4125 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4126 | if (inv2) |
e11c53d2 | 4127 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4128 | else |
e11c53d2 | 4129 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4130 | } |
c906108c SS |
4131 | } |
4132 | else | |
dd824b04 | 4133 | { |
f0ef6b29 | 4134 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4135 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
2f38ef89 | 4136 | flt1 = unpack_double (mips_float_register_type (), raw_buffer, &inv1); |
c906108c | 4137 | |
e11c53d2 | 4138 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f0ef6b29 KB |
4139 | doub = unpack_double (mips_double_register_type (), raw_buffer, &inv2); |
4140 | ||
361d1df0 | 4141 | |
6d82d43b AC |
4142 | print_scalar_formatted (raw_buffer, builtin_type_uint64, 'x', 'g', |
4143 | file); | |
f0ef6b29 | 4144 | |
e11c53d2 | 4145 | fprintf_filtered (file, " flt: "); |
1adad886 | 4146 | if (inv1) |
e11c53d2 | 4147 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4148 | else |
e11c53d2 | 4149 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4150 | |
e11c53d2 | 4151 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4152 | if (inv2) |
e11c53d2 | 4153 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4154 | else |
e11c53d2 | 4155 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4156 | } |
4157 | } | |
4158 | ||
4159 | static void | |
e11c53d2 | 4160 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4161 | int regnum) |
f0ef6b29 | 4162 | { |
a4b8ebc8 | 4163 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4164 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
f0ef6b29 | 4165 | int offset; |
1adad886 | 4166 | |
7b9ee6a8 | 4167 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4168 | { |
e11c53d2 | 4169 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4170 | return; |
4171 | } | |
4172 | ||
4173 | /* Get the data in raw format. */ | |
e11c53d2 | 4174 | if (!frame_register_read (frame, regnum, raw_buffer)) |
f0ef6b29 | 4175 | { |
c9f4d572 UW |
4176 | fprintf_filtered (file, "%s: [Invalid]", |
4177 | gdbarch_register_name (current_gdbarch, regnum)); | |
f0ef6b29 | 4178 | return; |
c906108c | 4179 | } |
f0ef6b29 | 4180 | |
c9f4d572 | 4181 | fputs_filtered (gdbarch_register_name (current_gdbarch, regnum), file); |
f0ef6b29 KB |
4182 | |
4183 | /* The problem with printing numeric register names (r26, etc.) is that | |
4184 | the user can't use them on input. Probably the best solution is to | |
4185 | fix it so that either the numeric or the funky (a2, etc.) names | |
4186 | are accepted on input. */ | |
4187 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4188 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4189 | else |
e11c53d2 | 4190 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4191 | |
4c6b5505 | 4192 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b AC |
4193 | offset = |
4194 | register_size (current_gdbarch, | |
4195 | regnum) - register_size (current_gdbarch, regnum); | |
f0ef6b29 KB |
4196 | else |
4197 | offset = 0; | |
4198 | ||
6d82d43b | 4199 | print_scalar_formatted (raw_buffer + offset, |
7b9ee6a8 | 4200 | register_type (gdbarch, regnum), 'x', 0, |
6d82d43b | 4201 | file); |
c906108c SS |
4202 | } |
4203 | ||
f0ef6b29 KB |
4204 | /* Replacement for generic do_registers_info. |
4205 | Print regs in pretty columns. */ | |
4206 | ||
4207 | static int | |
e11c53d2 AC |
4208 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4209 | int regnum) | |
f0ef6b29 | 4210 | { |
e11c53d2 AC |
4211 | fprintf_filtered (file, " "); |
4212 | mips_print_fp_register (file, frame, regnum); | |
4213 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4214 | return regnum + 1; |
4215 | } | |
4216 | ||
4217 | ||
c906108c SS |
4218 | /* Print a row's worth of GP (int) registers, with name labels above */ |
4219 | ||
4220 | static int | |
e11c53d2 | 4221 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4222 | int start_regnum) |
c906108c | 4223 | { |
a4b8ebc8 | 4224 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 4225 | /* do values for GP (int) regs */ |
47a35522 | 4226 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
d5ac5a39 | 4227 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row */ |
c906108c | 4228 | int col, byte; |
a4b8ebc8 | 4229 | int regnum; |
c906108c SS |
4230 | |
4231 | /* For GP registers, we print a separate row of names above the vals */ | |
a4b8ebc8 | 4232 | for (col = 0, regnum = start_regnum; |
f57d151a UW |
4233 | col < ncols && regnum < gdbarch_num_regs (current_gdbarch) |
4234 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4235 | regnum++) | |
c906108c | 4236 | { |
c9f4d572 | 4237 | if (*gdbarch_register_name (current_gdbarch, regnum) == '\0') |
c5aa993b | 4238 | continue; /* unused register */ |
7b9ee6a8 | 4239 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4240 | TYPE_CODE_FLT) |
c5aa993b | 4241 | break; /* end the row: reached FP register */ |
0cc93a06 DJ |
4242 | /* Large registers are handled separately. */ |
4243 | if (register_size (current_gdbarch, regnum) | |
4244 | > mips_abi_regsize (current_gdbarch)) | |
4245 | { | |
4246 | if (col > 0) | |
4247 | break; /* End the row before this register. */ | |
4248 | ||
4249 | /* Print this register on a row by itself. */ | |
4250 | mips_print_register (file, frame, regnum); | |
4251 | fprintf_filtered (file, "\n"); | |
4252 | return regnum + 1; | |
4253 | } | |
d05f6826 DJ |
4254 | if (col == 0) |
4255 | fprintf_filtered (file, " "); | |
6d82d43b | 4256 | fprintf_filtered (file, |
d5ac5a39 | 4257 | mips_abi_regsize (current_gdbarch) == 8 ? "%17s" : "%9s", |
c9f4d572 | 4258 | gdbarch_register_name (current_gdbarch, regnum)); |
c906108c SS |
4259 | col++; |
4260 | } | |
d05f6826 DJ |
4261 | |
4262 | if (col == 0) | |
4263 | return regnum; | |
4264 | ||
a4b8ebc8 | 4265 | /* print the R0 to R31 names */ |
f57d151a UW |
4266 | if ((start_regnum % gdbarch_num_regs (current_gdbarch)) < MIPS_NUMREGS) |
4267 | fprintf_filtered (file, "\n R%-4d", | |
4268 | start_regnum % gdbarch_num_regs (current_gdbarch)); | |
20e6603c AC |
4269 | else |
4270 | fprintf_filtered (file, "\n "); | |
c906108c | 4271 | |
c906108c | 4272 | /* now print the values in hex, 4 or 8 to the row */ |
a4b8ebc8 | 4273 | for (col = 0, regnum = start_regnum; |
f57d151a UW |
4274 | col < ncols && regnum < gdbarch_num_regs (current_gdbarch) |
4275 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4276 | regnum++) | |
c906108c | 4277 | { |
c9f4d572 | 4278 | if (*gdbarch_register_name (current_gdbarch, regnum) == '\0') |
c5aa993b | 4279 | continue; /* unused register */ |
7b9ee6a8 | 4280 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4281 | TYPE_CODE_FLT) |
c5aa993b | 4282 | break; /* end row: reached FP register */ |
0cc93a06 DJ |
4283 | if (register_size (current_gdbarch, regnum) |
4284 | > mips_abi_regsize (current_gdbarch)) | |
4285 | break; /* End row: large register. */ | |
4286 | ||
c906108c | 4287 | /* OK: get the data in raw format. */ |
e11c53d2 | 4288 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 UW |
4289 | error (_("can't read register %d (%s)"), |
4290 | regnum, gdbarch_register_name (current_gdbarch, regnum)); | |
c906108c | 4291 | /* pad small registers */ |
4246e332 | 4292 | for (byte = 0; |
d5ac5a39 | 4293 | byte < (mips_abi_regsize (current_gdbarch) |
6d82d43b | 4294 | - register_size (current_gdbarch, regnum)); byte++) |
c906108c SS |
4295 | printf_filtered (" "); |
4296 | /* Now print the register value in hex, endian order. */ | |
4c6b5505 | 4297 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b AC |
4298 | for (byte = |
4299 | register_size (current_gdbarch, | |
4300 | regnum) - register_size (current_gdbarch, regnum); | |
4301 | byte < register_size (current_gdbarch, regnum); byte++) | |
47a35522 | 4302 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4303 | else |
c73e8f27 | 4304 | for (byte = register_size (current_gdbarch, regnum) - 1; |
6d82d43b | 4305 | byte >= 0; byte--) |
47a35522 | 4306 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4307 | fprintf_filtered (file, " "); |
c906108c SS |
4308 | col++; |
4309 | } | |
c5aa993b | 4310 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4311 | fprintf_filtered (file, "\n"); |
c906108c SS |
4312 | |
4313 | return regnum; | |
4314 | } | |
4315 | ||
4316 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */ | |
4317 | ||
bf1f5b4c | 4318 | static void |
e11c53d2 AC |
4319 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4320 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4321 | { |
c5aa993b | 4322 | if (regnum != -1) /* do one specified register */ |
c906108c | 4323 | { |
f57d151a | 4324 | gdb_assert (regnum >= gdbarch_num_regs (current_gdbarch)); |
c9f4d572 | 4325 | if (*(gdbarch_register_name (current_gdbarch, regnum)) == '\0') |
8a3fe4f8 | 4326 | error (_("Not a valid register for the current processor type")); |
c906108c | 4327 | |
0cc93a06 | 4328 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4329 | fprintf_filtered (file, "\n"); |
c906108c | 4330 | } |
c5aa993b JM |
4331 | else |
4332 | /* do all (or most) registers */ | |
c906108c | 4333 | { |
f57d151a UW |
4334 | regnum = gdbarch_num_regs (current_gdbarch); |
4335 | while (regnum < gdbarch_num_regs (current_gdbarch) | |
4336 | + gdbarch_num_pseudo_regs (current_gdbarch)) | |
c906108c | 4337 | { |
7b9ee6a8 | 4338 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4339 | TYPE_CODE_FLT) |
e11c53d2 AC |
4340 | { |
4341 | if (all) /* true for "INFO ALL-REGISTERS" command */ | |
4342 | regnum = print_fp_register_row (file, frame, regnum); | |
4343 | else | |
4344 | regnum += MIPS_NUMREGS; /* skip floating point regs */ | |
4345 | } | |
c906108c | 4346 | else |
e11c53d2 | 4347 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4348 | } |
4349 | } | |
4350 | } | |
4351 | ||
c906108c SS |
4352 | /* Is this a branch with a delay slot? */ |
4353 | ||
c906108c | 4354 | static int |
acdb74a0 | 4355 | is_delayed (unsigned long insn) |
c906108c SS |
4356 | { |
4357 | int i; | |
4358 | for (i = 0; i < NUMOPCODES; ++i) | |
4359 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4360 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4361 | break; | |
4362 | return (i < NUMOPCODES | |
4363 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4364 | | INSN_COND_BRANCH_DELAY | |
4365 | | INSN_COND_BRANCH_LIKELY))); | |
4366 | } | |
4367 | ||
4368 | int | |
3352ef37 AC |
4369 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4370 | struct frame_info *frame) | |
c906108c | 4371 | { |
3352ef37 | 4372 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4373 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4374 | |
4375 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4376 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4377 | return 0; |
4378 | ||
06648491 MK |
4379 | if (!breakpoint_here_p (pc + 4)) |
4380 | return 0; | |
4381 | ||
3352ef37 AC |
4382 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4383 | /* If error reading memory, guess that it is not a delayed | |
4384 | branch. */ | |
c906108c | 4385 | return 0; |
4c7d22cb | 4386 | return is_delayed (extract_unsigned_integer (buf, sizeof buf)); |
c906108c SS |
4387 | } |
4388 | ||
6d82d43b AC |
4389 | /* To skip prologues, I use this predicate. Returns either PC itself |
4390 | if the code at PC does not look like a function prologue; otherwise | |
4391 | returns an address that (if we're lucky) follows the prologue. If | |
4392 | LENIENT, then we must skip everything which is involved in setting | |
4393 | up the frame (it's OK to skip more, just so long as we don't skip | |
4394 | anything which might clobber the registers which are being saved. | |
4395 | We must skip more in the case where part of the prologue is in the | |
4396 | delay slot of a non-prologue instruction). */ | |
4397 | ||
4398 | static CORE_ADDR | |
4399 | mips_skip_prologue (CORE_ADDR pc) | |
4400 | { | |
8b622e6a AC |
4401 | CORE_ADDR limit_pc; |
4402 | CORE_ADDR func_addr; | |
4403 | ||
6d82d43b AC |
4404 | /* See if we can determine the end of the prologue via the symbol table. |
4405 | If so, then return either PC, or the PC after the prologue, whichever | |
4406 | is greater. */ | |
8b622e6a AC |
4407 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4408 | { | |
4409 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
4410 | if (post_prologue_pc != 0) | |
4411 | return max (pc, post_prologue_pc); | |
4412 | } | |
6d82d43b AC |
4413 | |
4414 | /* Can't determine prologue from the symbol table, need to examine | |
4415 | instructions. */ | |
4416 | ||
98b4dd94 JB |
4417 | /* Find an upper limit on the function prologue using the debug |
4418 | information. If the debug information could not be used to provide | |
4419 | that bound, then use an arbitrary large number as the upper bound. */ | |
4420 | limit_pc = skip_prologue_using_sal (pc); | |
4421 | if (limit_pc == 0) | |
4422 | limit_pc = pc + 100; /* Magic. */ | |
4423 | ||
0fe7e7c8 | 4424 | if (mips_pc_is_mips16 (pc)) |
a65bbe44 | 4425 | return mips16_scan_prologue (pc, limit_pc, NULL, NULL); |
6d82d43b | 4426 | else |
a65bbe44 | 4427 | return mips32_scan_prologue (pc, limit_pc, NULL, NULL); |
88658117 AC |
4428 | } |
4429 | ||
97ab0fdd MR |
4430 | /* Check whether the PC is in a function epilogue (32-bit version). |
4431 | This is a helper function for mips_in_function_epilogue_p. */ | |
4432 | static int | |
4433 | mips32_in_function_epilogue_p (CORE_ADDR pc) | |
4434 | { | |
4435 | CORE_ADDR func_addr = 0, func_end = 0; | |
4436 | ||
4437 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4438 | { | |
4439 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4440 | CORE_ADDR addr = func_end - 12; | |
4441 | ||
4442 | if (addr < func_addr + 4) | |
4443 | addr = func_addr + 4; | |
4444 | if (pc < addr) | |
4445 | return 0; | |
4446 | ||
4447 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
4448 | { | |
4449 | unsigned long high_word; | |
4450 | unsigned long inst; | |
4451 | ||
4452 | inst = mips_fetch_instruction (pc); | |
4453 | high_word = (inst >> 16) & 0xffff; | |
4454 | ||
4455 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
4456 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
4457 | && inst != 0x03e00008 /* jr $ra */ | |
4458 | && inst != 0x00000000) /* nop */ | |
4459 | return 0; | |
4460 | } | |
4461 | ||
4462 | return 1; | |
4463 | } | |
4464 | ||
4465 | return 0; | |
4466 | } | |
4467 | ||
4468 | /* Check whether the PC is in a function epilogue (16-bit version). | |
4469 | This is a helper function for mips_in_function_epilogue_p. */ | |
4470 | static int | |
4471 | mips16_in_function_epilogue_p (CORE_ADDR pc) | |
4472 | { | |
4473 | CORE_ADDR func_addr = 0, func_end = 0; | |
4474 | ||
4475 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
4476 | { | |
4477 | /* The MIPS epilogue is max. 12 bytes long. */ | |
4478 | CORE_ADDR addr = func_end - 12; | |
4479 | ||
4480 | if (addr < func_addr + 4) | |
4481 | addr = func_addr + 4; | |
4482 | if (pc < addr) | |
4483 | return 0; | |
4484 | ||
4485 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
4486 | { | |
4487 | unsigned short inst; | |
4488 | ||
4489 | inst = mips_fetch_instruction (pc); | |
4490 | ||
4491 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
4492 | continue; | |
4493 | ||
4494 | if (inst != 0x6300 /* addiu $sp,offset */ | |
4495 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
4496 | && inst != 0xe820 /* jr $ra */ | |
4497 | && inst != 0xe8a0 /* jrc $ra */ | |
4498 | && inst != 0x6500) /* nop */ | |
4499 | return 0; | |
4500 | } | |
4501 | ||
4502 | return 1; | |
4503 | } | |
4504 | ||
4505 | return 0; | |
4506 | } | |
4507 | ||
4508 | /* The epilogue is defined here as the area at the end of a function, | |
4509 | after an instruction which destroys the function's stack frame. */ | |
4510 | static int | |
4511 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4512 | { | |
4513 | if (mips_pc_is_mips16 (pc)) | |
4514 | return mips16_in_function_epilogue_p (pc); | |
4515 | else | |
4516 | return mips32_in_function_epilogue_p (pc); | |
4517 | } | |
4518 | ||
a5ea2558 AC |
4519 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
4520 | used for all MIPS-specific commands. */ | |
4521 | ||
a5ea2558 | 4522 | static void |
acdb74a0 | 4523 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
4524 | { |
4525 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
4526 | } | |
4527 | ||
a5ea2558 | 4528 | static void |
acdb74a0 | 4529 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 4530 | { |
6d82d43b AC |
4531 | printf_unfiltered |
4532 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
4533 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
4534 | } | |
4535 | ||
c906108c SS |
4536 | /* Commands to show/set the MIPS FPU type. */ |
4537 | ||
c906108c | 4538 | static void |
acdb74a0 | 4539 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 4540 | { |
c906108c SS |
4541 | char *fpu; |
4542 | switch (MIPS_FPU_TYPE) | |
4543 | { | |
4544 | case MIPS_FPU_SINGLE: | |
4545 | fpu = "single-precision"; | |
4546 | break; | |
4547 | case MIPS_FPU_DOUBLE: | |
4548 | fpu = "double-precision"; | |
4549 | break; | |
4550 | case MIPS_FPU_NONE: | |
4551 | fpu = "absent (none)"; | |
4552 | break; | |
93d56215 | 4553 | default: |
e2e0b3e5 | 4554 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
4555 | } |
4556 | if (mips_fpu_type_auto) | |
6d82d43b AC |
4557 | printf_unfiltered |
4558 | ("The MIPS floating-point coprocessor is set automatically (currently %s)\n", | |
4559 | fpu); | |
c906108c | 4560 | else |
6d82d43b AC |
4561 | printf_unfiltered |
4562 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
4563 | } |
4564 | ||
4565 | ||
c906108c | 4566 | static void |
acdb74a0 | 4567 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 4568 | { |
6d82d43b AC |
4569 | printf_unfiltered |
4570 | ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
4571 | show_mipsfpu_command (args, from_tty); |
4572 | } | |
4573 | ||
c906108c | 4574 | static void |
acdb74a0 | 4575 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 4576 | { |
8d5838b5 AC |
4577 | struct gdbarch_info info; |
4578 | gdbarch_info_init (&info); | |
c906108c SS |
4579 | mips_fpu_type = MIPS_FPU_SINGLE; |
4580 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4581 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4582 | instead of relying on globals. Doing that would let generic code | |
4583 | handle the search for this specific architecture. */ | |
4584 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4585 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4586 | } |
4587 | ||
c906108c | 4588 | static void |
acdb74a0 | 4589 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 4590 | { |
8d5838b5 AC |
4591 | struct gdbarch_info info; |
4592 | gdbarch_info_init (&info); | |
c906108c SS |
4593 | mips_fpu_type = MIPS_FPU_DOUBLE; |
4594 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4595 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4596 | instead of relying on globals. Doing that would let generic code | |
4597 | handle the search for this specific architecture. */ | |
4598 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4599 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4600 | } |
4601 | ||
c906108c | 4602 | static void |
acdb74a0 | 4603 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 4604 | { |
8d5838b5 AC |
4605 | struct gdbarch_info info; |
4606 | gdbarch_info_init (&info); | |
c906108c SS |
4607 | mips_fpu_type = MIPS_FPU_NONE; |
4608 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
4609 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
4610 | instead of relying on globals. Doing that would let generic code | |
4611 | handle the search for this specific architecture. */ | |
4612 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 4613 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
4614 | } |
4615 | ||
c906108c | 4616 | static void |
acdb74a0 | 4617 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
4618 | { |
4619 | mips_fpu_type_auto = 1; | |
4620 | } | |
4621 | ||
c906108c | 4622 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
4623 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
4624 | the relevant processor still exists (it dates back to '94) and | |
4625 | secondly this is not the way to do this. The processor type should | |
4626 | be set by forcing an architecture change. */ | |
c906108c | 4627 | |
691c0433 AC |
4628 | void |
4629 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 4630 | { |
691c0433 | 4631 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
a9614958 | 4632 | ULONGEST prid; |
c906108c | 4633 | |
594f7785 | 4634 | regcache_cooked_read_unsigned (get_current_regcache (), |
a9614958 | 4635 | MIPS_PRID_REGNUM, &prid); |
c906108c | 4636 | if ((prid & ~0xf) == 0x700) |
691c0433 | 4637 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
4638 | } |
4639 | ||
4640 | /* Just like reinit_frame_cache, but with the right arguments to be | |
4641 | callable as an sfunc. */ | |
4642 | ||
4643 | static void | |
acdb74a0 AC |
4644 | reinit_frame_cache_sfunc (char *args, int from_tty, |
4645 | struct cmd_list_element *c) | |
c906108c SS |
4646 | { |
4647 | reinit_frame_cache (); | |
4648 | } | |
4649 | ||
a89aa300 AC |
4650 | static int |
4651 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 4652 | { |
e5ab0dce | 4653 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 4654 | |
d31431ed AC |
4655 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
4656 | disassembler needs to be able to locally determine the ISA, and | |
4657 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
4658 | work. */ | |
ec4045ea AC |
4659 | if (mips_pc_is_mips16 (memaddr)) |
4660 | info->mach = bfd_mach_mips16; | |
c906108c SS |
4661 | |
4662 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 4663 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 4664 | |
e5ab0dce | 4665 | /* Set the disassembler options. */ |
6d82d43b | 4666 | if (tdep->mips_abi == MIPS_ABI_N32 || tdep->mips_abi == MIPS_ABI_N64) |
e5ab0dce AC |
4667 | { |
4668 | /* Set up the disassembler info, so that we get the right | |
6d82d43b | 4669 | register names from libopcodes. */ |
e5ab0dce AC |
4670 | if (tdep->mips_abi == MIPS_ABI_N32) |
4671 | info->disassembler_options = "gpr-names=n32"; | |
4672 | else | |
4673 | info->disassembler_options = "gpr-names=64"; | |
4674 | info->flavour = bfd_target_elf_flavour; | |
4675 | } | |
4676 | else | |
4677 | /* This string is not recognized explicitly by the disassembler, | |
4678 | but it tells the disassembler to not try to guess the ABI from | |
4679 | the bfd elf headers, such that, if the user overrides the ABI | |
4680 | of a program linked as NewABI, the disassembly will follow the | |
4681 | register naming conventions specified by the user. */ | |
4682 | info->disassembler_options = "gpr-names=32"; | |
4683 | ||
c906108c | 4684 | /* Call the appropriate disassembler based on the target endian-ness. */ |
4c6b5505 | 4685 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c SS |
4686 | return print_insn_big_mips (memaddr, info); |
4687 | else | |
4688 | return print_insn_little_mips (memaddr, info); | |
4689 | } | |
4690 | ||
3b3b875c UW |
4691 | /* This function implements gdbarch_breakpoint_from_pc. It uses the program |
4692 | counter value to determine whether a 16- or 32-bit breakpoint should be used. | |
4693 | It returns a pointer to a string of bytes that encode a breakpoint | |
4694 | instruction, stores the length of the string to *lenptr, and adjusts pc (if | |
4695 | necessary) to point to the actual memory location where the breakpoint | |
4696 | should be inserted. */ | |
c906108c | 4697 | |
47a35522 | 4698 | static const gdb_byte * |
6d82d43b | 4699 | mips_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c | 4700 | { |
4c6b5505 | 4701 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 4702 | { |
0fe7e7c8 | 4703 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4704 | { |
47a35522 | 4705 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 4706 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4707 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
4708 | return mips16_big_breakpoint; |
4709 | } | |
4710 | else | |
4711 | { | |
aaab4dba AC |
4712 | /* The IDT board uses an unusual breakpoint value, and |
4713 | sometimes gets confused when it sees the usual MIPS | |
4714 | breakpoint instruction. */ | |
47a35522 MK |
4715 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
4716 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
4717 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
c906108c | 4718 | |
c5aa993b | 4719 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
4720 | |
4721 | if (strcmp (target_shortname, "mips") == 0) | |
4722 | return idt_big_breakpoint; | |
4723 | else if (strcmp (target_shortname, "ddb") == 0 | |
4724 | || strcmp (target_shortname, "pmon") == 0 | |
4725 | || strcmp (target_shortname, "lsi") == 0) | |
4726 | return pmon_big_breakpoint; | |
4727 | else | |
4728 | return big_breakpoint; | |
4729 | } | |
4730 | } | |
4731 | else | |
4732 | { | |
0fe7e7c8 | 4733 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 4734 | { |
47a35522 | 4735 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 4736 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 4737 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
4738 | return mips16_little_breakpoint; |
4739 | } | |
4740 | else | |
4741 | { | |
47a35522 MK |
4742 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
4743 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
4744 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 4745 | |
c5aa993b | 4746 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
4747 | |
4748 | if (strcmp (target_shortname, "mips") == 0) | |
4749 | return idt_little_breakpoint; | |
4750 | else if (strcmp (target_shortname, "ddb") == 0 | |
4751 | || strcmp (target_shortname, "pmon") == 0 | |
4752 | || strcmp (target_shortname, "lsi") == 0) | |
4753 | return pmon_little_breakpoint; | |
4754 | else | |
4755 | return little_breakpoint; | |
4756 | } | |
4757 | } | |
4758 | } | |
4759 | ||
4760 | /* If PC is in a mips16 call or return stub, return the address of the target | |
4761 | PC, which is either the callee or the caller. There are several | |
4762 | cases which must be handled: | |
4763 | ||
4764 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 4765 | target PC is in $31 ($ra). |
c906108c | 4766 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 4767 | and the target PC is in $2. |
c906108c | 4768 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b JM |
4769 | before the jal instruction, this is effectively a call stub |
4770 | and the the target PC is in $2. Otherwise this is effectively | |
4771 | a return stub and the target PC is in $18. | |
c906108c SS |
4772 | |
4773 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 4774 | gory details. */ |
c906108c | 4775 | |
757a7cc6 | 4776 | static CORE_ADDR |
52f729a7 | 4777 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c SS |
4778 | { |
4779 | char *name; | |
4780 | CORE_ADDR start_addr; | |
4781 | ||
4782 | /* Find the starting address and name of the function containing the PC. */ | |
4783 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
4784 | return 0; | |
4785 | ||
4786 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
4787 | target PC is in $31 ($ra). */ | |
4788 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
4789 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 4790 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
4791 | |
4792 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
4793 | { | |
4794 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
4795 | and the target PC is in $2. */ | |
4796 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 4797 | return get_frame_register_signed (frame, 2); |
c906108c SS |
4798 | |
4799 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b JM |
4800 | before the jal instruction, this is effectively a call stub |
4801 | and the the target PC is in $2. Otherwise this is effectively | |
4802 | a return stub and the target PC is in $18. */ | |
c906108c SS |
4803 | else if (name[19] == 's' || name[19] == 'd') |
4804 | { | |
4805 | if (pc == start_addr) | |
4806 | { | |
4807 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
4808 | stub. Such a stub for a function bar might have a name |
4809 | like __fn_stub_bar, and might look like this: | |
4810 | mfc1 $4,$f13 | |
4811 | mfc1 $5,$f12 | |
4812 | mfc1 $6,$f15 | |
4813 | mfc1 $7,$f14 | |
4814 | la $1,bar (becomes a lui/addiu pair) | |
4815 | jr $1 | |
4816 | So scan down to the lui/addi and extract the target | |
4817 | address from those two instructions. */ | |
c906108c | 4818 | |
52f729a7 | 4819 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
d37cca3d | 4820 | ULONGEST inst; |
c906108c SS |
4821 | int i; |
4822 | ||
4823 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
4824 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
4825 | 0) | |
c906108c SS |
4826 | return target_pc; |
4827 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
4828 | && strcmp (name, "etext") != 0 | |
4829 | && strcmp (name, "_etext") != 0) | |
4830 | return target_pc; | |
4831 | ||
4832 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
4833 | The limit on the search is arbitrarily set to 20 |
4834 | instructions. FIXME. */ | |
95ac2dcf | 4835 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 4836 | { |
c5aa993b JM |
4837 | inst = mips_fetch_instruction (target_pc); |
4838 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ | |
4839 | pc = (inst << 16) & 0xffff0000; /* high word */ | |
4840 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ | |
4841 | return pc | (inst & 0xffff); /* low word */ | |
c906108c SS |
4842 | } |
4843 | ||
4844 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
4845 | return target_pc; | |
4846 | } | |
4847 | else | |
4848 | /* This is the 'return' part of a call stub. The return | |
4849 | address is in $r18. */ | |
52f729a7 | 4850 | return get_frame_register_signed (frame, 18); |
c906108c SS |
4851 | } |
4852 | } | |
c5aa993b | 4853 | return 0; /* not a stub */ |
c906108c SS |
4854 | } |
4855 | ||
a4b8ebc8 | 4856 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 4857 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
4858 | |
4859 | static int | |
4860 | mips_stab_reg_to_regnum (int num) | |
4861 | { | |
a4b8ebc8 | 4862 | int regnum; |
2f38ef89 | 4863 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4864 | regnum = num; |
2f38ef89 | 4865 | else if (num >= 38 && num < 70) |
56cea623 | 4866 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 38; |
040b99fd | 4867 | else if (num == 70) |
56cea623 | 4868 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4869 | else if (num == 71) |
56cea623 | 4870 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4871 | else |
a4b8ebc8 AC |
4872 | /* This will hopefully (eventually) provoke a warning. Should |
4873 | we be calling complaint() here? */ | |
f57d151a UW |
4874 | return gdbarch_num_regs (current_gdbarch) |
4875 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4876 | return gdbarch_num_regs (current_gdbarch) + regnum; | |
88c72b7d AC |
4877 | } |
4878 | ||
2f38ef89 | 4879 | |
a4b8ebc8 | 4880 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 4881 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
4882 | |
4883 | static int | |
2f38ef89 | 4884 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num) |
88c72b7d | 4885 | { |
a4b8ebc8 | 4886 | int regnum; |
2f38ef89 | 4887 | if (num >= 0 && num < 32) |
a4b8ebc8 | 4888 | regnum = num; |
2f38ef89 | 4889 | else if (num >= 32 && num < 64) |
56cea623 | 4890 | regnum = num + mips_regnum (current_gdbarch)->fp0 - 32; |
040b99fd | 4891 | else if (num == 64) |
56cea623 | 4892 | regnum = mips_regnum (current_gdbarch)->hi; |
040b99fd | 4893 | else if (num == 65) |
56cea623 | 4894 | regnum = mips_regnum (current_gdbarch)->lo; |
2f38ef89 | 4895 | else |
a4b8ebc8 AC |
4896 | /* This will hopefully (eventually) provoke a warning. Should we |
4897 | be calling complaint() here? */ | |
f57d151a UW |
4898 | return gdbarch_num_regs (current_gdbarch) |
4899 | + gdbarch_num_pseudo_regs (current_gdbarch); | |
4900 | return gdbarch_num_regs (current_gdbarch) + regnum; | |
a4b8ebc8 AC |
4901 | } |
4902 | ||
4903 | static int | |
4904 | mips_register_sim_regno (int regnum) | |
4905 | { | |
4906 | /* Only makes sense to supply raw registers. */ | |
f57d151a | 4907 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch)); |
a4b8ebc8 AC |
4908 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
4909 | decide if it is valid. Should instead define a standard sim/gdb | |
4910 | register numbering scheme. */ | |
c9f4d572 UW |
4911 | if (gdbarch_register_name (current_gdbarch, |
4912 | gdbarch_num_regs | |
4913 | (current_gdbarch) + regnum) != NULL | |
4914 | && gdbarch_register_name (current_gdbarch, | |
4915 | gdbarch_num_regs | |
4916 | (current_gdbarch) + regnum)[0] != '\0') | |
a4b8ebc8 AC |
4917 | return regnum; |
4918 | else | |
6d82d43b | 4919 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
4920 | } |
4921 | ||
2f38ef89 | 4922 | |
4844f454 CV |
4923 | /* Convert an integer into an address. Extracting the value signed |
4924 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
4925 | |
4926 | static CORE_ADDR | |
79dd2d24 | 4927 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 4928 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 4929 | { |
4844f454 | 4930 | return (CORE_ADDR) extract_signed_integer (buf, TYPE_LENGTH (type)); |
fc0c74b1 AC |
4931 | } |
4932 | ||
82e91389 DJ |
4933 | /* Dummy virtual frame pointer method. This is no more or less accurate |
4934 | than most other architectures; we just need to be explicit about it, | |
4935 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
4936 | an assertion failure. */ | |
4937 | ||
4938 | static void | |
4939 | mips_virtual_frame_pointer (CORE_ADDR pc, int *reg, LONGEST *offset) | |
4940 | { | |
4941 | *reg = MIPS_SP_REGNUM; | |
4942 | *offset = 0; | |
4943 | } | |
4944 | ||
caaa3122 DJ |
4945 | static void |
4946 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
4947 | { | |
4948 | enum mips_abi *abip = (enum mips_abi *) obj; | |
4949 | const char *name = bfd_get_section_name (abfd, sect); | |
4950 | ||
4951 | if (*abip != MIPS_ABI_UNKNOWN) | |
4952 | return; | |
4953 | ||
4954 | if (strncmp (name, ".mdebug.", 8) != 0) | |
4955 | return; | |
4956 | ||
4957 | if (strcmp (name, ".mdebug.abi32") == 0) | |
4958 | *abip = MIPS_ABI_O32; | |
4959 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
4960 | *abip = MIPS_ABI_N32; | |
62a49b2c | 4961 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 4962 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
4963 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
4964 | *abip = MIPS_ABI_O64; | |
4965 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
4966 | *abip = MIPS_ABI_EABI32; | |
4967 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
4968 | *abip = MIPS_ABI_EABI64; | |
4969 | else | |
8a3fe4f8 | 4970 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
4971 | } |
4972 | ||
22e47e37 FF |
4973 | static void |
4974 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
4975 | { | |
4976 | int *lbp = (int *) obj; | |
4977 | const char *name = bfd_get_section_name (abfd, sect); | |
4978 | ||
4979 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
4980 | *lbp = 32; | |
4981 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
4982 | *lbp = 64; | |
4983 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
4984 | warning (_("unrecognized .gcc_compiled_longXX")); | |
4985 | } | |
4986 | ||
2e4ebe70 DJ |
4987 | static enum mips_abi |
4988 | global_mips_abi (void) | |
4989 | { | |
4990 | int i; | |
4991 | ||
4992 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
4993 | if (mips_abi_strings[i] == mips_abi_string) | |
4994 | return (enum mips_abi) i; | |
4995 | ||
e2e0b3e5 | 4996 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
4997 | } |
4998 | ||
29709017 DJ |
4999 | static void |
5000 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
5001 | { | |
29709017 DJ |
5002 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
5003 | assume that's what we've got. */ | |
4eb0ad19 DJ |
5004 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5005 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5006 | |
5007 | /* If the size matches the full set of registers GDB traditionally | |
5008 | knows about, including floating point, for either 32-bit or | |
5009 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5010 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5011 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5012 | |
5013 | /* Otherwise we don't have a useful guess. */ | |
5014 | } | |
5015 | ||
f8b73d13 DJ |
5016 | static struct value * |
5017 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5018 | { | |
5019 | const int *reg_p = baton; | |
5020 | return value_of_register (*reg_p, frame); | |
5021 | } | |
5022 | ||
c2d11a7d | 5023 | static struct gdbarch * |
6d82d43b | 5024 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5025 | { |
c2d11a7d JM |
5026 | struct gdbarch *gdbarch; |
5027 | struct gdbarch_tdep *tdep; | |
5028 | int elf_flags; | |
2e4ebe70 | 5029 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5030 | int i, num_regs; |
8d5838b5 | 5031 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5032 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5033 | int elf_fpu_type = 0; |
f8b73d13 DJ |
5034 | |
5035 | /* Check any target description for validity. */ | |
5036 | if (tdesc_has_registers (info.target_desc)) | |
5037 | { | |
5038 | static const char *const mips_gprs[] = { | |
5039 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5040 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
5041 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
5042 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
5043 | }; | |
5044 | static const char *const mips_fprs[] = { | |
5045 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
5046 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
5047 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
5048 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
5049 | }; | |
5050 | ||
5051 | const struct tdesc_feature *feature; | |
5052 | int valid_p; | |
5053 | ||
5054 | feature = tdesc_find_feature (info.target_desc, | |
5055 | "org.gnu.gdb.mips.cpu"); | |
5056 | if (feature == NULL) | |
5057 | return NULL; | |
5058 | ||
5059 | tdesc_data = tdesc_data_alloc (); | |
5060 | ||
5061 | valid_p = 1; | |
5062 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
5063 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
5064 | mips_gprs[i]); | |
5065 | ||
5066 | ||
5067 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5068 | MIPS_EMBED_LO_REGNUM, "lo"); | |
5069 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5070 | MIPS_EMBED_HI_REGNUM, "hi"); | |
5071 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5072 | MIPS_EMBED_PC_REGNUM, "pc"); | |
5073 | ||
5074 | if (!valid_p) | |
5075 | { | |
5076 | tdesc_data_cleanup (tdesc_data); | |
5077 | return NULL; | |
5078 | } | |
5079 | ||
5080 | feature = tdesc_find_feature (info.target_desc, | |
5081 | "org.gnu.gdb.mips.cp0"); | |
5082 | if (feature == NULL) | |
5083 | { | |
5084 | tdesc_data_cleanup (tdesc_data); | |
5085 | return NULL; | |
5086 | } | |
5087 | ||
5088 | valid_p = 1; | |
5089 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5090 | MIPS_EMBED_BADVADDR_REGNUM, | |
5091 | "badvaddr"); | |
5092 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5093 | MIPS_PS_REGNUM, "status"); | |
5094 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5095 | MIPS_EMBED_CAUSE_REGNUM, "cause"); | |
5096 | ||
5097 | if (!valid_p) | |
5098 | { | |
5099 | tdesc_data_cleanup (tdesc_data); | |
5100 | return NULL; | |
5101 | } | |
5102 | ||
5103 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
5104 | backend is not prepared for that, though. */ | |
5105 | feature = tdesc_find_feature (info.target_desc, | |
5106 | "org.gnu.gdb.mips.fpu"); | |
5107 | if (feature == NULL) | |
5108 | { | |
5109 | tdesc_data_cleanup (tdesc_data); | |
5110 | return NULL; | |
5111 | } | |
5112 | ||
5113 | valid_p = 1; | |
5114 | for (i = 0; i < 32; i++) | |
5115 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5116 | i + MIPS_EMBED_FP0_REGNUM, | |
5117 | mips_fprs[i]); | |
5118 | ||
5119 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5120 | MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | |
5121 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5122 | MIPS_EMBED_FP0_REGNUM + 33, "fir"); | |
5123 | ||
5124 | if (!valid_p) | |
5125 | { | |
5126 | tdesc_data_cleanup (tdesc_data); | |
5127 | return NULL; | |
5128 | } | |
5129 | ||
5130 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
5131 | when only 32-bit registers are provided. */ | |
5132 | } | |
c2d11a7d | 5133 | |
ec03c1ac AC |
5134 | /* First of all, extract the elf_flags, if available. */ |
5135 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5136 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
5137 | else if (arches != NULL) |
5138 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
5139 | else |
5140 | elf_flags = 0; | |
5141 | if (gdbarch_debug) | |
5142 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5143 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 5144 | |
102182a9 | 5145 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
5146 | switch ((elf_flags & EF_MIPS_ABI)) |
5147 | { | |
5148 | case E_MIPS_ABI_O32: | |
ec03c1ac | 5149 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
5150 | break; |
5151 | case E_MIPS_ABI_O64: | |
ec03c1ac | 5152 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
5153 | break; |
5154 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 5155 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
5156 | break; |
5157 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 5158 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
5159 | break; |
5160 | default: | |
acdb74a0 | 5161 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 5162 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 5163 | else |
ec03c1ac | 5164 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
5165 | break; |
5166 | } | |
acdb74a0 | 5167 | |
caaa3122 | 5168 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
5169 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
5170 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 5171 | |
dc305454 | 5172 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
5173 | MIPS architecture (if there is one). */ |
5174 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
5175 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 5176 | |
32a6503c | 5177 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 5178 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
5179 | && info.bfd_arch_info != NULL |
5180 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5181 | { | |
5182 | switch (info.bfd_arch_info->mach) | |
5183 | { | |
5184 | case bfd_mach_mips3900: | |
ec03c1ac | 5185 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
5186 | break; |
5187 | case bfd_mach_mips4100: | |
5188 | case bfd_mach_mips5000: | |
ec03c1ac | 5189 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 5190 | break; |
1d06468c EZ |
5191 | case bfd_mach_mips8000: |
5192 | case bfd_mach_mips10000: | |
32a6503c KB |
5193 | /* On Irix, ELF64 executables use the N64 ABI. The |
5194 | pseudo-sections which describe the ABI aren't present | |
5195 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
5196 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
5197 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 5198 | found_abi = MIPS_ABI_N64; |
28d169de | 5199 | else |
ec03c1ac | 5200 | found_abi = MIPS_ABI_N32; |
1d06468c | 5201 | break; |
bf64bfd6 AC |
5202 | } |
5203 | } | |
2e4ebe70 | 5204 | |
26c53e50 DJ |
5205 | /* Default 64-bit objects to N64 instead of O32. */ |
5206 | if (found_abi == MIPS_ABI_UNKNOWN | |
5207 | && info.abfd != NULL | |
5208 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
5209 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5210 | found_abi = MIPS_ABI_N64; | |
5211 | ||
ec03c1ac AC |
5212 | if (gdbarch_debug) |
5213 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
5214 | found_abi); | |
5215 | ||
5216 | /* What has the user specified from the command line? */ | |
5217 | wanted_abi = global_mips_abi (); | |
5218 | if (gdbarch_debug) | |
5219 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
5220 | wanted_abi); | |
2e4ebe70 DJ |
5221 | |
5222 | /* Now that we have found what the ABI for this binary would be, | |
5223 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
5224 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
5225 | mips_abi = wanted_abi; | |
ec03c1ac AC |
5226 | else if (found_abi != MIPS_ABI_UNKNOWN) |
5227 | mips_abi = found_abi; | |
5228 | else | |
5229 | mips_abi = MIPS_ABI_O32; | |
5230 | if (gdbarch_debug) | |
5231 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
5232 | mips_abi); | |
2e4ebe70 | 5233 | |
ec03c1ac | 5234 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 5235 | if (gdbarch_debug) |
ec03c1ac AC |
5236 | fprintf_unfiltered (gdb_stdlog, |
5237 | "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n", | |
5238 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 5239 | |
8d5838b5 | 5240 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
5241 | #ifdef HAVE_ELF |
5242 | if (info.abfd | |
5243 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
5244 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
5245 | Tag_GNU_MIPS_ABI_FP); | |
5246 | #endif /* HAVE_ELF */ | |
5247 | ||
8d5838b5 AC |
5248 | if (!mips_fpu_type_auto) |
5249 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
5250 | else if (elf_fpu_type != 0) |
5251 | { | |
5252 | switch (elf_fpu_type) | |
5253 | { | |
5254 | case 1: | |
5255 | fpu_type = MIPS_FPU_DOUBLE; | |
5256 | break; | |
5257 | case 2: | |
5258 | fpu_type = MIPS_FPU_SINGLE; | |
5259 | break; | |
5260 | case 3: | |
5261 | default: | |
5262 | /* Soft float or unknown. */ | |
5263 | fpu_type = MIPS_FPU_NONE; | |
5264 | break; | |
5265 | } | |
5266 | } | |
8d5838b5 AC |
5267 | else if (info.bfd_arch_info != NULL |
5268 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
5269 | switch (info.bfd_arch_info->mach) | |
5270 | { | |
5271 | case bfd_mach_mips3900: | |
5272 | case bfd_mach_mips4100: | |
5273 | case bfd_mach_mips4111: | |
a9d61c86 | 5274 | case bfd_mach_mips4120: |
8d5838b5 AC |
5275 | fpu_type = MIPS_FPU_NONE; |
5276 | break; | |
5277 | case bfd_mach_mips4650: | |
5278 | fpu_type = MIPS_FPU_SINGLE; | |
5279 | break; | |
5280 | default: | |
5281 | fpu_type = MIPS_FPU_DOUBLE; | |
5282 | break; | |
5283 | } | |
5284 | else if (arches != NULL) | |
5285 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
5286 | else | |
5287 | fpu_type = MIPS_FPU_DOUBLE; | |
5288 | if (gdbarch_debug) | |
5289 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 5290 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 5291 | |
29709017 DJ |
5292 | /* Check for blatant incompatibilities. */ |
5293 | ||
5294 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
5295 | ABI. */ | |
5296 | if (info.target_desc | |
5297 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
5298 | && mips_abi != MIPS_ABI_EABI32 | |
5299 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
5300 | { |
5301 | if (tdesc_data != NULL) | |
5302 | tdesc_data_cleanup (tdesc_data); | |
5303 | return NULL; | |
5304 | } | |
29709017 | 5305 | |
c2d11a7d JM |
5306 | /* try to find a pre-existing architecture */ |
5307 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
5308 | arches != NULL; | |
5309 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
5310 | { | |
5311 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 5312 | using. */ |
9103eae0 | 5313 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 5314 | continue; |
9103eae0 | 5315 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 5316 | continue; |
719ec221 AC |
5317 | /* Need to be pedantic about which register virtual size is |
5318 | used. */ | |
5319 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
5320 | != mips64_transfers_32bit_regs_p) | |
5321 | continue; | |
8d5838b5 AC |
5322 | /* Be pedantic about which FPU is selected. */ |
5323 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
5324 | continue; | |
f8b73d13 DJ |
5325 | |
5326 | if (tdesc_data != NULL) | |
5327 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 5328 | return arches->gdbarch; |
c2d11a7d JM |
5329 | } |
5330 | ||
102182a9 | 5331 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
5332 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5333 | gdbarch = gdbarch_alloc (&info, tdep); | |
5334 | tdep->elf_flags = elf_flags; | |
719ec221 | 5335 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
5336 | tdep->found_abi = found_abi; |
5337 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 5338 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
5339 | tdep->register_size_valid_p = 0; |
5340 | tdep->register_size = 0; | |
5341 | ||
5342 | if (info.target_desc) | |
5343 | { | |
5344 | /* Some useful properties can be inferred from the target. */ | |
5345 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
5346 | { | |
5347 | tdep->register_size_valid_p = 1; | |
5348 | tdep->register_size = 4; | |
5349 | } | |
5350 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
5351 | { | |
5352 | tdep->register_size_valid_p = 1; | |
5353 | tdep->register_size = 8; | |
5354 | } | |
5355 | } | |
c2d11a7d | 5356 | |
102182a9 | 5357 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
5358 | set_gdbarch_short_bit (gdbarch, 16); |
5359 | set_gdbarch_int_bit (gdbarch, 32); | |
5360 | set_gdbarch_float_bit (gdbarch, 32); | |
5361 | set_gdbarch_double_bit (gdbarch, 64); | |
5362 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
5363 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
5364 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
5365 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 5366 | |
6d82d43b | 5367 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
5368 | mips_elf_make_msymbol_special); |
5369 | ||
16e109ca | 5370 | /* Fill in the OS dependant register numbers and names. */ |
56cea623 | 5371 | { |
16e109ca | 5372 | const char **reg_names; |
56cea623 AC |
5373 | struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, |
5374 | struct mips_regnum); | |
f8b73d13 DJ |
5375 | if (tdesc_has_registers (info.target_desc)) |
5376 | { | |
5377 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5378 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5379 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5380 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5381 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5382 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5383 | regnum->fp_control_status = 70; | |
5384 | regnum->fp_implementation_revision = 71; | |
5385 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
5386 | reg_names = NULL; | |
5387 | } | |
5388 | else if (info.osabi == GDB_OSABI_IRIX) | |
56cea623 AC |
5389 | { |
5390 | regnum->fp0 = 32; | |
5391 | regnum->pc = 64; | |
5392 | regnum->cause = 65; | |
5393 | regnum->badvaddr = 66; | |
5394 | regnum->hi = 67; | |
5395 | regnum->lo = 68; | |
5396 | regnum->fp_control_status = 69; | |
5397 | regnum->fp_implementation_revision = 70; | |
5398 | num_regs = 71; | |
16e109ca | 5399 | reg_names = mips_irix_reg_names; |
56cea623 AC |
5400 | } |
5401 | else | |
5402 | { | |
5403 | regnum->lo = MIPS_EMBED_LO_REGNUM; | |
5404 | regnum->hi = MIPS_EMBED_HI_REGNUM; | |
5405 | regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
5406 | regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
5407 | regnum->pc = MIPS_EMBED_PC_REGNUM; | |
5408 | regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
5409 | regnum->fp_control_status = 70; | |
5410 | regnum->fp_implementation_revision = 71; | |
5411 | num_regs = 90; | |
16e109ca AC |
5412 | if (info.bfd_arch_info != NULL |
5413 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
5414 | reg_names = mips_tx39_reg_names; | |
5415 | else | |
5416 | reg_names = mips_generic_reg_names; | |
56cea623 | 5417 | } |
3e8c568d | 5418 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been |
56cea623 | 5419 | replaced by read_pc? */ |
f10683bb MH |
5420 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
5421 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
56cea623 AC |
5422 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5423 | set_gdbarch_num_regs (gdbarch, num_regs); | |
5424 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
16e109ca | 5425 | set_gdbarch_register_name (gdbarch, mips_register_name); |
82e91389 | 5426 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
16e109ca AC |
5427 | tdep->mips_processor_reg_names = reg_names; |
5428 | tdep->regnum = regnum; | |
56cea623 | 5429 | } |
fe29b929 | 5430 | |
0dadbba0 | 5431 | switch (mips_abi) |
c2d11a7d | 5432 | { |
0dadbba0 | 5433 | case MIPS_ABI_O32: |
25ab4790 | 5434 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 5435 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 5436 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5437 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 5438 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5439 | set_gdbarch_long_bit (gdbarch, 32); |
5440 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5441 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5442 | break; | |
0dadbba0 | 5443 | case MIPS_ABI_O64: |
25ab4790 | 5444 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 5445 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 5446 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 5447 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 5448 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5449 | set_gdbarch_long_bit (gdbarch, 32); |
5450 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5451 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5452 | break; | |
0dadbba0 | 5453 | case MIPS_ABI_EABI32: |
25ab4790 | 5454 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5455 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5456 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5457 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5458 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5459 | set_gdbarch_long_bit (gdbarch, 32); |
5460 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5461 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5462 | break; | |
0dadbba0 | 5463 | case MIPS_ABI_EABI64: |
25ab4790 | 5464 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 5465 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 5466 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5467 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5468 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
5469 | set_gdbarch_long_bit (gdbarch, 64); |
5470 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5471 | set_gdbarch_long_long_bit (gdbarch, 64); | |
5472 | break; | |
0dadbba0 | 5473 | case MIPS_ABI_N32: |
25ab4790 | 5474 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5475 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5476 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5477 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 5478 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
5479 | set_gdbarch_long_bit (gdbarch, 32); |
5480 | set_gdbarch_ptr_bit (gdbarch, 32); | |
5481 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5482 | set_gdbarch_long_double_bit (gdbarch, 128); |
8da61cc4 | 5483 | set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long); |
28d169de KB |
5484 | break; |
5485 | case MIPS_ABI_N64: | |
25ab4790 | 5486 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 5487 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 5488 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 5489 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
5490 | tdep->default_mask_address_p = 0; |
5491 | set_gdbarch_long_bit (gdbarch, 64); | |
5492 | set_gdbarch_ptr_bit (gdbarch, 64); | |
5493 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 5494 | set_gdbarch_long_double_bit (gdbarch, 128); |
8da61cc4 | 5495 | set_gdbarch_long_double_format (gdbarch, floatformats_n32n64_long); |
0dadbba0 | 5496 | break; |
c2d11a7d | 5497 | default: |
e2e0b3e5 | 5498 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
5499 | } |
5500 | ||
22e47e37 FF |
5501 | /* GCC creates a pseudo-section whose name specifies the size of |
5502 | longs, since -mlong32 or -mlong64 may be used independent of | |
5503 | other options. How those options affect pointer sizes is ABI and | |
5504 | architecture dependent, so use them to override the default sizes | |
5505 | set by the ABI. This table shows the relationship between ABI, | |
5506 | -mlongXX, and size of pointers: | |
5507 | ||
5508 | ABI -mlongXX ptr bits | |
5509 | --- -------- -------- | |
5510 | o32 32 32 | |
5511 | o32 64 32 | |
5512 | n32 32 32 | |
5513 | n32 64 64 | |
5514 | o64 32 32 | |
5515 | o64 64 64 | |
5516 | n64 32 32 | |
5517 | n64 64 64 | |
5518 | eabi32 32 32 | |
5519 | eabi32 64 32 | |
5520 | eabi64 32 32 | |
5521 | eabi64 64 64 | |
5522 | ||
5523 | Note that for o32 and eabi32, pointers are always 32 bits | |
5524 | regardless of any -mlongXX option. For all others, pointers and | |
5525 | longs are the same, as set by -mlongXX or set by defaults. | |
5526 | */ | |
5527 | ||
5528 | if (info.abfd != NULL) | |
5529 | { | |
5530 | int long_bit = 0; | |
5531 | ||
5532 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
5533 | if (long_bit) | |
5534 | { | |
5535 | set_gdbarch_long_bit (gdbarch, long_bit); | |
5536 | switch (mips_abi) | |
5537 | { | |
5538 | case MIPS_ABI_O32: | |
5539 | case MIPS_ABI_EABI32: | |
5540 | break; | |
5541 | case MIPS_ABI_N32: | |
5542 | case MIPS_ABI_O64: | |
5543 | case MIPS_ABI_N64: | |
5544 | case MIPS_ABI_EABI64: | |
5545 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
5546 | break; | |
5547 | default: | |
5548 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
5549 | } | |
5550 | } | |
5551 | } | |
5552 | ||
a5ea2558 AC |
5553 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
5554 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
5555 | comment: | |
5556 | ||
5557 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
5558 | flag in object files because to do so would make it impossible to | |
102182a9 | 5559 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 5560 | unnecessarily restrictive. |
361d1df0 | 5561 | |
a5ea2558 AC |
5562 | We could solve this problem by adding "-gp32" multilibs to gcc, |
5563 | but to set this flag before gcc is built with such multilibs will | |
5564 | break too many systems.'' | |
5565 | ||
5566 | But even more unhelpfully, the default linker output target for | |
5567 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
5568 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 5569 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
5570 | this flag to detect 32-bit mode would do the wrong thing given |
5571 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 5572 | as 32-bit programs by default. */ |
a5ea2558 | 5573 | |
6c997a34 | 5574 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 5575 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 5576 | |
102182a9 MS |
5577 | /* Add/remove bits from an address. The MIPS needs be careful to |
5578 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
5579 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
5580 | ||
58dfe9ff AC |
5581 | /* Unwind the frame. */ |
5582 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 5583 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
edfae063 | 5584 | set_gdbarch_unwind_dummy_id (gdbarch, mips_unwind_dummy_id); |
10312cc4 | 5585 | |
102182a9 | 5586 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 5587 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
5588 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
5589 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5590 | set_gdbarch_dwarf_reg_to_regnum (gdbarch, | |
5591 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
5592 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | |
5593 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 5594 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 5595 | |
c2d11a7d JM |
5596 | /* MIPS version of CALL_DUMMY */ |
5597 | ||
9710e734 AC |
5598 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
5599 | replaced by a command, and all targets will default to on stack | |
5600 | (regardless of the stack's execute status). */ | |
5601 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 5602 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 5603 | |
87783b8b AC |
5604 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
5605 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
5606 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
5607 | ||
f7b9e9fc AC |
5608 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
5609 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
f7b9e9fc AC |
5610 | |
5611 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 5612 | |
97ab0fdd MR |
5613 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
5614 | ||
fc0c74b1 AC |
5615 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
5616 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
5617 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 5618 | |
a4b8ebc8 | 5619 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 5620 | |
e11c53d2 | 5621 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 5622 | |
e5ab0dce AC |
5623 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
5624 | ||
3a3bc038 AC |
5625 | /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT, |
5626 | HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT | |
5627 | need to all be folded into the target vector. Since they are | |
5628 | being used as guards for STOPPED_BY_WATCHPOINT, why not have | |
5629 | STOPPED_BY_WATCHPOINT return the type of watchpoint that the code | |
5630 | is sitting on? */ | |
5631 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
5632 | ||
e7d6a6d2 | 5633 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 5634 | |
3352ef37 AC |
5635 | set_gdbarch_single_step_through_delay (gdbarch, mips_single_step_through_delay); |
5636 | ||
0d5de010 DJ |
5637 | /* Virtual tables. */ |
5638 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
5639 | ||
29709017 DJ |
5640 | mips_register_g_packet_guesses (gdbarch); |
5641 | ||
6de918a6 | 5642 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 5643 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 5644 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 5645 | |
5792a79b | 5646 | /* Unwind the frame. */ |
2bd0c3d7 | 5647 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
eec63939 | 5648 | frame_unwind_append_sniffer (gdbarch, mips_stub_frame_sniffer); |
45c9dd44 AC |
5649 | frame_unwind_append_sniffer (gdbarch, mips_insn16_frame_sniffer); |
5650 | frame_unwind_append_sniffer (gdbarch, mips_insn32_frame_sniffer); | |
2bd0c3d7 | 5651 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 5652 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
5653 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
5654 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 5655 | |
f8b73d13 DJ |
5656 | if (tdesc_data) |
5657 | { | |
5658 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
5659 | tdesc_use_registers (gdbarch, tdesc_data); | |
5660 | ||
5661 | /* Override the normal target description methods to handle our | |
5662 | dual real and pseudo registers. */ | |
5663 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
5664 | set_gdbarch_register_reggroup_p (gdbarch, mips_tdesc_register_reggroup_p); | |
5665 | ||
5666 | num_regs = gdbarch_num_regs (gdbarch); | |
5667 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
5668 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
5669 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
5670 | } | |
5671 | ||
5672 | /* Add ABI-specific aliases for the registers. */ | |
5673 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
5674 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
5675 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
5676 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
5677 | else | |
5678 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
5679 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
5680 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
5681 | ||
5682 | /* Add some other standard aliases. */ | |
5683 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
5684 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
5685 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
5686 | ||
4b9b3959 AC |
5687 | return gdbarch; |
5688 | } | |
5689 | ||
2e4ebe70 | 5690 | static void |
6d82d43b | 5691 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
5692 | { |
5693 | struct gdbarch_info info; | |
5694 | ||
5695 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
5696 | mips_gdbarch_init will take care of the rest. */ | |
5697 | gdbarch_info_init (&info); | |
5698 | gdbarch_update_p (info); | |
5699 | } | |
5700 | ||
ad188201 KB |
5701 | /* Print out which MIPS ABI is in use. */ |
5702 | ||
5703 | static void | |
1f8ca57c JB |
5704 | show_mips_abi (struct ui_file *file, |
5705 | int from_tty, | |
5706 | struct cmd_list_element *ignored_cmd, | |
5707 | const char *ignored_value) | |
ad188201 KB |
5708 | { |
5709 | if (gdbarch_bfd_arch_info (current_gdbarch)->arch != bfd_arch_mips) | |
1f8ca57c JB |
5710 | fprintf_filtered |
5711 | (file, | |
5712 | "The MIPS ABI is unknown because the current architecture " | |
5713 | "is not MIPS.\n"); | |
ad188201 KB |
5714 | else |
5715 | { | |
5716 | enum mips_abi global_abi = global_mips_abi (); | |
5717 | enum mips_abi actual_abi = mips_abi (current_gdbarch); | |
5718 | const char *actual_abi_str = mips_abi_strings[actual_abi]; | |
5719 | ||
5720 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
5721 | fprintf_filtered |
5722 | (file, | |
5723 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 5724 | actual_abi_str); |
ad188201 | 5725 | else if (global_abi == actual_abi) |
1f8ca57c JB |
5726 | fprintf_filtered |
5727 | (file, | |
5728 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 5729 | actual_abi_str); |
ad188201 KB |
5730 | else |
5731 | { | |
5732 | /* Probably shouldn't happen... */ | |
1f8ca57c JB |
5733 | fprintf_filtered |
5734 | (file, | |
5735 | "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n", | |
6d82d43b | 5736 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
5737 | } |
5738 | } | |
5739 | } | |
5740 | ||
4b9b3959 AC |
5741 | static void |
5742 | mips_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
5743 | { | |
5744 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
5745 | if (tdep != NULL) | |
c2d11a7d | 5746 | { |
acdb74a0 AC |
5747 | int ef_mips_arch; |
5748 | int ef_mips_32bitmode; | |
f49e4e6d | 5749 | /* Determine the ISA. */ |
acdb74a0 AC |
5750 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
5751 | { | |
5752 | case E_MIPS_ARCH_1: | |
5753 | ef_mips_arch = 1; | |
5754 | break; | |
5755 | case E_MIPS_ARCH_2: | |
5756 | ef_mips_arch = 2; | |
5757 | break; | |
5758 | case E_MIPS_ARCH_3: | |
5759 | ef_mips_arch = 3; | |
5760 | break; | |
5761 | case E_MIPS_ARCH_4: | |
93d56215 | 5762 | ef_mips_arch = 4; |
acdb74a0 AC |
5763 | break; |
5764 | default: | |
93d56215 | 5765 | ef_mips_arch = 0; |
acdb74a0 AC |
5766 | break; |
5767 | } | |
f49e4e6d | 5768 | /* Determine the size of a pointer. */ |
acdb74a0 | 5769 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
5770 | fprintf_unfiltered (file, |
5771 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 5772 | tdep->elf_flags); |
4b9b3959 | 5773 | fprintf_unfiltered (file, |
acdb74a0 AC |
5774 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
5775 | ef_mips_32bitmode); | |
5776 | fprintf_unfiltered (file, | |
5777 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
5778 | ef_mips_arch); | |
5779 | fprintf_unfiltered (file, | |
5780 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 5781 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b AC |
5782 | fprintf_unfiltered (file, |
5783 | "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 5784 | mips_mask_address_p (tdep), |
4014092b | 5785 | tdep->default_mask_address_p); |
c2d11a7d | 5786 | } |
4b9b3959 AC |
5787 | fprintf_unfiltered (file, |
5788 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
5789 | MIPS_DEFAULT_FPU_TYPE, | |
5790 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5791 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5792 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5793 | : "???")); | |
6d82d43b | 5794 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI); |
4b9b3959 AC |
5795 | fprintf_unfiltered (file, |
5796 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
5797 | MIPS_FPU_TYPE, | |
5798 | (MIPS_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
5799 | : MIPS_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
5800 | : MIPS_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
5801 | : "???")); | |
c2d11a7d JM |
5802 | } |
5803 | ||
6d82d43b | 5804 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 5805 | |
c906108c | 5806 | void |
acdb74a0 | 5807 | _initialize_mips_tdep (void) |
c906108c SS |
5808 | { |
5809 | static struct cmd_list_element *mipsfpulist = NULL; | |
5810 | struct cmd_list_element *c; | |
5811 | ||
6d82d43b | 5812 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
5813 | if (MIPS_ABI_LAST + 1 |
5814 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 5815 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 5816 | |
4b9b3959 | 5817 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 5818 | |
8d5f9dcb DJ |
5819 | mips_pdr_data = register_objfile_data (); |
5820 | ||
4eb0ad19 DJ |
5821 | /* Create feature sets with the appropriate properties. The values |
5822 | are not important. */ | |
5823 | mips_tdesc_gp32 = allocate_target_description (); | |
5824 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
5825 | ||
5826 | mips_tdesc_gp64 = allocate_target_description (); | |
5827 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
5828 | ||
a5ea2558 AC |
5829 | /* Add root prefix command for all "set mips"/"show mips" commands */ |
5830 | add_prefix_cmd ("mips", no_class, set_mips_command, | |
1bedd215 | 5831 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5832 | &setmipscmdlist, "set mips ", 0, &setlist); |
5833 | ||
5834 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 5835 | _("Various MIPS specific commands."), |
a5ea2558 AC |
5836 | &showmipscmdlist, "show mips ", 0, &showlist); |
5837 | ||
2e4ebe70 | 5838 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
5839 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
5840 | &mips_abi_string, _("\ | |
5841 | Set the MIPS ABI used by this program."), _("\ | |
5842 | Show the MIPS ABI used by this program."), _("\ | |
5843 | This option can be set to one of:\n\ | |
5844 | auto - the default ABI associated with the current binary\n\ | |
5845 | o32\n\ | |
5846 | o64\n\ | |
5847 | n32\n\ | |
5848 | n64\n\ | |
5849 | eabi32\n\ | |
5850 | eabi64"), | |
5851 | mips_abi_update, | |
5852 | show_mips_abi, | |
5853 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 5854 | |
c906108c SS |
5855 | /* Let the user turn off floating point and set the fence post for |
5856 | heuristic_proc_start. */ | |
5857 | ||
5858 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 5859 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
5860 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
5861 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 5862 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
5863 | &mipsfpulist); |
5864 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 5865 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
5866 | &mipsfpulist); |
5867 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
5868 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
5869 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
5870 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 5871 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
5872 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
5873 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
5874 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
5875 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 5876 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
5877 | &mipsfpulist); |
5878 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 5879 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
5880 | &showlist); |
5881 | ||
c906108c SS |
5882 | /* We really would like to have both "0" and "unlimited" work, but |
5883 | command.c doesn't deal with that. So make it a var_zinteger | |
5884 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 5885 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
5886 | &heuristic_fence_post, _("\ |
5887 | Set the distance searched for the start of a function."), _("\ | |
5888 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
5889 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
5890 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 5891 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 5892 | reinit_frame_cache_sfunc, |
7915a72c | 5893 | NULL, /* FIXME: i18n: The distance searched for the start of a function is %s. */ |
6bcadd06 | 5894 | &setlist, &showlist); |
c906108c SS |
5895 | |
5896 | /* Allow the user to control whether the upper bits of 64-bit | |
5897 | addresses should be zeroed. */ | |
7915a72c AC |
5898 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
5899 | &mask_address_var, _("\ | |
5900 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
5901 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
e9e68a56 | 5902 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\ |
7915a72c | 5903 | allow GDB to determine the correct value."), |
08546159 AC |
5904 | NULL, show_mask_address, |
5905 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
5906 | |
5907 | /* Allow the user to control the size of 32 bit registers within the | |
5908 | raw remote packet. */ | |
b3f42336 | 5909 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
5910 | &mips64_transfers_32bit_regs_p, _("\ |
5911 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5912 | _("\ | |
5913 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
5914 | _("\ | |
719ec221 AC |
5915 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
5916 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 5917 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 5918 | set_mips64_transfers_32bit_regs, |
7915a72c | 5919 | NULL, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */ |
7915a72c | 5920 | &setlist, &showlist); |
9ace0497 AC |
5921 | |
5922 | /* Debug this files internals. */ | |
6bcadd06 | 5923 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
5924 | &mips_debug, _("\ |
5925 | Set mips debugging."), _("\ | |
5926 | Show mips debugging."), _("\ | |
5927 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 5928 | NULL, |
7915a72c | 5929 | NULL, /* FIXME: i18n: Mips debugging is currently %s. */ |
6bcadd06 | 5930 | &setdebuglist, &showdebuglist); |
c906108c | 5931 | } |