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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
0b302171 | 3 | Copyright (C) 1988-2012 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "gdb_string.h" | |
5e2e9765 | 25 | #include "gdb_assert.h" |
c906108c SS |
26 | #include "frame.h" |
27 | #include "inferior.h" | |
28 | #include "symtab.h" | |
29 | #include "value.h" | |
30 | #include "gdbcmd.h" | |
31 | #include "language.h" | |
32 | #include "gdbcore.h" | |
33 | #include "symfile.h" | |
34 | #include "objfiles.h" | |
35 | #include "gdbtypes.h" | |
36 | #include "target.h" | |
28d069e6 | 37 | #include "arch-utils.h" |
4e052eda | 38 | #include "regcache.h" |
70f80edf | 39 | #include "osabi.h" |
d1973055 | 40 | #include "mips-tdep.h" |
fe898f56 | 41 | #include "block.h" |
a4b8ebc8 | 42 | #include "reggroups.h" |
c906108c | 43 | #include "opcode/mips.h" |
c2d11a7d JM |
44 | #include "elf/mips.h" |
45 | #include "elf-bfd.h" | |
2475bac3 | 46 | #include "symcat.h" |
a4b8ebc8 | 47 | #include "sim-regno.h" |
a89aa300 | 48 | #include "dis-asm.h" |
edfae063 AC |
49 | #include "frame-unwind.h" |
50 | #include "frame-base.h" | |
51 | #include "trad-frame.h" | |
7d9b040b | 52 | #include "infcall.h" |
fed7ba43 | 53 | #include "floatformat.h" |
29709017 DJ |
54 | #include "remote.h" |
55 | #include "target-descriptions.h" | |
2bd0c3d7 | 56 | #include "dwarf2-frame.h" |
f8b73d13 | 57 | #include "user-regs.h" |
79a45b7d | 58 | #include "valprint.h" |
175ff332 | 59 | #include "ax.h" |
c906108c | 60 | |
8d5f9dcb DJ |
61 | static const struct objfile_data *mips_pdr_data; |
62 | ||
5bbcb741 | 63 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 64 | |
24e05951 | 65 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
66 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
67 | #define ST0_FR (1 << 26) | |
68 | ||
b0069a17 AC |
69 | /* The sizes of floating point registers. */ |
70 | ||
71 | enum | |
72 | { | |
73 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
74 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
75 | }; | |
76 | ||
1a69e1e4 DJ |
77 | enum |
78 | { | |
79 | MIPS32_REGSIZE = 4, | |
80 | MIPS64_REGSIZE = 8 | |
81 | }; | |
0dadbba0 | 82 | |
2e4ebe70 DJ |
83 | static const char *mips_abi_string; |
84 | ||
40478521 | 85 | static const char *const mips_abi_strings[] = { |
2e4ebe70 DJ |
86 | "auto", |
87 | "n32", | |
88 | "o32", | |
28d169de | 89 | "n64", |
2e4ebe70 DJ |
90 | "o64", |
91 | "eabi32", | |
92 | "eabi64", | |
93 | NULL | |
94 | }; | |
95 | ||
f8b73d13 DJ |
96 | /* The standard register names, and all the valid aliases for them. */ |
97 | struct register_alias | |
98 | { | |
99 | const char *name; | |
100 | int regnum; | |
101 | }; | |
102 | ||
103 | /* Aliases for o32 and most other ABIs. */ | |
104 | const struct register_alias mips_o32_aliases[] = { | |
105 | { "ta0", 12 }, | |
106 | { "ta1", 13 }, | |
107 | { "ta2", 14 }, | |
108 | { "ta3", 15 } | |
109 | }; | |
110 | ||
111 | /* Aliases for n32 and n64. */ | |
112 | const struct register_alias mips_n32_n64_aliases[] = { | |
113 | { "ta0", 8 }, | |
114 | { "ta1", 9 }, | |
115 | { "ta2", 10 }, | |
116 | { "ta3", 11 } | |
117 | }; | |
118 | ||
119 | /* Aliases for ABI-independent registers. */ | |
120 | const struct register_alias mips_register_aliases[] = { | |
121 | /* The architecture manuals specify these ABI-independent names for | |
122 | the GPRs. */ | |
123 | #define R(n) { "r" #n, n } | |
124 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
125 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
126 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
127 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
128 | #undef R | |
129 | ||
130 | /* k0 and k1 are sometimes called these instead (for "kernel | |
131 | temp"). */ | |
132 | { "kt0", 26 }, | |
133 | { "kt1", 27 }, | |
134 | ||
135 | /* This is the traditional GDB name for the CP0 status register. */ | |
136 | { "sr", MIPS_PS_REGNUM }, | |
137 | ||
138 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
139 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
140 | ||
141 | /* This is the traditional GDB name for the FCSR. */ | |
142 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
143 | }; | |
144 | ||
865093a3 AR |
145 | const struct register_alias mips_numeric_register_aliases[] = { |
146 | #define R(n) { #n, n } | |
147 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
148 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
149 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
150 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
151 | #undef R | |
152 | }; | |
153 | ||
c906108c SS |
154 | #ifndef MIPS_DEFAULT_FPU_TYPE |
155 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
156 | #endif | |
157 | static int mips_fpu_type_auto = 1; | |
158 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 159 | |
9ace0497 | 160 | static int mips_debug = 0; |
7a292a7a | 161 | |
29709017 DJ |
162 | /* Properties (for struct target_desc) describing the g/G packet |
163 | layout. */ | |
164 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
165 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
166 | ||
4eb0ad19 DJ |
167 | struct target_desc *mips_tdesc_gp32; |
168 | struct target_desc *mips_tdesc_gp64; | |
169 | ||
56cea623 AC |
170 | const struct mips_regnum * |
171 | mips_regnum (struct gdbarch *gdbarch) | |
172 | { | |
173 | return gdbarch_tdep (gdbarch)->regnum; | |
174 | } | |
175 | ||
176 | static int | |
177 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
178 | { | |
179 | return mips_regnum (gdbarch)->fp0 + 12; | |
180 | } | |
181 | ||
74ed0bb4 MD |
182 | #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
183 | == MIPS_ABI_EABI32 \ | |
184 | || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | |
c2d11a7d | 185 | |
025bb325 MS |
186 | #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
187 | (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | |
c2d11a7d | 188 | |
025bb325 MS |
189 | #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
190 | (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | |
c2d11a7d | 191 | |
74ed0bb4 | 192 | #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
c2d11a7d | 193 | |
95404a3e AC |
194 | /* MIPS16 function addresses are odd (bit 0 is set). Here are some |
195 | functions to test, set, or clear bit 0 of addresses. */ | |
196 | ||
197 | static CORE_ADDR | |
198 | is_mips16_addr (CORE_ADDR addr) | |
199 | { | |
200 | return ((addr) & 1); | |
201 | } | |
202 | ||
95404a3e AC |
203 | static CORE_ADDR |
204 | unmake_mips16_addr (CORE_ADDR addr) | |
205 | { | |
5b652102 | 206 | return ((addr) & ~(CORE_ADDR) 1); |
95404a3e AC |
207 | } |
208 | ||
930bd0e0 KB |
209 | static CORE_ADDR |
210 | make_mips16_addr (CORE_ADDR addr) | |
211 | { | |
212 | return ((addr) | (CORE_ADDR) 1); | |
213 | } | |
214 | ||
d1973055 KB |
215 | /* Return the MIPS ABI associated with GDBARCH. */ |
216 | enum mips_abi | |
217 | mips_abi (struct gdbarch *gdbarch) | |
218 | { | |
219 | return gdbarch_tdep (gdbarch)->mips_abi; | |
220 | } | |
221 | ||
4246e332 | 222 | int |
1b13c4f6 | 223 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 224 | { |
29709017 DJ |
225 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
226 | ||
227 | /* If we know how big the registers are, use that size. */ | |
228 | if (tdep->register_size_valid_p) | |
229 | return tdep->register_size; | |
230 | ||
231 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
232 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
233 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
234 | } | |
235 | ||
025bb325 | 236 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 237 | |
e6bc2e8a | 238 | unsigned int |
13326b4e | 239 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 240 | { |
1a69e1e4 DJ |
241 | switch (mips_abi (gdbarch)) |
242 | { | |
243 | case MIPS_ABI_EABI32: | |
244 | case MIPS_ABI_O32: | |
245 | return 4; | |
246 | case MIPS_ABI_N32: | |
247 | case MIPS_ABI_N64: | |
248 | case MIPS_ABI_O64: | |
249 | case MIPS_ABI_EABI64: | |
250 | return 8; | |
251 | case MIPS_ABI_UNKNOWN: | |
252 | case MIPS_ABI_LAST: | |
253 | default: | |
254 | internal_error (__FILE__, __LINE__, _("bad switch")); | |
255 | } | |
d929b26f AC |
256 | } |
257 | ||
71b8ef93 | 258 | /* Functions for setting and testing a bit in a minimal symbol that |
5a89d8aa | 259 | marks it as 16-bit function. The MSB of the minimal symbol's |
f594e5e9 | 260 | "info" field is used for this purpose. |
5a89d8aa | 261 | |
95f1da47 | 262 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
5a89d8aa MS |
263 | i.e. refers to a 16-bit function, and sets a "special" bit in a |
264 | minimal symbol to mark it as a 16-bit function | |
265 | ||
f594e5e9 | 266 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
5a89d8aa | 267 | |
5a89d8aa | 268 | static void |
6d82d43b AC |
269 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
270 | { | |
271 | if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | |
272 | { | |
b887350f | 273 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
6d82d43b | 274 | } |
5a89d8aa MS |
275 | } |
276 | ||
71b8ef93 MS |
277 | static int |
278 | msymbol_is_special (struct minimal_symbol *msym) | |
279 | { | |
b887350f | 280 | return MSYMBOL_TARGET_FLAG_1 (msym); |
71b8ef93 MS |
281 | } |
282 | ||
88658117 AC |
283 | /* XFER a value from the big/little/left end of the register. |
284 | Depending on the size of the value it might occupy the entire | |
285 | register or just part of it. Make an allowance for this, aligning | |
286 | things accordingly. */ | |
287 | ||
288 | static void | |
ba32f989 DJ |
289 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
290 | int reg_num, int length, | |
870cd05e MK |
291 | enum bfd_endian endian, gdb_byte *in, |
292 | const gdb_byte *out, int buf_offset) | |
88658117 | 293 | { |
88658117 | 294 | int reg_offset = 0; |
72a155b4 UW |
295 | |
296 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
297 | /* Need to transfer the left or right part of the register, based on |
298 | the targets byte order. */ | |
88658117 AC |
299 | switch (endian) |
300 | { | |
301 | case BFD_ENDIAN_BIG: | |
72a155b4 | 302 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
303 | break; |
304 | case BFD_ENDIAN_LITTLE: | |
305 | reg_offset = 0; | |
306 | break; | |
6d82d43b | 307 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
308 | reg_offset = 0; |
309 | break; | |
310 | default: | |
e2e0b3e5 | 311 | internal_error (__FILE__, __LINE__, _("bad switch")); |
88658117 AC |
312 | } |
313 | if (mips_debug) | |
cb1d2653 AC |
314 | fprintf_unfiltered (gdb_stderr, |
315 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
316 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
317 | if (mips_debug && out != NULL) |
318 | { | |
319 | int i; | |
cb1d2653 | 320 | fprintf_unfiltered (gdb_stdlog, "out "); |
88658117 | 321 | for (i = 0; i < length; i++) |
cb1d2653 | 322 | fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
323 | } |
324 | if (in != NULL) | |
6d82d43b AC |
325 | regcache_cooked_read_part (regcache, reg_num, reg_offset, length, |
326 | in + buf_offset); | |
88658117 | 327 | if (out != NULL) |
6d82d43b AC |
328 | regcache_cooked_write_part (regcache, reg_num, reg_offset, length, |
329 | out + buf_offset); | |
88658117 AC |
330 | if (mips_debug && in != NULL) |
331 | { | |
332 | int i; | |
cb1d2653 | 333 | fprintf_unfiltered (gdb_stdlog, "in "); |
88658117 | 334 | for (i = 0; i < length; i++) |
cb1d2653 | 335 | fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
336 | } |
337 | if (mips_debug) | |
338 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
339 | } | |
340 | ||
dd824b04 DJ |
341 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
342 | compatiblity mode. A return value of 1 means that we have | |
343 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
344 | ||
345 | static int | |
9c9acae0 | 346 | mips2_fp_compat (struct frame_info *frame) |
dd824b04 | 347 | { |
72a155b4 | 348 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
349 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
350 | meaningful. */ | |
72a155b4 | 351 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
352 | return 0; |
353 | ||
354 | #if 0 | |
355 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
356 | in all the places we deal with FP registers. PR gdb/413. */ | |
357 | /* Otherwise check the FR bit in the status register - it controls | |
358 | the FP compatiblity mode. If it is clear we are in compatibility | |
359 | mode. */ | |
9c9acae0 | 360 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
361 | return 1; |
362 | #endif | |
361d1df0 | 363 | |
dd824b04 DJ |
364 | return 0; |
365 | } | |
366 | ||
7a292a7a | 367 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 368 | |
74ed0bb4 | 369 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 370 | |
a14ed312 | 371 | static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); |
c906108c | 372 | |
025bb325 | 373 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
374 | |
375 | static struct cmd_list_element *setmipscmdlist = NULL; | |
376 | static struct cmd_list_element *showmipscmdlist = NULL; | |
377 | ||
5e2e9765 KB |
378 | /* Integer registers 0 thru 31 are handled explicitly by |
379 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 380 | are listed in the following tables. */ |
691c0433 | 381 | |
6d82d43b AC |
382 | enum |
383 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
384 | |
385 | /* Generic MIPS. */ | |
386 | ||
387 | static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
388 | "sr", "lo", "hi", "bad", "cause", "pc", |
389 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
390 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
391 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
392 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
1faeff08 | 393 | "fsr", "fir", |
691c0433 AC |
394 | }; |
395 | ||
396 | /* Names of IDT R3041 registers. */ | |
397 | ||
398 | static const char *mips_r3041_reg_names[] = { | |
6d82d43b AC |
399 | "sr", "lo", "hi", "bad", "cause", "pc", |
400 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
401 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
402 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
403 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
404 | "fsr", "fir", "", /*"fp" */ "", | |
405 | "", "", "bus", "ccfg", "", "", "", "", | |
406 | "", "", "port", "cmp", "", "", "epc", "prid", | |
691c0433 AC |
407 | }; |
408 | ||
409 | /* Names of tx39 registers. */ | |
410 | ||
411 | static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
412 | "sr", "lo", "hi", "bad", "cause", "pc", |
413 | "", "", "", "", "", "", "", "", | |
414 | "", "", "", "", "", "", "", "", | |
415 | "", "", "", "", "", "", "", "", | |
416 | "", "", "", "", "", "", "", "", | |
417 | "", "", "", "", | |
418 | "", "", "", "", "", "", "", "", | |
1faeff08 | 419 | "", "", "config", "cache", "debug", "depc", "epc", |
691c0433 AC |
420 | }; |
421 | ||
422 | /* Names of IRIX registers. */ | |
423 | static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
6d82d43b AC |
424 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
425 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
426 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
427 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
428 | "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | |
691c0433 AC |
429 | }; |
430 | ||
1faeff08 MR |
431 | /* Names of Linux registers. */ |
432 | static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | |
433 | "sr", "lo", "hi", "bad", "cause", "pc", | |
434 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
435 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
436 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
437 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
438 | "fsr", "fir" | |
439 | }; | |
440 | ||
cce74817 | 441 | |
5e2e9765 | 442 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 443 | static const char * |
d93859e2 | 444 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 445 | { |
d93859e2 | 446 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
5e2e9765 KB |
447 | /* GPR names for all ABIs other than n32/n64. */ |
448 | static char *mips_gpr_names[] = { | |
6d82d43b AC |
449 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
450 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
451 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
452 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
453 | }; |
454 | ||
455 | /* GPR names for n32 and n64 ABIs. */ | |
456 | static char *mips_n32_n64_gpr_names[] = { | |
6d82d43b AC |
457 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
458 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
459 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
460 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
461 | }; |
462 | ||
d93859e2 | 463 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 464 | |
f57d151a | 465 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
466 | but then don't make the raw register names visible. This (upper) |
467 | range of user visible register numbers are the pseudo-registers. | |
468 | ||
469 | This approach was adopted accommodate the following scenario: | |
470 | It is possible to debug a 64-bit device using a 32-bit | |
471 | programming model. In such instances, the raw registers are | |
472 | configured to be 64-bits wide, while the pseudo registers are | |
473 | configured to be 32-bits wide. The registers that the user | |
474 | sees - the pseudo registers - match the users expectations | |
475 | given the programming model being used. */ | |
d93859e2 UW |
476 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
477 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
478 | return ""; |
479 | ||
5e2e9765 KB |
480 | /* The MIPS integer registers are always mapped from 0 to 31. The |
481 | names of the registers (which reflects the conventions regarding | |
482 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 483 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
484 | { |
485 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 486 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 487 | else |
a4b8ebc8 | 488 | return mips_gpr_names[rawnum]; |
5e2e9765 | 489 | } |
d93859e2 UW |
490 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
491 | return tdesc_register_name (gdbarch, rawnum); | |
492 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
493 | { |
494 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
1faeff08 MR |
495 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
496 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
497 | return ""; | |
691c0433 | 498 | } |
5e2e9765 KB |
499 | else |
500 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 501 | _("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 502 | } |
5e2e9765 | 503 | |
a4b8ebc8 | 504 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 505 | |
a4b8ebc8 AC |
506 | static int |
507 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
508 | struct reggroup *reggroup) | |
509 | { | |
510 | int vector_p; | |
511 | int float_p; | |
512 | int raw_p; | |
72a155b4 UW |
513 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
514 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
515 | if (reggroup == all_reggroup) |
516 | return pseudo; | |
517 | vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); | |
518 | float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; | |
519 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs | |
520 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 UW |
521 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
522 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
523 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
a4b8ebc8 AC |
524 | return 0; |
525 | if (reggroup == float_reggroup) | |
526 | return float_p && pseudo; | |
527 | if (reggroup == vector_reggroup) | |
528 | return vector_p && pseudo; | |
529 | if (reggroup == general_reggroup) | |
530 | return (!vector_p && !float_p) && pseudo; | |
531 | /* Save the pseudo registers. Need to make certain that any code | |
532 | extracting register values from a saved register cache also uses | |
533 | pseudo registers. */ | |
534 | if (reggroup == save_reggroup) | |
535 | return raw_p && pseudo; | |
536 | /* Restore the same pseudo register. */ | |
537 | if (reggroup == restore_reggroup) | |
538 | return raw_p && pseudo; | |
6d82d43b | 539 | return 0; |
a4b8ebc8 AC |
540 | } |
541 | ||
f8b73d13 DJ |
542 | /* Return the groups that a MIPS register can be categorised into. |
543 | This version is only used if we have a target description which | |
544 | describes real registers (and their groups). */ | |
545 | ||
546 | static int | |
547 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
548 | struct reggroup *reggroup) | |
549 | { | |
550 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
551 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
552 | int ret; | |
553 | ||
554 | /* Only save, restore, and display the pseudo registers. Need to | |
555 | make certain that any code extracting register values from a | |
556 | saved register cache also uses pseudo registers. | |
557 | ||
558 | Note: saving and restoring the pseudo registers is slightly | |
559 | strange; if we have 64 bits, we should save and restore all | |
560 | 64 bits. But this is hard and has little benefit. */ | |
561 | if (!pseudo) | |
562 | return 0; | |
563 | ||
564 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
565 | if (ret != -1) | |
566 | return ret; | |
567 | ||
568 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
569 | } | |
570 | ||
a4b8ebc8 | 571 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 572 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 573 | registers. Take care of alignment and size problems. */ |
c5aa993b | 574 | |
05d1431c | 575 | static enum register_status |
a4b8ebc8 | 576 | mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
47a35522 | 577 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 578 | { |
72a155b4 UW |
579 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
580 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
581 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 582 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
05d1431c | 583 | return regcache_raw_read (regcache, rawnum, buf); |
6d82d43b AC |
584 | else if (register_size (gdbarch, rawnum) > |
585 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 586 | { |
8bdf35dc | 587 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
05d1431c | 588 | return regcache_raw_read_part (regcache, rawnum, 0, 4, buf); |
47ebcfbe | 589 | else |
8bdf35dc KB |
590 | { |
591 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
592 | LONGEST regval; | |
05d1431c PA |
593 | enum register_status status; |
594 | ||
595 | status = regcache_raw_read_signed (regcache, rawnum, ®val); | |
596 | if (status == REG_VALID) | |
597 | store_signed_integer (buf, 4, byte_order, regval); | |
598 | return status; | |
8bdf35dc | 599 | } |
47ebcfbe AC |
600 | } |
601 | else | |
e2e0b3e5 | 602 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 AC |
603 | } |
604 | ||
605 | static void | |
6d82d43b AC |
606 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
607 | struct regcache *regcache, int cookednum, | |
47a35522 | 608 | const gdb_byte *buf) |
a4b8ebc8 | 609 | { |
72a155b4 UW |
610 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
611 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
612 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 613 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
de38af99 | 614 | regcache_raw_write (regcache, rawnum, buf); |
6d82d43b AC |
615 | else if (register_size (gdbarch, rawnum) > |
616 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 617 | { |
8bdf35dc | 618 | if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
47ebcfbe AC |
619 | regcache_raw_write_part (regcache, rawnum, 0, 4, buf); |
620 | else | |
8bdf35dc KB |
621 | { |
622 | /* Sign extend the shortened version of the register prior | |
623 | to placing it in the raw register. This is required for | |
624 | some mips64 parts in order to avoid unpredictable behavior. */ | |
625 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
626 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
627 | regcache_raw_write_signed (regcache, rawnum, regval); | |
628 | } | |
47ebcfbe AC |
629 | } |
630 | else | |
e2e0b3e5 | 631 | internal_error (__FILE__, __LINE__, _("bad register size")); |
a4b8ebc8 | 632 | } |
c5aa993b | 633 | |
175ff332 HZ |
634 | static int |
635 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
636 | struct agent_expr *ax, int reg) | |
637 | { | |
638 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
639 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
640 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
641 | ||
642 | ax_reg_mask (ax, rawnum); | |
643 | ||
644 | return 0; | |
645 | } | |
646 | ||
647 | static int | |
648 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
649 | struct agent_expr *ax, int reg) | |
650 | { | |
651 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
652 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
653 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
654 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
655 | { | |
656 | ax_reg (ax, rawnum); | |
657 | ||
658 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
659 | { | |
660 | if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p | |
661 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) | |
662 | { | |
663 | ax_const_l (ax, 32); | |
664 | ax_simple (ax, aop_lsh); | |
665 | } | |
666 | ax_const_l (ax, 32); | |
667 | ax_simple (ax, aop_rsh_signed); | |
668 | } | |
669 | } | |
670 | else | |
671 | internal_error (__FILE__, __LINE__, _("bad register size")); | |
672 | ||
673 | return 0; | |
674 | } | |
675 | ||
c906108c | 676 | /* Table to translate MIPS16 register field to actual register number. */ |
6d82d43b | 677 | static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
678 | |
679 | /* Heuristic_proc_start may hunt through the text section for a long | |
680 | time across a 2400 baud serial line. Allows the user to limit this | |
681 | search. */ | |
682 | ||
683 | static unsigned int heuristic_fence_post = 0; | |
684 | ||
46cd78fb | 685 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
686 | register N. NOTE: This defines the pseudo register type so need to |
687 | rebuild the architecture vector. */ | |
43e526b9 JM |
688 | |
689 | static int mips64_transfers_32bit_regs_p = 0; | |
690 | ||
719ec221 AC |
691 | static void |
692 | set_mips64_transfers_32bit_regs (char *args, int from_tty, | |
693 | struct cmd_list_element *c) | |
43e526b9 | 694 | { |
719ec221 AC |
695 | struct gdbarch_info info; |
696 | gdbarch_info_init (&info); | |
697 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" | |
698 | instead of relying on globals. Doing that would let generic code | |
699 | handle the search for this specific architecture. */ | |
700 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 701 | { |
719ec221 | 702 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 703 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 704 | } |
a4b8ebc8 AC |
705 | } |
706 | ||
47ebcfbe | 707 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 708 | |
ee51a8c7 KB |
709 | /* This predicate tests for the case of an 8 byte floating point |
710 | value that is being transferred to or from a pair of floating point | |
711 | registers each of which are (or are considered to be) only 4 bytes | |
712 | wide. */ | |
ff2e87ac | 713 | static int |
ee51a8c7 KB |
714 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
715 | struct type *type) | |
ff2e87ac | 716 | { |
0abe36f5 MD |
717 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
718 | && register_size (gdbarch, regnum) == 4 | |
719 | && (regnum % gdbarch_num_regs (gdbarch)) | |
720 | >= mips_regnum (gdbarch)->fp0 | |
721 | && (regnum % gdbarch_num_regs (gdbarch)) | |
722 | < mips_regnum (gdbarch)->fp0 + 32 | |
6d82d43b | 723 | && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
ff2e87ac AC |
724 | } |
725 | ||
ee51a8c7 KB |
726 | /* This predicate tests for the case of a value of less than 8 |
727 | bytes in width that is being transfered to or from an 8 byte | |
728 | general purpose register. */ | |
729 | static int | |
730 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
731 | struct type *type) | |
732 | { | |
733 | int num_regs = gdbarch_num_regs (gdbarch); | |
734 | ||
735 | return (register_size (gdbarch, regnum) == 8 | |
736 | && regnum % num_regs > 0 && regnum % num_regs < 32 | |
737 | && TYPE_LENGTH (type) < 8); | |
738 | } | |
739 | ||
740 | static int | |
025bb325 MS |
741 | mips_convert_register_p (struct gdbarch *gdbarch, |
742 | int regnum, struct type *type) | |
ee51a8c7 KB |
743 | { |
744 | return mips_convert_register_float_case_p (gdbarch, regnum, type) | |
745 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type); | |
746 | } | |
747 | ||
8dccd430 | 748 | static int |
ff2e87ac | 749 | mips_register_to_value (struct frame_info *frame, int regnum, |
8dccd430 PA |
750 | struct type *type, gdb_byte *to, |
751 | int *optimizedp, int *unavailablep) | |
102182a9 | 752 | { |
ee51a8c7 KB |
753 | struct gdbarch *gdbarch = get_frame_arch (frame); |
754 | ||
755 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
756 | { | |
757 | get_frame_register (frame, regnum + 0, to + 4); | |
758 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 PA |
759 | |
760 | if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, | |
761 | optimizedp, unavailablep)) | |
762 | return 0; | |
763 | ||
764 | if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, | |
765 | optimizedp, unavailablep)) | |
766 | return 0; | |
767 | *optimizedp = *unavailablep = 0; | |
768 | return 1; | |
ee51a8c7 KB |
769 | } |
770 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
771 | { | |
772 | int len = TYPE_LENGTH (type); | |
8dccd430 PA |
773 | CORE_ADDR offset; |
774 | ||
775 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
776 | if (!get_frame_register_bytes (frame, regnum, offset, len, to, | |
777 | optimizedp, unavailablep)) | |
778 | return 0; | |
779 | ||
780 | *optimizedp = *unavailablep = 0; | |
781 | return 1; | |
ee51a8c7 KB |
782 | } |
783 | else | |
784 | { | |
785 | internal_error (__FILE__, __LINE__, | |
786 | _("mips_register_to_value: unrecognized case")); | |
787 | } | |
102182a9 MS |
788 | } |
789 | ||
42c466d7 | 790 | static void |
ff2e87ac | 791 | mips_value_to_register (struct frame_info *frame, int regnum, |
47a35522 | 792 | struct type *type, const gdb_byte *from) |
102182a9 | 793 | { |
ee51a8c7 KB |
794 | struct gdbarch *gdbarch = get_frame_arch (frame); |
795 | ||
796 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
797 | { | |
798 | put_frame_register (frame, regnum + 0, from + 4); | |
799 | put_frame_register (frame, regnum + 1, from + 0); | |
800 | } | |
801 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
802 | { | |
803 | gdb_byte fill[8]; | |
804 | int len = TYPE_LENGTH (type); | |
805 | ||
806 | /* Sign extend values, irrespective of type, that are stored to | |
807 | a 64-bit general purpose register. (32-bit unsigned values | |
808 | are stored as signed quantities within a 64-bit register. | |
809 | When performing an operation, in compiled code, that combines | |
810 | a 32-bit unsigned value with a signed 64-bit value, a type | |
811 | conversion is first performed that zeroes out the high 32 bits.) */ | |
812 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
813 | { | |
814 | if (from[0] & 0x80) | |
815 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
816 | else | |
817 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
818 | put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); | |
819 | put_frame_register_bytes (frame, regnum, 8 - len, len, from); | |
820 | } | |
821 | else | |
822 | { | |
823 | if (from[len-1] & 0x80) | |
824 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
825 | else | |
826 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
827 | put_frame_register_bytes (frame, regnum, 0, len, from); | |
828 | put_frame_register_bytes (frame, regnum, len, 8 - len, fill); | |
829 | } | |
830 | } | |
831 | else | |
832 | { | |
833 | internal_error (__FILE__, __LINE__, | |
834 | _("mips_value_to_register: unrecognized case")); | |
835 | } | |
102182a9 MS |
836 | } |
837 | ||
a4b8ebc8 AC |
838 | /* Return the GDB type object for the "standard" data type of data in |
839 | register REG. */ | |
78fde5f8 KB |
840 | |
841 | static struct type * | |
a4b8ebc8 AC |
842 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
843 | { | |
72a155b4 UW |
844 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
845 | if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | |
846 | && (regnum % gdbarch_num_regs (gdbarch)) | |
847 | < mips_regnum (gdbarch)->fp0 + 32) | |
a6425924 | 848 | { |
5ef80fb0 | 849 | /* The floating-point registers raw, or cooked, always match |
1b13c4f6 | 850 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 851 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 852 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 853 | else |
27067745 | 854 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 855 | } |
72a155b4 | 856 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
857 | { |
858 | /* The raw or ISA registers. These are all sized according to | |
859 | the ISA regsize. */ | |
860 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 861 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 862 | else |
df4df182 | 863 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 864 | } |
78fde5f8 | 865 | else |
d5ac5a39 | 866 | { |
1faeff08 MR |
867 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
868 | ||
d5ac5a39 AC |
869 | /* The cooked or ABI registers. These are sized according to |
870 | the ABI (with a few complications). */ | |
1faeff08 MR |
871 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
872 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
873 | return builtin_type (gdbarch)->builtin_int32; | |
874 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX | |
875 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
876 | && rawnum >= MIPS_FIRST_EMBED_REGNUM | |
877 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
878 | /* The pseudo/cooked view of the embedded registers is always |
879 | 32-bit. The raw view is handled below. */ | |
df4df182 | 880 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
881 | else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
882 | /* The target, while possibly using a 64-bit register buffer, | |
883 | is only transfering 32-bits of each integer register. | |
884 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 885 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
886 | else if (mips_abi_regsize (gdbarch) == 4) |
887 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
888 | 32- or 64-bit). */ | |
df4df182 | 889 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
890 | else |
891 | /* 64-bit ABI. */ | |
df4df182 | 892 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 893 | } |
78fde5f8 KB |
894 | } |
895 | ||
f8b73d13 DJ |
896 | /* Return the GDB type for the pseudo register REGNUM, which is the |
897 | ABI-level view. This function is only called if there is a target | |
898 | description which includes registers, so we know precisely the | |
899 | types of hardware registers. */ | |
900 | ||
901 | static struct type * | |
902 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
903 | { | |
904 | const int num_regs = gdbarch_num_regs (gdbarch); | |
905 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
906 | int rawnum = regnum % num_regs; | |
907 | struct type *rawtype; | |
908 | ||
909 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
910 | ||
911 | /* Absent registers are still absent. */ | |
912 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
913 | if (TYPE_LENGTH (rawtype) == 0) | |
914 | return rawtype; | |
915 | ||
1faeff08 MR |
916 | if (rawnum >= mips_regnum (gdbarch)->fp0 |
917 | && rawnum < mips_regnum (gdbarch)->fp0 + 32) | |
f8b73d13 DJ |
918 | /* Present the floating point registers however the hardware did; |
919 | do not try to convert between FPU layouts. */ | |
920 | return rawtype; | |
921 | ||
f8b73d13 DJ |
922 | /* Use pointer types for registers if we can. For n32 we can not, |
923 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb UW |
924 | if (mips_abi_regsize (gdbarch) |
925 | == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
f8b73d13 | 926 | { |
1faeff08 MR |
927 | if (rawnum == MIPS_SP_REGNUM |
928 | || rawnum == mips_regnum (gdbarch)->badvaddr) | |
0dfff4cb | 929 | return builtin_type (gdbarch)->builtin_data_ptr; |
1faeff08 | 930 | else if (rawnum == mips_regnum (gdbarch)->pc) |
0dfff4cb | 931 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
932 | } |
933 | ||
934 | if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
1faeff08 MR |
935 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
936 | || rawnum == mips_regnum (gdbarch)->lo | |
937 | || rawnum == mips_regnum (gdbarch)->hi | |
938 | || rawnum == mips_regnum (gdbarch)->badvaddr | |
939 | || rawnum == mips_regnum (gdbarch)->cause | |
940 | || rawnum == mips_regnum (gdbarch)->pc | |
941 | || (mips_regnum (gdbarch)->dspacc != -1 | |
942 | && rawnum >= mips_regnum (gdbarch)->dspacc | |
943 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) | |
df4df182 | 944 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 | 945 | |
1faeff08 MR |
946 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX |
947 | && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX | |
948 | && rawnum >= MIPS_EMBED_FP0_REGNUM + 32 | |
949 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
950 | { | |
951 | /* The pseudo/cooked view of embedded registers is always | |
952 | 32-bit, even if the target transfers 64-bit values for them. | |
953 | New targets relying on XML descriptions should only transfer | |
954 | the necessary 32 bits, but older versions of GDB expected 64, | |
955 | so allow the target to provide 64 bits without interfering | |
956 | with the displayed type. */ | |
957 | return builtin_type (gdbarch)->builtin_int32; | |
958 | } | |
959 | ||
f8b73d13 DJ |
960 | /* For all other registers, pass through the hardware type. */ |
961 | return rawtype; | |
962 | } | |
bcb0cc15 | 963 | |
025bb325 | 964 | /* Should the upper word of 64-bit addresses be zeroed? */ |
7f19b9a2 | 965 | enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
966 | |
967 | static int | |
480d3dd2 | 968 | mips_mask_address_p (struct gdbarch_tdep *tdep) |
4014092b AC |
969 | { |
970 | switch (mask_address_var) | |
971 | { | |
7f19b9a2 | 972 | case AUTO_BOOLEAN_TRUE: |
4014092b | 973 | return 1; |
7f19b9a2 | 974 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
975 | return 0; |
976 | break; | |
7f19b9a2 | 977 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 978 | return tdep->default_mask_address_p; |
4014092b | 979 | default: |
025bb325 MS |
980 | internal_error (__FILE__, __LINE__, |
981 | _("mips_mask_address_p: bad switch")); | |
4014092b | 982 | return -1; |
361d1df0 | 983 | } |
4014092b AC |
984 | } |
985 | ||
986 | static void | |
08546159 AC |
987 | show_mask_address (struct ui_file *file, int from_tty, |
988 | struct cmd_list_element *c, const char *value) | |
4014092b | 989 | { |
1cf3db46 | 990 | struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch); |
08546159 AC |
991 | |
992 | deprecated_show_value_hack (file, from_tty, c, value); | |
4014092b AC |
993 | switch (mask_address_var) |
994 | { | |
7f19b9a2 | 995 | case AUTO_BOOLEAN_TRUE: |
4014092b AC |
996 | printf_filtered ("The 32 bit mips address mask is enabled\n"); |
997 | break; | |
7f19b9a2 | 998 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
999 | printf_filtered ("The 32 bit mips address mask is disabled\n"); |
1000 | break; | |
7f19b9a2 | 1001 | case AUTO_BOOLEAN_AUTO: |
6d82d43b AC |
1002 | printf_filtered |
1003 | ("The 32 bit address mask is set automatically. Currently %s\n", | |
1004 | mips_mask_address_p (tdep) ? "enabled" : "disabled"); | |
4014092b AC |
1005 | break; |
1006 | default: | |
e2e0b3e5 | 1007 | internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
4014092b | 1008 | break; |
361d1df0 | 1009 | } |
4014092b | 1010 | } |
c906108c | 1011 | |
c906108c SS |
1012 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
1013 | ||
0fe7e7c8 AC |
1014 | int |
1015 | mips_pc_is_mips16 (CORE_ADDR memaddr) | |
c906108c SS |
1016 | { |
1017 | struct minimal_symbol *sym; | |
1018 | ||
91912e4d MR |
1019 | /* A flag indicating that this is a MIPS16 function is stored by |
1020 | elfread.c in the high bit of the info field. Use this to decide | |
1021 | if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of | |
1022 | the address is set, assume this is a MIPS16 address. */ | |
c906108c SS |
1023 | sym = lookup_minimal_symbol_by_pc (memaddr); |
1024 | if (sym) | |
71b8ef93 | 1025 | return msymbol_is_special (sym); |
c906108c | 1026 | else |
91912e4d | 1027 | return is_mips16_addr (memaddr); |
c906108c SS |
1028 | } |
1029 | ||
b2fa5097 | 1030 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1031 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1032 | |
1033 | static CORE_ADDR | |
61a1198a | 1034 | mips_read_pc (struct regcache *regcache) |
6c997a34 | 1035 | { |
61a1198a UW |
1036 | ULONGEST pc; |
1037 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | |
1038 | regcache_cooked_read_signed (regcache, regnum, &pc); | |
930bd0e0 KB |
1039 | if (is_mips16_addr (pc)) |
1040 | pc = unmake_mips16_addr (pc); | |
61a1198a | 1041 | return pc; |
b6cb9035 AC |
1042 | } |
1043 | ||
58dfe9ff AC |
1044 | static CORE_ADDR |
1045 | mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1046 | { | |
930bd0e0 KB |
1047 | ULONGEST pc; |
1048 | ||
1049 | pc = frame_unwind_register_signed | |
1050 | (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | |
1051 | if (is_mips16_addr (pc)) | |
1052 | pc = unmake_mips16_addr (pc); | |
1053 | return pc; | |
edfae063 AC |
1054 | } |
1055 | ||
30244cd8 UW |
1056 | static CORE_ADDR |
1057 | mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1058 | { | |
72a155b4 UW |
1059 | return frame_unwind_register_signed |
1060 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1061 | } |
1062 | ||
b8a22b94 | 1063 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1064 | dummy frame. The frame ID's base needs to match the TOS value |
1065 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1066 | breakpoint. */ | |
1067 | ||
1068 | static struct frame_id | |
b8a22b94 | 1069 | mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
edfae063 | 1070 | { |
f57d151a | 1071 | return frame_id_build |
b8a22b94 DJ |
1072 | (get_frame_register_signed (this_frame, |
1073 | gdbarch_num_regs (gdbarch) | |
1074 | + MIPS_SP_REGNUM), | |
1075 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1076 | } |
1077 | ||
b6cb9035 | 1078 | static void |
61a1198a | 1079 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1080 | { |
61a1198a | 1081 | int regnum = mips_regnum (get_regcache_arch (regcache))->pc; |
930bd0e0 KB |
1082 | if (mips_pc_is_mips16 (pc)) |
1083 | regcache_cooked_write_unsigned (regcache, regnum, make_mips16_addr (pc)); | |
1084 | else | |
1085 | regcache_cooked_write_unsigned (regcache, regnum, pc); | |
6c997a34 | 1086 | } |
c906108c | 1087 | |
c906108c SS |
1088 | /* Fetch and return instruction from the specified location. If the PC |
1089 | is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | |
1090 | ||
d37cca3d | 1091 | static ULONGEST |
e17a4113 | 1092 | mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) |
c906108c | 1093 | { |
e17a4113 | 1094 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1095 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
1096 | int instlen; |
1097 | int status; | |
1098 | ||
0fe7e7c8 | 1099 | if (mips_pc_is_mips16 (addr)) |
c906108c | 1100 | { |
95ac2dcf | 1101 | instlen = MIPS_INSN16_SIZE; |
95404a3e | 1102 | addr = unmake_mips16_addr (addr); |
c906108c SS |
1103 | } |
1104 | else | |
95ac2dcf | 1105 | instlen = MIPS_INSN32_SIZE; |
8defab1a | 1106 | status = target_read_memory (addr, buf, instlen); |
c906108c SS |
1107 | if (status) |
1108 | memory_error (status, addr); | |
e17a4113 | 1109 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1110 | } |
1111 | ||
025bb325 | 1112 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1113 | #define mips32_op(x) (x >> 26) |
1114 | #define itype_op(x) (x >> 26) | |
1115 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1116 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1117 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1118 | |
e135b889 DJ |
1119 | #define jtype_op(x) (x >> 26) |
1120 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1121 | |
e135b889 DJ |
1122 | #define rtype_op(x) (x >> 26) |
1123 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1124 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1125 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1126 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1127 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1128 | |
06987e64 MK |
1129 | static LONGEST |
1130 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1131 | { |
06987e64 | 1132 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1133 | } |
1134 | ||
a385295e MR |
1135 | /* Determine the address of the next instruction executed after the INST |
1136 | floating condition branch instruction at PC. COUNT specifies the | |
1137 | number of the floating condition bits tested by the branch. */ | |
1138 | ||
1139 | static CORE_ADDR | |
1140 | mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, | |
1141 | ULONGEST inst, CORE_ADDR pc, int count) | |
1142 | { | |
1143 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1144 | int cnum = (itype_rt (inst) >> 2) & (count - 1); | |
1145 | int tf = itype_rt (inst) & 1; | |
1146 | int mask = (1 << count) - 1; | |
1147 | ULONGEST fcs; | |
1148 | int cond; | |
1149 | ||
1150 | if (fcsr == -1) | |
1151 | /* No way to handle; it'll most likely trap anyway. */ | |
1152 | return pc; | |
1153 | ||
1154 | fcs = get_frame_register_unsigned (frame, fcsr); | |
1155 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); | |
1156 | ||
1157 | if (((cond >> cnum) & mask) != mask * !tf) | |
1158 | pc += mips32_relative_offset (inst); | |
1159 | else | |
1160 | pc += 4; | |
1161 | ||
1162 | return pc; | |
1163 | } | |
1164 | ||
f49e4e6d MS |
1165 | /* Determine where to set a single step breakpoint while considering |
1166 | branch prediction. */ | |
5a89d8aa | 1167 | static CORE_ADDR |
0b1b3e42 | 1168 | mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c5aa993b | 1169 | { |
e17a4113 | 1170 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c5aa993b JM |
1171 | unsigned long inst; |
1172 | int op; | |
e17a4113 | 1173 | inst = mips_fetch_instruction (gdbarch, pc); |
025bb325 MS |
1174 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1175 | instruction. */ | |
c5aa993b | 1176 | { |
e135b889 | 1177 | if (itype_op (inst) >> 2 == 5) |
6d82d43b | 1178 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1179 | { |
e135b889 | 1180 | op = (itype_op (inst) & 0x03); |
c906108c SS |
1181 | switch (op) |
1182 | { | |
e135b889 DJ |
1183 | case 0: /* BEQL */ |
1184 | goto equal_branch; | |
1185 | case 1: /* BNEL */ | |
1186 | goto neq_branch; | |
1187 | case 2: /* BLEZL */ | |
1188 | goto less_branch; | |
313628cc | 1189 | case 3: /* BGTZL */ |
e135b889 | 1190 | goto greater_branch; |
c5aa993b JM |
1191 | default: |
1192 | pc += 4; | |
c906108c SS |
1193 | } |
1194 | } | |
e135b889 | 1195 | else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
6d82d43b | 1196 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
1197 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1); |
1198 | else if (itype_op (inst) == 17 && itype_rs (inst) == 9 | |
1199 | && (itype_rt (inst) & 2) == 0) | |
1200 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ | |
1201 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2); | |
1202 | else if (itype_op (inst) == 17 && itype_rs (inst) == 10 | |
1203 | && (itype_rt (inst) & 2) == 0) | |
1204 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ | |
1205 | pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4); | |
c5aa993b | 1206 | else |
025bb325 | 1207 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1208 | } |
1209 | else | |
025bb325 | 1210 | { /* This gets way messy. */ |
c5aa993b | 1211 | |
025bb325 MS |
1212 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
1213 | switch (op = itype_op (inst) & 0x07) /* Extract bits 28,27,26. */ | |
c906108c | 1214 | { |
c5aa993b JM |
1215 | case 0: /* SPECIAL */ |
1216 | op = rtype_funct (inst); | |
1217 | switch (op) | |
1218 | { | |
1219 | case 8: /* JR */ | |
1220 | case 9: /* JALR */ | |
025bb325 | 1221 | /* Set PC to that address. */ |
0b1b3e42 | 1222 | pc = get_frame_register_signed (frame, rtype_rs (inst)); |
c5aa993b | 1223 | break; |
e38d4e1a DJ |
1224 | case 12: /* SYSCALL */ |
1225 | { | |
1226 | struct gdbarch_tdep *tdep; | |
1227 | ||
1228 | tdep = gdbarch_tdep (get_frame_arch (frame)); | |
1229 | if (tdep->syscall_next_pc != NULL) | |
1230 | pc = tdep->syscall_next_pc (frame); | |
1231 | else | |
1232 | pc += 4; | |
1233 | } | |
1234 | break; | |
c5aa993b JM |
1235 | default: |
1236 | pc += 4; | |
1237 | } | |
1238 | ||
6d82d43b | 1239 | break; /* end SPECIAL */ |
025bb325 | 1240 | case 1: /* REGIMM */ |
c906108c | 1241 | { |
e135b889 DJ |
1242 | op = itype_rt (inst); /* branch condition */ |
1243 | switch (op) | |
c906108c | 1244 | { |
c5aa993b | 1245 | case 0: /* BLTZ */ |
e135b889 DJ |
1246 | case 2: /* BLTZL */ |
1247 | case 16: /* BLTZAL */ | |
c5aa993b | 1248 | case 18: /* BLTZALL */ |
c906108c | 1249 | less_branch: |
0b1b3e42 | 1250 | if (get_frame_register_signed (frame, itype_rs (inst)) < 0) |
c5aa993b JM |
1251 | pc += mips32_relative_offset (inst) + 4; |
1252 | else | |
1253 | pc += 8; /* after the delay slot */ | |
1254 | break; | |
e135b889 | 1255 | case 1: /* BGEZ */ |
c5aa993b JM |
1256 | case 3: /* BGEZL */ |
1257 | case 17: /* BGEZAL */ | |
1258 | case 19: /* BGEZALL */ | |
0b1b3e42 | 1259 | if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
c5aa993b JM |
1260 | pc += mips32_relative_offset (inst) + 4; |
1261 | else | |
1262 | pc += 8; /* after the delay slot */ | |
1263 | break; | |
a385295e MR |
1264 | case 0x1c: /* BPOSGE32 */ |
1265 | case 0x1e: /* BPOSGE64 */ | |
1266 | pc += 4; | |
1267 | if (itype_rs (inst) == 0) | |
1268 | { | |
1269 | unsigned int pos = (op & 2) ? 64 : 32; | |
1270 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1271 | ||
1272 | if (dspctl == -1) | |
1273 | /* No way to handle; it'll most likely trap anyway. */ | |
1274 | break; | |
1275 | ||
1276 | if ((get_frame_register_unsigned (frame, | |
1277 | dspctl) & 0x7f) >= pos) | |
1278 | pc += mips32_relative_offset (inst); | |
1279 | else | |
1280 | pc += 4; | |
1281 | } | |
1282 | break; | |
e135b889 | 1283 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1284 | default: |
1285 | pc += 4; | |
c906108c SS |
1286 | } |
1287 | } | |
6d82d43b | 1288 | break; /* end REGIMM */ |
c5aa993b JM |
1289 | case 2: /* J */ |
1290 | case 3: /* JAL */ | |
1291 | { | |
1292 | unsigned long reg; | |
1293 | reg = jtype_target (inst) << 2; | |
025bb325 | 1294 | /* Upper four bits get never changed... */ |
5b652102 | 1295 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1296 | } |
c5aa993b JM |
1297 | break; |
1298 | /* FIXME case JALX : */ | |
1299 | { | |
1300 | unsigned long reg; | |
1301 | reg = jtype_target (inst) << 2; | |
025bb325 | 1302 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ |
c906108c SS |
1303 | /* Add 1 to indicate 16 bit mode - Invert ISA mode */ |
1304 | } | |
c5aa993b | 1305 | break; /* The new PC will be alternate mode */ |
e135b889 | 1306 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1307 | equal_branch: |
0b1b3e42 UW |
1308 | if (get_frame_register_signed (frame, itype_rs (inst)) == |
1309 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1310 | pc += mips32_relative_offset (inst) + 4; |
1311 | else | |
1312 | pc += 8; | |
1313 | break; | |
e135b889 | 1314 | case 5: /* BNE, BNEL */ |
c5aa993b | 1315 | neq_branch: |
0b1b3e42 UW |
1316 | if (get_frame_register_signed (frame, itype_rs (inst)) != |
1317 | get_frame_register_signed (frame, itype_rt (inst))) | |
c5aa993b JM |
1318 | pc += mips32_relative_offset (inst) + 4; |
1319 | else | |
1320 | pc += 8; | |
1321 | break; | |
e135b889 | 1322 | case 6: /* BLEZ, BLEZL */ |
0b1b3e42 | 1323 | if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) |
c5aa993b JM |
1324 | pc += mips32_relative_offset (inst) + 4; |
1325 | else | |
1326 | pc += 8; | |
1327 | break; | |
1328 | case 7: | |
e135b889 DJ |
1329 | default: |
1330 | greater_branch: /* BGTZ, BGTZL */ | |
0b1b3e42 | 1331 | if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
c5aa993b JM |
1332 | pc += mips32_relative_offset (inst) + 4; |
1333 | else | |
1334 | pc += 8; | |
1335 | break; | |
c5aa993b JM |
1336 | } /* switch */ |
1337 | } /* else */ | |
1338 | return pc; | |
1339 | } /* mips32_next_pc */ | |
c906108c SS |
1340 | |
1341 | /* Decoding the next place to set a breakpoint is irregular for the | |
025bb325 MS |
1342 | mips 16 variant, but fortunately, there fewer instructions. We have |
1343 | to cope ith extensions for 16 bit instructions and a pair of actual | |
1344 | 32 bit instructions. We dont want to set a single step instruction | |
1345 | on the extend instruction either. */ | |
c906108c SS |
1346 | |
1347 | /* Lots of mips16 instruction formats */ | |
1348 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 1349 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
1350 | enum mips16_inst_fmts |
1351 | { | |
c5aa993b JM |
1352 | itype, /* 0 immediate 5,10 */ |
1353 | ritype, /* 1 5,3,8 */ | |
1354 | rrtype, /* 2 5,3,3,5 */ | |
1355 | rritype, /* 3 5,3,3,5 */ | |
1356 | rrrtype, /* 4 5,3,3,3,2 */ | |
1357 | rriatype, /* 5 5,3,3,1,4 */ | |
1358 | shifttype, /* 6 5,3,3,3,2 */ | |
1359 | i8type, /* 7 5,3,8 */ | |
1360 | i8movtype, /* 8 5,3,3,5 */ | |
1361 | i8mov32rtype, /* 9 5,3,5,3 */ | |
1362 | i64type, /* 10 5,3,8 */ | |
1363 | ri64type, /* 11 5,3,3,5 */ | |
1364 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
1365 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
1366 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
1367 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
1368 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
1369 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
1370 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
1371 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
1372 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
1373 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
1374 | }; | |
12f02c2a | 1375 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 1376 | then, only the fields which are involved in instruction extension. */ |
c906108c | 1377 | struct upk_mips16 |
6d82d43b AC |
1378 | { |
1379 | CORE_ADDR offset; | |
025bb325 | 1380 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
1381 | unsigned int regy; |
1382 | }; | |
c906108c SS |
1383 | |
1384 | ||
12f02c2a | 1385 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 1386 | for the bits which make up the immediate extension. */ |
c906108c | 1387 | |
12f02c2a AC |
1388 | static CORE_ADDR |
1389 | extended_offset (unsigned int extension) | |
c906108c | 1390 | { |
12f02c2a | 1391 | CORE_ADDR value; |
130854df | 1392 | |
4c2051c6 | 1393 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 1394 | value = value << 6; |
4c2051c6 | 1395 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 1396 | value = value << 5; |
130854df MR |
1397 | value |= extension & 0x1f; /* Extract 4:0. */ |
1398 | ||
c5aa993b | 1399 | return value; |
c906108c SS |
1400 | } |
1401 | ||
1402 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
1403 | instruction. It won't malfunction, but why make excess remote memory |
1404 | references? If the immediate operands get sign extended or something, | |
1405 | do it after the extension is performed. */ | |
c906108c | 1406 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 1407 | when the offset is to be used in relative addressing. */ |
c906108c | 1408 | |
12f02c2a | 1409 | static unsigned int |
e17a4113 | 1410 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 1411 | { |
e17a4113 | 1412 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1413 | gdb_byte buf[8]; |
025bb325 | 1414 | pc &= 0xfffffffe; /* Clear the low order bit. */ |
c5aa993b | 1415 | target_read_memory (pc, buf, 2); |
e17a4113 | 1416 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
1417 | } |
1418 | ||
1419 | static void | |
e17a4113 | 1420 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
1421 | unsigned int extension, |
1422 | unsigned int inst, | |
6d82d43b | 1423 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 1424 | { |
12f02c2a AC |
1425 | CORE_ADDR offset; |
1426 | int regx; | |
1427 | int regy; | |
1428 | switch (insn_format) | |
c906108c | 1429 | { |
c5aa993b | 1430 | case itype: |
c906108c | 1431 | { |
12f02c2a AC |
1432 | CORE_ADDR value; |
1433 | if (extension) | |
c5aa993b | 1434 | { |
4c2051c6 MR |
1435 | value = extended_offset ((extension << 16) | inst); |
1436 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
1437 | } |
1438 | else | |
c5aa993b | 1439 | { |
12f02c2a | 1440 | value = inst & 0x7ff; |
4c2051c6 | 1441 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 1442 | } |
12f02c2a AC |
1443 | offset = value; |
1444 | regx = -1; | |
1445 | regy = -1; | |
c906108c | 1446 | } |
c5aa993b JM |
1447 | break; |
1448 | case ritype: | |
1449 | case i8type: | |
025bb325 | 1450 | { /* A register identifier and an offset. */ |
c906108c | 1451 | /* Most of the fields are the same as I type but the |
025bb325 | 1452 | immediate value is of a different length. */ |
12f02c2a AC |
1453 | CORE_ADDR value; |
1454 | if (extension) | |
c906108c | 1455 | { |
4c2051c6 MR |
1456 | value = extended_offset ((extension << 16) | inst); |
1457 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 1458 | } |
c5aa993b JM |
1459 | else |
1460 | { | |
4c2051c6 MR |
1461 | value = inst & 0xff; /* 8 bits */ |
1462 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 1463 | } |
12f02c2a | 1464 | offset = value; |
4c2051c6 | 1465 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 1466 | regy = -1; |
c5aa993b | 1467 | break; |
c906108c | 1468 | } |
c5aa993b | 1469 | case jalxtype: |
c906108c | 1470 | { |
c5aa993b | 1471 | unsigned long value; |
12f02c2a AC |
1472 | unsigned int nexthalf; |
1473 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 1474 | value = value << 16; |
025bb325 MS |
1475 | nexthalf = mips_fetch_instruction (gdbarch, pc + 2); /* low bit |
1476 | still set. */ | |
c5aa993b | 1477 | value |= nexthalf; |
12f02c2a AC |
1478 | offset = value; |
1479 | regx = -1; | |
1480 | regy = -1; | |
c5aa993b | 1481 | break; |
c906108c SS |
1482 | } |
1483 | default: | |
e2e0b3e5 | 1484 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c | 1485 | } |
12f02c2a AC |
1486 | upk->offset = offset; |
1487 | upk->regx = regx; | |
1488 | upk->regy = regy; | |
c906108c SS |
1489 | } |
1490 | ||
1491 | ||
c5aa993b JM |
1492 | static CORE_ADDR |
1493 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 1494 | { |
5b652102 | 1495 | return ((offset << 2) | ((pc + 2) & (~(CORE_ADDR) 0x0fffffff))); |
c906108c SS |
1496 | } |
1497 | ||
12f02c2a | 1498 | static CORE_ADDR |
0b1b3e42 | 1499 | extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
6d82d43b | 1500 | unsigned int extension, unsigned int insn) |
c906108c | 1501 | { |
e17a4113 | 1502 | struct gdbarch *gdbarch = get_frame_arch (frame); |
12f02c2a AC |
1503 | int op = (insn >> 11); |
1504 | switch (op) | |
c906108c | 1505 | { |
6d82d43b | 1506 | case 2: /* Branch */ |
12f02c2a AC |
1507 | { |
1508 | CORE_ADDR offset; | |
1509 | struct upk_mips16 upk; | |
e17a4113 | 1510 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
4c2051c6 | 1511 | pc += (upk.offset << 1) + 2; |
12f02c2a AC |
1512 | break; |
1513 | } | |
025bb325 MS |
1514 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
1515 | instructions. */ | |
12f02c2a AC |
1516 | { |
1517 | struct upk_mips16 upk; | |
e17a4113 | 1518 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
12f02c2a AC |
1519 | pc = add_offset_16 (pc, upk.offset); |
1520 | if ((insn >> 10) & 0x01) /* Exchange mode */ | |
025bb325 | 1521 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
1522 | else |
1523 | pc |= 0x01; | |
1524 | break; | |
1525 | } | |
6d82d43b | 1526 | case 4: /* beqz */ |
12f02c2a AC |
1527 | { |
1528 | struct upk_mips16 upk; | |
1529 | int reg; | |
e17a4113 | 1530 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4c2051c6 | 1531 | reg = get_frame_register_signed (frame, mips16_to_32_reg[upk.regx]); |
12f02c2a AC |
1532 | if (reg == 0) |
1533 | pc += (upk.offset << 1) + 2; | |
1534 | else | |
1535 | pc += 2; | |
1536 | break; | |
1537 | } | |
6d82d43b | 1538 | case 5: /* bnez */ |
12f02c2a AC |
1539 | { |
1540 | struct upk_mips16 upk; | |
1541 | int reg; | |
e17a4113 | 1542 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
4c2051c6 | 1543 | reg = get_frame_register_signed (frame, mips16_to_32_reg[upk.regx]); |
12f02c2a AC |
1544 | if (reg != 0) |
1545 | pc += (upk.offset << 1) + 2; | |
1546 | else | |
1547 | pc += 2; | |
1548 | break; | |
1549 | } | |
6d82d43b | 1550 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
1551 | { |
1552 | struct upk_mips16 upk; | |
1553 | int reg; | |
e17a4113 | 1554 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 1555 | /* upk.regx contains the opcode */ |
0b1b3e42 | 1556 | reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ |
12f02c2a AC |
1557 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
1558 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
1559 | /* pc = add_offset_16(pc,upk.offset) ; */ | |
1560 | pc += (upk.offset << 1) + 2; | |
1561 | else | |
1562 | pc += 2; | |
1563 | break; | |
1564 | } | |
6d82d43b | 1565 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
1566 | { |
1567 | struct upk_mips16 upk; | |
1568 | /* upk.fmt = rrtype; */ | |
1569 | op = insn & 0x1f; | |
1570 | if (op == 0) | |
c5aa993b | 1571 | { |
12f02c2a AC |
1572 | int reg; |
1573 | upk.regx = (insn >> 8) & 0x07; | |
1574 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 MR |
1575 | if ((upk.regy & 1) == 0) |
1576 | reg = mips16_to_32_reg[upk.regx]; | |
1577 | else | |
1578 | reg = 31; /* Function return instruction. */ | |
0b1b3e42 | 1579 | pc = get_frame_register_signed (frame, reg); |
c906108c | 1580 | } |
12f02c2a | 1581 | else |
c5aa993b | 1582 | pc += 2; |
12f02c2a AC |
1583 | break; |
1584 | } | |
1585 | case 30: | |
1586 | /* This is an instruction extension. Fetch the real instruction | |
1587 | (which follows the extension) and decode things based on | |
025bb325 | 1588 | that. */ |
12f02c2a AC |
1589 | { |
1590 | pc += 2; | |
e17a4113 UW |
1591 | pc = extended_mips16_next_pc (frame, pc, insn, |
1592 | fetch_mips_16 (gdbarch, pc)); | |
12f02c2a AC |
1593 | break; |
1594 | } | |
1595 | default: | |
1596 | { | |
1597 | pc += 2; | |
1598 | break; | |
1599 | } | |
c906108c | 1600 | } |
c5aa993b | 1601 | return pc; |
12f02c2a | 1602 | } |
c906108c | 1603 | |
5a89d8aa | 1604 | static CORE_ADDR |
0b1b3e42 | 1605 | mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) |
12f02c2a | 1606 | { |
e17a4113 UW |
1607 | struct gdbarch *gdbarch = get_frame_arch (frame); |
1608 | unsigned int insn = fetch_mips_16 (gdbarch, pc); | |
0b1b3e42 | 1609 | return extended_mips16_next_pc (frame, pc, 0, insn); |
12f02c2a AC |
1610 | } |
1611 | ||
1612 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 1613 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 1614 | It works by decoding the current instruction and predicting where a |
025bb325 | 1615 | branch will go. This isnt hard because all the data is available. |
ce1f96de | 1616 | The MIPS32 and MIPS16 variants are quite different. */ |
ad527d2e | 1617 | static CORE_ADDR |
0b1b3e42 | 1618 | mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1619 | { |
91912e4d | 1620 | if (mips_pc_is_mips16 (pc)) |
0b1b3e42 | 1621 | return mips16_next_pc (frame, pc); |
c5aa993b | 1622 | else |
0b1b3e42 | 1623 | return mips32_next_pc (frame, pc); |
12f02c2a | 1624 | } |
c906108c | 1625 | |
edfae063 AC |
1626 | struct mips_frame_cache |
1627 | { | |
1628 | CORE_ADDR base; | |
1629 | struct trad_frame_saved_reg *saved_regs; | |
1630 | }; | |
1631 | ||
29639122 JB |
1632 | /* Set a register's saved stack address in temp_saved_regs. If an |
1633 | address has already been set for this register, do nothing; this | |
1634 | way we will only recognize the first save of a given register in a | |
1635 | function prologue. | |
eec63939 | 1636 | |
f57d151a UW |
1637 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
1638 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
1639 | Strictly speaking, only the second range is used as it is only second | |
1640 | range (the ABI instead of ISA registers) that comes into play when finding | |
1641 | saved registers in a frame. */ | |
eec63939 AC |
1642 | |
1643 | static void | |
74ed0bb4 MD |
1644 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
1645 | int regnum, CORE_ADDR offset) | |
eec63939 | 1646 | { |
29639122 JB |
1647 | if (this_cache != NULL |
1648 | && this_cache->saved_regs[regnum].addr == -1) | |
1649 | { | |
74ed0bb4 MD |
1650 | this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr |
1651 | = offset; | |
1652 | this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr | |
1653 | = offset; | |
29639122 | 1654 | } |
eec63939 AC |
1655 | } |
1656 | ||
eec63939 | 1657 | |
29639122 JB |
1658 | /* Fetch the immediate value from a MIPS16 instruction. |
1659 | If the previous instruction was an EXTEND, use it to extend | |
1660 | the upper bits of the immediate value. This is a helper function | |
1661 | for mips16_scan_prologue. */ | |
eec63939 | 1662 | |
29639122 JB |
1663 | static int |
1664 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
1665 | unsigned short inst, /* current instruction */ | |
1666 | int nbits, /* number of bits in imm field */ | |
1667 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 1668 | int is_signed) /* is the imm field signed? */ |
eec63939 | 1669 | { |
29639122 | 1670 | int offset; |
eec63939 | 1671 | |
29639122 JB |
1672 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
1673 | { | |
1674 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
1675 | if (offset & 0x8000) /* check for negative extend */ | |
1676 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
1677 | return offset | (inst & 0x1f); | |
1678 | } | |
eec63939 | 1679 | else |
29639122 JB |
1680 | { |
1681 | int max_imm = 1 << nbits; | |
1682 | int mask = max_imm - 1; | |
1683 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 1684 | |
29639122 JB |
1685 | offset = inst & mask; |
1686 | if (is_signed && (offset & sign_bit)) | |
1687 | offset = 0 - (max_imm - offset); | |
1688 | return offset * scale; | |
1689 | } | |
1690 | } | |
eec63939 | 1691 | |
65596487 | 1692 | |
29639122 JB |
1693 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
1694 | the associated FRAME_CACHE if not null. | |
1695 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 1696 | |
29639122 | 1697 | static CORE_ADDR |
e17a4113 UW |
1698 | mips16_scan_prologue (struct gdbarch *gdbarch, |
1699 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 1700 | struct frame_info *this_frame, |
29639122 JB |
1701 | struct mips_frame_cache *this_cache) |
1702 | { | |
1703 | CORE_ADDR cur_pc; | |
025bb325 | 1704 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
1705 | CORE_ADDR sp; |
1706 | long frame_offset = 0; /* Size of stack frame. */ | |
1707 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
1708 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 1709 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
1710 | unsigned inst = 0; /* current instruction */ |
1711 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 1712 | unsigned save_inst = 0; /* the save instruction */ |
29639122 | 1713 | int reg, offset; |
a343eb3c | 1714 | |
29639122 JB |
1715 | int extend_bytes = 0; |
1716 | int prev_extend_bytes; | |
1717 | CORE_ADDR end_prologue_addr = 0; | |
a343eb3c | 1718 | |
29639122 | 1719 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
1720 | THIS_FRAME. */ |
1721 | if (this_frame != NULL) | |
1722 | sp = get_frame_register_signed (this_frame, | |
1723 | gdbarch_num_regs (gdbarch) | |
1724 | + MIPS_SP_REGNUM); | |
29639122 JB |
1725 | else |
1726 | sp = 0; | |
eec63939 | 1727 | |
29639122 JB |
1728 | if (limit_pc > start_pc + 200) |
1729 | limit_pc = start_pc + 200; | |
eec63939 | 1730 | |
95ac2dcf | 1731 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 JB |
1732 | { |
1733 | /* Save the previous instruction. If it's an EXTEND, we'll extract | |
1734 | the immediate offset extension from it in mips16_get_imm. */ | |
1735 | prev_inst = inst; | |
eec63939 | 1736 | |
025bb325 | 1737 | /* Fetch and decode the instruction. */ |
e17a4113 | 1738 | inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc); |
eec63939 | 1739 | |
29639122 JB |
1740 | /* Normally we ignore extend instructions. However, if it is |
1741 | not followed by a valid prologue instruction, then this | |
1742 | instruction is not part of the prologue either. We must | |
1743 | remember in this case to adjust the end_prologue_addr back | |
1744 | over the extend. */ | |
1745 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
1746 | { | |
95ac2dcf | 1747 | extend_bytes = MIPS_INSN16_SIZE; |
29639122 JB |
1748 | continue; |
1749 | } | |
eec63939 | 1750 | |
29639122 JB |
1751 | prev_extend_bytes = extend_bytes; |
1752 | extend_bytes = 0; | |
eec63939 | 1753 | |
29639122 JB |
1754 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
1755 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
1756 | { | |
1757 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 1758 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
1759 | frame_offset -= offset; |
1760 | else | |
1761 | /* Exit loop if a positive stack adjustment is found, which | |
1762 | usually means that the stack cleanup code in the function | |
1763 | epilogue is reached. */ | |
1764 | break; | |
1765 | } | |
1766 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
1767 | { | |
1768 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1769 | reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | |
74ed0bb4 | 1770 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1771 | } |
1772 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
1773 | { | |
1774 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1775 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1776 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
1777 | } |
1778 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
1779 | { | |
1780 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 1781 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1782 | } |
1783 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
1784 | { | |
1785 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 1786 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
1787 | } |
1788 | else if (inst == 0x673d) /* move $s1, $sp */ | |
1789 | { | |
1790 | frame_addr = sp; | |
1791 | frame_reg = 17; | |
1792 | } | |
1793 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
1794 | { | |
1795 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
1796 | frame_addr = sp + offset; | |
1797 | frame_reg = 17; | |
1798 | frame_adjust = offset; | |
1799 | } | |
1800 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
1801 | { | |
1802 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
1803 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1804 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1805 | } |
1806 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
1807 | { | |
1808 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
1809 | reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | |
74ed0bb4 | 1810 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
1811 | } |
1812 | else if ((inst & 0xf81f) == 0xe809 | |
1813 | && (inst & 0x700) != 0x700) /* entry */ | |
025bb325 | 1814 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
1815 | else if ((inst & 0xff80) == 0x6480) /* save */ |
1816 | { | |
025bb325 | 1817 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
1818 | if (prev_extend_bytes) /* extend */ |
1819 | save_inst |= prev_inst << 16; | |
1820 | } | |
29639122 | 1821 | else if ((inst & 0xf800) == 0x1800) /* jal(x) */ |
95ac2dcf | 1822 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ |
29639122 JB |
1823 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
1824 | { | |
1825 | /* This instruction is part of the prologue, but we don't | |
1826 | need to do anything special to handle it. */ | |
1827 | } | |
1828 | else | |
1829 | { | |
1830 | /* This instruction is not an instruction typically found | |
1831 | in a prologue, so we must have reached the end of the | |
1832 | prologue. */ | |
1833 | if (end_prologue_addr == 0) | |
1834 | end_prologue_addr = cur_pc - prev_extend_bytes; | |
1835 | } | |
1836 | } | |
eec63939 | 1837 | |
29639122 JB |
1838 | /* The entry instruction is typically the first instruction in a function, |
1839 | and it stores registers at offsets relative to the value of the old SP | |
1840 | (before the prologue). But the value of the sp parameter to this | |
1841 | function is the new SP (after the prologue has been executed). So we | |
1842 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 1843 | and can calculate what the old SP must have been. */ |
29639122 JB |
1844 | if (entry_inst != 0) |
1845 | { | |
1846 | int areg_count = (entry_inst >> 8) & 7; | |
1847 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 1848 | |
29639122 JB |
1849 | /* The entry instruction always subtracts 32 from the SP. */ |
1850 | frame_offset += 32; | |
1851 | ||
1852 | /* Now we can calculate what the SP must have been at the | |
1853 | start of the function prologue. */ | |
1854 | sp += frame_offset; | |
1855 | ||
1856 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
1857 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
1858 | { | |
74ed0bb4 | 1859 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1860 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
1861 | } |
1862 | ||
1863 | /* Check if the ra register was pushed on the stack. */ | |
1864 | offset = -4; | |
1865 | if (entry_inst & 0x20) | |
1866 | { | |
74ed0bb4 | 1867 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 1868 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1869 | } |
1870 | ||
1871 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
1872 | for (reg = 16; reg < sreg_count + 16; reg++) | |
1873 | { | |
74ed0bb4 | 1874 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 1875 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
1876 | } |
1877 | } | |
1878 | ||
2207132d MR |
1879 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
1880 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
1881 | size of the frame is specified as an immediate field of instruction | |
1882 | and an extended variation exists which lets additional registers and | |
1883 | frame space to be specified. The instruction always treats registers | |
1884 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
1885 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
1886 | { | |
1887 | static int args_table[16] = { | |
1888 | 0, 0, 0, 0, 1, 1, 1, 1, | |
1889 | 2, 2, 2, 0, 3, 3, 4, -1, | |
1890 | }; | |
1891 | static int astatic_table[16] = { | |
1892 | 0, 1, 2, 3, 0, 1, 2, 3, | |
1893 | 0, 1, 2, 4, 0, 1, 0, -1, | |
1894 | }; | |
1895 | int aregs = (save_inst >> 16) & 0xf; | |
1896 | int xsregs = (save_inst >> 24) & 0x7; | |
1897 | int args = args_table[aregs]; | |
1898 | int astatic = astatic_table[aregs]; | |
1899 | long frame_size; | |
1900 | ||
1901 | if (args < 0) | |
1902 | { | |
1903 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
1904 | args = 0; | |
1905 | } | |
1906 | if (astatic < 0) | |
1907 | { | |
1908 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
1909 | astatic = 0; | |
1910 | } | |
1911 | ||
1912 | /* For standard SAVE the frame size of 0 means 128. */ | |
1913 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
1914 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
1915 | frame_size = 16; | |
1916 | frame_size *= 8; | |
1917 | frame_offset += frame_size; | |
1918 | ||
1919 | /* Now we can calculate what the SP must have been at the | |
1920 | start of the function prologue. */ | |
1921 | sp += frame_offset; | |
1922 | ||
1923 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
1924 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
1925 | { | |
74ed0bb4 | 1926 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1927 | offset += mips_abi_regsize (gdbarch); |
1928 | } | |
1929 | ||
1930 | offset = -4; | |
1931 | ||
1932 | /* Check if the RA register was pushed on the stack. */ | |
1933 | if (save_inst & 0x40) | |
1934 | { | |
74ed0bb4 | 1935 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
1936 | offset -= mips_abi_regsize (gdbarch); |
1937 | } | |
1938 | ||
1939 | /* Check if the S8 register was pushed on the stack. */ | |
1940 | if (xsregs > 6) | |
1941 | { | |
74ed0bb4 | 1942 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
1943 | offset -= mips_abi_regsize (gdbarch); |
1944 | xsregs--; | |
1945 | } | |
1946 | /* Check if S2-S7 were pushed on the stack. */ | |
1947 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
1948 | { | |
74ed0bb4 | 1949 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1950 | offset -= mips_abi_regsize (gdbarch); |
1951 | } | |
1952 | ||
1953 | /* Check if the S1 register was pushed on the stack. */ | |
1954 | if (save_inst & 0x10) | |
1955 | { | |
74ed0bb4 | 1956 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
1957 | offset -= mips_abi_regsize (gdbarch); |
1958 | } | |
1959 | /* Check if the S0 register was pushed on the stack. */ | |
1960 | if (save_inst & 0x20) | |
1961 | { | |
74ed0bb4 | 1962 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
1963 | offset -= mips_abi_regsize (gdbarch); |
1964 | } | |
1965 | ||
1966 | /* Check if A0-A3 were pushed on the stack. */ | |
1967 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
1968 | { | |
74ed0bb4 | 1969 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
1970 | offset -= mips_abi_regsize (gdbarch); |
1971 | } | |
1972 | } | |
1973 | ||
29639122 JB |
1974 | if (this_cache != NULL) |
1975 | { | |
1976 | this_cache->base = | |
b8a22b94 DJ |
1977 | (get_frame_register_signed (this_frame, |
1978 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
1979 | + frame_offset - frame_adjust); |
1980 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should | |
025bb325 | 1981 | be able to get rid of the assignment below, evetually. But it's |
29639122 | 1982 | still needed for now. */ |
72a155b4 UW |
1983 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
1984 | + mips_regnum (gdbarch)->pc] | |
1985 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; | |
29639122 JB |
1986 | } |
1987 | ||
1988 | /* If we didn't reach the end of the prologue when scanning the function | |
1989 | instructions, then set end_prologue_addr to the address of the | |
1990 | instruction immediately after the last one we scanned. */ | |
1991 | if (end_prologue_addr == 0) | |
1992 | end_prologue_addr = cur_pc; | |
1993 | ||
1994 | return end_prologue_addr; | |
eec63939 AC |
1995 | } |
1996 | ||
29639122 JB |
1997 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). |
1998 | Procedures that use the 32-bit instruction set are handled by the | |
1999 | mips_insn32 unwinder. */ | |
2000 | ||
2001 | static struct mips_frame_cache * | |
b8a22b94 | 2002 | mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) |
eec63939 | 2003 | { |
e17a4113 | 2004 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 2005 | struct mips_frame_cache *cache; |
eec63939 AC |
2006 | |
2007 | if ((*this_cache) != NULL) | |
2008 | return (*this_cache); | |
29639122 JB |
2009 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2010 | (*this_cache) = cache; | |
b8a22b94 | 2011 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 2012 | |
29639122 JB |
2013 | /* Analyze the function prologue. */ |
2014 | { | |
b8a22b94 | 2015 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2016 | CORE_ADDR start_addr; |
eec63939 | 2017 | |
29639122 JB |
2018 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2019 | if (start_addr == 0) | |
e17a4113 | 2020 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
2021 | /* We can't analyze the prologue if we couldn't find the begining |
2022 | of the function. */ | |
2023 | if (start_addr == 0) | |
2024 | return cache; | |
eec63939 | 2025 | |
e17a4113 | 2026 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2027 | } |
2028 | ||
3e8c568d | 2029 | /* gdbarch_sp_regnum contains the value and not the address. */ |
72a155b4 | 2030 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 2031 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
72a155b4 | 2032 | cache->base); |
eec63939 | 2033 | |
29639122 | 2034 | return (*this_cache); |
eec63939 AC |
2035 | } |
2036 | ||
2037 | static void | |
b8a22b94 | 2038 | mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2039 | struct frame_id *this_id) |
eec63939 | 2040 | { |
b8a22b94 | 2041 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 2042 | this_cache); |
21327321 DJ |
2043 | /* This marks the outermost frame. */ |
2044 | if (info->base == 0) | |
2045 | return; | |
b8a22b94 | 2046 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
2047 | } |
2048 | ||
b8a22b94 DJ |
2049 | static struct value * |
2050 | mips_insn16_frame_prev_register (struct frame_info *this_frame, | |
2051 | void **this_cache, int regnum) | |
eec63939 | 2052 | { |
b8a22b94 | 2053 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 | 2054 | this_cache); |
b8a22b94 DJ |
2055 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2056 | } | |
2057 | ||
2058 | static int | |
2059 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
2060 | struct frame_info *this_frame, void **this_cache) | |
2061 | { | |
2062 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2063 | if (mips_pc_is_mips16 (pc)) | |
2064 | return 1; | |
2065 | return 0; | |
eec63939 AC |
2066 | } |
2067 | ||
29639122 | 2068 | static const struct frame_unwind mips_insn16_frame_unwind = |
eec63939 AC |
2069 | { |
2070 | NORMAL_FRAME, | |
8fbca658 | 2071 | default_frame_unwind_stop_reason, |
29639122 | 2072 | mips_insn16_frame_this_id, |
b8a22b94 DJ |
2073 | mips_insn16_frame_prev_register, |
2074 | NULL, | |
2075 | mips_insn16_frame_sniffer | |
eec63939 AC |
2076 | }; |
2077 | ||
eec63939 | 2078 | static CORE_ADDR |
b8a22b94 | 2079 | mips_insn16_frame_base_address (struct frame_info *this_frame, |
29639122 | 2080 | void **this_cache) |
eec63939 | 2081 | { |
b8a22b94 | 2082 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
29639122 JB |
2083 | this_cache); |
2084 | return info->base; | |
eec63939 AC |
2085 | } |
2086 | ||
29639122 | 2087 | static const struct frame_base mips_insn16_frame_base = |
eec63939 | 2088 | { |
29639122 JB |
2089 | &mips_insn16_frame_unwind, |
2090 | mips_insn16_frame_base_address, | |
2091 | mips_insn16_frame_base_address, | |
2092 | mips_insn16_frame_base_address | |
eec63939 AC |
2093 | }; |
2094 | ||
2095 | static const struct frame_base * | |
b8a22b94 | 2096 | mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
eec63939 | 2097 | { |
b8a22b94 DJ |
2098 | CORE_ADDR pc = get_frame_pc (this_frame); |
2099 | if (mips_pc_is_mips16 (pc)) | |
29639122 | 2100 | return &mips_insn16_frame_base; |
eec63939 AC |
2101 | else |
2102 | return NULL; | |
edfae063 AC |
2103 | } |
2104 | ||
29639122 JB |
2105 | /* Mark all the registers as unset in the saved_regs array |
2106 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
2107 | ||
74ed0bb4 MD |
2108 | static void |
2109 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 2110 | { |
29639122 JB |
2111 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
2112 | return; | |
2113 | ||
2114 | { | |
74ed0bb4 | 2115 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 2116 | int i; |
64159455 | 2117 | |
29639122 JB |
2118 | for (i = 0; i < num_regs; i++) |
2119 | { | |
2120 | this_cache->saved_regs[i].addr = -1; | |
2121 | } | |
2122 | } | |
c906108c SS |
2123 | } |
2124 | ||
025bb325 | 2125 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
2126 | the associated FRAME_CACHE if not null. |
2127 | Return the address of the first instruction past the prologue. */ | |
c906108c | 2128 | |
875e1767 | 2129 | static CORE_ADDR |
e17a4113 UW |
2130 | mips32_scan_prologue (struct gdbarch *gdbarch, |
2131 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
b8a22b94 | 2132 | struct frame_info *this_frame, |
29639122 | 2133 | struct mips_frame_cache *this_cache) |
c906108c | 2134 | { |
29639122 | 2135 | CORE_ADDR cur_pc; |
025bb325 MS |
2136 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
2137 | frame-pointer. */ | |
29639122 JB |
2138 | CORE_ADDR sp; |
2139 | long frame_offset; | |
2140 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 2141 | |
29639122 JB |
2142 | CORE_ADDR end_prologue_addr = 0; |
2143 | int seen_sp_adjust = 0; | |
2144 | int load_immediate_bytes = 0; | |
db5f024e | 2145 | int in_delay_slot = 0; |
7d1e6fb8 | 2146 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 2147 | |
29639122 | 2148 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2149 | THIS_FRAME. */ |
2150 | if (this_frame != NULL) | |
2151 | sp = get_frame_register_signed (this_frame, | |
2152 | gdbarch_num_regs (gdbarch) | |
2153 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 2154 | else |
29639122 | 2155 | sp = 0; |
9022177c | 2156 | |
29639122 JB |
2157 | if (limit_pc > start_pc + 200) |
2158 | limit_pc = start_pc + 200; | |
9022177c | 2159 | |
29639122 | 2160 | restart: |
9022177c | 2161 | |
29639122 | 2162 | frame_offset = 0; |
95ac2dcf | 2163 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 2164 | { |
29639122 JB |
2165 | unsigned long inst, high_word, low_word; |
2166 | int reg; | |
9022177c | 2167 | |
025bb325 | 2168 | /* Fetch the instruction. */ |
e17a4113 | 2169 | inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc); |
9022177c | 2170 | |
29639122 JB |
2171 | /* Save some code by pre-extracting some useful fields. */ |
2172 | high_word = (inst >> 16) & 0xffff; | |
2173 | low_word = inst & 0xffff; | |
2174 | reg = high_word & 0x1f; | |
fe29b929 | 2175 | |
025bb325 | 2176 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
2177 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2178 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
2179 | { | |
025bb325 | 2180 | if (low_word & 0x8000) /* Negative stack adjustment? */ |
29639122 JB |
2181 | frame_offset += 0x10000 - low_word; |
2182 | else | |
2183 | /* Exit loop if a positive stack adjustment is found, which | |
2184 | usually means that the stack cleanup code in the function | |
2185 | epilogue is reached. */ | |
2186 | break; | |
2187 | seen_sp_adjust = 1; | |
2188 | } | |
7d1e6fb8 KB |
2189 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
2190 | && !regsize_is_64_bits) | |
29639122 | 2191 | { |
74ed0bb4 | 2192 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 | 2193 | } |
7d1e6fb8 KB |
2194 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
2195 | && regsize_is_64_bits) | |
29639122 JB |
2196 | { |
2197 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
74ed0bb4 | 2198 | set_reg_offset (gdbarch, this_cache, reg, sp + low_word); |
29639122 JB |
2199 | } |
2200 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
2201 | { | |
2202 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
2203 | if ((long) low_word != frame_offset) | |
2204 | frame_addr = sp + low_word; | |
b8a22b94 | 2205 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2206 | { |
2207 | unsigned alloca_adjust; | |
a4b8ebc8 | 2208 | |
29639122 | 2209 | frame_reg = 30; |
b8a22b94 DJ |
2210 | frame_addr = get_frame_register_signed |
2211 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2212 | |
29639122 JB |
2213 | alloca_adjust = (unsigned) (frame_addr - (sp + low_word)); |
2214 | if (alloca_adjust > 0) | |
2215 | { | |
025bb325 | 2216 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
2217 | an alloca or somethings similar. Fix sp to |
2218 | "pre-alloca" value, and try again. */ | |
2219 | sp += alloca_adjust; | |
2220 | /* Need to reset the status of all registers. Otherwise, | |
2221 | we will hit a guard that prevents the new address | |
2222 | for each register to be recomputed during the second | |
2223 | pass. */ | |
74ed0bb4 | 2224 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2225 | goto restart; |
2226 | } | |
2227 | } | |
2228 | } | |
2229 | /* move $30,$sp. With different versions of gas this will be either | |
2230 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. | |
2231 | Accept any one of these. */ | |
2232 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) | |
2233 | { | |
2234 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 2235 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
2236 | { |
2237 | unsigned alloca_adjust; | |
c906108c | 2238 | |
29639122 | 2239 | frame_reg = 30; |
b8a22b94 DJ |
2240 | frame_addr = get_frame_register_signed |
2241 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 2242 | |
29639122 JB |
2243 | alloca_adjust = (unsigned) (frame_addr - sp); |
2244 | if (alloca_adjust > 0) | |
2245 | { | |
025bb325 | 2246 | /* FP > SP + frame_size. This may be because of |
29639122 JB |
2247 | an alloca or somethings similar. Fix sp to |
2248 | "pre-alloca" value, and try again. */ | |
2249 | sp = frame_addr; | |
2250 | /* Need to reset the status of all registers. Otherwise, | |
2251 | we will hit a guard that prevents the new address | |
2252 | for each register to be recomputed during the second | |
2253 | pass. */ | |
74ed0bb4 | 2254 | reset_saved_regs (gdbarch, this_cache); |
29639122 JB |
2255 | goto restart; |
2256 | } | |
2257 | } | |
2258 | } | |
7d1e6fb8 KB |
2259 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
2260 | && !regsize_is_64_bits) | |
29639122 | 2261 | { |
74ed0bb4 | 2262 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
29639122 JB |
2263 | } |
2264 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
2265 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | |
2266 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
2267 | || high_word == 0x3c1c /* lui $gp,n */ | |
2268 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
2269 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | |
2270 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
2271 | ) | |
19080931 MR |
2272 | { |
2273 | /* These instructions are part of the prologue, but we don't | |
2274 | need to do anything special to handle them. */ | |
2275 | } | |
29639122 JB |
2276 | /* The instructions below load $at or $t0 with an immediate |
2277 | value in preparation for a stack adjustment via | |
025bb325 | 2278 | subu $sp,$sp,[$at,$t0]. These instructions could also |
29639122 JB |
2279 | initialize a local variable, so we accept them only before |
2280 | a stack adjustment instruction was seen. */ | |
2281 | else if (!seen_sp_adjust | |
19080931 MR |
2282 | && (high_word == 0x3c01 /* lui $at,n */ |
2283 | || high_word == 0x3c08 /* lui $t0,n */ | |
2284 | || high_word == 0x3421 /* ori $at,$at,n */ | |
2285 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
2286 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
2287 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
2288 | )) | |
2289 | { | |
2290 | if (end_prologue_addr == 0) | |
2291 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ | |
2292 | } | |
29639122 | 2293 | else |
19080931 MR |
2294 | { |
2295 | /* This instruction is not an instruction typically found | |
2296 | in a prologue, so we must have reached the end of the | |
2297 | prologue. */ | |
2298 | /* FIXME: brobecker/2004-10-10: Can't we just break out of this | |
2299 | loop now? Why would we need to continue scanning the function | |
2300 | instructions? */ | |
2301 | if (end_prologue_addr == 0) | |
2302 | end_prologue_addr = cur_pc; | |
2303 | ||
2304 | /* Check for branches and jumps. For now, only jump to | |
2305 | register are caught (i.e. returns). */ | |
2306 | if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | |
2307 | in_delay_slot = 1; | |
2308 | } | |
db5f024e DJ |
2309 | |
2310 | /* If the previous instruction was a jump, we must have reached | |
2311 | the end of the prologue by now. Stop scanning so that we do | |
2312 | not go past the function return. */ | |
2313 | if (in_delay_slot) | |
2314 | break; | |
a4b8ebc8 | 2315 | } |
c906108c | 2316 | |
29639122 JB |
2317 | if (this_cache != NULL) |
2318 | { | |
2319 | this_cache->base = | |
b8a22b94 DJ |
2320 | (get_frame_register_signed (this_frame, |
2321 | gdbarch_num_regs (gdbarch) + frame_reg) | |
29639122 JB |
2322 | + frame_offset); |
2323 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of | |
2324 | this assignment below, eventually. But it's still needed | |
2325 | for now. */ | |
72a155b4 UW |
2326 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2327 | + mips_regnum (gdbarch)->pc] | |
2328 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) | |
f57d151a | 2329 | + MIPS_RA_REGNUM]; |
29639122 | 2330 | } |
c906108c | 2331 | |
29639122 JB |
2332 | /* If we didn't reach the end of the prologue when scanning the function |
2333 | instructions, then set end_prologue_addr to the address of the | |
2334 | instruction immediately after the last one we scanned. */ | |
2335 | /* brobecker/2004-10-10: I don't think this would ever happen, but | |
2336 | we may as well be careful and do our best if we have a null | |
2337 | end_prologue_addr. */ | |
2338 | if (end_prologue_addr == 0) | |
2339 | end_prologue_addr = cur_pc; | |
2340 | ||
2341 | /* In a frameless function, we might have incorrectly | |
025bb325 | 2342 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
2343 | if the load immediate was not followed by a stack adjustment. */ |
2344 | if (load_immediate_bytes && !seen_sp_adjust) | |
2345 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 2346 | |
29639122 | 2347 | return end_prologue_addr; |
c906108c SS |
2348 | } |
2349 | ||
29639122 JB |
2350 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2351 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
2352 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
2353 | unwinder. */ | |
c906108c | 2354 | |
29639122 | 2355 | static struct mips_frame_cache * |
b8a22b94 | 2356 | mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 2357 | { |
e17a4113 | 2358 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 2359 | struct mips_frame_cache *cache; |
c906108c | 2360 | |
29639122 JB |
2361 | if ((*this_cache) != NULL) |
2362 | return (*this_cache); | |
c5aa993b | 2363 | |
29639122 JB |
2364 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2365 | (*this_cache) = cache; | |
b8a22b94 | 2366 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 2367 | |
29639122 JB |
2368 | /* Analyze the function prologue. */ |
2369 | { | |
b8a22b94 | 2370 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 2371 | CORE_ADDR start_addr; |
c906108c | 2372 | |
29639122 JB |
2373 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
2374 | if (start_addr == 0) | |
e17a4113 | 2375 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
2376 | /* We can't analyze the prologue if we couldn't find the begining |
2377 | of the function. */ | |
2378 | if (start_addr == 0) | |
2379 | return cache; | |
c5aa993b | 2380 | |
e17a4113 | 2381 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
29639122 JB |
2382 | } |
2383 | ||
3e8c568d | 2384 | /* gdbarch_sp_regnum contains the value and not the address. */ |
f57d151a | 2385 | trad_frame_set_value (cache->saved_regs, |
e17a4113 | 2386 | gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
f57d151a | 2387 | cache->base); |
c5aa993b | 2388 | |
29639122 | 2389 | return (*this_cache); |
c906108c SS |
2390 | } |
2391 | ||
29639122 | 2392 | static void |
b8a22b94 | 2393 | mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 | 2394 | struct frame_id *this_id) |
c906108c | 2395 | { |
b8a22b94 | 2396 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2397 | this_cache); |
21327321 DJ |
2398 | /* This marks the outermost frame. */ |
2399 | if (info->base == 0) | |
2400 | return; | |
b8a22b94 | 2401 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 2402 | } |
c906108c | 2403 | |
b8a22b94 DJ |
2404 | static struct value * |
2405 | mips_insn32_frame_prev_register (struct frame_info *this_frame, | |
2406 | void **this_cache, int regnum) | |
29639122 | 2407 | { |
b8a22b94 | 2408 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 2409 | this_cache); |
b8a22b94 DJ |
2410 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2411 | } | |
2412 | ||
2413 | static int | |
2414 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
2415 | struct frame_info *this_frame, void **this_cache) | |
2416 | { | |
2417 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2418 | if (! mips_pc_is_mips16 (pc)) | |
2419 | return 1; | |
2420 | return 0; | |
c906108c SS |
2421 | } |
2422 | ||
29639122 JB |
2423 | static const struct frame_unwind mips_insn32_frame_unwind = |
2424 | { | |
2425 | NORMAL_FRAME, | |
8fbca658 | 2426 | default_frame_unwind_stop_reason, |
29639122 | 2427 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
2428 | mips_insn32_frame_prev_register, |
2429 | NULL, | |
2430 | mips_insn32_frame_sniffer | |
29639122 | 2431 | }; |
c906108c | 2432 | |
1c645fec | 2433 | static CORE_ADDR |
b8a22b94 | 2434 | mips_insn32_frame_base_address (struct frame_info *this_frame, |
29639122 | 2435 | void **this_cache) |
c906108c | 2436 | { |
b8a22b94 | 2437 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
2438 | this_cache); |
2439 | return info->base; | |
2440 | } | |
c906108c | 2441 | |
29639122 JB |
2442 | static const struct frame_base mips_insn32_frame_base = |
2443 | { | |
2444 | &mips_insn32_frame_unwind, | |
2445 | mips_insn32_frame_base_address, | |
2446 | mips_insn32_frame_base_address, | |
2447 | mips_insn32_frame_base_address | |
2448 | }; | |
1c645fec | 2449 | |
29639122 | 2450 | static const struct frame_base * |
b8a22b94 | 2451 | mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2452 | { |
b8a22b94 DJ |
2453 | CORE_ADDR pc = get_frame_pc (this_frame); |
2454 | if (! mips_pc_is_mips16 (pc)) | |
29639122 | 2455 | return &mips_insn32_frame_base; |
a65bbe44 | 2456 | else |
29639122 JB |
2457 | return NULL; |
2458 | } | |
a65bbe44 | 2459 | |
29639122 | 2460 | static struct trad_frame_cache * |
b8a22b94 | 2461 | mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
29639122 JB |
2462 | { |
2463 | CORE_ADDR pc; | |
2464 | CORE_ADDR start_addr; | |
2465 | CORE_ADDR stack_addr; | |
2466 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
2467 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2468 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 2469 | |
29639122 JB |
2470 | if ((*this_cache) != NULL) |
2471 | return (*this_cache); | |
b8a22b94 | 2472 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 2473 | (*this_cache) = this_trad_cache; |
1c645fec | 2474 | |
29639122 | 2475 | /* The return address is in the link register. */ |
3e8c568d | 2476 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 2477 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 2478 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 2479 | |
29639122 JB |
2480 | /* Frame ID, since it's a frameless / stackless function, no stack |
2481 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 2482 | pc = get_frame_pc (this_frame); |
29639122 | 2483 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
2484 | stack_addr = get_frame_register_signed (this_frame, |
2485 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 2486 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 2487 | |
29639122 JB |
2488 | /* Assume that the frame's base is the same as the |
2489 | stack-pointer. */ | |
2490 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 2491 | |
29639122 JB |
2492 | return this_trad_cache; |
2493 | } | |
c906108c | 2494 | |
29639122 | 2495 | static void |
b8a22b94 | 2496 | mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, |
29639122 JB |
2497 | struct frame_id *this_id) |
2498 | { | |
2499 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2500 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2501 | trad_frame_get_id (this_trad_cache, this_id); |
2502 | } | |
c906108c | 2503 | |
b8a22b94 DJ |
2504 | static struct value * |
2505 | mips_stub_frame_prev_register (struct frame_info *this_frame, | |
2506 | void **this_cache, int regnum) | |
29639122 JB |
2507 | { |
2508 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
2509 | = mips_stub_frame_cache (this_frame, this_cache); |
2510 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 2511 | } |
c906108c | 2512 | |
b8a22b94 DJ |
2513 | static int |
2514 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
2515 | struct frame_info *this_frame, void **this_cache) | |
29639122 | 2516 | { |
aa6c981f | 2517 | gdb_byte dummy[4]; |
979b38e0 | 2518 | struct obj_section *s; |
b8a22b94 | 2519 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
db5f024e | 2520 | struct minimal_symbol *msym; |
979b38e0 | 2521 | |
aa6c981f | 2522 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
2523 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
2524 | return 1; | |
aa6c981f | 2525 | |
29639122 | 2526 | if (in_plt_section (pc, NULL)) |
b8a22b94 | 2527 | return 1; |
979b38e0 DJ |
2528 | |
2529 | /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */ | |
2530 | s = find_pc_section (pc); | |
2531 | ||
2532 | if (s != NULL | |
2533 | && strcmp (bfd_get_section_name (s->objfile->obfd, s->the_bfd_section), | |
2534 | ".MIPS.stubs") == 0) | |
b8a22b94 | 2535 | return 1; |
979b38e0 | 2536 | |
db5f024e DJ |
2537 | /* Calling a PIC function from a non-PIC function passes through a |
2538 | stub. The stub for foo is named ".pic.foo". */ | |
2539 | msym = lookup_minimal_symbol_by_pc (pc); | |
2540 | if (msym != NULL | |
2541 | && SYMBOL_LINKAGE_NAME (msym) != NULL | |
2542 | && strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) == 0) | |
2543 | return 1; | |
2544 | ||
b8a22b94 | 2545 | return 0; |
29639122 | 2546 | } |
c906108c | 2547 | |
b8a22b94 DJ |
2548 | static const struct frame_unwind mips_stub_frame_unwind = |
2549 | { | |
2550 | NORMAL_FRAME, | |
8fbca658 | 2551 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
2552 | mips_stub_frame_this_id, |
2553 | mips_stub_frame_prev_register, | |
2554 | NULL, | |
2555 | mips_stub_frame_sniffer | |
2556 | }; | |
2557 | ||
29639122 | 2558 | static CORE_ADDR |
b8a22b94 | 2559 | mips_stub_frame_base_address (struct frame_info *this_frame, |
29639122 JB |
2560 | void **this_cache) |
2561 | { | |
2562 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 2563 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
2564 | return trad_frame_get_this_base (this_trad_cache); |
2565 | } | |
0fce0821 | 2566 | |
29639122 JB |
2567 | static const struct frame_base mips_stub_frame_base = |
2568 | { | |
2569 | &mips_stub_frame_unwind, | |
2570 | mips_stub_frame_base_address, | |
2571 | mips_stub_frame_base_address, | |
2572 | mips_stub_frame_base_address | |
2573 | }; | |
2574 | ||
2575 | static const struct frame_base * | |
b8a22b94 | 2576 | mips_stub_frame_base_sniffer (struct frame_info *this_frame) |
29639122 | 2577 | { |
b8a22b94 | 2578 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
2579 | return &mips_stub_frame_base; |
2580 | else | |
2581 | return NULL; | |
2582 | } | |
2583 | ||
29639122 | 2584 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 2585 | |
29639122 | 2586 | static CORE_ADDR |
24568a2c | 2587 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 2588 | { |
24568a2c | 2589 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
930bd0e0 KB |
2590 | |
2591 | if (is_mips16_addr (addr)) | |
2592 | addr = unmake_mips16_addr (addr); | |
2593 | ||
29639122 JB |
2594 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
2595 | /* This hack is a work-around for existing boards using PMON, the | |
2596 | simulator, and any other 64-bit targets that doesn't have true | |
2597 | 64-bit addressing. On these targets, the upper 32 bits of | |
2598 | addresses are ignored by the hardware. Thus, the PC or SP are | |
2599 | likely to have been sign extended to all 1s by instruction | |
2600 | sequences that load 32-bit addresses. For example, a typical | |
2601 | piece of code that loads an address is this: | |
65596487 | 2602 | |
29639122 JB |
2603 | lui $r2, <upper 16 bits> |
2604 | ori $r2, <lower 16 bits> | |
65596487 | 2605 | |
29639122 JB |
2606 | But the lui sign-extends the value such that the upper 32 bits |
2607 | may be all 1s. The workaround is simply to mask off these | |
2608 | bits. In the future, gcc may be changed to support true 64-bit | |
2609 | addressing, and this masking will have to be disabled. */ | |
2610 | return addr &= 0xffffffffUL; | |
2611 | else | |
2612 | return addr; | |
65596487 JB |
2613 | } |
2614 | ||
3d5f6d12 DJ |
2615 | /* Instructions used during single-stepping of atomic sequences. */ |
2616 | #define LL_OPCODE 0x30 | |
2617 | #define LLD_OPCODE 0x34 | |
2618 | #define SC_OPCODE 0x38 | |
2619 | #define SCD_OPCODE 0x3c | |
2620 | ||
2621 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
2622 | instruction and ending with a SC/SCD instruction. If such a sequence | |
2623 | is found, attempt to step through it. A breakpoint is placed at the end of | |
2624 | the sequence. */ | |
2625 | ||
2626 | static int | |
6c95b8df PA |
2627 | deal_with_atomic_sequence (struct gdbarch *gdbarch, |
2628 | struct address_space *aspace, CORE_ADDR pc) | |
3d5f6d12 DJ |
2629 | { |
2630 | CORE_ADDR breaks[2] = {-1, -1}; | |
2631 | CORE_ADDR loc = pc; | |
2632 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
2633 | unsigned long insn; | |
2634 | int insn_count; | |
2635 | int index; | |
2636 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
2637 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
2638 | ||
2639 | if (pc & 0x01) | |
2640 | return 0; | |
2641 | ||
e17a4113 | 2642 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2643 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
2644 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
2645 | return 0; | |
2646 | ||
2647 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
2648 | instructions. */ | |
2649 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2650 | { | |
2651 | int is_branch = 0; | |
2652 | loc += MIPS_INSN32_SIZE; | |
e17a4113 | 2653 | insn = mips_fetch_instruction (gdbarch, loc); |
3d5f6d12 DJ |
2654 | |
2655 | /* Assume that there is at most one branch in the atomic | |
2656 | sequence. If a branch is found, put a breakpoint in its | |
2657 | destination address. */ | |
2658 | switch (itype_op (insn)) | |
2659 | { | |
2660 | case 0: /* SPECIAL */ | |
2661 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
025bb325 | 2662 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
2663 | break; |
2664 | case 1: /* REGIMM */ | |
a385295e MR |
2665 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
2666 | || ((itype_rt (insn) & 0x1e) == 0 | |
2667 | && itype_rs (insn) == 0)); /* BPOSGE* */ | |
3d5f6d12 DJ |
2668 | break; |
2669 | case 2: /* J */ | |
2670 | case 3: /* JAL */ | |
025bb325 | 2671 | return 0; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
2672 | case 4: /* BEQ */ |
2673 | case 5: /* BNE */ | |
2674 | case 6: /* BLEZ */ | |
2675 | case 7: /* BGTZ */ | |
2676 | case 20: /* BEQL */ | |
2677 | case 21: /* BNEL */ | |
2678 | case 22: /* BLEZL */ | |
2679 | case 23: /* BGTTL */ | |
2680 | is_branch = 1; | |
2681 | break; | |
2682 | case 17: /* COP1 */ | |
a385295e MR |
2683 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
2684 | && (itype_rt (insn) & 0x2) == 0); | |
2685 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ | |
2686 | break; | |
2687 | /* Fall through. */ | |
3d5f6d12 DJ |
2688 | case 18: /* COP2 */ |
2689 | case 19: /* COP3 */ | |
2690 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
2691 | break; | |
2692 | } | |
2693 | if (is_branch) | |
2694 | { | |
2695 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
2696 | if (last_breakpoint >= 1) | |
2697 | return 0; /* More than one branch found, fallback to the | |
2698 | standard single-step code. */ | |
2699 | breaks[1] = branch_bp; | |
2700 | last_breakpoint++; | |
2701 | } | |
2702 | ||
2703 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
2704 | break; | |
2705 | } | |
2706 | ||
2707 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
2708 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
2709 | return 0; | |
2710 | ||
2711 | loc += MIPS_INSN32_SIZE; | |
2712 | ||
2713 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
2714 | breaks[0] = loc; | |
2715 | ||
2716 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 2717 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
2718 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
2719 | last_breakpoint = 0; | |
2720 | ||
2721 | /* Effectively inserts the breakpoints. */ | |
2722 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 2723 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
3d5f6d12 DJ |
2724 | |
2725 | return 1; | |
2726 | } | |
2727 | ||
29639122 JB |
2728 | /* mips_software_single_step() is called just before we want to resume |
2729 | the inferior, if we want to single-step it but there is no hardware | |
2730 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 2731 | the target of the coming instruction and breakpoint it. */ |
29639122 | 2732 | |
e6590a1b | 2733 | int |
0b1b3e42 | 2734 | mips_software_single_step (struct frame_info *frame) |
c906108c | 2735 | { |
a6d9a66e | 2736 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 2737 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 2738 | CORE_ADDR pc, next_pc; |
65596487 | 2739 | |
0b1b3e42 | 2740 | pc = get_frame_pc (frame); |
6c95b8df | 2741 | if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
3d5f6d12 DJ |
2742 | return 1; |
2743 | ||
0b1b3e42 | 2744 | next_pc = mips_next_pc (frame, pc); |
e6590a1b | 2745 | |
6c95b8df | 2746 | insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
e6590a1b | 2747 | return 1; |
29639122 | 2748 | } |
a65bbe44 | 2749 | |
29639122 | 2750 | /* Test whether the PC points to the return instruction at the |
025bb325 | 2751 | end of a function. */ |
65596487 | 2752 | |
29639122 | 2753 | static int |
e17a4113 | 2754 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 2755 | { |
0fe7e7c8 | 2756 | if (mips_pc_is_mips16 (pc)) |
29639122 JB |
2757 | /* This mips16 case isn't necessarily reliable. Sometimes the compiler |
2758 | generates a "jr $ra"; other times it generates code to load | |
2759 | the return address from the stack to an accessible register (such | |
2760 | as $a3), then a "jr" using that register. This second case | |
2761 | is almost impossible to distinguish from an indirect jump | |
2762 | used for switch statements, so we don't even try. */ | |
e17a4113 | 2763 | return mips_fetch_instruction (gdbarch, pc) == 0xe820; /* jr $ra */ |
29639122 | 2764 | else |
e17a4113 | 2765 | return mips_fetch_instruction (gdbarch, pc) == 0x3e00008; /* jr $ra */ |
29639122 | 2766 | } |
c906108c | 2767 | |
c906108c | 2768 | |
29639122 JB |
2769 | /* This fencepost looks highly suspicious to me. Removing it also |
2770 | seems suspicious as it could affect remote debugging across serial | |
2771 | lines. */ | |
c906108c | 2772 | |
29639122 | 2773 | static CORE_ADDR |
74ed0bb4 | 2774 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
2775 | { |
2776 | CORE_ADDR start_pc; | |
2777 | CORE_ADDR fence; | |
2778 | int instlen; | |
2779 | int seen_adjsp = 0; | |
d6b48e9c | 2780 | struct inferior *inf; |
65596487 | 2781 | |
74ed0bb4 | 2782 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
2783 | start_pc = pc; |
2784 | fence = start_pc - heuristic_fence_post; | |
2785 | if (start_pc == 0) | |
2786 | return 0; | |
65596487 | 2787 | |
29639122 JB |
2788 | if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2789 | fence = VM_MIN_ADDRESS; | |
65596487 | 2790 | |
95ac2dcf | 2791 | instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; |
98b4dd94 | 2792 | |
d6b48e9c PA |
2793 | inf = current_inferior (); |
2794 | ||
025bb325 | 2795 | /* Search back for previous return. */ |
29639122 JB |
2796 | for (start_pc -= instlen;; start_pc -= instlen) |
2797 | if (start_pc < fence) | |
2798 | { | |
2799 | /* It's not clear to me why we reach this point when | |
2800 | stop_soon, but with this test, at least we | |
2801 | don't print out warnings for every child forked (eg, on | |
2802 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 2803 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
2804 | { |
2805 | static int blurb_printed = 0; | |
98b4dd94 | 2806 | |
5af949e3 UW |
2807 | warning (_("GDB can't find the start of the function at %s."), |
2808 | paddress (gdbarch, pc)); | |
29639122 JB |
2809 | |
2810 | if (!blurb_printed) | |
2811 | { | |
2812 | /* This actually happens frequently in embedded | |
2813 | development, when you first connect to a board | |
2814 | and your stack pointer and pc are nowhere in | |
2815 | particular. This message needs to give people | |
2816 | in that situation enough information to | |
2817 | determine that it's no big deal. */ | |
2818 | printf_filtered ("\n\ | |
5af949e3 | 2819 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
2820 | and thus can't determine the size of that function's stack frame.\n\ |
2821 | This means that GDB may be unable to access that stack frame, or\n\ | |
2822 | the frames below it.\n\ | |
2823 | This problem is most likely caused by an invalid program counter or\n\ | |
2824 | stack pointer.\n\ | |
2825 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 2826 | from %s for code which looks like the beginning of a\n\ |
29639122 | 2827 | function, you can increase the range of the search using the `set\n\ |
5af949e3 UW |
2828 | heuristic-fence-post' command.\n", |
2829 | paddress (gdbarch, pc), paddress (gdbarch, pc)); | |
29639122 JB |
2830 | blurb_printed = 1; |
2831 | } | |
2832 | } | |
2833 | ||
2834 | return 0; | |
2835 | } | |
0fe7e7c8 | 2836 | else if (mips_pc_is_mips16 (start_pc)) |
29639122 JB |
2837 | { |
2838 | unsigned short inst; | |
2839 | ||
2840 | /* On MIPS16, any one of the following is likely to be the | |
2841 | start of a function: | |
193774b3 MR |
2842 | extend save |
2843 | save | |
29639122 JB |
2844 | entry |
2845 | addiu sp,-n | |
2846 | daddiu sp,-n | |
025bb325 | 2847 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
e17a4113 | 2848 | inst = mips_fetch_instruction (gdbarch, start_pc); |
193774b3 MR |
2849 | if ((inst & 0xff80) == 0x6480) /* save */ |
2850 | { | |
2851 | if (start_pc - instlen >= fence) | |
2852 | { | |
e17a4113 | 2853 | inst = mips_fetch_instruction (gdbarch, start_pc - instlen); |
193774b3 MR |
2854 | if ((inst & 0xf800) == 0xf000) /* extend */ |
2855 | start_pc -= instlen; | |
2856 | } | |
2857 | break; | |
2858 | } | |
2859 | else if (((inst & 0xf81f) == 0xe809 | |
2860 | && (inst & 0x700) != 0x700) /* entry */ | |
2861 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
2862 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
2863 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
2864 | break; |
2865 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
2866 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2867 | seen_adjsp = 1; | |
2868 | else | |
2869 | seen_adjsp = 0; | |
2870 | } | |
e17a4113 | 2871 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 2872 | { |
4c7d22cb | 2873 | /* Skip return and its delay slot. */ |
95ac2dcf | 2874 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
2875 | break; |
2876 | } | |
2877 | ||
2878 | return start_pc; | |
c906108c SS |
2879 | } |
2880 | ||
6c0d6680 DJ |
2881 | struct mips_objfile_private |
2882 | { | |
2883 | bfd_size_type size; | |
2884 | char *contents; | |
2885 | }; | |
2886 | ||
f09ded24 AC |
2887 | /* According to the current ABI, should the type be passed in a |
2888 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 2889 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 2890 | FP registers and, consequently this returns false - forces FP |
025bb325 | 2891 | arguments into integer registers. */ |
f09ded24 AC |
2892 | |
2893 | static int | |
74ed0bb4 MD |
2894 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
2895 | struct type *arg_type) | |
f09ded24 AC |
2896 | { |
2897 | return ((typecode == TYPE_CODE_FLT | |
74ed0bb4 | 2898 | || (MIPS_EABI (gdbarch) |
6d82d43b AC |
2899 | && (typecode == TYPE_CODE_STRUCT |
2900 | || typecode == TYPE_CODE_UNION) | |
f09ded24 | 2901 | && TYPE_NFIELDS (arg_type) == 1 |
b2d6f210 MS |
2902 | && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) |
2903 | == TYPE_CODE_FLT)) | |
74ed0bb4 | 2904 | && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
2905 | } |
2906 | ||
49e790b0 | 2907 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 2908 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
2909 | |
2910 | static int | |
2911 | mips_type_needs_double_align (struct type *type) | |
2912 | { | |
2913 | enum type_code typecode = TYPE_CODE (type); | |
361d1df0 | 2914 | |
49e790b0 DJ |
2915 | if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) |
2916 | return 1; | |
2917 | else if (typecode == TYPE_CODE_STRUCT) | |
2918 | { | |
2919 | if (TYPE_NFIELDS (type) < 1) | |
2920 | return 0; | |
2921 | return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); | |
2922 | } | |
2923 | else if (typecode == TYPE_CODE_UNION) | |
2924 | { | |
361d1df0 | 2925 | int i, n; |
49e790b0 DJ |
2926 | |
2927 | n = TYPE_NFIELDS (type); | |
2928 | for (i = 0; i < n; i++) | |
2929 | if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) | |
2930 | return 1; | |
2931 | return 0; | |
2932 | } | |
2933 | return 0; | |
2934 | } | |
2935 | ||
dc604539 AC |
2936 | /* Adjust the address downward (direction of stack growth) so that it |
2937 | is correctly aligned for a new stack frame. */ | |
2938 | static CORE_ADDR | |
2939 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2940 | { | |
5b03f266 | 2941 | return align_down (addr, 16); |
dc604539 AC |
2942 | } |
2943 | ||
f7ab6ec6 | 2944 | static CORE_ADDR |
7d9b040b | 2945 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
2946 | struct regcache *regcache, CORE_ADDR bp_addr, |
2947 | int nargs, struct value **args, CORE_ADDR sp, | |
2948 | int struct_return, CORE_ADDR struct_addr) | |
c906108c SS |
2949 | { |
2950 | int argreg; | |
2951 | int float_argreg; | |
2952 | int argnum; | |
2953 | int len = 0; | |
2954 | int stack_offset = 0; | |
480d3dd2 | 2955 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 2956 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 2957 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
1a69e1e4 | 2958 | int regsize = mips_abi_regsize (gdbarch); |
c906108c | 2959 | |
25ab4790 AC |
2960 | /* For shared libraries, "t9" needs to point at the function |
2961 | address. */ | |
4c7d22cb | 2962 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
2963 | |
2964 | /* Set the return address register to point to the entry point of | |
2965 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 2966 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 2967 | |
c906108c | 2968 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
2969 | are properly aligned. The stack has to be at least 64-bit |
2970 | aligned even on 32-bit machines, because doubles must be 64-bit | |
2971 | aligned. For n32 and n64, stack frames need to be 128-bit | |
2972 | aligned, so we round to this widest known alignment. */ | |
2973 | ||
5b03f266 AC |
2974 | sp = align_down (sp, 16); |
2975 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 2976 | |
46e0f506 | 2977 | /* Now make space on the stack for the args. We allocate more |
c906108c | 2978 | than necessary for EABI, because the first few arguments are |
46e0f506 | 2979 | passed in registers, but that's OK. */ |
c906108c | 2980 | for (argnum = 0; argnum < nargs; argnum++) |
1a69e1e4 | 2981 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); |
5b03f266 | 2982 | sp -= align_up (len, 16); |
c906108c | 2983 | |
9ace0497 | 2984 | if (mips_debug) |
6d82d43b | 2985 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
2986 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", |
2987 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
9ace0497 | 2988 | |
c906108c | 2989 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 2990 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 2991 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 2992 | |
46e0f506 | 2993 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
c906108c | 2994 | if (struct_return) |
9ace0497 AC |
2995 | { |
2996 | if (mips_debug) | |
2997 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
2998 | "mips_eabi_push_dummy_call: " |
2999 | "struct_return reg=%d %s\n", | |
5af949e3 | 3000 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3001 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 3002 | } |
c906108c SS |
3003 | |
3004 | /* Now load as many as possible of the first arguments into | |
3005 | registers, and push the rest onto the stack. Loop thru args | |
3006 | from first to last. */ | |
3007 | for (argnum = 0; argnum < nargs; argnum++) | |
3008 | { | |
47a35522 MK |
3009 | const gdb_byte *val; |
3010 | gdb_byte valbuf[MAX_REGISTER_SIZE]; | |
ea7c478f | 3011 | struct value *arg = args[argnum]; |
4991999e | 3012 | struct type *arg_type = check_typedef (value_type (arg)); |
c906108c SS |
3013 | int len = TYPE_LENGTH (arg_type); |
3014 | enum type_code typecode = TYPE_CODE (arg_type); | |
3015 | ||
9ace0497 AC |
3016 | if (mips_debug) |
3017 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3018 | "mips_eabi_push_dummy_call: %d len=%d type=%d", |
acdb74a0 | 3019 | argnum + 1, len, (int) typecode); |
9ace0497 | 3020 | |
930bd0e0 KB |
3021 | /* Function pointer arguments to mips16 code need to be made into |
3022 | mips16 pointers. */ | |
3023 | if (typecode == TYPE_CODE_PTR | |
3024 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
3025 | { | |
3026 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
3027 | len, byte_order); | |
3028 | if (mips_pc_is_mips16 (addr)) | |
3029 | { | |
3030 | store_signed_integer (valbuf, len, byte_order, | |
3031 | make_mips16_addr (addr)); | |
3032 | val = valbuf; | |
3033 | } | |
3034 | else | |
3035 | val = value_contents (arg); | |
3036 | } | |
c906108c | 3037 | /* The EABI passes structures that do not fit in a register by |
46e0f506 | 3038 | reference. */ |
930bd0e0 | 3039 | else if (len > regsize |
9ace0497 | 3040 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 3041 | { |
e17a4113 UW |
3042 | store_unsigned_integer (valbuf, regsize, byte_order, |
3043 | value_address (arg)); | |
c906108c | 3044 | typecode = TYPE_CODE_PTR; |
1a69e1e4 | 3045 | len = regsize; |
c906108c | 3046 | val = valbuf; |
9ace0497 AC |
3047 | if (mips_debug) |
3048 | fprintf_unfiltered (gdb_stdlog, " push"); | |
c906108c SS |
3049 | } |
3050 | else | |
47a35522 | 3051 | val = value_contents (arg); |
c906108c SS |
3052 | |
3053 | /* 32-bit ABIs always start floating point arguments in an | |
acdb74a0 AC |
3054 | even-numbered floating point register. Round the FP register |
3055 | up before the check to see if there are any FP registers | |
46e0f506 MS |
3056 | left. Non MIPS_EABI targets also pass the FP in the integer |
3057 | registers so also round up normal registers. */ | |
74ed0bb4 | 3058 | if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
3059 | { |
3060 | if ((float_argreg & 1)) | |
3061 | float_argreg++; | |
3062 | } | |
c906108c SS |
3063 | |
3064 | /* Floating point arguments passed in registers have to be | |
3065 | treated specially. On 32-bit architectures, doubles | |
c5aa993b JM |
3066 | are passed in register pairs; the even register gets |
3067 | the low word, and the odd register gets the high word. | |
3068 | On non-EABI processors, the first two floating point arguments are | |
3069 | also copied to general registers, because MIPS16 functions | |
3070 | don't use float registers for arguments. This duplication of | |
3071 | arguments in general registers can't hurt non-MIPS16 functions | |
3072 | because those registers are normally skipped. */ | |
1012bd0e EZ |
3073 | /* MIPS_EABI squeezes a struct that contains a single floating |
3074 | point value into an FP register instead of pushing it onto the | |
46e0f506 | 3075 | stack. */ |
74ed0bb4 MD |
3076 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3077 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
c906108c | 3078 | { |
6da397e0 KB |
3079 | /* EABI32 will pass doubles in consecutive registers, even on |
3080 | 64-bit cores. At one time, we used to check the size of | |
3081 | `float_argreg' to determine whether or not to pass doubles | |
3082 | in consecutive registers, but this is not sufficient for | |
3083 | making the ABI determination. */ | |
3084 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 3085 | { |
72a155b4 | 3086 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3087 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 3088 | long regval; |
c906108c SS |
3089 | |
3090 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
3091 | regval = extract_signed_integer (val + low_offset, |
3092 | 4, byte_order); | |
9ace0497 | 3093 | if (mips_debug) |
acdb74a0 | 3094 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3095 | float_argreg, phex (regval, 4)); |
a8852dc5 | 3096 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3097 | |
3098 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
3099 | regval = extract_signed_integer (val + 4 - low_offset, |
3100 | 4, byte_order); | |
9ace0497 | 3101 | if (mips_debug) |
acdb74a0 | 3102 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3103 | float_argreg, phex (regval, 4)); |
a8852dc5 | 3104 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3105 | } |
3106 | else | |
3107 | { | |
3108 | /* This is a floating point value that fits entirely | |
3109 | in a single register. */ | |
53a5351d | 3110 | /* On 32 bit ABI's the float_argreg is further adjusted |
6d82d43b | 3111 | above to ensure that it is even register aligned. */ |
a8852dc5 | 3112 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 3113 | if (mips_debug) |
acdb74a0 | 3114 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
9ace0497 | 3115 | float_argreg, phex (regval, len)); |
a8852dc5 | 3116 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
3117 | } |
3118 | } | |
3119 | else | |
3120 | { | |
3121 | /* Copy the argument to general registers or the stack in | |
3122 | register-sized pieces. Large arguments are split between | |
3123 | registers and stack. */ | |
1a69e1e4 DJ |
3124 | /* Note: structs whose size is not a multiple of regsize |
3125 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3126 | them in registers where gcc sometimes puts them on the |
3127 | stack. For maximum compatibility, we will put them in | |
3128 | both places. */ | |
1a69e1e4 | 3129 | int odd_sized_struct = (len > regsize && len % regsize != 0); |
46e0f506 | 3130 | |
f09ded24 | 3131 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3132 | register are only written to memory. */ |
c906108c SS |
3133 | while (len > 0) |
3134 | { | |
ebafbe83 | 3135 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 3136 | int stack_used_p = 0; |
1a69e1e4 | 3137 | int partial_len = (len < regsize ? len : regsize); |
c906108c | 3138 | |
acdb74a0 AC |
3139 | if (mips_debug) |
3140 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3141 | partial_len); | |
3142 | ||
566f0f7a | 3143 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3144 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
f09ded24 | 3145 | || odd_sized_struct |
74ed0bb4 | 3146 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 3147 | { |
c906108c | 3148 | /* Should shorter than int integer values be |
025bb325 | 3149 | promoted to int before being stored? */ |
c906108c | 3150 | int longword_offset = 0; |
9ace0497 | 3151 | CORE_ADDR addr; |
566f0f7a | 3152 | stack_used_p = 1; |
72a155b4 | 3153 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 3154 | { |
1a69e1e4 | 3155 | if (regsize == 8 |
480d3dd2 AC |
3156 | && (typecode == TYPE_CODE_INT |
3157 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 3158 | || typecode == TYPE_CODE_FLT) && len <= 4) |
1a69e1e4 | 3159 | longword_offset = regsize - len; |
480d3dd2 AC |
3160 | else if ((typecode == TYPE_CODE_STRUCT |
3161 | || typecode == TYPE_CODE_UNION) | |
1a69e1e4 DJ |
3162 | && TYPE_LENGTH (arg_type) < regsize) |
3163 | longword_offset = regsize - len; | |
7a292a7a | 3164 | } |
c5aa993b | 3165 | |
9ace0497 AC |
3166 | if (mips_debug) |
3167 | { | |
5af949e3 UW |
3168 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3169 | paddress (gdbarch, stack_offset)); | |
3170 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3171 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 3172 | } |
361d1df0 | 3173 | |
9ace0497 AC |
3174 | addr = sp + stack_offset + longword_offset; |
3175 | ||
3176 | if (mips_debug) | |
3177 | { | |
3178 | int i; | |
5af949e3 UW |
3179 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3180 | paddress (gdbarch, addr)); | |
9ace0497 AC |
3181 | for (i = 0; i < partial_len; i++) |
3182 | { | |
6d82d43b | 3183 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 | 3184 | val[i] & 0xff); |
9ace0497 AC |
3185 | } |
3186 | } | |
3187 | write_memory (addr, val, partial_len); | |
c906108c SS |
3188 | } |
3189 | ||
f09ded24 AC |
3190 | /* Note!!! This is NOT an else clause. Odd sized |
3191 | structs may go thru BOTH paths. Floating point | |
46e0f506 | 3192 | arguments will not. */ |
566f0f7a | 3193 | /* Write this portion of the argument to a general |
6d82d43b | 3194 | purpose register. */ |
74ed0bb4 MD |
3195 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) |
3196 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) | |
c906108c | 3197 | { |
6d82d43b | 3198 | LONGEST regval = |
a8852dc5 | 3199 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 3200 | |
9ace0497 | 3201 | if (mips_debug) |
acdb74a0 | 3202 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", |
9ace0497 | 3203 | argreg, |
1a69e1e4 | 3204 | phex (regval, regsize)); |
a8852dc5 | 3205 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 3206 | argreg++; |
c906108c | 3207 | } |
c5aa993b | 3208 | |
c906108c SS |
3209 | len -= partial_len; |
3210 | val += partial_len; | |
3211 | ||
b021a221 MS |
3212 | /* Compute the offset into the stack at which we will |
3213 | copy the next parameter. | |
566f0f7a | 3214 | |
566f0f7a | 3215 | In the new EABI (and the NABI32), the stack_offset |
46e0f506 | 3216 | only needs to be adjusted when it has been used. */ |
c906108c | 3217 | |
46e0f506 | 3218 | if (stack_used_p) |
1a69e1e4 | 3219 | stack_offset += align_up (partial_len, regsize); |
c906108c SS |
3220 | } |
3221 | } | |
9ace0497 AC |
3222 | if (mips_debug) |
3223 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
c906108c SS |
3224 | } |
3225 | ||
f10683bb | 3226 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3227 | |
0f71a2f6 JM |
3228 | /* Return adjusted stack pointer. */ |
3229 | return sp; | |
3230 | } | |
3231 | ||
a1f5b845 | 3232 | /* Determine the return value convention being used. */ |
6d82d43b | 3233 | |
9c8fdbfa | 3234 | static enum return_value_convention |
c055b101 | 3235 | mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 3236 | struct type *type, struct regcache *regcache, |
47a35522 | 3237 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 3238 | { |
609ba780 JM |
3239 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3240 | int fp_return_type = 0; | |
3241 | int offset, regnum, xfer; | |
3242 | ||
9c8fdbfa AC |
3243 | if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
3244 | return RETURN_VALUE_STRUCT_CONVENTION; | |
609ba780 JM |
3245 | |
3246 | /* Floating point type? */ | |
3247 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3248 | { | |
3249 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
3250 | fp_return_type = 1; | |
3251 | /* Structs with a single field of float type | |
3252 | are returned in a floating point register. */ | |
3253 | if ((TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3254 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
3255 | && TYPE_NFIELDS (type) == 1) | |
3256 | { | |
3257 | struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); | |
3258 | ||
3259 | if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) | |
3260 | fp_return_type = 1; | |
3261 | } | |
3262 | } | |
3263 | ||
3264 | if (fp_return_type) | |
3265 | { | |
3266 | /* A floating-point value belongs in the least significant part | |
3267 | of FP0/FP1. */ | |
3268 | if (mips_debug) | |
3269 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
3270 | regnum = mips_regnum (gdbarch)->fp0; | |
3271 | } | |
3272 | else | |
3273 | { | |
3274 | /* An integer value goes in V0/V1. */ | |
3275 | if (mips_debug) | |
3276 | fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); | |
3277 | regnum = MIPS_V0_REGNUM; | |
3278 | } | |
3279 | for (offset = 0; | |
3280 | offset < TYPE_LENGTH (type); | |
3281 | offset += mips_abi_regsize (gdbarch), regnum++) | |
3282 | { | |
3283 | xfer = mips_abi_regsize (gdbarch); | |
3284 | if (offset + xfer > TYPE_LENGTH (type)) | |
3285 | xfer = TYPE_LENGTH (type) - offset; | |
3286 | mips_xfer_register (gdbarch, regcache, | |
3287 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
3288 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
3289 | offset); | |
3290 | } | |
3291 | ||
9c8fdbfa | 3292 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
3293 | } |
3294 | ||
6d82d43b AC |
3295 | |
3296 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 3297 | |
8d26208a DJ |
3298 | /* Search for a naturally aligned double at OFFSET inside a struct |
3299 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
3300 | registers. */ | |
3301 | ||
3302 | static int | |
74ed0bb4 MD |
3303 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
3304 | int offset) | |
8d26208a DJ |
3305 | { |
3306 | int i; | |
3307 | ||
3308 | if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) | |
3309 | return 0; | |
3310 | ||
74ed0bb4 | 3311 | if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
3312 | return 0; |
3313 | ||
3314 | if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) | |
3315 | return 0; | |
3316 | ||
3317 | for (i = 0; i < TYPE_NFIELDS (arg_type); i++) | |
3318 | { | |
3319 | int pos; | |
3320 | struct type *field_type; | |
3321 | ||
3322 | /* We're only looking at normal fields. */ | |
5bc60cfb | 3323 | if (field_is_static (&TYPE_FIELD (arg_type, i)) |
8d26208a DJ |
3324 | || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) |
3325 | continue; | |
3326 | ||
3327 | /* If we have gone past the offset, there is no double to pass. */ | |
3328 | pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; | |
3329 | if (pos > offset) | |
3330 | return 0; | |
3331 | ||
3332 | field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); | |
3333 | ||
3334 | /* If this field is entirely before the requested offset, go | |
3335 | on to the next one. */ | |
3336 | if (pos + TYPE_LENGTH (field_type) <= offset) | |
3337 | continue; | |
3338 | ||
3339 | /* If this is our special aligned double, we can stop. */ | |
3340 | if (TYPE_CODE (field_type) == TYPE_CODE_FLT | |
3341 | && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) | |
3342 | return 1; | |
3343 | ||
3344 | /* This field starts at or before the requested offset, and | |
3345 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 3346 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
3347 | } |
3348 | ||
3349 | return 0; | |
3350 | } | |
3351 | ||
f7ab6ec6 | 3352 | static CORE_ADDR |
7d9b040b | 3353 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3354 | struct regcache *regcache, CORE_ADDR bp_addr, |
3355 | int nargs, struct value **args, CORE_ADDR sp, | |
3356 | int struct_return, CORE_ADDR struct_addr) | |
cb3d25d1 MS |
3357 | { |
3358 | int argreg; | |
3359 | int float_argreg; | |
3360 | int argnum; | |
3361 | int len = 0; | |
3362 | int stack_offset = 0; | |
480d3dd2 | 3363 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3364 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3365 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 3366 | |
25ab4790 AC |
3367 | /* For shared libraries, "t9" needs to point at the function |
3368 | address. */ | |
4c7d22cb | 3369 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
3370 | |
3371 | /* Set the return address register to point to the entry point of | |
3372 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3373 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 3374 | |
cb3d25d1 MS |
3375 | /* First ensure that the stack and structure return address (if any) |
3376 | are properly aligned. The stack has to be at least 64-bit | |
3377 | aligned even on 32-bit machines, because doubles must be 64-bit | |
3378 | aligned. For n32 and n64, stack frames need to be 128-bit | |
3379 | aligned, so we round to this widest known alignment. */ | |
3380 | ||
5b03f266 AC |
3381 | sp = align_down (sp, 16); |
3382 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
3383 | |
3384 | /* Now make space on the stack for the args. */ | |
3385 | for (argnum = 0; argnum < nargs; argnum++) | |
1a69e1e4 | 3386 | len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); |
5b03f266 | 3387 | sp -= align_up (len, 16); |
cb3d25d1 MS |
3388 | |
3389 | if (mips_debug) | |
6d82d43b | 3390 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3391 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", |
3392 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
cb3d25d1 MS |
3393 | |
3394 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3395 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3396 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 3397 | |
46e0f506 | 3398 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cb3d25d1 MS |
3399 | if (struct_return) |
3400 | { | |
3401 | if (mips_debug) | |
3402 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
3403 | "mips_n32n64_push_dummy_call: " |
3404 | "struct_return reg=%d %s\n", | |
5af949e3 | 3405 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3406 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
3407 | } |
3408 | ||
3409 | /* Now load as many as possible of the first arguments into | |
3410 | registers, and push the rest onto the stack. Loop thru args | |
3411 | from first to last. */ | |
3412 | for (argnum = 0; argnum < nargs; argnum++) | |
3413 | { | |
47a35522 | 3414 | const gdb_byte *val; |
cb3d25d1 | 3415 | struct value *arg = args[argnum]; |
4991999e | 3416 | struct type *arg_type = check_typedef (value_type (arg)); |
cb3d25d1 MS |
3417 | int len = TYPE_LENGTH (arg_type); |
3418 | enum type_code typecode = TYPE_CODE (arg_type); | |
3419 | ||
3420 | if (mips_debug) | |
3421 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3422 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", |
cb3d25d1 MS |
3423 | argnum + 1, len, (int) typecode); |
3424 | ||
47a35522 | 3425 | val = value_contents (arg); |
cb3d25d1 | 3426 | |
5b68030f JM |
3427 | /* A 128-bit long double value requires an even-odd pair of |
3428 | floating-point registers. */ | |
3429 | if (len == 16 | |
3430 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
3431 | && (float_argreg & 1)) | |
3432 | { | |
3433 | float_argreg++; | |
3434 | argreg++; | |
3435 | } | |
3436 | ||
74ed0bb4 MD |
3437 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3438 | && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) | |
cb3d25d1 MS |
3439 | { |
3440 | /* This is a floating point value that fits entirely | |
5b68030f JM |
3441 | in a single register or a pair of registers. */ |
3442 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 3443 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 MS |
3444 | if (mips_debug) |
3445 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
5b68030f | 3446 | float_argreg, phex (regval, reglen)); |
8d26208a | 3447 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
3448 | |
3449 | if (mips_debug) | |
3450 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
5b68030f | 3451 | argreg, phex (regval, reglen)); |
9c9acae0 | 3452 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
3453 | float_argreg++; |
3454 | argreg++; | |
5b68030f JM |
3455 | if (len == 16) |
3456 | { | |
e17a4113 UW |
3457 | regval = extract_unsigned_integer (val + reglen, |
3458 | reglen, byte_order); | |
5b68030f JM |
3459 | if (mips_debug) |
3460 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3461 | float_argreg, phex (regval, reglen)); | |
3462 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); | |
3463 | ||
3464 | if (mips_debug) | |
3465 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3466 | argreg, phex (regval, reglen)); | |
3467 | regcache_cooked_write_unsigned (regcache, argreg, regval); | |
3468 | float_argreg++; | |
3469 | argreg++; | |
3470 | } | |
cb3d25d1 MS |
3471 | } |
3472 | else | |
3473 | { | |
3474 | /* Copy the argument to general registers or the stack in | |
3475 | register-sized pieces. Large arguments are split between | |
3476 | registers and stack. */ | |
ab2e1992 MR |
3477 | /* For N32/N64, structs, unions, or other composite types are |
3478 | treated as a sequence of doublewords, and are passed in integer | |
3479 | or floating point registers as though they were simple scalar | |
3480 | parameters to the extent that they fit, with any excess on the | |
3481 | stack packed according to the normal memory layout of the | |
3482 | object. | |
3483 | The caller does not reserve space for the register arguments; | |
3484 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 3485 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 3486 | register are only written to memory. */ |
cb3d25d1 MS |
3487 | while (len > 0) |
3488 | { | |
ad018eee | 3489 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 3490 | int stack_used_p = 0; |
1a69e1e4 | 3491 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
3492 | |
3493 | if (mips_debug) | |
3494 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3495 | partial_len); | |
3496 | ||
74ed0bb4 MD |
3497 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
3498 | gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); | |
8d26208a | 3499 | |
cb3d25d1 | 3500 | /* Write this portion of the argument to the stack. */ |
74ed0bb4 | 3501 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 MS |
3502 | { |
3503 | /* Should shorter than int integer values be | |
025bb325 | 3504 | promoted to int before being stored? */ |
cb3d25d1 MS |
3505 | int longword_offset = 0; |
3506 | CORE_ADDR addr; | |
3507 | stack_used_p = 1; | |
72a155b4 | 3508 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 3509 | { |
1a69e1e4 | 3510 | if ((typecode == TYPE_CODE_INT |
5b68030f | 3511 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
3512 | && len <= 4) |
3513 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
3514 | } |
3515 | ||
3516 | if (mips_debug) | |
3517 | { | |
5af949e3 UW |
3518 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
3519 | paddress (gdbarch, stack_offset)); | |
3520 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
3521 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
3522 | } |
3523 | ||
3524 | addr = sp + stack_offset + longword_offset; | |
3525 | ||
3526 | if (mips_debug) | |
3527 | { | |
3528 | int i; | |
5af949e3 UW |
3529 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
3530 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
3531 | for (i = 0; i < partial_len; i++) |
3532 | { | |
6d82d43b | 3533 | fprintf_unfiltered (gdb_stdlog, "%02x", |
cb3d25d1 MS |
3534 | val[i] & 0xff); |
3535 | } | |
3536 | } | |
3537 | write_memory (addr, val, partial_len); | |
3538 | } | |
3539 | ||
3540 | /* Note!!! This is NOT an else clause. Odd sized | |
8d26208a | 3541 | structs may go thru BOTH paths. */ |
cb3d25d1 | 3542 | /* Write this portion of the argument to a general |
6d82d43b | 3543 | purpose register. */ |
74ed0bb4 | 3544 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
cb3d25d1 | 3545 | { |
5863b5d5 MR |
3546 | LONGEST regval; |
3547 | ||
3548 | /* Sign extend pointers, 32-bit integers and signed | |
3549 | 16-bit and 8-bit integers; everything else is taken | |
3550 | as is. */ | |
3551 | ||
3552 | if ((partial_len == 4 | |
3553 | && (typecode == TYPE_CODE_PTR | |
3554 | || typecode == TYPE_CODE_INT)) | |
3555 | || (partial_len < 4 | |
3556 | && typecode == TYPE_CODE_INT | |
3557 | && !TYPE_UNSIGNED (arg_type))) | |
e17a4113 UW |
3558 | regval = extract_signed_integer (val, partial_len, |
3559 | byte_order); | |
5863b5d5 | 3560 | else |
e17a4113 UW |
3561 | regval = extract_unsigned_integer (val, partial_len, |
3562 | byte_order); | |
cb3d25d1 MS |
3563 | |
3564 | /* A non-floating-point argument being passed in a | |
3565 | general register. If a struct or union, and if | |
3566 | the remaining length is smaller than the register | |
3567 | size, we have to adjust the register value on | |
3568 | big endian targets. | |
3569 | ||
3570 | It does not seem to be necessary to do the | |
1a69e1e4 | 3571 | same for integral types. */ |
cb3d25d1 | 3572 | |
72a155b4 | 3573 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 3574 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
3575 | && (typecode == TYPE_CODE_STRUCT |
3576 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 3577 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 3578 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
3579 | |
3580 | if (mips_debug) | |
3581 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
3582 | argreg, | |
1a69e1e4 | 3583 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 3584 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 3585 | |
74ed0bb4 | 3586 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
8d26208a DJ |
3587 | TYPE_LENGTH (arg_type) - len)) |
3588 | { | |
3589 | if (mips_debug) | |
3590 | fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", | |
3591 | float_argreg, | |
3592 | phex (regval, MIPS64_REGSIZE)); | |
3593 | regcache_cooked_write_unsigned (regcache, float_argreg, | |
3594 | regval); | |
3595 | } | |
3596 | ||
3597 | float_argreg++; | |
cb3d25d1 MS |
3598 | argreg++; |
3599 | } | |
3600 | ||
3601 | len -= partial_len; | |
3602 | val += partial_len; | |
3603 | ||
b021a221 MS |
3604 | /* Compute the offset into the stack at which we will |
3605 | copy the next parameter. | |
cb3d25d1 MS |
3606 | |
3607 | In N32 (N64?), the stack_offset only needs to be | |
3608 | adjusted when it has been used. */ | |
3609 | ||
3610 | if (stack_used_p) | |
1a69e1e4 | 3611 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
3612 | } |
3613 | } | |
3614 | if (mips_debug) | |
3615 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
3616 | } | |
3617 | ||
f10683bb | 3618 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 3619 | |
cb3d25d1 MS |
3620 | /* Return adjusted stack pointer. */ |
3621 | return sp; | |
3622 | } | |
3623 | ||
6d82d43b | 3624 | static enum return_value_convention |
c055b101 | 3625 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
6d82d43b | 3626 | struct type *type, struct regcache *regcache, |
47a35522 | 3627 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 3628 | { |
72a155b4 | 3629 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
b18bb924 MR |
3630 | |
3631 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
3632 | ||
3633 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
3634 | if needed), as appropriate for the type. Composite results (struct, | |
3635 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
3636 | following rules: | |
3637 | ||
3638 | * A struct with only one or two floating point fields is returned in $f0 | |
3639 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
3640 | case. | |
3641 | ||
f08877ba | 3642 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
3643 | $2 (first 64 bits) and $3 (remainder, if necessary). |
3644 | ||
3645 | * Larger composite results are handled by converting the function to a | |
3646 | procedure with an implicit first parameter, which is a pointer to an area | |
3647 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
3648 | that all composite results be handled by conversion to implicit first | |
3649 | parameters. The MIPS/SGI Fortran implementation has always made a | |
3650 | specific exception to return COMPLEX results in the floating point | |
3651 | registers.] */ | |
3652 | ||
f08877ba | 3653 | if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) |
6d82d43b | 3654 | return RETURN_VALUE_STRUCT_CONVENTION; |
d05f6826 DJ |
3655 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3656 | && TYPE_LENGTH (type) == 16 | |
3657 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3658 | { | |
3659 | /* A 128-bit floating-point value fills both $f0 and $f2. The | |
3660 | two registers are used in the same as memory order, so the | |
3661 | eight bytes with the lower memory address are in $f0. */ | |
3662 | if (mips_debug) | |
3663 | fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | |
ba32f989 | 3664 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3665 | gdbarch_num_regs (gdbarch) |
3666 | + mips_regnum (gdbarch)->fp0, | |
3667 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3668 | readbuf, writebuf, 0); |
ba32f989 | 3669 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3670 | gdbarch_num_regs (gdbarch) |
3671 | + mips_regnum (gdbarch)->fp0 + 2, | |
3672 | 8, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 3673 | readbuf ? readbuf + 8 : readbuf, |
d05f6826 DJ |
3674 | writebuf ? writebuf + 8 : writebuf, 0); |
3675 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3676 | } | |
6d82d43b AC |
3677 | else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3678 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
3679 | { | |
59aa1faa | 3680 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b AC |
3681 | if (mips_debug) |
3682 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 3683 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
3684 | gdbarch_num_regs (gdbarch) |
3685 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 3686 | TYPE_LENGTH (type), |
72a155b4 | 3687 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 3688 | readbuf, writebuf, 0); |
6d82d43b AC |
3689 | return RETURN_VALUE_REGISTER_CONVENTION; |
3690 | } | |
3691 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
3692 | && TYPE_NFIELDS (type) <= 2 | |
3693 | && TYPE_NFIELDS (type) >= 1 | |
3694 | && ((TYPE_NFIELDS (type) == 1 | |
b18bb924 | 3695 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b AC |
3696 | == TYPE_CODE_FLT)) |
3697 | || (TYPE_NFIELDS (type) == 2 | |
b18bb924 | 3698 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
6d82d43b | 3699 | == TYPE_CODE_FLT) |
b18bb924 | 3700 | && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) |
5b68030f | 3701 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
3702 | { |
3703 | /* A struct that contains one or two floats. Each value is part | |
3704 | in the least significant part of their floating point | |
5b68030f | 3705 | register (or GPR, for soft float). */ |
6d82d43b AC |
3706 | int regnum; |
3707 | int field; | |
5b68030f JM |
3708 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
3709 | ? mips_regnum (gdbarch)->fp0 | |
3710 | : MIPS_V0_REGNUM); | |
6d82d43b AC |
3711 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
3712 | { | |
3713 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
3714 | / TARGET_CHAR_BIT); | |
3715 | if (mips_debug) | |
3716 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
3717 | offset); | |
5b68030f JM |
3718 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) |
3719 | { | |
3720 | /* A 16-byte long double field goes in two consecutive | |
3721 | registers. */ | |
3722 | mips_xfer_register (gdbarch, regcache, | |
3723 | gdbarch_num_regs (gdbarch) + regnum, | |
3724 | 8, | |
3725 | gdbarch_byte_order (gdbarch), | |
3726 | readbuf, writebuf, offset); | |
3727 | mips_xfer_register (gdbarch, regcache, | |
3728 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
3729 | 8, | |
3730 | gdbarch_byte_order (gdbarch), | |
3731 | readbuf, writebuf, offset + 8); | |
3732 | } | |
3733 | else | |
3734 | mips_xfer_register (gdbarch, regcache, | |
3735 | gdbarch_num_regs (gdbarch) + regnum, | |
3736 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), | |
3737 | gdbarch_byte_order (gdbarch), | |
3738 | readbuf, writebuf, offset); | |
6d82d43b AC |
3739 | } |
3740 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3741 | } | |
3742 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
f08877ba JB |
3743 | || TYPE_CODE (type) == TYPE_CODE_UNION |
3744 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
6d82d43b | 3745 | { |
f08877ba | 3746 | /* A composite type. Extract the left justified value, |
6d82d43b AC |
3747 | regardless of the byte order. I.e. DO NOT USE |
3748 | mips_xfer_lower. */ | |
3749 | int offset; | |
3750 | int regnum; | |
4c7d22cb | 3751 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3752 | offset < TYPE_LENGTH (type); |
72a155b4 | 3753 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3754 | { |
72a155b4 | 3755 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3756 | if (offset + xfer > TYPE_LENGTH (type)) |
3757 | xfer = TYPE_LENGTH (type) - offset; | |
3758 | if (mips_debug) | |
3759 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
3760 | offset, xfer, regnum); | |
ba32f989 DJ |
3761 | mips_xfer_register (gdbarch, regcache, |
3762 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
3763 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
3764 | offset); | |
6d82d43b AC |
3765 | } |
3766 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3767 | } | |
3768 | else | |
3769 | { | |
3770 | /* A scalar extract each part but least-significant-byte | |
3771 | justified. */ | |
3772 | int offset; | |
3773 | int regnum; | |
4c7d22cb | 3774 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 3775 | offset < TYPE_LENGTH (type); |
72a155b4 | 3776 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 3777 | { |
72a155b4 | 3778 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
3779 | if (offset + xfer > TYPE_LENGTH (type)) |
3780 | xfer = TYPE_LENGTH (type) - offset; | |
3781 | if (mips_debug) | |
3782 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
3783 | offset, xfer, regnum); | |
ba32f989 DJ |
3784 | mips_xfer_register (gdbarch, regcache, |
3785 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 3786 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 3787 | readbuf, writebuf, offset); |
6d82d43b AC |
3788 | } |
3789 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3790 | } | |
3791 | } | |
3792 | ||
3793 | /* O32 ABI stuff. */ | |
3794 | ||
3795 | static CORE_ADDR | |
7d9b040b | 3796 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
3797 | struct regcache *regcache, CORE_ADDR bp_addr, |
3798 | int nargs, struct value **args, CORE_ADDR sp, | |
3799 | int struct_return, CORE_ADDR struct_addr) | |
3800 | { | |
3801 | int argreg; | |
3802 | int float_argreg; | |
3803 | int argnum; | |
3804 | int len = 0; | |
3805 | int stack_offset = 0; | |
3806 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 3807 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 3808 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
3809 | |
3810 | /* For shared libraries, "t9" needs to point at the function | |
3811 | address. */ | |
4c7d22cb | 3812 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
3813 | |
3814 | /* Set the return address register to point to the entry point of | |
3815 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 3816 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
3817 | |
3818 | /* First ensure that the stack and structure return address (if any) | |
3819 | are properly aligned. The stack has to be at least 64-bit | |
3820 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
3821 | aligned. For n32 and n64, stack frames need to be 128-bit |
3822 | aligned, so we round to this widest known alignment. */ | |
3823 | ||
5b03f266 AC |
3824 | sp = align_down (sp, 16); |
3825 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
3826 | |
3827 | /* Now make space on the stack for the args. */ | |
3828 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
3829 | { |
3830 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
3831 | int arglen = TYPE_LENGTH (arg_type); | |
3832 | ||
3833 | /* Align to double-word if necessary. */ | |
2afd3f0a | 3834 | if (mips_type_needs_double_align (arg_type)) |
1a69e1e4 | 3835 | len = align_up (len, MIPS32_REGSIZE * 2); |
968b5391 | 3836 | /* Allocate space on the stack. */ |
1a69e1e4 | 3837 | len += align_up (arglen, MIPS32_REGSIZE); |
968b5391 | 3838 | } |
5b03f266 | 3839 | sp -= align_up (len, 16); |
ebafbe83 MS |
3840 | |
3841 | if (mips_debug) | |
6d82d43b | 3842 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
3843 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", |
3844 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
ebafbe83 MS |
3845 | |
3846 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 3847 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 3848 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 3849 | |
bcb0cc15 | 3850 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
ebafbe83 MS |
3851 | if (struct_return) |
3852 | { | |
3853 | if (mips_debug) | |
3854 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
3855 | "mips_o32_push_dummy_call: " |
3856 | "struct_return reg=%d %s\n", | |
5af949e3 | 3857 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 3858 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 3859 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
3860 | } |
3861 | ||
3862 | /* Now load as many as possible of the first arguments into | |
3863 | registers, and push the rest onto the stack. Loop thru args | |
3864 | from first to last. */ | |
3865 | for (argnum = 0; argnum < nargs; argnum++) | |
3866 | { | |
47a35522 | 3867 | const gdb_byte *val; |
ebafbe83 | 3868 | struct value *arg = args[argnum]; |
4991999e | 3869 | struct type *arg_type = check_typedef (value_type (arg)); |
ebafbe83 MS |
3870 | int len = TYPE_LENGTH (arg_type); |
3871 | enum type_code typecode = TYPE_CODE (arg_type); | |
3872 | ||
3873 | if (mips_debug) | |
3874 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 3875 | "mips_o32_push_dummy_call: %d len=%d type=%d", |
46cac009 AC |
3876 | argnum + 1, len, (int) typecode); |
3877 | ||
47a35522 | 3878 | val = value_contents (arg); |
46cac009 AC |
3879 | |
3880 | /* 32-bit ABIs always start floating point arguments in an | |
3881 | even-numbered floating point register. Round the FP register | |
3882 | up before the check to see if there are any FP registers | |
3883 | left. O32/O64 targets also pass the FP in the integer | |
3884 | registers so also round up normal registers. */ | |
74ed0bb4 | 3885 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
3886 | { |
3887 | if ((float_argreg & 1)) | |
3888 | float_argreg++; | |
3889 | } | |
3890 | ||
3891 | /* Floating point arguments passed in registers have to be | |
3892 | treated specially. On 32-bit architectures, doubles | |
3893 | are passed in register pairs; the even register gets | |
3894 | the low word, and the odd register gets the high word. | |
3895 | On O32/O64, the first two floating point arguments are | |
3896 | also copied to general registers, because MIPS16 functions | |
3897 | don't use float registers for arguments. This duplication of | |
3898 | arguments in general registers can't hurt non-MIPS16 functions | |
3899 | because those registers are normally skipped. */ | |
3900 | ||
74ed0bb4 MD |
3901 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3902 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
46cac009 | 3903 | { |
8b07f6d8 | 3904 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 3905 | { |
72a155b4 | 3906 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 3907 | == BFD_ENDIAN_BIG ? 4 : 0; |
46cac009 AC |
3908 | unsigned long regval; |
3909 | ||
3910 | /* Write the low word of the double to the even register(s). */ | |
e17a4113 UW |
3911 | regval = extract_unsigned_integer (val + low_offset, |
3912 | 4, byte_order); | |
46cac009 AC |
3913 | if (mips_debug) |
3914 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3915 | float_argreg, phex (regval, 4)); | |
025bb325 MS |
3916 | regcache_cooked_write_unsigned (regcache, |
3917 | float_argreg++, regval); | |
46cac009 AC |
3918 | if (mips_debug) |
3919 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3920 | argreg, phex (regval, 4)); | |
9c9acae0 | 3921 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3922 | |
3923 | /* Write the high word of the double to the odd register(s). */ | |
e17a4113 UW |
3924 | regval = extract_unsigned_integer (val + 4 - low_offset, |
3925 | 4, byte_order); | |
46cac009 AC |
3926 | if (mips_debug) |
3927 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3928 | float_argreg, phex (regval, 4)); | |
025bb325 MS |
3929 | regcache_cooked_write_unsigned (regcache, |
3930 | float_argreg++, regval); | |
46cac009 AC |
3931 | |
3932 | if (mips_debug) | |
3933 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3934 | argreg, phex (regval, 4)); | |
9c9acae0 | 3935 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3936 | } |
3937 | else | |
3938 | { | |
3939 | /* This is a floating point value that fits entirely | |
3940 | in a single register. */ | |
3941 | /* On 32 bit ABI's the float_argreg is further adjusted | |
6d82d43b | 3942 | above to ensure that it is even register aligned. */ |
e17a4113 | 3943 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 AC |
3944 | if (mips_debug) |
3945 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
3946 | float_argreg, phex (regval, len)); | |
025bb325 MS |
3947 | regcache_cooked_write_unsigned (regcache, |
3948 | float_argreg++, regval); | |
5b68030f JM |
3949 | /* Although two FP registers are reserved for each |
3950 | argument, only one corresponding integer register is | |
3951 | reserved. */ | |
46cac009 AC |
3952 | if (mips_debug) |
3953 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
3954 | argreg, phex (regval, len)); | |
5b68030f | 3955 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
3956 | } |
3957 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 3958 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
3959 | } |
3960 | else | |
3961 | { | |
3962 | /* Copy the argument to general registers or the stack in | |
3963 | register-sized pieces. Large arguments are split between | |
3964 | registers and stack. */ | |
1a69e1e4 DJ |
3965 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
3966 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
3967 | them in registers where gcc sometimes puts them on the |
3968 | stack. For maximum compatibility, we will put them in | |
3969 | both places. */ | |
1a69e1e4 DJ |
3970 | int odd_sized_struct = (len > MIPS32_REGSIZE |
3971 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
3972 | /* Structures should be aligned to eight bytes (even arg registers) |
3973 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 3974 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
3975 | { |
3976 | if ((argreg & 1)) | |
968b5391 MR |
3977 | { |
3978 | argreg++; | |
1a69e1e4 | 3979 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 3980 | } |
46cac009 | 3981 | } |
46cac009 AC |
3982 | while (len > 0) |
3983 | { | |
3984 | /* Remember if the argument was written to the stack. */ | |
3985 | int stack_used_p = 0; | |
1a69e1e4 | 3986 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
3987 | |
3988 | if (mips_debug) | |
3989 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
3990 | partial_len); | |
3991 | ||
3992 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 3993 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 3994 | || odd_sized_struct) |
46cac009 AC |
3995 | { |
3996 | /* Should shorter than int integer values be | |
025bb325 | 3997 | promoted to int before being stored? */ |
46cac009 AC |
3998 | int longword_offset = 0; |
3999 | CORE_ADDR addr; | |
4000 | stack_used_p = 1; | |
46cac009 AC |
4001 | |
4002 | if (mips_debug) | |
4003 | { | |
5af949e3 UW |
4004 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4005 | paddress (gdbarch, stack_offset)); | |
4006 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4007 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
4008 | } |
4009 | ||
4010 | addr = sp + stack_offset + longword_offset; | |
4011 | ||
4012 | if (mips_debug) | |
4013 | { | |
4014 | int i; | |
5af949e3 UW |
4015 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4016 | paddress (gdbarch, addr)); | |
46cac009 AC |
4017 | for (i = 0; i < partial_len; i++) |
4018 | { | |
6d82d43b | 4019 | fprintf_unfiltered (gdb_stdlog, "%02x", |
46cac009 AC |
4020 | val[i] & 0xff); |
4021 | } | |
4022 | } | |
4023 | write_memory (addr, val, partial_len); | |
4024 | } | |
4025 | ||
4026 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4027 | structs may go thru BOTH paths. */ |
46cac009 | 4028 | /* Write this portion of the argument to a general |
6d82d43b | 4029 | purpose register. */ |
74ed0bb4 | 4030 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
46cac009 | 4031 | { |
e17a4113 UW |
4032 | LONGEST regval = extract_signed_integer (val, partial_len, |
4033 | byte_order); | |
4246e332 | 4034 | /* Value may need to be sign extended, because |
1b13c4f6 | 4035 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
4036 | |
4037 | /* A non-floating-point argument being passed in a | |
4038 | general register. If a struct or union, and if | |
4039 | the remaining length is smaller than the register | |
4040 | size, we have to adjust the register value on | |
4041 | big endian targets. | |
4042 | ||
4043 | It does not seem to be necessary to do the | |
4044 | same for integral types. | |
4045 | ||
4046 | Also don't do this adjustment on O64 binaries. | |
4047 | ||
4048 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
4049 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
4050 | mips_abi_regsize(), generates a left shift |
4051 | as part of storing the argument in a register | |
4052 | (the left shift isn't generated when | |
1b13c4f6 | 4053 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
4054 | it is quite possible that this is GCC |
4055 | contradicting the LE/O32 ABI, GDB has not been | |
4056 | adjusted to accommodate this. Either someone | |
4057 | needs to demonstrate that the LE/O32 ABI | |
4058 | specifies such a left shift OR this new ABI gets | |
4059 | identified as such and GDB gets tweaked | |
4060 | accordingly. */ | |
4061 | ||
72a155b4 | 4062 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4063 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
4064 | && (typecode == TYPE_CODE_STRUCT |
4065 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4066 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 4067 | * TARGET_CHAR_BIT); |
46cac009 AC |
4068 | |
4069 | if (mips_debug) | |
4070 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4071 | argreg, | |
1a69e1e4 | 4072 | phex (regval, MIPS32_REGSIZE)); |
9c9acae0 | 4073 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
4074 | argreg++; |
4075 | ||
4076 | /* Prevent subsequent floating point arguments from | |
4077 | being passed in floating point registers. */ | |
74ed0bb4 | 4078 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
46cac009 AC |
4079 | } |
4080 | ||
4081 | len -= partial_len; | |
4082 | val += partial_len; | |
4083 | ||
b021a221 MS |
4084 | /* Compute the offset into the stack at which we will |
4085 | copy the next parameter. | |
46cac009 | 4086 | |
6d82d43b AC |
4087 | In older ABIs, the caller reserved space for |
4088 | registers that contained arguments. This was loosely | |
4089 | refered to as their "home". Consequently, space is | |
4090 | always allocated. */ | |
46cac009 | 4091 | |
1a69e1e4 | 4092 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
4093 | } |
4094 | } | |
4095 | if (mips_debug) | |
4096 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4097 | } | |
4098 | ||
f10683bb | 4099 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4100 | |
46cac009 AC |
4101 | /* Return adjusted stack pointer. */ |
4102 | return sp; | |
4103 | } | |
4104 | ||
6d82d43b | 4105 | static enum return_value_convention |
c055b101 CV |
4106 | mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
4107 | struct type *type, struct regcache *regcache, | |
47a35522 | 4108 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4109 | { |
72a155b4 | 4110 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6d82d43b AC |
4111 | |
4112 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4113 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4114 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4115 | return RETURN_VALUE_STRUCT_CONVENTION; | |
4116 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4117 | && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4118 | { | |
4119 | /* A single-precision floating-point value. It fits in the | |
4120 | least significant part of FP0. */ | |
4121 | if (mips_debug) | |
4122 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4123 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4124 | gdbarch_num_regs (gdbarch) |
4125 | + mips_regnum (gdbarch)->fp0, | |
6d82d43b | 4126 | TYPE_LENGTH (type), |
72a155b4 | 4127 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4128 | readbuf, writebuf, 0); |
6d82d43b AC |
4129 | return RETURN_VALUE_REGISTER_CONVENTION; |
4130 | } | |
4131 | else if (TYPE_CODE (type) == TYPE_CODE_FLT | |
4132 | && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4133 | { | |
4134 | /* A double-precision floating-point value. The most | |
4135 | significant part goes in FP1, and the least significant in | |
4136 | FP0. */ | |
4137 | if (mips_debug) | |
4138 | fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | |
72a155b4 | 4139 | switch (gdbarch_byte_order (gdbarch)) |
6d82d43b AC |
4140 | { |
4141 | case BFD_ENDIAN_LITTLE: | |
ba32f989 | 4142 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4143 | gdbarch_num_regs (gdbarch) |
4144 | + mips_regnum (gdbarch)->fp0 + | |
4145 | 0, 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4146 | readbuf, writebuf, 0); |
ba32f989 | 4147 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4148 | gdbarch_num_regs (gdbarch) |
4149 | + mips_regnum (gdbarch)->fp0 + 1, | |
4150 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4151 | readbuf, writebuf, 4); |
6d82d43b AC |
4152 | break; |
4153 | case BFD_ENDIAN_BIG: | |
ba32f989 | 4154 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4155 | gdbarch_num_regs (gdbarch) |
4156 | + mips_regnum (gdbarch)->fp0 + 1, | |
4157 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4158 | readbuf, writebuf, 0); |
ba32f989 | 4159 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4160 | gdbarch_num_regs (gdbarch) |
4161 | + mips_regnum (gdbarch)->fp0 + 0, | |
4162 | 4, gdbarch_byte_order (gdbarch), | |
4c6b5505 | 4163 | readbuf, writebuf, 4); |
6d82d43b AC |
4164 | break; |
4165 | default: | |
e2e0b3e5 | 4166 | internal_error (__FILE__, __LINE__, _("bad switch")); |
6d82d43b AC |
4167 | } |
4168 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4169 | } | |
4170 | #if 0 | |
4171 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4172 | && TYPE_NFIELDS (type) <= 2 | |
4173 | && TYPE_NFIELDS (type) >= 1 | |
4174 | && ((TYPE_NFIELDS (type) == 1 | |
4175 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4176 | == TYPE_CODE_FLT)) | |
4177 | || (TYPE_NFIELDS (type) == 2 | |
4178 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | |
4179 | == TYPE_CODE_FLT) | |
4180 | && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) | |
4181 | == TYPE_CODE_FLT))) | |
4182 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4183 | { | |
4184 | /* A struct that contains one or two floats. Each value is part | |
4185 | in the least significant part of their floating point | |
4186 | register.. */ | |
870cd05e | 4187 | gdb_byte reg[MAX_REGISTER_SIZE]; |
6d82d43b AC |
4188 | int regnum; |
4189 | int field; | |
72a155b4 | 4190 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
6d82d43b AC |
4191 | field < TYPE_NFIELDS (type); field++, regnum += 2) |
4192 | { | |
4193 | int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) | |
4194 | / TARGET_CHAR_BIT); | |
4195 | if (mips_debug) | |
4196 | fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", | |
4197 | offset); | |
ba32f989 DJ |
4198 | mips_xfer_register (gdbarch, regcache, |
4199 | gdbarch_num_regs (gdbarch) + regnum, | |
6d82d43b | 4200 | TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), |
72a155b4 | 4201 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4202 | readbuf, writebuf, offset); |
6d82d43b AC |
4203 | } |
4204 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4205 | } | |
4206 | #endif | |
4207 | #if 0 | |
4208 | else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4209 | || TYPE_CODE (type) == TYPE_CODE_UNION) | |
4210 | { | |
4211 | /* A structure or union. Extract the left justified value, | |
4212 | regardless of the byte order. I.e. DO NOT USE | |
4213 | mips_xfer_lower. */ | |
4214 | int offset; | |
4215 | int regnum; | |
4c7d22cb | 4216 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4217 | offset < TYPE_LENGTH (type); |
72a155b4 | 4218 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 4219 | { |
72a155b4 | 4220 | int xfer = register_size (gdbarch, regnum); |
6d82d43b AC |
4221 | if (offset + xfer > TYPE_LENGTH (type)) |
4222 | xfer = TYPE_LENGTH (type) - offset; | |
4223 | if (mips_debug) | |
4224 | fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", | |
4225 | offset, xfer, regnum); | |
ba32f989 DJ |
4226 | mips_xfer_register (gdbarch, regcache, |
4227 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
4228 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
4229 | } | |
4230 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4231 | } | |
4232 | #endif | |
4233 | else | |
4234 | { | |
4235 | /* A scalar extract each part but least-significant-byte | |
4236 | justified. o32 thinks registers are 4 byte, regardless of | |
1a69e1e4 | 4237 | the ISA. */ |
6d82d43b AC |
4238 | int offset; |
4239 | int regnum; | |
4c7d22cb | 4240 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
6d82d43b | 4241 | offset < TYPE_LENGTH (type); |
1a69e1e4 | 4242 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 4243 | { |
1a69e1e4 | 4244 | int xfer = MIPS32_REGSIZE; |
6d82d43b AC |
4245 | if (offset + xfer > TYPE_LENGTH (type)) |
4246 | xfer = TYPE_LENGTH (type) - offset; | |
4247 | if (mips_debug) | |
4248 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4249 | offset, xfer, regnum); | |
ba32f989 DJ |
4250 | mips_xfer_register (gdbarch, regcache, |
4251 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 4252 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4253 | readbuf, writebuf, offset); |
6d82d43b AC |
4254 | } |
4255 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4256 | } | |
4257 | } | |
4258 | ||
4259 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
4260 | ABI. */ | |
46cac009 AC |
4261 | |
4262 | static CORE_ADDR | |
7d9b040b | 4263 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4264 | struct regcache *regcache, CORE_ADDR bp_addr, |
4265 | int nargs, | |
4266 | struct value **args, CORE_ADDR sp, | |
4267 | int struct_return, CORE_ADDR struct_addr) | |
46cac009 AC |
4268 | { |
4269 | int argreg; | |
4270 | int float_argreg; | |
4271 | int argnum; | |
4272 | int len = 0; | |
4273 | int stack_offset = 0; | |
480d3dd2 | 4274 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 4275 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4276 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 4277 | |
25ab4790 AC |
4278 | /* For shared libraries, "t9" needs to point at the function |
4279 | address. */ | |
4c7d22cb | 4280 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4281 | |
4282 | /* Set the return address register to point to the entry point of | |
4283 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4284 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4285 | |
46cac009 AC |
4286 | /* First ensure that the stack and structure return address (if any) |
4287 | are properly aligned. The stack has to be at least 64-bit | |
4288 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4289 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4290 | aligned, so we round to this widest known alignment. */ | |
4291 | ||
5b03f266 AC |
4292 | sp = align_down (sp, 16); |
4293 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
4294 | |
4295 | /* Now make space on the stack for the args. */ | |
4296 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 MR |
4297 | { |
4298 | struct type *arg_type = check_typedef (value_type (args[argnum])); | |
4299 | int arglen = TYPE_LENGTH (arg_type); | |
4300 | ||
968b5391 | 4301 | /* Allocate space on the stack. */ |
1a69e1e4 | 4302 | len += align_up (arglen, MIPS64_REGSIZE); |
968b5391 | 4303 | } |
5b03f266 | 4304 | sp -= align_up (len, 16); |
46cac009 AC |
4305 | |
4306 | if (mips_debug) | |
6d82d43b | 4307 | fprintf_unfiltered (gdb_stdlog, |
5af949e3 UW |
4308 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", |
4309 | paddress (gdbarch, sp), (long) align_up (len, 16)); | |
46cac009 AC |
4310 | |
4311 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4312 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4313 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
4314 | |
4315 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
4316 | if (struct_return) | |
4317 | { | |
4318 | if (mips_debug) | |
4319 | fprintf_unfiltered (gdb_stdlog, | |
025bb325 MS |
4320 | "mips_o64_push_dummy_call: " |
4321 | "struct_return reg=%d %s\n", | |
5af949e3 | 4322 | argreg, paddress (gdbarch, struct_addr)); |
9c9acae0 | 4323 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 4324 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
4325 | } |
4326 | ||
4327 | /* Now load as many as possible of the first arguments into | |
4328 | registers, and push the rest onto the stack. Loop thru args | |
4329 | from first to last. */ | |
4330 | for (argnum = 0; argnum < nargs; argnum++) | |
4331 | { | |
47a35522 | 4332 | const gdb_byte *val; |
930bd0e0 | 4333 | gdb_byte valbuf[MAX_REGISTER_SIZE]; |
46cac009 | 4334 | struct value *arg = args[argnum]; |
4991999e | 4335 | struct type *arg_type = check_typedef (value_type (arg)); |
46cac009 AC |
4336 | int len = TYPE_LENGTH (arg_type); |
4337 | enum type_code typecode = TYPE_CODE (arg_type); | |
4338 | ||
4339 | if (mips_debug) | |
4340 | fprintf_unfiltered (gdb_stdlog, | |
25ab4790 | 4341 | "mips_o64_push_dummy_call: %d len=%d type=%d", |
ebafbe83 MS |
4342 | argnum + 1, len, (int) typecode); |
4343 | ||
47a35522 | 4344 | val = value_contents (arg); |
ebafbe83 | 4345 | |
930bd0e0 KB |
4346 | /* Function pointer arguments to mips16 code need to be made into |
4347 | mips16 pointers. */ | |
4348 | if (typecode == TYPE_CODE_PTR | |
4349 | && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | |
4350 | { | |
4351 | CORE_ADDR addr = extract_signed_integer (value_contents (arg), | |
4352 | len, byte_order); | |
4353 | if (mips_pc_is_mips16 (addr)) | |
4354 | { | |
4355 | store_signed_integer (valbuf, len, byte_order, | |
4356 | make_mips16_addr (addr)); | |
4357 | val = valbuf; | |
4358 | } | |
4359 | } | |
4360 | ||
ebafbe83 MS |
4361 | /* Floating point arguments passed in registers have to be |
4362 | treated specially. On 32-bit architectures, doubles | |
4363 | are passed in register pairs; the even register gets | |
4364 | the low word, and the odd register gets the high word. | |
4365 | On O32/O64, the first two floating point arguments are | |
4366 | also copied to general registers, because MIPS16 functions | |
4367 | don't use float registers for arguments. This duplication of | |
4368 | arguments in general registers can't hurt non-MIPS16 functions | |
4369 | because those registers are normally skipped. */ | |
4370 | ||
74ed0bb4 MD |
4371 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4372 | && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | |
ebafbe83 | 4373 | { |
e17a4113 | 4374 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a MR |
4375 | if (mips_debug) |
4376 | fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | |
4377 | float_argreg, phex (regval, len)); | |
9c9acae0 | 4378 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a MR |
4379 | if (mips_debug) |
4380 | fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | |
4381 | argreg, phex (regval, len)); | |
9c9acae0 | 4382 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 4383 | argreg++; |
ebafbe83 | 4384 | /* Reserve space for the FP register. */ |
1a69e1e4 | 4385 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
4386 | } |
4387 | else | |
4388 | { | |
4389 | /* Copy the argument to general registers or the stack in | |
4390 | register-sized pieces. Large arguments are split between | |
4391 | registers and stack. */ | |
1a69e1e4 | 4392 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
4393 | are treated specially: Irix cc passes them in registers |
4394 | where gcc sometimes puts them on the stack. For maximum | |
4395 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
4396 | int odd_sized_struct = (len > MIPS64_REGSIZE |
4397 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
4398 | while (len > 0) |
4399 | { | |
4400 | /* Remember if the argument was written to the stack. */ | |
4401 | int stack_used_p = 0; | |
1a69e1e4 | 4402 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
4403 | |
4404 | if (mips_debug) | |
4405 | fprintf_unfiltered (gdb_stdlog, " -- partial=%d", | |
4406 | partial_len); | |
4407 | ||
4408 | /* Write this portion of the argument to the stack. */ | |
74ed0bb4 | 4409 | if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) |
968b5391 | 4410 | || odd_sized_struct) |
ebafbe83 MS |
4411 | { |
4412 | /* Should shorter than int integer values be | |
025bb325 | 4413 | promoted to int before being stored? */ |
ebafbe83 MS |
4414 | int longword_offset = 0; |
4415 | CORE_ADDR addr; | |
4416 | stack_used_p = 1; | |
72a155b4 | 4417 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 4418 | { |
1a69e1e4 DJ |
4419 | if ((typecode == TYPE_CODE_INT |
4420 | || typecode == TYPE_CODE_PTR | |
4421 | || typecode == TYPE_CODE_FLT) | |
4422 | && len <= 4) | |
4423 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
4424 | } |
4425 | ||
4426 | if (mips_debug) | |
4427 | { | |
5af949e3 UW |
4428 | fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", |
4429 | paddress (gdbarch, stack_offset)); | |
4430 | fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", | |
4431 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
4432 | } |
4433 | ||
4434 | addr = sp + stack_offset + longword_offset; | |
4435 | ||
4436 | if (mips_debug) | |
4437 | { | |
4438 | int i; | |
5af949e3 UW |
4439 | fprintf_unfiltered (gdb_stdlog, " @%s ", |
4440 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
4441 | for (i = 0; i < partial_len; i++) |
4442 | { | |
6d82d43b | 4443 | fprintf_unfiltered (gdb_stdlog, "%02x", |
ebafbe83 MS |
4444 | val[i] & 0xff); |
4445 | } | |
4446 | } | |
4447 | write_memory (addr, val, partial_len); | |
4448 | } | |
4449 | ||
4450 | /* Note!!! This is NOT an else clause. Odd sized | |
968b5391 | 4451 | structs may go thru BOTH paths. */ |
ebafbe83 | 4452 | /* Write this portion of the argument to a general |
6d82d43b | 4453 | purpose register. */ |
74ed0bb4 | 4454 | if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) |
ebafbe83 | 4455 | { |
e17a4113 UW |
4456 | LONGEST regval = extract_signed_integer (val, partial_len, |
4457 | byte_order); | |
4246e332 | 4458 | /* Value may need to be sign extended, because |
1b13c4f6 | 4459 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
4460 | |
4461 | /* A non-floating-point argument being passed in a | |
4462 | general register. If a struct or union, and if | |
4463 | the remaining length is smaller than the register | |
4464 | size, we have to adjust the register value on | |
4465 | big endian targets. | |
4466 | ||
4467 | It does not seem to be necessary to do the | |
025bb325 | 4468 | same for integral types. */ |
480d3dd2 | 4469 | |
72a155b4 | 4470 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 4471 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
4472 | && (typecode == TYPE_CODE_STRUCT |
4473 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 4474 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 4475 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
4476 | |
4477 | if (mips_debug) | |
4478 | fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", | |
4479 | argreg, | |
1a69e1e4 | 4480 | phex (regval, MIPS64_REGSIZE)); |
9c9acae0 | 4481 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
4482 | argreg++; |
4483 | ||
4484 | /* Prevent subsequent floating point arguments from | |
4485 | being passed in floating point registers. */ | |
74ed0bb4 | 4486 | float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; |
ebafbe83 MS |
4487 | } |
4488 | ||
4489 | len -= partial_len; | |
4490 | val += partial_len; | |
4491 | ||
b021a221 MS |
4492 | /* Compute the offset into the stack at which we will |
4493 | copy the next parameter. | |
ebafbe83 | 4494 | |
6d82d43b AC |
4495 | In older ABIs, the caller reserved space for |
4496 | registers that contained arguments. This was loosely | |
4497 | refered to as their "home". Consequently, space is | |
4498 | always allocated. */ | |
ebafbe83 | 4499 | |
1a69e1e4 | 4500 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
4501 | } |
4502 | } | |
4503 | if (mips_debug) | |
4504 | fprintf_unfiltered (gdb_stdlog, "\n"); | |
4505 | } | |
4506 | ||
f10683bb | 4507 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4508 | |
ebafbe83 MS |
4509 | /* Return adjusted stack pointer. */ |
4510 | return sp; | |
4511 | } | |
4512 | ||
9c8fdbfa | 4513 | static enum return_value_convention |
c055b101 | 4514 | mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
9c8fdbfa | 4515 | struct type *type, struct regcache *regcache, |
47a35522 | 4516 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4517 | { |
72a155b4 | 4518 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a076fd2 FF |
4519 | |
4520 | if (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
4521 | || TYPE_CODE (type) == TYPE_CODE_UNION | |
4522 | || TYPE_CODE (type) == TYPE_CODE_ARRAY) | |
4523 | return RETURN_VALUE_STRUCT_CONVENTION; | |
74ed0bb4 | 4524 | else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
7a076fd2 FF |
4525 | { |
4526 | /* A floating-point value. It fits in the least significant | |
4527 | part of FP0. */ | |
4528 | if (mips_debug) | |
4529 | fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | |
ba32f989 | 4530 | mips_xfer_register (gdbarch, regcache, |
72a155b4 UW |
4531 | gdbarch_num_regs (gdbarch) |
4532 | + mips_regnum (gdbarch)->fp0, | |
7a076fd2 | 4533 | TYPE_LENGTH (type), |
72a155b4 | 4534 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 4535 | readbuf, writebuf, 0); |
7a076fd2 FF |
4536 | return RETURN_VALUE_REGISTER_CONVENTION; |
4537 | } | |
4538 | else | |
4539 | { | |
4540 | /* A scalar extract each part but least-significant-byte | |
025bb325 | 4541 | justified. */ |
7a076fd2 FF |
4542 | int offset; |
4543 | int regnum; | |
4544 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
4545 | offset < TYPE_LENGTH (type); | |
1a69e1e4 | 4546 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 4547 | { |
1a69e1e4 | 4548 | int xfer = MIPS64_REGSIZE; |
7a076fd2 FF |
4549 | if (offset + xfer > TYPE_LENGTH (type)) |
4550 | xfer = TYPE_LENGTH (type) - offset; | |
4551 | if (mips_debug) | |
4552 | fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", | |
4553 | offset, xfer, regnum); | |
ba32f989 DJ |
4554 | mips_xfer_register (gdbarch, regcache, |
4555 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 4556 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 4557 | readbuf, writebuf, offset); |
7a076fd2 FF |
4558 | } |
4559 | return RETURN_VALUE_REGISTER_CONVENTION; | |
4560 | } | |
6d82d43b AC |
4561 | } |
4562 | ||
dd824b04 DJ |
4563 | /* Floating point register management. |
4564 | ||
4565 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
4566 | 64bit operations, these early MIPS cpus treat fp register pairs | |
4567 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
4568 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
4569 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
4570 | double precision floats into two 32-bit chunks and store them in | |
4571 | consecutive fp regs. To display 64-bit floats stored in this | |
4572 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
4573 | Throw in user-configurable endianness and you have a real mess. | |
4574 | ||
4575 | The way this works is: | |
4576 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
4577 | double-precision value will be split across two logical registers. | |
4578 | The lower-numbered logical register will hold the low-order bits, | |
4579 | regardless of the processor's endianness. | |
4580 | - If we are on a 64-bit processor, and we are looking for a | |
4581 | single-precision value, it will be in the low ordered bits | |
4582 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
4583 | save slot in memory. | |
4584 | - If we are in 64-bit mode, everything is straightforward. | |
4585 | ||
4586 | Note that this code only deals with "live" registers at the top of the | |
4587 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 4588 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
4589 | interface that can deal with dynamic saved register sizes -- fp |
4590 | regs could be 32 bits wide in one frame and 64 on the frame above | |
4591 | and below). */ | |
4592 | ||
4593 | /* Copy a 32-bit single-precision value from the current frame | |
4594 | into rare_buffer. */ | |
4595 | ||
4596 | static void | |
e11c53d2 | 4597 | mips_read_fp_register_single (struct frame_info *frame, int regno, |
47a35522 | 4598 | gdb_byte *rare_buffer) |
dd824b04 | 4599 | { |
72a155b4 UW |
4600 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4601 | int raw_size = register_size (gdbarch, regno); | |
47a35522 | 4602 | gdb_byte *raw_buffer = alloca (raw_size); |
dd824b04 | 4603 | |
e11c53d2 | 4604 | if (!frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 4605 | error (_("can't read register %d (%s)"), |
72a155b4 | 4606 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4607 | if (raw_size == 8) |
4608 | { | |
4609 | /* We have a 64-bit value for this register. Find the low-order | |
6d82d43b | 4610 | 32 bits. */ |
dd824b04 DJ |
4611 | int offset; |
4612 | ||
72a155b4 | 4613 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
4614 | offset = 4; |
4615 | else | |
4616 | offset = 0; | |
4617 | ||
4618 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
4619 | } | |
4620 | else | |
4621 | { | |
4622 | memcpy (rare_buffer, raw_buffer, 4); | |
4623 | } | |
4624 | } | |
4625 | ||
4626 | /* Copy a 64-bit double-precision value from the current frame into | |
4627 | rare_buffer. This may include getting half of it from the next | |
4628 | register. */ | |
4629 | ||
4630 | static void | |
e11c53d2 | 4631 | mips_read_fp_register_double (struct frame_info *frame, int regno, |
47a35522 | 4632 | gdb_byte *rare_buffer) |
dd824b04 | 4633 | { |
72a155b4 UW |
4634 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4635 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 4636 | |
9c9acae0 | 4637 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
4638 | { |
4639 | /* We have a 64-bit value for this register, and we should use | |
6d82d43b | 4640 | all 64 bits. */ |
e11c53d2 | 4641 | if (!frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 4642 | error (_("can't read register %d (%s)"), |
72a155b4 | 4643 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
4644 | } |
4645 | else | |
4646 | { | |
72a155b4 | 4647 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 4648 | |
72a155b4 | 4649 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
dd824b04 | 4650 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
4651 | _("mips_read_fp_register_double: bad access to " |
4652 | "odd-numbered FP register")); | |
dd824b04 DJ |
4653 | |
4654 | /* mips_read_fp_register_single will find the correct 32 bits from | |
6d82d43b | 4655 | each register. */ |
72a155b4 | 4656 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 4657 | { |
e11c53d2 AC |
4658 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
4659 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 4660 | } |
361d1df0 | 4661 | else |
dd824b04 | 4662 | { |
e11c53d2 AC |
4663 | mips_read_fp_register_single (frame, regno, rare_buffer); |
4664 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
4665 | } |
4666 | } | |
4667 | } | |
4668 | ||
c906108c | 4669 | static void |
e11c53d2 AC |
4670 | mips_print_fp_register (struct ui_file *file, struct frame_info *frame, |
4671 | int regnum) | |
025bb325 | 4672 | { /* Do values for FP (float) regs. */ |
72a155b4 | 4673 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 4674 | gdb_byte *raw_buffer; |
025bb325 | 4675 | double doub, flt1; /* Doubles extracted from raw hex data. */ |
3903d437 | 4676 | int inv1, inv2; |
c5aa993b | 4677 | |
025bb325 MS |
4678 | raw_buffer = alloca (2 * register_size (gdbarch, |
4679 | mips_regnum (gdbarch)->fp0)); | |
c906108c | 4680 | |
72a155b4 | 4681 | fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
c9f4d572 | 4682 | fprintf_filtered (file, "%*s", |
72a155b4 | 4683 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), |
e11c53d2 | 4684 | ""); |
f0ef6b29 | 4685 | |
72a155b4 | 4686 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 4687 | { |
79a45b7d TT |
4688 | struct value_print_options opts; |
4689 | ||
f0ef6b29 KB |
4690 | /* 4-byte registers: Print hex and floating. Also print even |
4691 | numbered registers as doubles. */ | |
e11c53d2 | 4692 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
025bb325 MS |
4693 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4694 | raw_buffer, &inv1); | |
c5aa993b | 4695 | |
79a45b7d | 4696 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4697 | print_scalar_formatted (raw_buffer, |
4698 | builtin_type (gdbarch)->builtin_uint32, | |
4699 | &opts, 'w', file); | |
dd824b04 | 4700 | |
e11c53d2 | 4701 | fprintf_filtered (file, " flt: "); |
1adad886 | 4702 | if (inv1) |
e11c53d2 | 4703 | fprintf_filtered (file, " <invalid float> "); |
1adad886 | 4704 | else |
e11c53d2 | 4705 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4706 | |
72a155b4 | 4707 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 4708 | { |
e11c53d2 | 4709 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4710 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4711 | raw_buffer, &inv2); | |
1adad886 | 4712 | |
e11c53d2 | 4713 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4714 | if (inv2) |
e11c53d2 | 4715 | fprintf_filtered (file, "<invalid double>"); |
f0ef6b29 | 4716 | else |
e11c53d2 | 4717 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 | 4718 | } |
c906108c SS |
4719 | } |
4720 | else | |
dd824b04 | 4721 | { |
79a45b7d TT |
4722 | struct value_print_options opts; |
4723 | ||
f0ef6b29 | 4724 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 4725 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
27067745 UW |
4726 | flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, |
4727 | raw_buffer, &inv1); | |
c906108c | 4728 | |
e11c53d2 | 4729 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
27067745 UW |
4730 | doub = unpack_double (builtin_type (gdbarch)->builtin_double, |
4731 | raw_buffer, &inv2); | |
f0ef6b29 | 4732 | |
79a45b7d | 4733 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
4734 | print_scalar_formatted (raw_buffer, |
4735 | builtin_type (gdbarch)->builtin_uint64, | |
4736 | &opts, 'g', file); | |
f0ef6b29 | 4737 | |
e11c53d2 | 4738 | fprintf_filtered (file, " flt: "); |
1adad886 | 4739 | if (inv1) |
e11c53d2 | 4740 | fprintf_filtered (file, "<invalid float>"); |
1adad886 | 4741 | else |
e11c53d2 | 4742 | fprintf_filtered (file, "%-17.9g", flt1); |
1adad886 | 4743 | |
e11c53d2 | 4744 | fprintf_filtered (file, " dbl: "); |
f0ef6b29 | 4745 | if (inv2) |
e11c53d2 | 4746 | fprintf_filtered (file, "<invalid double>"); |
1adad886 | 4747 | else |
e11c53d2 | 4748 | fprintf_filtered (file, "%-24.17g", doub); |
f0ef6b29 KB |
4749 | } |
4750 | } | |
4751 | ||
4752 | static void | |
e11c53d2 | 4753 | mips_print_register (struct ui_file *file, struct frame_info *frame, |
0cc93a06 | 4754 | int regnum) |
f0ef6b29 | 4755 | { |
a4b8ebc8 | 4756 | struct gdbarch *gdbarch = get_frame_arch (frame); |
f0ef6b29 | 4757 | int offset; |
79a45b7d | 4758 | struct value_print_options opts; |
de15c4ab | 4759 | struct value *val; |
1adad886 | 4760 | |
7b9ee6a8 | 4761 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
f0ef6b29 | 4762 | { |
e11c53d2 | 4763 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
4764 | return; |
4765 | } | |
4766 | ||
de15c4ab PA |
4767 | val = get_frame_register_value (frame, regnum); |
4768 | if (value_optimized_out (val)) | |
f0ef6b29 | 4769 | { |
c9f4d572 | 4770 | fprintf_filtered (file, "%s: [Invalid]", |
72a155b4 | 4771 | gdbarch_register_name (gdbarch, regnum)); |
f0ef6b29 | 4772 | return; |
c906108c | 4773 | } |
f0ef6b29 | 4774 | |
72a155b4 | 4775 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
4776 | |
4777 | /* The problem with printing numeric register names (r26, etc.) is that | |
4778 | the user can't use them on input. Probably the best solution is to | |
4779 | fix it so that either the numeric or the funky (a2, etc.) names | |
4780 | are accepted on input. */ | |
4781 | if (regnum < MIPS_NUMREGS) | |
e11c53d2 | 4782 | fprintf_filtered (file, "(r%d): ", regnum); |
f0ef6b29 | 4783 | else |
e11c53d2 | 4784 | fprintf_filtered (file, ": "); |
f0ef6b29 | 4785 | |
79a45b7d | 4786 | get_formatted_print_options (&opts, 'x'); |
de15c4ab PA |
4787 | val_print_scalar_formatted (value_type (val), |
4788 | value_contents_for_printing (val), | |
4789 | value_embedded_offset (val), | |
4790 | val, | |
4791 | &opts, 0, file); | |
c906108c SS |
4792 | } |
4793 | ||
f0ef6b29 KB |
4794 | /* Replacement for generic do_registers_info. |
4795 | Print regs in pretty columns. */ | |
4796 | ||
4797 | static int | |
e11c53d2 AC |
4798 | print_fp_register_row (struct ui_file *file, struct frame_info *frame, |
4799 | int regnum) | |
f0ef6b29 | 4800 | { |
e11c53d2 AC |
4801 | fprintf_filtered (file, " "); |
4802 | mips_print_fp_register (file, frame, regnum); | |
4803 | fprintf_filtered (file, "\n"); | |
f0ef6b29 KB |
4804 | return regnum + 1; |
4805 | } | |
4806 | ||
4807 | ||
025bb325 | 4808 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
4809 | |
4810 | static int | |
e11c53d2 | 4811 | print_gp_register_row (struct ui_file *file, struct frame_info *frame, |
a4b8ebc8 | 4812 | int start_regnum) |
c906108c | 4813 | { |
a4b8ebc8 | 4814 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 4815 | /* Do values for GP (int) regs. */ |
47a35522 | 4816 | gdb_byte raw_buffer[MAX_REGISTER_SIZE]; |
025bb325 MS |
4817 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
4818 | per row. */ | |
c906108c | 4819 | int col, byte; |
a4b8ebc8 | 4820 | int regnum; |
c906108c | 4821 | |
025bb325 | 4822 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 4823 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4824 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4825 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4826 | regnum++) |
c906108c | 4827 | { |
72a155b4 | 4828 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4829 | continue; /* unused register */ |
7b9ee6a8 | 4830 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4831 | TYPE_CODE_FLT) |
025bb325 | 4832 | break; /* End the row: reached FP register. */ |
0cc93a06 | 4833 | /* Large registers are handled separately. */ |
72a155b4 | 4834 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4835 | { |
4836 | if (col > 0) | |
4837 | break; /* End the row before this register. */ | |
4838 | ||
4839 | /* Print this register on a row by itself. */ | |
4840 | mips_print_register (file, frame, regnum); | |
4841 | fprintf_filtered (file, "\n"); | |
4842 | return regnum + 1; | |
4843 | } | |
d05f6826 DJ |
4844 | if (col == 0) |
4845 | fprintf_filtered (file, " "); | |
6d82d43b | 4846 | fprintf_filtered (file, |
72a155b4 UW |
4847 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", |
4848 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
4849 | col++; |
4850 | } | |
d05f6826 DJ |
4851 | |
4852 | if (col == 0) | |
4853 | return regnum; | |
4854 | ||
025bb325 | 4855 | /* Print the R0 to R31 names. */ |
72a155b4 | 4856 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
f57d151a | 4857 | fprintf_filtered (file, "\n R%-4d", |
72a155b4 | 4858 | start_regnum % gdbarch_num_regs (gdbarch)); |
20e6603c AC |
4859 | else |
4860 | fprintf_filtered (file, "\n "); | |
c906108c | 4861 | |
025bb325 | 4862 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 4863 | for (col = 0, regnum = start_regnum; |
72a155b4 UW |
4864 | col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4865 | + gdbarch_num_pseudo_regs (gdbarch); | |
f57d151a | 4866 | regnum++) |
c906108c | 4867 | { |
72a155b4 | 4868 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 4869 | continue; /* unused register */ |
7b9ee6a8 | 4870 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4871 | TYPE_CODE_FLT) |
025bb325 | 4872 | break; /* End row: reached FP register. */ |
72a155b4 | 4873 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
4874 | break; /* End row: large register. */ |
4875 | ||
c906108c | 4876 | /* OK: get the data in raw format. */ |
e11c53d2 | 4877 | if (!frame_register_read (frame, regnum, raw_buffer)) |
c9f4d572 | 4878 | error (_("can't read register %d (%s)"), |
72a155b4 | 4879 | regnum, gdbarch_register_name (gdbarch, regnum)); |
c906108c | 4880 | /* pad small registers */ |
4246e332 | 4881 | for (byte = 0; |
72a155b4 UW |
4882 | byte < (mips_abi_regsize (gdbarch) |
4883 | - register_size (gdbarch, regnum)); byte++) | |
c906108c | 4884 | printf_filtered (" "); |
025bb325 | 4885 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 4886 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 4887 | for (byte = |
72a155b4 UW |
4888 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
4889 | byte < register_size (gdbarch, regnum); byte++) | |
47a35522 | 4890 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
c906108c | 4891 | else |
72a155b4 | 4892 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 4893 | byte >= 0; byte--) |
47a35522 | 4894 | fprintf_filtered (file, "%02x", raw_buffer[byte]); |
e11c53d2 | 4895 | fprintf_filtered (file, " "); |
c906108c SS |
4896 | col++; |
4897 | } | |
025bb325 | 4898 | if (col > 0) /* ie. if we actually printed anything... */ |
e11c53d2 | 4899 | fprintf_filtered (file, "\n"); |
c906108c SS |
4900 | |
4901 | return regnum; | |
4902 | } | |
4903 | ||
025bb325 | 4904 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 4905 | |
bf1f5b4c | 4906 | static void |
e11c53d2 AC |
4907 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4908 | struct frame_info *frame, int regnum, int all) | |
c906108c | 4909 | { |
025bb325 | 4910 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 4911 | { |
72a155b4 UW |
4912 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
4913 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 4914 | error (_("Not a valid register for the current processor type")); |
c906108c | 4915 | |
0cc93a06 | 4916 | mips_print_register (file, frame, regnum); |
e11c53d2 | 4917 | fprintf_filtered (file, "\n"); |
c906108c | 4918 | } |
c5aa993b | 4919 | else |
025bb325 | 4920 | /* Do all (or most) registers. */ |
c906108c | 4921 | { |
72a155b4 UW |
4922 | regnum = gdbarch_num_regs (gdbarch); |
4923 | while (regnum < gdbarch_num_regs (gdbarch) | |
4924 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c906108c | 4925 | { |
7b9ee6a8 | 4926 | if (TYPE_CODE (register_type (gdbarch, regnum)) == |
6d82d43b | 4927 | TYPE_CODE_FLT) |
e11c53d2 | 4928 | { |
025bb325 | 4929 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
4930 | regnum = print_fp_register_row (file, frame, regnum); |
4931 | else | |
025bb325 | 4932 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 4933 | } |
c906108c | 4934 | else |
e11c53d2 | 4935 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
4936 | } |
4937 | } | |
4938 | } | |
4939 | ||
c906108c SS |
4940 | /* Is this a branch with a delay slot? */ |
4941 | ||
c906108c | 4942 | static int |
acdb74a0 | 4943 | is_delayed (unsigned long insn) |
c906108c SS |
4944 | { |
4945 | int i; | |
4946 | for (i = 0; i < NUMOPCODES; ++i) | |
4947 | if (mips_opcodes[i].pinfo != INSN_MACRO | |
4948 | && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4949 | break; | |
4950 | return (i < NUMOPCODES | |
4951 | && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4952 | | INSN_COND_BRANCH_DELAY | |
4953 | | INSN_COND_BRANCH_LIKELY))); | |
4954 | } | |
4955 | ||
63807e1d | 4956 | static int |
3352ef37 AC |
4957 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
4958 | struct frame_info *frame) | |
c906108c | 4959 | { |
e17a4113 | 4960 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3352ef37 | 4961 | CORE_ADDR pc = get_frame_pc (frame); |
47a35522 | 4962 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c SS |
4963 | |
4964 | /* There is no branch delay slot on MIPS16. */ | |
0fe7e7c8 | 4965 | if (mips_pc_is_mips16 (pc)) |
c906108c SS |
4966 | return 0; |
4967 | ||
6c95b8df | 4968 | if (!breakpoint_here_p (get_frame_address_space (frame), pc + 4)) |
06648491 MK |
4969 | return 0; |
4970 | ||
3352ef37 AC |
4971 | if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) |
4972 | /* If error reading memory, guess that it is not a delayed | |
4973 | branch. */ | |
c906108c | 4974 | return 0; |
e17a4113 | 4975 | return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order)); |
c906108c SS |
4976 | } |
4977 | ||
6d82d43b AC |
4978 | /* To skip prologues, I use this predicate. Returns either PC itself |
4979 | if the code at PC does not look like a function prologue; otherwise | |
4980 | returns an address that (if we're lucky) follows the prologue. If | |
4981 | LENIENT, then we must skip everything which is involved in setting | |
4982 | up the frame (it's OK to skip more, just so long as we don't skip | |
4983 | anything which might clobber the registers which are being saved. | |
4984 | We must skip more in the case where part of the prologue is in the | |
4985 | delay slot of a non-prologue instruction). */ | |
4986 | ||
4987 | static CORE_ADDR | |
6093d2eb | 4988 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 4989 | { |
8b622e6a AC |
4990 | CORE_ADDR limit_pc; |
4991 | CORE_ADDR func_addr; | |
4992 | ||
6d82d43b AC |
4993 | /* See if we can determine the end of the prologue via the symbol table. |
4994 | If so, then return either PC, or the PC after the prologue, whichever | |
4995 | is greater. */ | |
8b622e6a AC |
4996 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
4997 | { | |
d80b854b UW |
4998 | CORE_ADDR post_prologue_pc |
4999 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a AC |
5000 | if (post_prologue_pc != 0) |
5001 | return max (pc, post_prologue_pc); | |
5002 | } | |
6d82d43b AC |
5003 | |
5004 | /* Can't determine prologue from the symbol table, need to examine | |
5005 | instructions. */ | |
5006 | ||
98b4dd94 JB |
5007 | /* Find an upper limit on the function prologue using the debug |
5008 | information. If the debug information could not be used to provide | |
5009 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 5010 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
5011 | if (limit_pc == 0) |
5012 | limit_pc = pc + 100; /* Magic. */ | |
5013 | ||
0fe7e7c8 | 5014 | if (mips_pc_is_mips16 (pc)) |
e17a4113 | 5015 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
6d82d43b | 5016 | else |
e17a4113 | 5017 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
5018 | } |
5019 | ||
97ab0fdd MR |
5020 | /* Check whether the PC is in a function epilogue (32-bit version). |
5021 | This is a helper function for mips_in_function_epilogue_p. */ | |
5022 | static int | |
e17a4113 | 5023 | mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
5024 | { |
5025 | CORE_ADDR func_addr = 0, func_end = 0; | |
5026 | ||
5027 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
5028 | { | |
5029 | /* The MIPS epilogue is max. 12 bytes long. */ | |
5030 | CORE_ADDR addr = func_end - 12; | |
5031 | ||
5032 | if (addr < func_addr + 4) | |
5033 | addr = func_addr + 4; | |
5034 | if (pc < addr) | |
5035 | return 0; | |
5036 | ||
5037 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
5038 | { | |
5039 | unsigned long high_word; | |
5040 | unsigned long inst; | |
5041 | ||
e17a4113 | 5042 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
5043 | high_word = (inst >> 16) & 0xffff; |
5044 | ||
5045 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
5046 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
5047 | && inst != 0x03e00008 /* jr $ra */ | |
5048 | && inst != 0x00000000) /* nop */ | |
5049 | return 0; | |
5050 | } | |
5051 | ||
5052 | return 1; | |
5053 | } | |
5054 | ||
5055 | return 0; | |
5056 | } | |
5057 | ||
5058 | /* Check whether the PC is in a function epilogue (16-bit version). | |
5059 | This is a helper function for mips_in_function_epilogue_p. */ | |
5060 | static int | |
e17a4113 | 5061 | mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
5062 | { |
5063 | CORE_ADDR func_addr = 0, func_end = 0; | |
5064 | ||
5065 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
5066 | { | |
5067 | /* The MIPS epilogue is max. 12 bytes long. */ | |
5068 | CORE_ADDR addr = func_end - 12; | |
5069 | ||
5070 | if (addr < func_addr + 4) | |
5071 | addr = func_addr + 4; | |
5072 | if (pc < addr) | |
5073 | return 0; | |
5074 | ||
5075 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
5076 | { | |
5077 | unsigned short inst; | |
5078 | ||
e17a4113 | 5079 | inst = mips_fetch_instruction (gdbarch, pc); |
97ab0fdd MR |
5080 | |
5081 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
5082 | continue; | |
5083 | ||
5084 | if (inst != 0x6300 /* addiu $sp,offset */ | |
5085 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
5086 | && inst != 0xe820 /* jr $ra */ | |
5087 | && inst != 0xe8a0 /* jrc $ra */ | |
5088 | && inst != 0x6500) /* nop */ | |
5089 | return 0; | |
5090 | } | |
5091 | ||
5092 | return 1; | |
5093 | } | |
5094 | ||
5095 | return 0; | |
5096 | } | |
5097 | ||
5098 | /* The epilogue is defined here as the area at the end of a function, | |
5099 | after an instruction which destroys the function's stack frame. */ | |
5100 | static int | |
5101 | mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
5102 | { | |
5103 | if (mips_pc_is_mips16 (pc)) | |
e17a4113 | 5104 | return mips16_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd | 5105 | else |
e17a4113 | 5106 | return mips32_in_function_epilogue_p (gdbarch, pc); |
97ab0fdd MR |
5107 | } |
5108 | ||
025bb325 | 5109 | /* Root of all "set mips "/"show mips " commands. This will eventually be |
a5ea2558 AC |
5110 | used for all MIPS-specific commands. */ |
5111 | ||
a5ea2558 | 5112 | static void |
acdb74a0 | 5113 | show_mips_command (char *args, int from_tty) |
a5ea2558 AC |
5114 | { |
5115 | help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); | |
5116 | } | |
5117 | ||
a5ea2558 | 5118 | static void |
acdb74a0 | 5119 | set_mips_command (char *args, int from_tty) |
a5ea2558 | 5120 | { |
6d82d43b AC |
5121 | printf_unfiltered |
5122 | ("\"set mips\" must be followed by an appropriate subcommand.\n"); | |
a5ea2558 AC |
5123 | help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); |
5124 | } | |
5125 | ||
c906108c SS |
5126 | /* Commands to show/set the MIPS FPU type. */ |
5127 | ||
c906108c | 5128 | static void |
acdb74a0 | 5129 | show_mipsfpu_command (char *args, int from_tty) |
c906108c | 5130 | { |
c906108c | 5131 | char *fpu; |
6ca0852e | 5132 | |
1cf3db46 | 5133 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
6ca0852e UW |
5134 | { |
5135 | printf_unfiltered | |
5136 | ("The MIPS floating-point coprocessor is unknown " | |
5137 | "because the current architecture is not MIPS.\n"); | |
5138 | return; | |
5139 | } | |
5140 | ||
1cf3db46 | 5141 | switch (MIPS_FPU_TYPE (target_gdbarch)) |
c906108c SS |
5142 | { |
5143 | case MIPS_FPU_SINGLE: | |
5144 | fpu = "single-precision"; | |
5145 | break; | |
5146 | case MIPS_FPU_DOUBLE: | |
5147 | fpu = "double-precision"; | |
5148 | break; | |
5149 | case MIPS_FPU_NONE: | |
5150 | fpu = "absent (none)"; | |
5151 | break; | |
93d56215 | 5152 | default: |
e2e0b3e5 | 5153 | internal_error (__FILE__, __LINE__, _("bad switch")); |
c906108c SS |
5154 | } |
5155 | if (mips_fpu_type_auto) | |
025bb325 MS |
5156 | printf_unfiltered ("The MIPS floating-point coprocessor " |
5157 | "is set automatically (currently %s)\n", | |
5158 | fpu); | |
c906108c | 5159 | else |
6d82d43b AC |
5160 | printf_unfiltered |
5161 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); | |
c906108c SS |
5162 | } |
5163 | ||
5164 | ||
c906108c | 5165 | static void |
acdb74a0 | 5166 | set_mipsfpu_command (char *args, int from_tty) |
c906108c | 5167 | { |
025bb325 MS |
5168 | printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " |
5169 | "\"single\",\"none\" or \"auto\".\n"); | |
c906108c SS |
5170 | show_mipsfpu_command (args, from_tty); |
5171 | } | |
5172 | ||
c906108c | 5173 | static void |
acdb74a0 | 5174 | set_mipsfpu_single_command (char *args, int from_tty) |
c906108c | 5175 | { |
8d5838b5 AC |
5176 | struct gdbarch_info info; |
5177 | gdbarch_info_init (&info); | |
c906108c SS |
5178 | mips_fpu_type = MIPS_FPU_SINGLE; |
5179 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5180 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5181 | instead of relying on globals. Doing that would let generic code | |
5182 | handle the search for this specific architecture. */ | |
5183 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5184 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5185 | } |
5186 | ||
c906108c | 5187 | static void |
acdb74a0 | 5188 | set_mipsfpu_double_command (char *args, int from_tty) |
c906108c | 5189 | { |
8d5838b5 AC |
5190 | struct gdbarch_info info; |
5191 | gdbarch_info_init (&info); | |
c906108c SS |
5192 | mips_fpu_type = MIPS_FPU_DOUBLE; |
5193 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5194 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5195 | instead of relying on globals. Doing that would let generic code | |
5196 | handle the search for this specific architecture. */ | |
5197 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5198 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5199 | } |
5200 | ||
c906108c | 5201 | static void |
acdb74a0 | 5202 | set_mipsfpu_none_command (char *args, int from_tty) |
c906108c | 5203 | { |
8d5838b5 AC |
5204 | struct gdbarch_info info; |
5205 | gdbarch_info_init (&info); | |
c906108c SS |
5206 | mips_fpu_type = MIPS_FPU_NONE; |
5207 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
5208 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
5209 | instead of relying on globals. Doing that would let generic code | |
5210 | handle the search for this specific architecture. */ | |
5211 | if (!gdbarch_update_p (info)) | |
e2e0b3e5 | 5212 | internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); |
c906108c SS |
5213 | } |
5214 | ||
c906108c | 5215 | static void |
acdb74a0 | 5216 | set_mipsfpu_auto_command (char *args, int from_tty) |
c906108c SS |
5217 | { |
5218 | mips_fpu_type_auto = 1; | |
5219 | } | |
5220 | ||
c906108c | 5221 | /* Attempt to identify the particular processor model by reading the |
691c0433 AC |
5222 | processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that |
5223 | the relevant processor still exists (it dates back to '94) and | |
5224 | secondly this is not the way to do this. The processor type should | |
5225 | be set by forcing an architecture change. */ | |
c906108c | 5226 | |
691c0433 AC |
5227 | void |
5228 | deprecated_mips_set_processor_regs_hack (void) | |
c906108c | 5229 | { |
bb486190 UW |
5230 | struct regcache *regcache = get_current_regcache (); |
5231 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
5232 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
a9614958 | 5233 | ULONGEST prid; |
c906108c | 5234 | |
bb486190 | 5235 | regcache_cooked_read_unsigned (regcache, MIPS_PRID_REGNUM, &prid); |
c906108c | 5236 | if ((prid & ~0xf) == 0x700) |
691c0433 | 5237 | tdep->mips_processor_reg_names = mips_r3041_reg_names; |
c906108c SS |
5238 | } |
5239 | ||
5240 | /* Just like reinit_frame_cache, but with the right arguments to be | |
5241 | callable as an sfunc. */ | |
5242 | ||
5243 | static void | |
acdb74a0 AC |
5244 | reinit_frame_cache_sfunc (char *args, int from_tty, |
5245 | struct cmd_list_element *c) | |
c906108c SS |
5246 | { |
5247 | reinit_frame_cache (); | |
5248 | } | |
5249 | ||
a89aa300 AC |
5250 | static int |
5251 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 5252 | { |
d31431ed AC |
5253 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5254 | disassembler needs to be able to locally determine the ISA, and | |
5255 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
5256 | work. */ | |
ec4045ea AC |
5257 | if (mips_pc_is_mips16 (memaddr)) |
5258 | info->mach = bfd_mach_mips16; | |
c906108c SS |
5259 | |
5260 | /* Round down the instruction address to the appropriate boundary. */ | |
65c11066 | 5261 | memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); |
c5aa993b | 5262 | |
e5ab0dce | 5263 | /* Set the disassembler options. */ |
9dae60cc | 5264 | if (!info->disassembler_options) |
e5ab0dce AC |
5265 | /* This string is not recognized explicitly by the disassembler, |
5266 | but it tells the disassembler to not try to guess the ABI from | |
5267 | the bfd elf headers, such that, if the user overrides the ABI | |
5268 | of a program linked as NewABI, the disassembly will follow the | |
5269 | register naming conventions specified by the user. */ | |
5270 | info->disassembler_options = "gpr-names=32"; | |
5271 | ||
c906108c | 5272 | /* Call the appropriate disassembler based on the target endian-ness. */ |
40887e1a | 5273 | if (info->endian == BFD_ENDIAN_BIG) |
c906108c SS |
5274 | return print_insn_big_mips (memaddr, info); |
5275 | else | |
5276 | return print_insn_little_mips (memaddr, info); | |
5277 | } | |
5278 | ||
9dae60cc UW |
5279 | static int |
5280 | gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) | |
5281 | { | |
5282 | /* Set up the disassembler info, so that we get the right | |
5283 | register names from libopcodes. */ | |
5284 | info->disassembler_options = "gpr-names=n32"; | |
5285 | info->flavour = bfd_target_elf_flavour; | |
5286 | ||
5287 | return gdb_print_insn_mips (memaddr, info); | |
5288 | } | |
5289 | ||
5290 | static int | |
5291 | gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) | |
5292 | { | |
5293 | /* Set up the disassembler info, so that we get the right | |
5294 | register names from libopcodes. */ | |
5295 | info->disassembler_options = "gpr-names=64"; | |
5296 | info->flavour = bfd_target_elf_flavour; | |
5297 | ||
5298 | return gdb_print_insn_mips (memaddr, info); | |
5299 | } | |
5300 | ||
025bb325 MS |
5301 | /* This function implements gdbarch_breakpoint_from_pc. It uses the |
5302 | program counter value to determine whether a 16- or 32-bit breakpoint | |
5303 | should be used. It returns a pointer to a string of bytes that encode a | |
5304 | breakpoint instruction, stores the length of the string to *lenptr, and | |
5305 | adjusts pc (if necessary) to point to the actual memory location where | |
5306 | the breakpoint should be inserted. */ | |
c906108c | 5307 | |
47a35522 | 5308 | static const gdb_byte * |
025bb325 MS |
5309 | mips_breakpoint_from_pc (struct gdbarch *gdbarch, |
5310 | CORE_ADDR *pcptr, int *lenptr) | |
c906108c | 5311 | { |
67d57894 | 5312 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c | 5313 | { |
0fe7e7c8 | 5314 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5315 | { |
47a35522 | 5316 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
95404a3e | 5317 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5318 | *lenptr = sizeof (mips16_big_breakpoint); |
c906108c SS |
5319 | return mips16_big_breakpoint; |
5320 | } | |
5321 | else | |
5322 | { | |
aaab4dba AC |
5323 | /* The IDT board uses an unusual breakpoint value, and |
5324 | sometimes gets confused when it sees the usual MIPS | |
5325 | breakpoint instruction. */ | |
47a35522 MK |
5326 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5327 | static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | |
5328 | static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | |
f2ec0ecf | 5329 | /* Likewise, IRIX appears to expect a different breakpoint, |
025bb325 | 5330 | although this is not apparent until you try to use pthreads. */ |
f2ec0ecf | 5331 | static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; |
c906108c | 5332 | |
c5aa993b | 5333 | *lenptr = sizeof (big_breakpoint); |
c906108c SS |
5334 | |
5335 | if (strcmp (target_shortname, "mips") == 0) | |
5336 | return idt_big_breakpoint; | |
5337 | else if (strcmp (target_shortname, "ddb") == 0 | |
5338 | || strcmp (target_shortname, "pmon") == 0 | |
5339 | || strcmp (target_shortname, "lsi") == 0) | |
5340 | return pmon_big_breakpoint; | |
f2ec0ecf JB |
5341 | else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
5342 | return irix_big_breakpoint; | |
c906108c SS |
5343 | else |
5344 | return big_breakpoint; | |
5345 | } | |
5346 | } | |
5347 | else | |
5348 | { | |
0fe7e7c8 | 5349 | if (mips_pc_is_mips16 (*pcptr)) |
c906108c | 5350 | { |
47a35522 | 5351 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
95404a3e | 5352 | *pcptr = unmake_mips16_addr (*pcptr); |
c5aa993b | 5353 | *lenptr = sizeof (mips16_little_breakpoint); |
c906108c SS |
5354 | return mips16_little_breakpoint; |
5355 | } | |
5356 | else | |
5357 | { | |
47a35522 MK |
5358 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5359 | static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | |
5360 | static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | |
c906108c | 5361 | |
c5aa993b | 5362 | *lenptr = sizeof (little_breakpoint); |
c906108c SS |
5363 | |
5364 | if (strcmp (target_shortname, "mips") == 0) | |
5365 | return idt_little_breakpoint; | |
5366 | else if (strcmp (target_shortname, "ddb") == 0 | |
5367 | || strcmp (target_shortname, "pmon") == 0 | |
5368 | || strcmp (target_shortname, "lsi") == 0) | |
5369 | return pmon_little_breakpoint; | |
5370 | else | |
5371 | return little_breakpoint; | |
5372 | } | |
5373 | } | |
5374 | } | |
5375 | ||
c8cef75f MR |
5376 | /* Return non-zero if the ADDR instruction has a branch delay slot |
5377 | (i.e. it is a jump or branch instruction). This function is based | |
5378 | on mips32_next_pc. */ | |
5379 | ||
5380 | static int | |
5381 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) | |
5382 | { | |
5383 | gdb_byte buf[MIPS_INSN32_SIZE]; | |
5384 | unsigned long inst; | |
5385 | int status; | |
5386 | int op; | |
a385295e MR |
5387 | int rs; |
5388 | int rt; | |
c8cef75f MR |
5389 | |
5390 | status = target_read_memory (addr, buf, MIPS_INSN32_SIZE); | |
5391 | if (status) | |
5392 | return 0; | |
5393 | ||
5394 | inst = mips_fetch_instruction (gdbarch, addr); | |
5395 | op = itype_op (inst); | |
5396 | if ((inst & 0xe0000000) != 0) | |
a385295e MR |
5397 | { |
5398 | rs = itype_rs (inst); | |
5399 | rt = itype_rt (inst); | |
5400 | return (op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
5401 | || op == 29 /* JALX: bits 011101 */ | |
5402 | || (op == 17 | |
5403 | && (rs == 8 | |
c8cef75f | 5404 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
5405 | || (rs == 9 && (rt & 0x2) == 0) |
5406 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ | |
5407 | || (rs == 10 && (rt & 0x2) == 0)))); | |
5408 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ | |
5409 | } | |
c8cef75f MR |
5410 | else |
5411 | switch (op & 0x07) /* extract bits 28,27,26 */ | |
5412 | { | |
5413 | case 0: /* SPECIAL */ | |
5414 | op = rtype_funct (inst); | |
5415 | return (op == 8 /* JR */ | |
5416 | || op == 9); /* JALR */ | |
5417 | break; /* end SPECIAL */ | |
5418 | case 1: /* REGIMM */ | |
a385295e MR |
5419 | rs = itype_rs (inst); |
5420 | rt = itype_rt (inst); /* branch condition */ | |
5421 | return ((rt & 0xc) == 0 | |
c8cef75f MR |
5422 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
5423 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ | |
a385295e MR |
5424 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
5425 | /* BPOSGE32, BPOSGE64: bits 1110x */ | |
c8cef75f MR |
5426 | break; /* end REGIMM */ |
5427 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ | |
5428 | return 1; | |
5429 | break; | |
5430 | } | |
5431 | } | |
5432 | ||
5433 | /* Return non-zero if the ADDR instruction, which must be a 32-bit | |
5434 | instruction if MUSTBE32 is set or can be any instruction otherwise, | |
5435 | has a branch delay slot (i.e. it is a non-compact jump instruction). */ | |
5436 | ||
5437 | static int | |
5438 | mips16_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr, | |
5439 | int mustbe32) | |
5440 | { | |
5441 | gdb_byte buf[MIPS_INSN16_SIZE]; | |
5442 | unsigned short inst; | |
5443 | int status; | |
5444 | ||
5445 | status = target_read_memory (addr, buf, MIPS_INSN16_SIZE); | |
5446 | if (status) | |
5447 | return 0; | |
5448 | ||
5449 | inst = mips_fetch_instruction (gdbarch, addr); | |
5450 | if (!mustbe32) | |
5451 | return (inst & 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */ | |
5452 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ | |
5453 | } | |
5454 | ||
5455 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. | |
5456 | This assumes KSSEG exists. */ | |
5457 | ||
5458 | static CORE_ADDR | |
5459 | mips_segment_boundary (CORE_ADDR bpaddr) | |
5460 | { | |
5461 | CORE_ADDR mask = CORE_ADDR_MAX; | |
5462 | int segsize; | |
5463 | ||
5464 | if (sizeof (CORE_ADDR) == 8) | |
5465 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid | |
5466 | a compiler warning produced where CORE_ADDR is a 32-bit type even | |
5467 | though in that case this is dead code). */ | |
5468 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) | |
5469 | { | |
5470 | case 3: | |
5471 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) | |
5472 | segsize = 29; /* 32-bit compatibility segment */ | |
5473 | else | |
5474 | segsize = 62; /* xkseg */ | |
5475 | break; | |
5476 | case 2: /* xkphys */ | |
5477 | segsize = 59; | |
5478 | break; | |
5479 | default: /* xksseg (1), xkuseg/kuseg (0) */ | |
5480 | segsize = 62; | |
5481 | break; | |
5482 | } | |
5483 | else if (bpaddr & 0x80000000) /* kernel segment */ | |
5484 | segsize = 29; | |
5485 | else | |
5486 | segsize = 31; /* user segment */ | |
5487 | mask <<= segsize; | |
5488 | return bpaddr & mask; | |
5489 | } | |
5490 | ||
5491 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting | |
5492 | it backwards if necessary. Return the address of the new location. */ | |
5493 | ||
5494 | static CORE_ADDR | |
5495 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
5496 | { | |
5497 | CORE_ADDR prev_addr, next_addr; | |
5498 | CORE_ADDR boundary; | |
5499 | CORE_ADDR func_addr; | |
5500 | ||
5501 | /* If a breakpoint is set on the instruction in a branch delay slot, | |
5502 | GDB gets confused. When the breakpoint is hit, the PC isn't on | |
5503 | the instruction in the branch delay slot, the PC will point to | |
5504 | the branch instruction. Since the PC doesn't match any known | |
5505 | breakpoints, GDB reports a trap exception. | |
5506 | ||
5507 | There are two possible fixes for this problem. | |
5508 | ||
5509 | 1) When the breakpoint gets hit, see if the BD bit is set in the | |
5510 | Cause register (which indicates the last exception occurred in a | |
5511 | branch delay slot). If the BD bit is set, fix the PC to point to | |
5512 | the instruction in the branch delay slot. | |
5513 | ||
5514 | 2) When the user sets the breakpoint, don't allow him to set the | |
5515 | breakpoint on the instruction in the branch delay slot. Instead | |
5516 | move the breakpoint to the branch instruction (which will have | |
5517 | the same result). | |
5518 | ||
5519 | The problem with the first solution is that if the user then | |
5520 | single-steps the processor, the branch instruction will get | |
5521 | skipped (since GDB thinks the PC is on the instruction in the | |
5522 | branch delay slot). | |
5523 | ||
5524 | So, we'll use the second solution. To do this we need to know if | |
5525 | the instruction we're trying to set the breakpoint on is in the | |
5526 | branch delay slot. */ | |
5527 | ||
5528 | boundary = mips_segment_boundary (bpaddr); | |
5529 | ||
5530 | /* Make sure we don't scan back before the beginning of the current | |
5531 | function, since we may fetch constant data or insns that look like | |
5532 | a jump. Of course we might do that anyway if the compiler has | |
5533 | moved constants inline. :-( */ | |
5534 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) | |
5535 | && func_addr > boundary && func_addr <= bpaddr) | |
5536 | boundary = func_addr; | |
5537 | ||
5538 | if (!mips_pc_is_mips16 (bpaddr)) | |
5539 | { | |
5540 | if (bpaddr == boundary) | |
5541 | return bpaddr; | |
5542 | ||
5543 | /* If the previous instruction has a branch delay slot, we have | |
5544 | to move the breakpoint to the branch instruction. */ | |
5545 | prev_addr = bpaddr - 4; | |
5546 | if (mips32_instruction_has_delay_slot (gdbarch, prev_addr)) | |
5547 | bpaddr = prev_addr; | |
5548 | } | |
5549 | else | |
5550 | { | |
5551 | struct minimal_symbol *sym; | |
5552 | CORE_ADDR addr, jmpaddr; | |
5553 | int i; | |
5554 | ||
5555 | boundary = unmake_mips16_addr (boundary); | |
5556 | ||
5557 | /* The only MIPS16 instructions with delay slots are JAL, JALX, | |
5558 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, | |
5559 | so try for that first, then try the 2 byte JALR/JR. | |
5560 | FIXME: We have to assume that bpaddr is not the second half | |
5561 | of an extended instruction. */ | |
5562 | ||
5563 | jmpaddr = 0; | |
5564 | addr = bpaddr; | |
5565 | for (i = 1; i < 4; i++) | |
5566 | { | |
5567 | if (unmake_mips16_addr (addr) == boundary) | |
5568 | break; | |
5569 | addr -= 2; | |
5570 | if (i == 1 && mips16_instruction_has_delay_slot (gdbarch, addr, 0)) | |
5571 | /* Looks like a JR/JALR at [target-1], but it could be | |
5572 | the second word of a previous JAL/JALX, so record it | |
5573 | and check back one more. */ | |
5574 | jmpaddr = addr; | |
5575 | else if (i > 1 | |
5576 | && mips16_instruction_has_delay_slot (gdbarch, addr, 1)) | |
5577 | { | |
5578 | if (i == 2) | |
5579 | /* Looks like a JAL/JALX at [target-2], but it could also | |
5580 | be the second word of a previous JAL/JALX, record it, | |
5581 | and check back one more. */ | |
5582 | jmpaddr = addr; | |
5583 | else | |
5584 | /* Looks like a JAL/JALX at [target-3], so any previously | |
5585 | recorded JAL/JALX or JR/JALR must be wrong, because: | |
5586 | ||
5587 | >-3: JAL | |
5588 | -2: JAL-ext (can't be JAL/JALX) | |
5589 | -1: bdslot (can't be JR/JALR) | |
5590 | 0: target insn | |
5591 | ||
5592 | Of course it could be another JAL-ext which looks | |
5593 | like a JAL, but in that case we'd have broken out | |
5594 | of this loop at [target-2]: | |
5595 | ||
5596 | -4: JAL | |
5597 | >-3: JAL-ext | |
5598 | -2: bdslot (can't be jmp) | |
5599 | -1: JR/JALR | |
5600 | 0: target insn */ | |
5601 | jmpaddr = 0; | |
5602 | } | |
5603 | else | |
5604 | { | |
5605 | /* Not a jump instruction: if we're at [target-1] this | |
5606 | could be the second word of a JAL/JALX, so continue; | |
5607 | otherwise we're done. */ | |
5608 | if (i > 1) | |
5609 | break; | |
5610 | } | |
5611 | } | |
5612 | ||
5613 | if (jmpaddr) | |
5614 | bpaddr = jmpaddr; | |
5615 | } | |
5616 | ||
5617 | return bpaddr; | |
5618 | } | |
5619 | ||
c906108c SS |
5620 | /* If PC is in a mips16 call or return stub, return the address of the target |
5621 | PC, which is either the callee or the caller. There are several | |
5622 | cases which must be handled: | |
5623 | ||
5624 | * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
c5aa993b | 5625 | target PC is in $31 ($ra). |
c906108c | 5626 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
c5aa993b | 5627 | and the target PC is in $2. |
c906108c | 5628 | * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. |
c5aa993b | 5629 | before the jal instruction, this is effectively a call stub |
b021a221 | 5630 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 5631 | a return stub and the target PC is in $18. |
c906108c SS |
5632 | |
5633 | See the source code for the stubs in gcc/config/mips/mips16.S for | |
e7d6a6d2 | 5634 | gory details. */ |
c906108c | 5635 | |
757a7cc6 | 5636 | static CORE_ADDR |
db5f024e | 5637 | mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 5638 | { |
e17a4113 | 5639 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2c02bd72 | 5640 | const char *name; |
c906108c SS |
5641 | CORE_ADDR start_addr; |
5642 | ||
5643 | /* Find the starting address and name of the function containing the PC. */ | |
5644 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
5645 | return 0; | |
5646 | ||
5647 | /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | |
5648 | target PC is in $31 ($ra). */ | |
5649 | if (strcmp (name, "__mips16_ret_sf") == 0 | |
5650 | || strcmp (name, "__mips16_ret_df") == 0) | |
52f729a7 | 5651 | return get_frame_register_signed (frame, MIPS_RA_REGNUM); |
c906108c SS |
5652 | |
5653 | if (strncmp (name, "__mips16_call_stub_", 19) == 0) | |
5654 | { | |
5655 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
5656 | and the target PC is in $2. */ | |
5657 | if (name[19] >= '0' && name[19] <= '9') | |
52f729a7 | 5658 | return get_frame_register_signed (frame, 2); |
c906108c SS |
5659 | |
5660 | /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | |
c5aa993b | 5661 | before the jal instruction, this is effectively a call stub |
b021a221 | 5662 | and the target PC is in $2. Otherwise this is effectively |
c5aa993b | 5663 | a return stub and the target PC is in $18. */ |
c906108c SS |
5664 | else if (name[19] == 's' || name[19] == 'd') |
5665 | { | |
5666 | if (pc == start_addr) | |
5667 | { | |
5668 | /* Check if the target of the stub is a compiler-generated | |
c5aa993b JM |
5669 | stub. Such a stub for a function bar might have a name |
5670 | like __fn_stub_bar, and might look like this: | |
5671 | mfc1 $4,$f13 | |
5672 | mfc1 $5,$f12 | |
5673 | mfc1 $6,$f15 | |
5674 | mfc1 $7,$f14 | |
5675 | la $1,bar (becomes a lui/addiu pair) | |
5676 | jr $1 | |
5677 | So scan down to the lui/addi and extract the target | |
5678 | address from those two instructions. */ | |
c906108c | 5679 | |
52f729a7 | 5680 | CORE_ADDR target_pc = get_frame_register_signed (frame, 2); |
c906108c SS |
5681 | int i; |
5682 | ||
5683 | /* See if the name of the target function is __fn_stub_*. */ | |
6d82d43b AC |
5684 | if (find_pc_partial_function (target_pc, &name, NULL, NULL) == |
5685 | 0) | |
c906108c SS |
5686 | return target_pc; |
5687 | if (strncmp (name, "__fn_stub_", 10) != 0 | |
5688 | && strcmp (name, "etext") != 0 | |
5689 | && strcmp (name, "_etext") != 0) | |
5690 | return target_pc; | |
5691 | ||
5692 | /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
c5aa993b JM |
5693 | The limit on the search is arbitrarily set to 20 |
5694 | instructions. FIXME. */ | |
95ac2dcf | 5695 | for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) |
c906108c | 5696 | { |
280711e7 MR |
5697 | ULONGEST inst = mips_fetch_instruction (gdbarch, target_pc); |
5698 | CORE_ADDR addr = inst; | |
5699 | ||
c5aa993b | 5700 | if ((inst & 0xffff0000) == 0x3c010000) /* lui $at */ |
280711e7 MR |
5701 | pc = (((addr & 0xffff) ^ 0x8000) - 0x8000) << 16; |
5702 | /* high word */ | |
c5aa993b | 5703 | else if ((inst & 0xffff0000) == 0x24210000) /* addiu $at */ |
280711e7 MR |
5704 | return pc + ((addr & 0xffff) ^ 0x8000) - 0x8000; |
5705 | /* low word */ | |
c906108c SS |
5706 | } |
5707 | ||
5708 | /* Couldn't find the lui/addui pair, so return stub address. */ | |
5709 | return target_pc; | |
5710 | } | |
5711 | else | |
5712 | /* This is the 'return' part of a call stub. The return | |
5713 | address is in $r18. */ | |
52f729a7 | 5714 | return get_frame_register_signed (frame, 18); |
c906108c SS |
5715 | } |
5716 | } | |
c5aa993b | 5717 | return 0; /* not a stub */ |
c906108c SS |
5718 | } |
5719 | ||
db5f024e DJ |
5720 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
5721 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
5722 | so that $t9 has the correct value at function entry. */ | |
5723 | ||
5724 | static CORE_ADDR | |
5725 | mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5726 | { | |
e17a4113 UW |
5727 | struct gdbarch *gdbarch = get_frame_arch (frame); |
5728 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
db5f024e DJ |
5729 | struct minimal_symbol *msym; |
5730 | int i; | |
5731 | gdb_byte stub_code[16]; | |
5732 | int32_t stub_words[4]; | |
5733 | ||
5734 | /* The stub for foo is named ".pic.foo", and is either two | |
5735 | instructions inserted before foo or a three instruction sequence | |
5736 | which jumps to foo. */ | |
5737 | msym = lookup_minimal_symbol_by_pc (pc); | |
5738 | if (msym == NULL | |
5739 | || SYMBOL_VALUE_ADDRESS (msym) != pc | |
5740 | || SYMBOL_LINKAGE_NAME (msym) == NULL | |
5741 | || strncmp (SYMBOL_LINKAGE_NAME (msym), ".pic.", 5) != 0) | |
5742 | return 0; | |
5743 | ||
5744 | /* A two-instruction header. */ | |
5745 | if (MSYMBOL_SIZE (msym) == 8) | |
5746 | return pc + 8; | |
5747 | ||
5748 | /* A three-instruction (plus delay slot) trampoline. */ | |
5749 | if (MSYMBOL_SIZE (msym) == 16) | |
5750 | { | |
5751 | if (target_read_memory (pc, stub_code, 16) != 0) | |
5752 | return 0; | |
5753 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
5754 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
5755 | 4, byte_order); | |
db5f024e DJ |
5756 | |
5757 | /* A stub contains these instructions: | |
5758 | lui t9, %hi(target) | |
5759 | j target | |
5760 | addiu t9, t9, %lo(target) | |
5761 | nop | |
5762 | ||
5763 | This works even for N64, since stubs are only generated with | |
5764 | -msym32. */ | |
5765 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
5766 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
5767 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
5768 | && stub_words[3] == 0x00000000) | |
5769 | return (((stub_words[0] & 0x0000ffff) << 16) | |
5770 | + (stub_words[2] & 0x0000ffff)); | |
5771 | } | |
5772 | ||
5773 | /* Not a recognized stub. */ | |
5774 | return 0; | |
5775 | } | |
5776 | ||
5777 | static CORE_ADDR | |
5778 | mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | |
5779 | { | |
5780 | CORE_ADDR target_pc; | |
5781 | ||
5782 | target_pc = mips_skip_mips16_trampoline_code (frame, pc); | |
5783 | if (target_pc) | |
5784 | return target_pc; | |
5785 | ||
5786 | target_pc = find_solib_trampoline_target (frame, pc); | |
5787 | if (target_pc) | |
5788 | return target_pc; | |
5789 | ||
5790 | target_pc = mips_skip_pic_trampoline_code (frame, pc); | |
5791 | if (target_pc) | |
5792 | return target_pc; | |
5793 | ||
5794 | return 0; | |
5795 | } | |
5796 | ||
a4b8ebc8 | 5797 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 5798 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5799 | |
5800 | static int | |
d3f73121 | 5801 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5802 | { |
a4b8ebc8 | 5803 | int regnum; |
2f38ef89 | 5804 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5805 | regnum = num; |
2f38ef89 | 5806 | else if (num >= 38 && num < 70) |
d3f73121 | 5807 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 5808 | else if (num == 70) |
d3f73121 | 5809 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5810 | else if (num == 71) |
d3f73121 | 5811 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
5812 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
5813 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; | |
2f38ef89 | 5814 | else |
a4b8ebc8 AC |
5815 | /* This will hopefully (eventually) provoke a warning. Should |
5816 | we be calling complaint() here? */ | |
d3f73121 MD |
5817 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5818 | return gdbarch_num_regs (gdbarch) + regnum; | |
88c72b7d AC |
5819 | } |
5820 | ||
2f38ef89 | 5821 | |
a4b8ebc8 | 5822 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 5823 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
5824 | |
5825 | static int | |
d3f73121 | 5826 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 5827 | { |
a4b8ebc8 | 5828 | int regnum; |
2f38ef89 | 5829 | if (num >= 0 && num < 32) |
a4b8ebc8 | 5830 | regnum = num; |
2f38ef89 | 5831 | else if (num >= 32 && num < 64) |
d3f73121 | 5832 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 5833 | else if (num == 64) |
d3f73121 | 5834 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 5835 | else if (num == 65) |
d3f73121 | 5836 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
5837 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
5838 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; | |
2f38ef89 | 5839 | else |
a4b8ebc8 AC |
5840 | /* This will hopefully (eventually) provoke a warning. Should we |
5841 | be calling complaint() here? */ | |
d3f73121 MD |
5842 | return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5843 | return gdbarch_num_regs (gdbarch) + regnum; | |
a4b8ebc8 AC |
5844 | } |
5845 | ||
5846 | static int | |
e7faf938 | 5847 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
5848 | { |
5849 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 5850 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
5851 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
5852 | decide if it is valid. Should instead define a standard sim/gdb | |
5853 | register numbering scheme. */ | |
e7faf938 MD |
5854 | if (gdbarch_register_name (gdbarch, |
5855 | gdbarch_num_regs (gdbarch) + regnum) != NULL | |
5856 | && gdbarch_register_name (gdbarch, | |
025bb325 MS |
5857 | gdbarch_num_regs (gdbarch) |
5858 | + regnum)[0] != '\0') | |
a4b8ebc8 AC |
5859 | return regnum; |
5860 | else | |
6d82d43b | 5861 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
5862 | } |
5863 | ||
2f38ef89 | 5864 | |
4844f454 CV |
5865 | /* Convert an integer into an address. Extracting the value signed |
5866 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
5867 | |
5868 | static CORE_ADDR | |
79dd2d24 | 5869 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 5870 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 5871 | { |
e17a4113 UW |
5872 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
5873 | return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); | |
fc0c74b1 AC |
5874 | } |
5875 | ||
82e91389 DJ |
5876 | /* Dummy virtual frame pointer method. This is no more or less accurate |
5877 | than most other architectures; we just need to be explicit about it, | |
5878 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
5879 | an assertion failure. */ | |
5880 | ||
5881 | static void | |
a54fba4c MD |
5882 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
5883 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
5884 | { |
5885 | *reg = MIPS_SP_REGNUM; | |
5886 | *offset = 0; | |
5887 | } | |
5888 | ||
caaa3122 DJ |
5889 | static void |
5890 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
5891 | { | |
5892 | enum mips_abi *abip = (enum mips_abi *) obj; | |
5893 | const char *name = bfd_get_section_name (abfd, sect); | |
5894 | ||
5895 | if (*abip != MIPS_ABI_UNKNOWN) | |
5896 | return; | |
5897 | ||
5898 | if (strncmp (name, ".mdebug.", 8) != 0) | |
5899 | return; | |
5900 | ||
5901 | if (strcmp (name, ".mdebug.abi32") == 0) | |
5902 | *abip = MIPS_ABI_O32; | |
5903 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
5904 | *abip = MIPS_ABI_N32; | |
62a49b2c | 5905 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 5906 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
5907 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
5908 | *abip = MIPS_ABI_O64; | |
5909 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
5910 | *abip = MIPS_ABI_EABI32; | |
5911 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
5912 | *abip = MIPS_ABI_EABI64; | |
5913 | else | |
8a3fe4f8 | 5914 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
5915 | } |
5916 | ||
22e47e37 FF |
5917 | static void |
5918 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
5919 | { | |
5920 | int *lbp = (int *) obj; | |
5921 | const char *name = bfd_get_section_name (abfd, sect); | |
5922 | ||
5923 | if (strncmp (name, ".gcc_compiled_long32", 20) == 0) | |
5924 | *lbp = 32; | |
5925 | else if (strncmp (name, ".gcc_compiled_long64", 20) == 0) | |
5926 | *lbp = 64; | |
5927 | else if (strncmp (name, ".gcc_compiled_long", 18) == 0) | |
5928 | warning (_("unrecognized .gcc_compiled_longXX")); | |
5929 | } | |
5930 | ||
2e4ebe70 DJ |
5931 | static enum mips_abi |
5932 | global_mips_abi (void) | |
5933 | { | |
5934 | int i; | |
5935 | ||
5936 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
5937 | if (mips_abi_strings[i] == mips_abi_string) | |
5938 | return (enum mips_abi) i; | |
5939 | ||
e2e0b3e5 | 5940 | internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
2e4ebe70 DJ |
5941 | } |
5942 | ||
29709017 DJ |
5943 | static void |
5944 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
5945 | { | |
29709017 DJ |
5946 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
5947 | assume that's what we've got. */ | |
4eb0ad19 DJ |
5948 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5949 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5950 | |
5951 | /* If the size matches the full set of registers GDB traditionally | |
5952 | knows about, including floating point, for either 32-bit or | |
5953 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
5954 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
5955 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
5956 | |
5957 | /* Otherwise we don't have a useful guess. */ | |
5958 | } | |
5959 | ||
f8b73d13 DJ |
5960 | static struct value * |
5961 | value_of_mips_user_reg (struct frame_info *frame, const void *baton) | |
5962 | { | |
5963 | const int *reg_p = baton; | |
5964 | return value_of_register (*reg_p, frame); | |
5965 | } | |
5966 | ||
c2d11a7d | 5967 | static struct gdbarch * |
6d82d43b | 5968 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 5969 | { |
c2d11a7d JM |
5970 | struct gdbarch *gdbarch; |
5971 | struct gdbarch_tdep *tdep; | |
5972 | int elf_flags; | |
2e4ebe70 | 5973 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 5974 | int i, num_regs; |
8d5838b5 | 5975 | enum mips_fpu_type fpu_type; |
f8b73d13 | 5976 | struct tdesc_arch_data *tdesc_data = NULL; |
609ca2b9 | 5977 | int elf_fpu_type = 0; |
1faeff08 MR |
5978 | const char **reg_names; |
5979 | struct mips_regnum mips_regnum, *regnum; | |
5980 | int dspacc; | |
5981 | int dspctl; | |
5982 | ||
5983 | /* Fill in the OS dependent register numbers and names. */ | |
5984 | if (info.osabi == GDB_OSABI_IRIX) | |
5985 | { | |
5986 | mips_regnum.fp0 = 32; | |
5987 | mips_regnum.pc = 64; | |
5988 | mips_regnum.cause = 65; | |
5989 | mips_regnum.badvaddr = 66; | |
5990 | mips_regnum.hi = 67; | |
5991 | mips_regnum.lo = 68; | |
5992 | mips_regnum.fp_control_status = 69; | |
5993 | mips_regnum.fp_implementation_revision = 70; | |
5994 | mips_regnum.dspacc = dspacc = -1; | |
5995 | mips_regnum.dspctl = dspctl = -1; | |
5996 | num_regs = 71; | |
5997 | reg_names = mips_irix_reg_names; | |
5998 | } | |
5999 | else if (info.osabi == GDB_OSABI_LINUX) | |
6000 | { | |
6001 | mips_regnum.fp0 = 38; | |
6002 | mips_regnum.pc = 37; | |
6003 | mips_regnum.cause = 36; | |
6004 | mips_regnum.badvaddr = 35; | |
6005 | mips_regnum.hi = 34; | |
6006 | mips_regnum.lo = 33; | |
6007 | mips_regnum.fp_control_status = 70; | |
6008 | mips_regnum.fp_implementation_revision = 71; | |
6009 | mips_regnum.dspacc = -1; | |
6010 | mips_regnum.dspctl = -1; | |
6011 | dspacc = 72; | |
6012 | dspctl = 78; | |
6013 | num_regs = 79; | |
6014 | reg_names = mips_linux_reg_names; | |
6015 | } | |
6016 | else | |
6017 | { | |
6018 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; | |
6019 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; | |
6020 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
6021 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; | |
6022 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; | |
6023 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; | |
6024 | mips_regnum.fp_control_status = 70; | |
6025 | mips_regnum.fp_implementation_revision = 71; | |
6026 | mips_regnum.dspacc = dspacc = -1; | |
6027 | mips_regnum.dspctl = dspctl = -1; | |
6028 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
6029 | if (info.bfd_arch_info != NULL | |
6030 | && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
6031 | reg_names = mips_tx39_reg_names; | |
6032 | else | |
6033 | reg_names = mips_generic_reg_names; | |
6034 | } | |
f8b73d13 DJ |
6035 | |
6036 | /* Check any target description for validity. */ | |
6037 | if (tdesc_has_registers (info.target_desc)) | |
6038 | { | |
6039 | static const char *const mips_gprs[] = { | |
6040 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
6041 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
6042 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
6043 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
6044 | }; | |
6045 | static const char *const mips_fprs[] = { | |
6046 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
6047 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
6048 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
6049 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
6050 | }; | |
6051 | ||
6052 | const struct tdesc_feature *feature; | |
6053 | int valid_p; | |
6054 | ||
6055 | feature = tdesc_find_feature (info.target_desc, | |
6056 | "org.gnu.gdb.mips.cpu"); | |
6057 | if (feature == NULL) | |
6058 | return NULL; | |
6059 | ||
6060 | tdesc_data = tdesc_data_alloc (); | |
6061 | ||
6062 | valid_p = 1; | |
6063 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
6064 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | |
6065 | mips_gprs[i]); | |
6066 | ||
6067 | ||
6068 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 6069 | mips_regnum.lo, "lo"); |
f8b73d13 | 6070 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 6071 | mips_regnum.hi, "hi"); |
f8b73d13 | 6072 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
1faeff08 | 6073 | mips_regnum.pc, "pc"); |
f8b73d13 DJ |
6074 | |
6075 | if (!valid_p) | |
6076 | { | |
6077 | tdesc_data_cleanup (tdesc_data); | |
6078 | return NULL; | |
6079 | } | |
6080 | ||
6081 | feature = tdesc_find_feature (info.target_desc, | |
6082 | "org.gnu.gdb.mips.cp0"); | |
6083 | if (feature == NULL) | |
6084 | { | |
6085 | tdesc_data_cleanup (tdesc_data); | |
6086 | return NULL; | |
6087 | } | |
6088 | ||
6089 | valid_p = 1; | |
6090 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 6091 | mips_regnum.badvaddr, "badvaddr"); |
f8b73d13 DJ |
6092 | valid_p &= tdesc_numbered_register (feature, tdesc_data, |
6093 | MIPS_PS_REGNUM, "status"); | |
6094 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 6095 | mips_regnum.cause, "cause"); |
f8b73d13 DJ |
6096 | |
6097 | if (!valid_p) | |
6098 | { | |
6099 | tdesc_data_cleanup (tdesc_data); | |
6100 | return NULL; | |
6101 | } | |
6102 | ||
6103 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
6104 | backend is not prepared for that, though. */ | |
6105 | feature = tdesc_find_feature (info.target_desc, | |
6106 | "org.gnu.gdb.mips.fpu"); | |
6107 | if (feature == NULL) | |
6108 | { | |
6109 | tdesc_data_cleanup (tdesc_data); | |
6110 | return NULL; | |
6111 | } | |
6112 | ||
6113 | valid_p = 1; | |
6114 | for (i = 0; i < 32; i++) | |
6115 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 | 6116 | i + mips_regnum.fp0, mips_fprs[i]); |
f8b73d13 DJ |
6117 | |
6118 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
1faeff08 MR |
6119 | mips_regnum.fp_control_status, |
6120 | "fcsr"); | |
6121 | valid_p | |
6122 | &= tdesc_numbered_register (feature, tdesc_data, | |
6123 | mips_regnum.fp_implementation_revision, | |
6124 | "fir"); | |
f8b73d13 DJ |
6125 | |
6126 | if (!valid_p) | |
6127 | { | |
6128 | tdesc_data_cleanup (tdesc_data); | |
6129 | return NULL; | |
6130 | } | |
6131 | ||
1faeff08 MR |
6132 | if (dspacc >= 0) |
6133 | { | |
6134 | feature = tdesc_find_feature (info.target_desc, | |
6135 | "org.gnu.gdb.mips.dsp"); | |
6136 | /* The DSP registers are optional; it's OK if they are absent. */ | |
6137 | if (feature != NULL) | |
6138 | { | |
6139 | i = 0; | |
6140 | valid_p = 1; | |
6141 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6142 | dspacc + i++, "hi1"); | |
6143 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6144 | dspacc + i++, "lo1"); | |
6145 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6146 | dspacc + i++, "hi2"); | |
6147 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6148 | dspacc + i++, "lo2"); | |
6149 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6150 | dspacc + i++, "hi3"); | |
6151 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6152 | dspacc + i++, "lo3"); | |
6153 | ||
6154 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6155 | dspctl, "dspctl"); | |
6156 | ||
6157 | if (!valid_p) | |
6158 | { | |
6159 | tdesc_data_cleanup (tdesc_data); | |
6160 | return NULL; | |
6161 | } | |
6162 | ||
6163 | mips_regnum.dspacc = dspacc; | |
6164 | mips_regnum.dspctl = dspctl; | |
6165 | } | |
6166 | } | |
6167 | ||
f8b73d13 DJ |
6168 | /* It would be nice to detect an attempt to use a 64-bit ABI |
6169 | when only 32-bit registers are provided. */ | |
1faeff08 | 6170 | reg_names = NULL; |
f8b73d13 | 6171 | } |
c2d11a7d | 6172 | |
ec03c1ac AC |
6173 | /* First of all, extract the elf_flags, if available. */ |
6174 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
6175 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 AC |
6176 | else if (arches != NULL) |
6177 | elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | |
ec03c1ac AC |
6178 | else |
6179 | elf_flags = 0; | |
6180 | if (gdbarch_debug) | |
6181 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 6182 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); |
c2d11a7d | 6183 | |
102182a9 | 6184 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
6185 | switch ((elf_flags & EF_MIPS_ABI)) |
6186 | { | |
6187 | case E_MIPS_ABI_O32: | |
ec03c1ac | 6188 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
6189 | break; |
6190 | case E_MIPS_ABI_O64: | |
ec03c1ac | 6191 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
6192 | break; |
6193 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 6194 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
6195 | break; |
6196 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 6197 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
6198 | break; |
6199 | default: | |
acdb74a0 | 6200 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 6201 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 6202 | else |
ec03c1ac | 6203 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
6204 | break; |
6205 | } | |
acdb74a0 | 6206 | |
caaa3122 | 6207 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
6208 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
6209 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 6210 | |
dc305454 | 6211 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
6212 | MIPS architecture (if there is one). */ |
6213 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
6214 | found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; | |
2e4ebe70 | 6215 | |
32a6503c | 6216 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 6217 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
6218 | && info.bfd_arch_info != NULL |
6219 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
6220 | { | |
6221 | switch (info.bfd_arch_info->mach) | |
6222 | { | |
6223 | case bfd_mach_mips3900: | |
ec03c1ac | 6224 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
6225 | break; |
6226 | case bfd_mach_mips4100: | |
6227 | case bfd_mach_mips5000: | |
ec03c1ac | 6228 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 6229 | break; |
1d06468c EZ |
6230 | case bfd_mach_mips8000: |
6231 | case bfd_mach_mips10000: | |
32a6503c KB |
6232 | /* On Irix, ELF64 executables use the N64 ABI. The |
6233 | pseudo-sections which describe the ABI aren't present | |
6234 | on IRIX. (Even for executables created by gcc.) */ | |
28d169de KB |
6235 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour |
6236 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
ec03c1ac | 6237 | found_abi = MIPS_ABI_N64; |
28d169de | 6238 | else |
ec03c1ac | 6239 | found_abi = MIPS_ABI_N32; |
1d06468c | 6240 | break; |
bf64bfd6 AC |
6241 | } |
6242 | } | |
2e4ebe70 | 6243 | |
26c53e50 DJ |
6244 | /* Default 64-bit objects to N64 instead of O32. */ |
6245 | if (found_abi == MIPS_ABI_UNKNOWN | |
6246 | && info.abfd != NULL | |
6247 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
6248 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
6249 | found_abi = MIPS_ABI_N64; | |
6250 | ||
ec03c1ac AC |
6251 | if (gdbarch_debug) |
6252 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", | |
6253 | found_abi); | |
6254 | ||
6255 | /* What has the user specified from the command line? */ | |
6256 | wanted_abi = global_mips_abi (); | |
6257 | if (gdbarch_debug) | |
6258 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", | |
6259 | wanted_abi); | |
2e4ebe70 DJ |
6260 | |
6261 | /* Now that we have found what the ABI for this binary would be, | |
6262 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
6263 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
6264 | mips_abi = wanted_abi; | |
ec03c1ac AC |
6265 | else if (found_abi != MIPS_ABI_UNKNOWN) |
6266 | mips_abi = found_abi; | |
6267 | else | |
6268 | mips_abi = MIPS_ABI_O32; | |
6269 | if (gdbarch_debug) | |
6270 | fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | |
6271 | mips_abi); | |
2e4ebe70 | 6272 | |
ec03c1ac | 6273 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 6274 | if (gdbarch_debug) |
ec03c1ac | 6275 | fprintf_unfiltered (gdb_stdlog, |
025bb325 MS |
6276 | "mips_gdbarch_init: " |
6277 | "mips64_transfers_32bit_regs_p = %d\n", | |
ec03c1ac | 6278 | mips64_transfers_32bit_regs_p); |
0dadbba0 | 6279 | |
8d5838b5 | 6280 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
6281 | #ifdef HAVE_ELF |
6282 | if (info.abfd | |
6283 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
6284 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
6285 | Tag_GNU_MIPS_ABI_FP); | |
6286 | #endif /* HAVE_ELF */ | |
6287 | ||
8d5838b5 AC |
6288 | if (!mips_fpu_type_auto) |
6289 | fpu_type = mips_fpu_type; | |
609ca2b9 DJ |
6290 | else if (elf_fpu_type != 0) |
6291 | { | |
6292 | switch (elf_fpu_type) | |
6293 | { | |
6294 | case 1: | |
6295 | fpu_type = MIPS_FPU_DOUBLE; | |
6296 | break; | |
6297 | case 2: | |
6298 | fpu_type = MIPS_FPU_SINGLE; | |
6299 | break; | |
6300 | case 3: | |
6301 | default: | |
6302 | /* Soft float or unknown. */ | |
6303 | fpu_type = MIPS_FPU_NONE; | |
6304 | break; | |
6305 | } | |
6306 | } | |
8d5838b5 AC |
6307 | else if (info.bfd_arch_info != NULL |
6308 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
6309 | switch (info.bfd_arch_info->mach) | |
6310 | { | |
6311 | case bfd_mach_mips3900: | |
6312 | case bfd_mach_mips4100: | |
6313 | case bfd_mach_mips4111: | |
a9d61c86 | 6314 | case bfd_mach_mips4120: |
8d5838b5 AC |
6315 | fpu_type = MIPS_FPU_NONE; |
6316 | break; | |
6317 | case bfd_mach_mips4650: | |
6318 | fpu_type = MIPS_FPU_SINGLE; | |
6319 | break; | |
6320 | default: | |
6321 | fpu_type = MIPS_FPU_DOUBLE; | |
6322 | break; | |
6323 | } | |
6324 | else if (arches != NULL) | |
6325 | fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; | |
6326 | else | |
6327 | fpu_type = MIPS_FPU_DOUBLE; | |
6328 | if (gdbarch_debug) | |
6329 | fprintf_unfiltered (gdb_stdlog, | |
6d82d43b | 6330 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); |
8d5838b5 | 6331 | |
29709017 DJ |
6332 | /* Check for blatant incompatibilities. */ |
6333 | ||
6334 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
6335 | ABI. */ | |
6336 | if (info.target_desc | |
6337 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
6338 | && mips_abi != MIPS_ABI_EABI32 | |
6339 | && mips_abi != MIPS_ABI_O32) | |
f8b73d13 DJ |
6340 | { |
6341 | if (tdesc_data != NULL) | |
6342 | tdesc_data_cleanup (tdesc_data); | |
6343 | return NULL; | |
6344 | } | |
29709017 | 6345 | |
025bb325 | 6346 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
6347 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
6348 | arches != NULL; | |
6349 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
6350 | { | |
6351 | /* MIPS needs to be pedantic about which ABI the object is | |
102182a9 | 6352 | using. */ |
9103eae0 | 6353 | if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) |
c2d11a7d | 6354 | continue; |
9103eae0 | 6355 | if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) |
0dadbba0 | 6356 | continue; |
719ec221 AC |
6357 | /* Need to be pedantic about which register virtual size is |
6358 | used. */ | |
6359 | if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p | |
6360 | != mips64_transfers_32bit_regs_p) | |
6361 | continue; | |
8d5838b5 AC |
6362 | /* Be pedantic about which FPU is selected. */ |
6363 | if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) | |
6364 | continue; | |
f8b73d13 DJ |
6365 | |
6366 | if (tdesc_data != NULL) | |
6367 | tdesc_data_cleanup (tdesc_data); | |
4be87837 | 6368 | return arches->gdbarch; |
c2d11a7d JM |
6369 | } |
6370 | ||
102182a9 | 6371 | /* Need a new architecture. Fill in a target specific vector. */ |
c2d11a7d JM |
6372 | tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
6373 | gdbarch = gdbarch_alloc (&info, tdep); | |
6374 | tdep->elf_flags = elf_flags; | |
719ec221 | 6375 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
6376 | tdep->found_abi = found_abi; |
6377 | tdep->mips_abi = mips_abi; | |
8d5838b5 | 6378 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
6379 | tdep->register_size_valid_p = 0; |
6380 | tdep->register_size = 0; | |
50e8a0d5 HZ |
6381 | tdep->gregset = NULL; |
6382 | tdep->gregset64 = NULL; | |
6383 | tdep->fpregset = NULL; | |
6384 | tdep->fpregset64 = NULL; | |
29709017 DJ |
6385 | |
6386 | if (info.target_desc) | |
6387 | { | |
6388 | /* Some useful properties can be inferred from the target. */ | |
6389 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
6390 | { | |
6391 | tdep->register_size_valid_p = 1; | |
6392 | tdep->register_size = 4; | |
6393 | } | |
6394 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
6395 | { | |
6396 | tdep->register_size_valid_p = 1; | |
6397 | tdep->register_size = 8; | |
6398 | } | |
6399 | } | |
c2d11a7d | 6400 | |
102182a9 | 6401 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
6402 | set_gdbarch_short_bit (gdbarch, 16); |
6403 | set_gdbarch_int_bit (gdbarch, 32); | |
6404 | set_gdbarch_float_bit (gdbarch, 32); | |
6405 | set_gdbarch_double_bit (gdbarch, 64); | |
6406 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
6407 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
6408 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
6409 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 6410 | |
175ff332 HZ |
6411 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
6412 | mips_ax_pseudo_register_collect); | |
6413 | set_gdbarch_ax_pseudo_register_push_stack | |
6414 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
6415 | ||
6d82d43b | 6416 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 MS |
6417 | mips_elf_make_msymbol_special); |
6418 | ||
1faeff08 MR |
6419 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
6420 | *regnum = mips_regnum; | |
1faeff08 MR |
6421 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
6422 | set_gdbarch_num_regs (gdbarch, num_regs); | |
6423 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6424 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
6425 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
6426 | tdep->mips_processor_reg_names = reg_names; | |
6427 | tdep->regnum = regnum; | |
fe29b929 | 6428 | |
0dadbba0 | 6429 | switch (mips_abi) |
c2d11a7d | 6430 | { |
0dadbba0 | 6431 | case MIPS_ABI_O32: |
25ab4790 | 6432 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 6433 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 6434 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 6435 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 6436 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6437 | set_gdbarch_long_bit (gdbarch, 32); |
6438 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6439 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6440 | break; | |
0dadbba0 | 6441 | case MIPS_ABI_O64: |
25ab4790 | 6442 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 6443 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 6444 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 6445 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 6446 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6447 | set_gdbarch_long_bit (gdbarch, 32); |
6448 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6449 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6450 | break; | |
0dadbba0 | 6451 | case MIPS_ABI_EABI32: |
25ab4790 | 6452 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 6453 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 6454 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6455 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6456 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6457 | set_gdbarch_long_bit (gdbarch, 32); |
6458 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6459 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6460 | break; | |
0dadbba0 | 6461 | case MIPS_ABI_EABI64: |
25ab4790 | 6462 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 6463 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 6464 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6465 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6466 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
6467 | set_gdbarch_long_bit (gdbarch, 64); |
6468 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6469 | set_gdbarch_long_long_bit (gdbarch, 64); | |
6470 | break; | |
0dadbba0 | 6471 | case MIPS_ABI_N32: |
25ab4790 | 6472 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6473 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 6474 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6475 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 6476 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
6477 | set_gdbarch_long_bit (gdbarch, 32); |
6478 | set_gdbarch_ptr_bit (gdbarch, 32); | |
6479 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6480 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6481 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
6482 | break; |
6483 | case MIPS_ABI_N64: | |
25ab4790 | 6484 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 6485 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 6486 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 6487 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
6488 | tdep->default_mask_address_p = 0; |
6489 | set_gdbarch_long_bit (gdbarch, 64); | |
6490 | set_gdbarch_ptr_bit (gdbarch, 64); | |
6491 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 6492 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 6493 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 6494 | break; |
c2d11a7d | 6495 | default: |
e2e0b3e5 | 6496 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); |
c2d11a7d JM |
6497 | } |
6498 | ||
22e47e37 FF |
6499 | /* GCC creates a pseudo-section whose name specifies the size of |
6500 | longs, since -mlong32 or -mlong64 may be used independent of | |
6501 | other options. How those options affect pointer sizes is ABI and | |
6502 | architecture dependent, so use them to override the default sizes | |
6503 | set by the ABI. This table shows the relationship between ABI, | |
6504 | -mlongXX, and size of pointers: | |
6505 | ||
6506 | ABI -mlongXX ptr bits | |
6507 | --- -------- -------- | |
6508 | o32 32 32 | |
6509 | o32 64 32 | |
6510 | n32 32 32 | |
6511 | n32 64 64 | |
6512 | o64 32 32 | |
6513 | o64 64 64 | |
6514 | n64 32 32 | |
6515 | n64 64 64 | |
6516 | eabi32 32 32 | |
6517 | eabi32 64 32 | |
6518 | eabi64 32 32 | |
6519 | eabi64 64 64 | |
6520 | ||
6521 | Note that for o32 and eabi32, pointers are always 32 bits | |
6522 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 6523 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
6524 | |
6525 | if (info.abfd != NULL) | |
6526 | { | |
6527 | int long_bit = 0; | |
6528 | ||
6529 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
6530 | if (long_bit) | |
6531 | { | |
6532 | set_gdbarch_long_bit (gdbarch, long_bit); | |
6533 | switch (mips_abi) | |
6534 | { | |
6535 | case MIPS_ABI_O32: | |
6536 | case MIPS_ABI_EABI32: | |
6537 | break; | |
6538 | case MIPS_ABI_N32: | |
6539 | case MIPS_ABI_O64: | |
6540 | case MIPS_ABI_N64: | |
6541 | case MIPS_ABI_EABI64: | |
6542 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
6543 | break; | |
6544 | default: | |
6545 | internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); | |
6546 | } | |
6547 | } | |
6548 | } | |
6549 | ||
a5ea2558 AC |
6550 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
6551 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
6552 | comment: | |
6553 | ||
6554 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
6555 | flag in object files because to do so would make it impossible to | |
102182a9 | 6556 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 6557 | unnecessarily restrictive. |
361d1df0 | 6558 | |
a5ea2558 AC |
6559 | We could solve this problem by adding "-gp32" multilibs to gcc, |
6560 | but to set this flag before gcc is built with such multilibs will | |
6561 | break too many systems.'' | |
6562 | ||
6563 | But even more unhelpfully, the default linker output target for | |
6564 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
6565 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 6566 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
6567 | this flag to detect 32-bit mode would do the wrong thing given |
6568 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 6569 | as 32-bit programs by default. */ |
a5ea2558 | 6570 | |
6c997a34 | 6571 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 6572 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 6573 | |
102182a9 MS |
6574 | /* Add/remove bits from an address. The MIPS needs be careful to |
6575 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
6576 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
6577 | ||
58dfe9ff AC |
6578 | /* Unwind the frame. */ |
6579 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 6580 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 6581 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 6582 | |
102182a9 | 6583 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 6584 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
6585 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
6586 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
6587 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
6588 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 6589 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 6590 | |
025bb325 | 6591 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 6592 | |
9710e734 AC |
6593 | /* NOTE: cagney/2003-08-05: Eventually call dummy location will be |
6594 | replaced by a command, and all targets will default to on stack | |
6595 | (regardless of the stack's execute status). */ | |
6596 | set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
dc604539 | 6597 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 6598 | |
87783b8b AC |
6599 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6600 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
6601 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
6602 | ||
f7b9e9fc AC |
6603 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6604 | set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | |
c8cef75f MR |
6605 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
6606 | mips_adjust_breakpoint_address); | |
f7b9e9fc AC |
6607 | |
6608 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 6609 | |
97ab0fdd MR |
6610 | set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
6611 | ||
fc0c74b1 AC |
6612 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6613 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
6614 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 6615 | |
a4b8ebc8 | 6616 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 6617 | |
e11c53d2 | 6618 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 6619 | |
9dae60cc UW |
6620 | if (mips_abi == MIPS_ABI_N32) |
6621 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); | |
6622 | else if (mips_abi == MIPS_ABI_N64) | |
6623 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); | |
6624 | else | |
6625 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); | |
e5ab0dce | 6626 | |
d92524f1 PM |
6627 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
6628 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 6629 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
6630 | being used as guards for target_stopped_by_watchpoint, why not have |
6631 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
6632 | is sitting on? */ |
6633 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
6634 | ||
e7d6a6d2 | 6635 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 6636 | |
025bb325 MS |
6637 | set_gdbarch_single_step_through_delay (gdbarch, |
6638 | mips_single_step_through_delay); | |
3352ef37 | 6639 | |
0d5de010 DJ |
6640 | /* Virtual tables. */ |
6641 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
6642 | ||
29709017 DJ |
6643 | mips_register_g_packet_guesses (gdbarch); |
6644 | ||
6de918a6 | 6645 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
822b6570 | 6646 | info.tdep_info = (void *) tdesc_data; |
6de918a6 | 6647 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 6648 | |
9aac7884 MR |
6649 | /* The hook may have adjusted num_regs, fetch the final value and |
6650 | set pc_regnum and sp_regnum now that it has been fixed. */ | |
6651 | /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been | |
6652 | replaced by gdbarch_read_pc? */ | |
6653 | num_regs = gdbarch_num_regs (gdbarch); | |
6654 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
6655 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
6656 | ||
5792a79b | 6657 | /* Unwind the frame. */ |
b8a22b94 DJ |
6658 | dwarf2_append_unwinders (gdbarch); |
6659 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
6660 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
6661 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); | |
2bd0c3d7 | 6662 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 6663 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 AC |
6664 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
6665 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | |
5792a79b | 6666 | |
f8b73d13 DJ |
6667 | if (tdesc_data) |
6668 | { | |
6669 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
7cc46491 | 6670 | tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
f8b73d13 DJ |
6671 | |
6672 | /* Override the normal target description methods to handle our | |
6673 | dual real and pseudo registers. */ | |
6674 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
6675 | set_gdbarch_register_reggroup_p (gdbarch, |
6676 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
6677 | |
6678 | num_regs = gdbarch_num_regs (gdbarch); | |
6679 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6680 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
6681 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
6682 | } | |
6683 | ||
6684 | /* Add ABI-specific aliases for the registers. */ | |
6685 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
6686 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
6687 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
6688 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
6689 | else | |
6690 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
6691 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
6692 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
6693 | ||
6694 | /* Add some other standard aliases. */ | |
6695 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
6696 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
6697 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
6698 | ||
865093a3 AR |
6699 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
6700 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
6701 | value_of_mips_user_reg, | |
6702 | &mips_numeric_register_aliases[i].regnum); | |
6703 | ||
4b9b3959 AC |
6704 | return gdbarch; |
6705 | } | |
6706 | ||
2e4ebe70 | 6707 | static void |
6d82d43b | 6708 | mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) |
2e4ebe70 DJ |
6709 | { |
6710 | struct gdbarch_info info; | |
6711 | ||
6712 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
6713 | mips_gdbarch_init will take care of the rest. */ | |
6714 | gdbarch_info_init (&info); | |
6715 | gdbarch_update_p (info); | |
6716 | } | |
6717 | ||
ad188201 KB |
6718 | /* Print out which MIPS ABI is in use. */ |
6719 | ||
6720 | static void | |
1f8ca57c JB |
6721 | show_mips_abi (struct ui_file *file, |
6722 | int from_tty, | |
6723 | struct cmd_list_element *ignored_cmd, | |
6724 | const char *ignored_value) | |
ad188201 | 6725 | { |
1cf3db46 | 6726 | if (gdbarch_bfd_arch_info (target_gdbarch)->arch != bfd_arch_mips) |
1f8ca57c JB |
6727 | fprintf_filtered |
6728 | (file, | |
6729 | "The MIPS ABI is unknown because the current architecture " | |
6730 | "is not MIPS.\n"); | |
ad188201 KB |
6731 | else |
6732 | { | |
6733 | enum mips_abi global_abi = global_mips_abi (); | |
1cf3db46 | 6734 | enum mips_abi actual_abi = mips_abi (target_gdbarch); |
ad188201 KB |
6735 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
6736 | ||
6737 | if (global_abi == MIPS_ABI_UNKNOWN) | |
1f8ca57c JB |
6738 | fprintf_filtered |
6739 | (file, | |
6740 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 6741 | actual_abi_str); |
ad188201 | 6742 | else if (global_abi == actual_abi) |
1f8ca57c JB |
6743 | fprintf_filtered |
6744 | (file, | |
6745 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 6746 | actual_abi_str); |
ad188201 KB |
6747 | else |
6748 | { | |
6749 | /* Probably shouldn't happen... */ | |
025bb325 MS |
6750 | fprintf_filtered (file, |
6751 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
6752 | "even though the user setting was \"%s\".\n", | |
6d82d43b | 6753 | actual_abi_str, mips_abi_strings[global_abi]); |
ad188201 KB |
6754 | } |
6755 | } | |
6756 | } | |
6757 | ||
4b9b3959 | 6758 | static void |
72a155b4 | 6759 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 6760 | { |
72a155b4 | 6761 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
4b9b3959 | 6762 | if (tdep != NULL) |
c2d11a7d | 6763 | { |
acdb74a0 AC |
6764 | int ef_mips_arch; |
6765 | int ef_mips_32bitmode; | |
f49e4e6d | 6766 | /* Determine the ISA. */ |
acdb74a0 AC |
6767 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
6768 | { | |
6769 | case E_MIPS_ARCH_1: | |
6770 | ef_mips_arch = 1; | |
6771 | break; | |
6772 | case E_MIPS_ARCH_2: | |
6773 | ef_mips_arch = 2; | |
6774 | break; | |
6775 | case E_MIPS_ARCH_3: | |
6776 | ef_mips_arch = 3; | |
6777 | break; | |
6778 | case E_MIPS_ARCH_4: | |
93d56215 | 6779 | ef_mips_arch = 4; |
acdb74a0 AC |
6780 | break; |
6781 | default: | |
93d56215 | 6782 | ef_mips_arch = 0; |
acdb74a0 AC |
6783 | break; |
6784 | } | |
f49e4e6d | 6785 | /* Determine the size of a pointer. */ |
acdb74a0 | 6786 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
4b9b3959 AC |
6787 | fprintf_unfiltered (file, |
6788 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
0dadbba0 | 6789 | tdep->elf_flags); |
4b9b3959 | 6790 | fprintf_unfiltered (file, |
acdb74a0 AC |
6791 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", |
6792 | ef_mips_32bitmode); | |
6793 | fprintf_unfiltered (file, | |
6794 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
6795 | ef_mips_arch); | |
6796 | fprintf_unfiltered (file, | |
6797 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
6d82d43b | 6798 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); |
4014092b | 6799 | fprintf_unfiltered (file, |
025bb325 MS |
6800 | "mips_dump_tdep: " |
6801 | "mips_mask_address_p() %d (default %d)\n", | |
480d3dd2 | 6802 | mips_mask_address_p (tdep), |
4014092b | 6803 | tdep->default_mask_address_p); |
c2d11a7d | 6804 | } |
4b9b3959 AC |
6805 | fprintf_unfiltered (file, |
6806 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
6807 | MIPS_DEFAULT_FPU_TYPE, | |
6808 | (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" | |
6809 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" | |
6810 | : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" | |
6811 | : "???")); | |
74ed0bb4 MD |
6812 | fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", |
6813 | MIPS_EABI (gdbarch)); | |
4b9b3959 AC |
6814 | fprintf_unfiltered (file, |
6815 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
74ed0bb4 MD |
6816 | MIPS_FPU_TYPE (gdbarch), |
6817 | (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" | |
6818 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" | |
6819 | : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" | |
4b9b3959 | 6820 | : "???")); |
c2d11a7d JM |
6821 | } |
6822 | ||
025bb325 | 6823 | extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ |
a78f21af | 6824 | |
c906108c | 6825 | void |
acdb74a0 | 6826 | _initialize_mips_tdep (void) |
c906108c SS |
6827 | { |
6828 | static struct cmd_list_element *mipsfpulist = NULL; | |
6829 | struct cmd_list_element *c; | |
6830 | ||
6d82d43b | 6831 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
6832 | if (MIPS_ABI_LAST + 1 |
6833 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
e2e0b3e5 | 6834 | internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); |
2e4ebe70 | 6835 | |
4b9b3959 | 6836 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 6837 | |
8d5f9dcb DJ |
6838 | mips_pdr_data = register_objfile_data (); |
6839 | ||
4eb0ad19 DJ |
6840 | /* Create feature sets with the appropriate properties. The values |
6841 | are not important. */ | |
6842 | mips_tdesc_gp32 = allocate_target_description (); | |
6843 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); | |
6844 | ||
6845 | mips_tdesc_gp64 = allocate_target_description (); | |
6846 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); | |
6847 | ||
025bb325 | 6848 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
a5ea2558 | 6849 | add_prefix_cmd ("mips", no_class, set_mips_command, |
1bedd215 | 6850 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6851 | &setmipscmdlist, "set mips ", 0, &setlist); |
6852 | ||
6853 | add_prefix_cmd ("mips", no_class, show_mips_command, | |
1bedd215 | 6854 | _("Various MIPS specific commands."), |
a5ea2558 AC |
6855 | &showmipscmdlist, "show mips ", 0, &showlist); |
6856 | ||
025bb325 | 6857 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
6858 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
6859 | &mips_abi_string, _("\ | |
6860 | Set the MIPS ABI used by this program."), _("\ | |
6861 | Show the MIPS ABI used by this program."), _("\ | |
6862 | This option can be set to one of:\n\ | |
6863 | auto - the default ABI associated with the current binary\n\ | |
6864 | o32\n\ | |
6865 | o64\n\ | |
6866 | n32\n\ | |
6867 | n64\n\ | |
6868 | eabi32\n\ | |
6869 | eabi64"), | |
6870 | mips_abi_update, | |
6871 | show_mips_abi, | |
6872 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 6873 | |
c906108c SS |
6874 | /* Let the user turn off floating point and set the fence post for |
6875 | heuristic_proc_start. */ | |
6876 | ||
6877 | add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | |
1bedd215 | 6878 | _("Set use of MIPS floating-point coprocessor."), |
c906108c SS |
6879 | &mipsfpulist, "set mipsfpu ", 0, &setlist); |
6880 | add_cmd ("single", class_support, set_mipsfpu_single_command, | |
1a966eab | 6881 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c SS |
6882 | &mipsfpulist); |
6883 | add_cmd ("double", class_support, set_mipsfpu_double_command, | |
1a966eab | 6884 | _("Select double-precision MIPS floating-point coprocessor."), |
c906108c SS |
6885 | &mipsfpulist); |
6886 | add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); | |
6887 | add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); | |
6888 | add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); | |
6889 | add_cmd ("none", class_support, set_mipsfpu_none_command, | |
1a966eab | 6890 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); |
c906108c SS |
6891 | add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); |
6892 | add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); | |
6893 | add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); | |
6894 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, | |
1a966eab | 6895 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
6896 | &mipsfpulist); |
6897 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 6898 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
6899 | &showlist); |
6900 | ||
c906108c SS |
6901 | /* We really would like to have both "0" and "unlimited" work, but |
6902 | command.c doesn't deal with that. So make it a var_zinteger | |
6903 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 6904 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
6905 | &heuristic_fence_post, _("\ |
6906 | Set the distance searched for the start of a function."), _("\ | |
6907 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
6908 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
6909 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 6910 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 6911 | reinit_frame_cache_sfunc, |
025bb325 MS |
6912 | NULL, /* FIXME: i18n: The distance searched for |
6913 | the start of a function is %s. */ | |
6bcadd06 | 6914 | &setlist, &showlist); |
c906108c SS |
6915 | |
6916 | /* Allow the user to control whether the upper bits of 64-bit | |
6917 | addresses should be zeroed. */ | |
7915a72c AC |
6918 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
6919 | &mask_address_var, _("\ | |
6920 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
6921 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 6922 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 6923 | allow GDB to determine the correct value."), |
08546159 AC |
6924 | NULL, show_mask_address, |
6925 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
6926 | |
6927 | /* Allow the user to control the size of 32 bit registers within the | |
6928 | raw remote packet. */ | |
b3f42336 | 6929 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
6930 | &mips64_transfers_32bit_regs_p, _("\ |
6931 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6932 | _("\ | |
6933 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
6934 | _("\ | |
719ec221 AC |
6935 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
6936 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 6937 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 6938 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
6939 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
6940 | MIPS target that transfers 32-bit | |
6941 | quantities is %s. */ | |
7915a72c | 6942 | &setlist, &showlist); |
9ace0497 | 6943 | |
025bb325 | 6944 | /* Debug this files internals. */ |
6bcadd06 | 6945 | add_setshow_zinteger_cmd ("mips", class_maintenance, |
7915a72c AC |
6946 | &mips_debug, _("\ |
6947 | Set mips debugging."), _("\ | |
6948 | Show mips debugging."), _("\ | |
6949 | When non-zero, mips specific debugging is enabled."), | |
2c5b56ce | 6950 | NULL, |
025bb325 MS |
6951 | NULL, /* FIXME: i18n: Mips debugging is |
6952 | currently %s. */ | |
6bcadd06 | 6953 | &setdebuglist, &showdebuglist); |
c906108c | 6954 | } |