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1 | /* Debug register code for the i386. |
2 | ||
3 | Copyright (C) 2001-2014 Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #ifdef GDBSERVER | |
21 | #include "server.h" | |
22 | #include "i386-low.h" | |
23 | #else | |
24 | #include "defs.h" | |
25 | #include "i386-nat.h" | |
26 | #include "inferior.h" | |
27 | #endif | |
28 | ||
29 | /* Support for hardware watchpoints and breakpoints using the i386 | |
30 | debug registers. | |
31 | ||
32 | This provides several functions for inserting and removing | |
33 | hardware-assisted breakpoints and watchpoints, testing if one or | |
34 | more of the watchpoints triggered and at what address, checking | |
35 | whether a given region can be watched, etc. | |
36 | ||
37 | The functions below implement debug registers sharing by reference | |
38 | counts, and allow to watch regions up to 16 bytes long. */ | |
39 | ||
40 | /* Support for 8-byte wide hw watchpoints. */ | |
41 | #define TARGET_HAS_DR_LEN_8 (i386_get_debug_register_length () == 8) | |
42 | ||
43 | /* DR7 Debug Control register fields. */ | |
44 | ||
45 | /* How many bits to skip in DR7 to get to R/W and LEN fields. */ | |
46 | #define DR_CONTROL_SHIFT 16 | |
47 | /* How many bits in DR7 per R/W and LEN field for each watchpoint. */ | |
48 | #define DR_CONTROL_SIZE 4 | |
49 | ||
50 | /* Watchpoint/breakpoint read/write fields in DR7. */ | |
51 | #define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ | |
52 | #define DR_RW_WRITE (0x1) /* Break on data writes. */ | |
53 | #define DR_RW_READ (0x3) /* Break on data reads or writes. */ | |
54 | ||
55 | /* This is here for completeness. No platform supports this | |
56 | functionality yet (as of March 2001). Note that the DE flag in the | |
57 | CR4 register needs to be set to support this. */ | |
58 | #ifndef DR_RW_IORW | |
59 | #define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ | |
60 | #endif | |
61 | ||
62 | /* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift | |
63 | is so we could OR this with the read/write field defined above. */ | |
64 | #define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ | |
65 | #define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ | |
66 | #define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ | |
67 | #define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ | |
68 | ||
69 | /* Local and Global Enable flags in DR7. | |
70 | ||
71 | When the Local Enable flag is set, the breakpoint/watchpoint is | |
72 | enabled only for the current task; the processor automatically | |
73 | clears this flag on every task switch. When the Global Enable flag | |
74 | is set, the breakpoint/watchpoint is enabled for all tasks; the | |
75 | processor never clears this flag. | |
76 | ||
77 | Currently, all watchpoint are locally enabled. If you need to | |
78 | enable them globally, read the comment which pertains to this in | |
79 | i386_insert_aligned_watchpoint below. */ | |
80 | #define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ | |
81 | #define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ | |
82 | #define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ | |
83 | ||
84 | /* Local and global exact breakpoint enable flags (a.k.a. slowdown | |
85 | flags). These are only required on i386, to allow detection of the | |
86 | exact instruction which caused a watchpoint to break; i486 and | |
87 | later processors do that automatically. We set these flags for | |
88 | backwards compatibility. */ | |
89 | #define DR_LOCAL_SLOWDOWN (0x100) | |
90 | #define DR_GLOBAL_SLOWDOWN (0x200) | |
91 | ||
92 | /* Fields reserved by Intel. This includes the GD (General Detect | |
93 | Enable) flag, which causes a debug exception to be generated when a | |
94 | MOV instruction accesses one of the debug registers. | |
95 | ||
96 | FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ | |
97 | #define DR_CONTROL_RESERVED (0xFC00) | |
98 | ||
99 | /* Auxiliary helper macros. */ | |
100 | ||
101 | /* A value that masks all fields in DR7 that are reserved by Intel. */ | |
102 | #define I386_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) | |
103 | ||
104 | /* The I'th debug register is vacant if its Local and Global Enable | |
105 | bits are reset in the Debug Control register. */ | |
106 | #define I386_DR_VACANT(state, i) \ | |
107 | (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) | |
108 | ||
109 | /* Locally enable the break/watchpoint in the I'th debug register. */ | |
110 | #define I386_DR_LOCAL_ENABLE(state, i) \ | |
111 | do { \ | |
112 | (state)->dr_control_mirror |= \ | |
113 | (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
114 | } while (0) | |
115 | ||
116 | /* Globally enable the break/watchpoint in the I'th debug register. */ | |
117 | #define I386_DR_GLOBAL_ENABLE(state, i) \ | |
118 | do { \ | |
119 | (state)->dr_control_mirror |= \ | |
120 | (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ | |
121 | } while (0) | |
122 | ||
123 | /* Disable the break/watchpoint in the I'th debug register. */ | |
124 | #define I386_DR_DISABLE(state, i) \ | |
125 | do { \ | |
126 | (state)->dr_control_mirror &= \ | |
127 | ~(3 << (DR_ENABLE_SIZE * (i))); \ | |
128 | } while (0) | |
129 | ||
130 | /* Set in DR7 the RW and LEN fields for the I'th debug register. */ | |
131 | #define I386_DR_SET_RW_LEN(state, i, rwlen) \ | |
132 | do { \ | |
133 | (state)->dr_control_mirror &= \ | |
134 | ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
135 | (state)->dr_control_mirror |= \ | |
136 | ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ | |
137 | } while (0) | |
138 | ||
139 | /* Get from DR7 the RW and LEN fields for the I'th debug register. */ | |
140 | #define I386_DR_GET_RW_LEN(dr7, i) \ | |
141 | (((dr7) \ | |
142 | >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) | |
143 | ||
144 | /* Did the watchpoint whose address is in the I'th register break? */ | |
145 | #define I386_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) | |
146 | ||
147 | /* Types of operations supported by i386_handle_nonaligned_watchpoint. */ | |
148 | typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } i386_wp_op_t; | |
149 | ||
150 | /* Print debugging messages. */ | |
151 | #ifndef GDBSERVER | |
152 | #define debug_printf(fmt, args...) \ | |
153 | fprintf_unfiltered (gdb_stdlog, fmt, ##args); | |
154 | #endif | |
155 | ||
156 | /* Print the values of the mirrored debug registers. */ | |
157 | ||
158 | static void | |
159 | i386_show_dr (struct i386_debug_reg_state *state, | |
160 | const char *func, CORE_ADDR addr, | |
161 | int len, enum target_hw_bp_type type) | |
162 | { | |
163 | int i; | |
164 | ||
165 | debug_printf ("%s", func); | |
166 | if (addr || len) | |
167 | debug_printf (" (addr=%s, len=%d, type=%s)", | |
168 | phex (addr, 8), len, | |
169 | type == hw_write ? "data-write" | |
170 | : (type == hw_read ? "data-read" | |
171 | : (type == hw_access ? "data-read/write" | |
172 | : (type == hw_execute ? "instruction-execute" | |
173 | /* FIXME: if/when I/O read/write | |
174 | watchpoints are supported, add them | |
175 | here. */ | |
176 | : "??unknown??")))); | |
177 | debug_printf (":\n"); | |
178 | debug_printf ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", | |
179 | phex (state->dr_control_mirror, 8), | |
180 | phex (state->dr_status_mirror, 8)); | |
181 | ALL_DEBUG_REGISTERS (i) | |
182 | { | |
183 | debug_printf ("\ | |
184 | \tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", | |
185 | i, phex (state->dr_mirror[i], | |
186 | i386_get_debug_register_length ()), | |
187 | state->dr_ref_count[i], | |
188 | i + 1, phex (state->dr_mirror[i + 1], | |
189 | i386_get_debug_register_length ()), | |
190 | state->dr_ref_count[i + 1]); | |
191 | i++; | |
192 | } | |
193 | } | |
194 | ||
195 | /* Return the value of a 4-bit field for DR7 suitable for watching a | |
196 | region of LEN bytes for accesses of type TYPE. LEN is assumed to | |
197 | have the value of 1, 2, or 4. */ | |
198 | ||
199 | static unsigned | |
200 | i386_length_and_rw_bits (int len, enum target_hw_bp_type type) | |
201 | { | |
202 | unsigned rw; | |
203 | ||
204 | switch (type) | |
205 | { | |
206 | case hw_execute: | |
207 | rw = DR_RW_EXECUTE; | |
208 | break; | |
209 | case hw_write: | |
210 | rw = DR_RW_WRITE; | |
211 | break; | |
212 | case hw_read: | |
213 | internal_error (__FILE__, __LINE__, | |
214 | _("The i386 doesn't support " | |
215 | "data-read watchpoints.\n")); | |
216 | case hw_access: | |
217 | rw = DR_RW_READ; | |
218 | break; | |
219 | #if 0 | |
220 | /* Not yet supported. */ | |
221 | case hw_io_access: | |
222 | rw = DR_RW_IORW; | |
223 | break; | |
224 | #endif | |
225 | default: | |
226 | internal_error (__FILE__, __LINE__, _("\ | |
227 | Invalid hardware breakpoint type %d in i386_length_and_rw_bits.\n"), | |
228 | (int) type); | |
229 | } | |
230 | ||
231 | switch (len) | |
232 | { | |
233 | case 1: | |
234 | return (DR_LEN_1 | rw); | |
235 | case 2: | |
236 | return (DR_LEN_2 | rw); | |
237 | case 4: | |
238 | return (DR_LEN_4 | rw); | |
239 | case 8: | |
240 | if (TARGET_HAS_DR_LEN_8) | |
241 | return (DR_LEN_8 | rw); | |
242 | /* ELSE FALL THROUGH */ | |
243 | default: | |
244 | internal_error (__FILE__, __LINE__, _("\ | |
245 | Invalid hardware breakpoint length %d in i386_length_and_rw_bits.\n"), len); | |
246 | } | |
247 | } | |
248 | ||
249 | /* Insert a watchpoint at address ADDR, which is assumed to be aligned | |
250 | according to the length of the region to watch. LEN_RW_BITS is the | |
251 | value of the bits from DR7 which describes the length and access | |
252 | type of the region to be watched by this watchpoint. Return 0 on | |
253 | success, -1 on failure. */ | |
254 | ||
255 | static int | |
256 | i386_insert_aligned_watchpoint (struct i386_debug_reg_state *state, | |
257 | CORE_ADDR addr, unsigned len_rw_bits) | |
258 | { | |
259 | int i; | |
260 | ||
261 | if (!i386_dr_low_can_set_addr () || !i386_dr_low_can_set_control ()) | |
262 | return -1; | |
263 | ||
264 | /* First, look for an occupied debug register with the same address | |
265 | and the same RW and LEN definitions. If we find one, we can | |
266 | reuse it for this watchpoint as well (and save a register). */ | |
267 | ALL_DEBUG_REGISTERS (i) | |
268 | { | |
269 | if (!I386_DR_VACANT (state, i) | |
270 | && state->dr_mirror[i] == addr | |
271 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
272 | { | |
273 | state->dr_ref_count[i]++; | |
274 | return 0; | |
275 | } | |
276 | } | |
277 | ||
278 | /* Next, look for a vacant debug register. */ | |
279 | ALL_DEBUG_REGISTERS (i) | |
280 | { | |
281 | if (I386_DR_VACANT (state, i)) | |
282 | break; | |
283 | } | |
284 | ||
285 | /* No more debug registers! */ | |
286 | if (i >= DR_NADDR) | |
287 | return -1; | |
288 | ||
289 | /* Now set up the register I to watch our region. */ | |
290 | ||
291 | /* Record the info in our local mirrored array. */ | |
292 | state->dr_mirror[i] = addr; | |
293 | state->dr_ref_count[i] = 1; | |
294 | I386_DR_SET_RW_LEN (state, i, len_rw_bits); | |
295 | /* Note: we only enable the watchpoint locally, i.e. in the current | |
296 | task. Currently, no i386 target allows or supports global | |
297 | watchpoints; however, if any target would want that in the | |
298 | future, GDB should probably provide a command to control whether | |
299 | to enable watchpoints globally or locally, and the code below | |
300 | should use global or local enable and slow-down flags as | |
301 | appropriate. */ | |
302 | I386_DR_LOCAL_ENABLE (state, i); | |
303 | state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; | |
304 | state->dr_control_mirror &= I386_DR_CONTROL_MASK; | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
309 | /* Remove a watchpoint at address ADDR, which is assumed to be aligned | |
310 | according to the length of the region to watch. LEN_RW_BITS is the | |
311 | value of the bits from DR7 which describes the length and access | |
312 | type of the region watched by this watchpoint. Return 0 on | |
313 | success, -1 on failure. */ | |
314 | ||
315 | static int | |
316 | i386_remove_aligned_watchpoint (struct i386_debug_reg_state *state, | |
317 | CORE_ADDR addr, unsigned len_rw_bits) | |
318 | { | |
319 | int i, retval = -1; | |
320 | ||
321 | ALL_DEBUG_REGISTERS (i) | |
322 | { | |
323 | if (!I386_DR_VACANT (state, i) | |
324 | && state->dr_mirror[i] == addr | |
325 | && I386_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) | |
326 | { | |
327 | if (--state->dr_ref_count[i] == 0) /* No longer in use? */ | |
328 | { | |
329 | /* Reset our mirror. */ | |
330 | state->dr_mirror[i] = 0; | |
331 | I386_DR_DISABLE (state, i); | |
332 | } | |
333 | retval = 0; | |
334 | } | |
335 | } | |
336 | ||
337 | return retval; | |
338 | } | |
339 | ||
340 | /* Insert or remove a (possibly non-aligned) watchpoint, or count the | |
341 | number of debug registers required to watch a region at address | |
342 | ADDR whose length is LEN for accesses of type TYPE. Return 0 on | |
343 | successful insertion or removal, a positive number when queried | |
344 | about the number of registers, or -1 on failure. If WHAT is not a | |
345 | valid value, bombs through internal_error. */ | |
346 | ||
347 | static int | |
348 | i386_handle_nonaligned_watchpoint (struct i386_debug_reg_state *state, | |
349 | i386_wp_op_t what, CORE_ADDR addr, int len, | |
350 | enum target_hw_bp_type type) | |
351 | { | |
352 | int retval = 0; | |
353 | int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; | |
354 | ||
355 | static const int size_try_array[8][8] = | |
356 | { | |
357 | {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ | |
358 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ | |
359 | {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ | |
360 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ | |
361 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ | |
362 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ | |
363 | {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ | |
364 | {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ | |
365 | }; | |
366 | ||
367 | while (len > 0) | |
368 | { | |
369 | int align = addr % max_wp_len; | |
370 | /* Four (eight on AMD64) is the maximum length a debug register | |
371 | can watch. */ | |
372 | int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); | |
373 | int size = size_try_array[try][align]; | |
374 | ||
375 | if (what == WP_COUNT) | |
376 | { | |
377 | /* size_try_array[] is defined such that each iteration | |
378 | through the loop is guaranteed to produce an address and a | |
379 | size that can be watched with a single debug register. | |
380 | Thus, for counting the registers required to watch a | |
381 | region, we simply need to increment the count on each | |
382 | iteration. */ | |
383 | retval++; | |
384 | } | |
385 | else | |
386 | { | |
387 | unsigned len_rw = i386_length_and_rw_bits (size, type); | |
388 | ||
389 | if (what == WP_INSERT) | |
390 | retval = i386_insert_aligned_watchpoint (state, addr, len_rw); | |
391 | else if (what == WP_REMOVE) | |
392 | retval = i386_remove_aligned_watchpoint (state, addr, len_rw); | |
393 | else | |
394 | internal_error (__FILE__, __LINE__, _("\ | |
395 | Invalid value %d of operation in i386_handle_nonaligned_watchpoint.\n"), | |
396 | (int) what); | |
397 | if (retval) | |
398 | break; | |
399 | } | |
400 | ||
401 | addr += size; | |
402 | len -= size; | |
403 | } | |
404 | ||
405 | return retval; | |
406 | } | |
407 | ||
408 | /* Update the inferior debug registers state, in STATE, with the | |
409 | new debug registers state, in NEW_STATE. */ | |
410 | ||
411 | static void | |
412 | i386_update_inferior_debug_regs (struct i386_debug_reg_state *state, | |
413 | struct i386_debug_reg_state *new_state) | |
414 | { | |
415 | int i; | |
416 | ||
417 | ALL_DEBUG_REGISTERS (i) | |
418 | { | |
419 | if (I386_DR_VACANT (new_state, i) != I386_DR_VACANT (state, i)) | |
420 | i386_dr_low_set_addr (new_state, i); | |
421 | else | |
422 | gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]); | |
423 | } | |
424 | ||
425 | if (new_state->dr_control_mirror != state->dr_control_mirror) | |
426 | i386_dr_low_set_control (new_state); | |
427 | ||
428 | *state = *new_state; | |
429 | } | |
430 | ||
431 | /* Insert a watchpoint to watch a memory region which starts at | |
432 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
433 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
434 | ||
435 | int | |
436 | i386_dr_insert_watchpoint (struct i386_debug_reg_state *state, | |
437 | enum target_hw_bp_type type, | |
438 | CORE_ADDR addr, int len) | |
439 | { | |
440 | int retval; | |
441 | /* Work on a local copy of the debug registers, and on success, | |
442 | commit the change back to the inferior. */ | |
443 | struct i386_debug_reg_state local_state = *state; | |
444 | ||
445 | if (type == hw_read) | |
446 | return 1; /* unsupported */ | |
447 | ||
448 | if (((len != 1 && len != 2 && len != 4) | |
449 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
450 | || addr % len != 0) | |
451 | { | |
452 | retval = i386_handle_nonaligned_watchpoint (&local_state, | |
453 | WP_INSERT, | |
454 | addr, len, type); | |
455 | } | |
456 | else | |
457 | { | |
458 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
459 | ||
460 | retval = i386_insert_aligned_watchpoint (&local_state, | |
461 | addr, len_rw); | |
462 | } | |
463 | ||
464 | if (retval == 0) | |
465 | i386_update_inferior_debug_regs (state, &local_state); | |
466 | ||
467 | if (debug_hw_points) | |
468 | i386_show_dr (state, "insert_watchpoint", addr, len, type); | |
469 | ||
470 | return retval; | |
471 | } | |
472 | ||
473 | /* Remove a watchpoint that watched the memory region which starts at | |
474 | address ADDR, whose length is LEN bytes, and for accesses of the | |
475 | type TYPE. Return 0 on success, -1 on failure. */ | |
476 | ||
477 | int | |
478 | i386_dr_remove_watchpoint (struct i386_debug_reg_state *state, | |
479 | enum target_hw_bp_type type, | |
480 | CORE_ADDR addr, int len) | |
481 | { | |
482 | int retval; | |
483 | /* Work on a local copy of the debug registers, and on success, | |
484 | commit the change back to the inferior. */ | |
485 | struct i386_debug_reg_state local_state = *state; | |
486 | ||
487 | if (((len != 1 && len != 2 && len != 4) | |
488 | && !(TARGET_HAS_DR_LEN_8 && len == 8)) | |
489 | || addr % len != 0) | |
490 | { | |
491 | retval = i386_handle_nonaligned_watchpoint (&local_state, | |
492 | WP_REMOVE, | |
493 | addr, len, type); | |
494 | } | |
495 | else | |
496 | { | |
497 | unsigned len_rw = i386_length_and_rw_bits (len, type); | |
498 | ||
499 | retval = i386_remove_aligned_watchpoint (&local_state, | |
500 | addr, len_rw); | |
501 | } | |
502 | ||
503 | if (retval == 0) | |
504 | i386_update_inferior_debug_regs (state, &local_state); | |
505 | ||
506 | if (debug_hw_points) | |
507 | i386_show_dr (state, "remove_watchpoint", addr, len, type); | |
508 | ||
509 | return retval; | |
510 | } | |
511 | ||
512 | /* Return non-zero if we can watch a memory region that starts at | |
513 | address ADDR and whose length is LEN bytes. */ | |
514 | ||
515 | int | |
516 | i386_dr_region_ok_for_watchpoint (struct i386_debug_reg_state *state, | |
517 | CORE_ADDR addr, int len) | |
518 | { | |
519 | int nregs; | |
520 | ||
521 | /* Compute how many aligned watchpoints we would need to cover this | |
522 | region. */ | |
523 | nregs = i386_handle_nonaligned_watchpoint (state, WP_COUNT, | |
524 | addr, len, hw_write); | |
525 | return nregs <= DR_NADDR ? 1 : 0; | |
526 | } | |
527 | ||
528 | /* If the inferior has some break/watchpoint that triggered, set the | |
529 | address associated with that break/watchpoint and return non-zero. | |
530 | Otherwise, return zero. */ | |
531 | ||
532 | int | |
533 | i386_dr_stopped_data_address (struct i386_debug_reg_state *state, | |
534 | CORE_ADDR *addr_p) | |
535 | { | |
536 | CORE_ADDR addr = 0; | |
537 | int i; | |
538 | int rc = 0; | |
539 | /* The current thread's DR_STATUS. We always need to read this to | |
540 | check whether some watchpoint caused the trap. */ | |
541 | unsigned status; | |
542 | /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a | |
543 | data breakpoint trap. Only fetch it when necessary, to avoid an | |
544 | unnecessary extra syscall when no watchpoint triggered. */ | |
545 | int control_p = 0; | |
546 | unsigned control = 0; | |
547 | ||
548 | /* In non-stop/async, threads can be running while we change the | |
549 | global dr_mirror (and friends). Say, we set a watchpoint, and | |
550 | let threads resume. Now, say you delete the watchpoint, or | |
551 | add/remove watchpoints such that dr_mirror changes while threads | |
552 | are running. On targets that support non-stop, | |
553 | inserting/deleting watchpoints updates the global dr_mirror only. | |
554 | It does not update the real thread's debug registers; that's only | |
555 | done prior to resume. Instead, if threads are running when the | |
556 | mirror changes, a temporary and transparent stop on all threads | |
557 | is forced so they can get their copy of the debug registers | |
558 | updated on re-resume. Now, say, a thread hit a watchpoint before | |
559 | having been updated with the new dr_mirror contents, and we | |
560 | haven't yet handled the corresponding SIGTRAP. If we trusted | |
561 | dr_mirror below, we'd mistake the real trapped address (from the | |
562 | last time we had updated debug registers in the thread) with | |
563 | whatever was currently in dr_mirror. So to fix this, dr_mirror | |
564 | always represents intention, what we _want_ threads to have in | |
565 | debug registers. To get at the address and cause of the trap, we | |
566 | need to read the state the thread still has in its debug | |
567 | registers. | |
568 | ||
569 | In sum, always get the current debug register values the current | |
570 | thread has, instead of trusting the global mirror. If the thread | |
571 | was running when we last changed watchpoints, the mirror no | |
572 | longer represents what was set in this thread's debug | |
573 | registers. */ | |
574 | status = i386_dr_low_get_status (); | |
575 | ||
576 | ALL_DEBUG_REGISTERS (i) | |
577 | { | |
578 | if (!I386_DR_WATCH_HIT (status, i)) | |
579 | continue; | |
580 | ||
581 | if (!control_p) | |
582 | { | |
583 | control = i386_dr_low_get_control (); | |
584 | control_p = 1; | |
585 | } | |
586 | ||
587 | /* This second condition makes sure DRi is set up for a data | |
588 | watchpoint, not a hardware breakpoint. The reason is that | |
589 | GDB doesn't call the target_stopped_data_address method | |
590 | except for data watchpoints. In other words, I'm being | |
591 | paranoiac. */ | |
592 | if (I386_DR_GET_RW_LEN (control, i) != 0) | |
593 | { | |
594 | addr = i386_dr_low_get_addr (i); | |
595 | rc = 1; | |
596 | if (debug_hw_points) | |
597 | i386_show_dr (state, "watchpoint_hit", addr, -1, hw_write); | |
598 | } | |
599 | } | |
600 | ||
601 | if (debug_hw_points && addr == 0) | |
602 | i386_show_dr (state, "stopped_data_addr", 0, 0, hw_write); | |
603 | ||
604 | if (rc) | |
605 | *addr_p = addr; | |
606 | return rc; | |
607 | } | |
608 | ||
609 | /* Return non-zero if the inferior has some watchpoint that triggered. | |
610 | Otherwise return zero. */ | |
611 | ||
612 | int | |
613 | i386_dr_stopped_by_watchpoint (struct i386_debug_reg_state *state) | |
614 | { | |
615 | CORE_ADDR addr = 0; | |
616 | return i386_dr_stopped_data_address (state, &addr); | |
617 | } |