]>
Commit | Line | Data |
---|---|---|
9abe5450 | 1 | /* PPC GNU/Linux native support. |
2555fe1a | 2 | |
1d506c26 | 3 | Copyright (C) 1988-2024 Free Software Foundation, Inc. |
c877c8e6 KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c877c8e6 KB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c877c8e6 KB |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "inferior.h" | |
6ffbb7ab | 23 | #include "gdbthread.h" |
c877c8e6 | 24 | #include "gdbcore.h" |
4e052eda | 25 | #include "regcache.h" |
1d75a658 | 26 | #include "regset.h" |
10d6c8cd DJ |
27 | #include "target.h" |
28 | #include "linux-nat.h" | |
c877c8e6 | 29 | #include <sys/types.h> |
c877c8e6 KB |
30 | #include <signal.h> |
31 | #include <sys/user.h> | |
32 | #include <sys/ioctl.h> | |
7ca18ed6 | 33 | #include <sys/uio.h> |
268a13a5 | 34 | #include "gdbsupport/gdb_wait.h" |
c877c8e6 KB |
35 | #include <fcntl.h> |
36 | #include <sys/procfs.h> | |
5826e159 | 37 | #include "nat/gdb_ptrace.h" |
64f57f3d | 38 | #include "nat/linux-ptrace.h" |
bcc0c096 | 39 | #include "inf-ptrace.h" |
227c0bf4 PFC |
40 | #include <algorithm> |
41 | #include <unordered_map> | |
42 | #include <list> | |
c877c8e6 | 43 | |
0df8b418 | 44 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f | 45 | #include "gregset.h" |
16333c4f | 46 | #include "ppc-tdep.h" |
7284e1be UW |
47 | #include "ppc-linux-tdep.h" |
48 | ||
b7622095 LM |
49 | /* Required when using the AUXV. */ |
50 | #include "elf/common.h" | |
51 | #include "auxv.h" | |
52 | ||
bd64614e PFC |
53 | #include "arch/ppc-linux-common.h" |
54 | #include "arch/ppc-linux-tdesc.h" | |
514c5338 | 55 | #include "nat/ppc-linux.h" |
53c973f2 | 56 | #include "linux-tdep.h" |
413403fc | 57 | #include "expop.h" |
01904826 | 58 | |
6ffbb7ab | 59 | /* Similarly for the hardware watchpoint support. These requests are used |
926bf92d | 60 | when the PowerPC HWDEBUG ptrace interface is not available. */ |
e0d24f8d WZ |
61 | #ifndef PTRACE_GET_DEBUGREG |
62 | #define PTRACE_GET_DEBUGREG 25 | |
63 | #endif | |
64 | #ifndef PTRACE_SET_DEBUGREG | |
65 | #define PTRACE_SET_DEBUGREG 26 | |
66 | #endif | |
67 | #ifndef PTRACE_GETSIGINFO | |
68 | #define PTRACE_GETSIGINFO 0x4202 | |
69 | #endif | |
01904826 | 70 | |
926bf92d UW |
71 | /* These requests are used when the PowerPC HWDEBUG ptrace interface is |
72 | available. It exposes the debug facilities of PowerPC processors, as well | |
73 | as additional features of BookE processors, such as ranged breakpoints and | |
74 | watchpoints and hardware-accelerated condition evaluation. */ | |
6ffbb7ab TJB |
75 | #ifndef PPC_PTRACE_GETHWDBGINFO |
76 | ||
926bf92d UW |
77 | /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG |
78 | ptrace interface is not present in ptrace.h, so we'll have to pretty much | |
79 | include it all here so that the code at least compiles on older systems. */ | |
6ffbb7ab TJB |
80 | #define PPC_PTRACE_GETHWDBGINFO 0x89 |
81 | #define PPC_PTRACE_SETHWDEBUG 0x88 | |
82 | #define PPC_PTRACE_DELHWDEBUG 0x87 | |
83 | ||
84 | struct ppc_debug_info | |
85 | { | |
dda83cd7 SM |
86 | uint32_t version; /* Only version 1 exists to date. */ |
87 | uint32_t num_instruction_bps; | |
88 | uint32_t num_data_bps; | |
89 | uint32_t num_condition_regs; | |
90 | uint32_t data_bp_alignment; | |
91 | uint32_t sizeof_condition; /* size of the DVC register. */ | |
92 | uint64_t features; | |
6ffbb7ab TJB |
93 | }; |
94 | ||
95 | /* Features will have bits indicating whether there is support for: */ | |
96 | #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1 | |
97 | #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2 | |
98 | #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4 | |
99 | #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8 | |
100 | ||
101 | struct ppc_hw_breakpoint | |
102 | { | |
dda83cd7 SM |
103 | uint32_t version; /* currently, version must be 1 */ |
104 | uint32_t trigger_type; /* only some combinations allowed */ | |
105 | uint32_t addr_mode; /* address match mode */ | |
106 | uint32_t condition_mode; /* break/watchpoint condition flags */ | |
107 | uint64_t addr; /* break/watchpoint address */ | |
108 | uint64_t addr2; /* range end or mask */ | |
109 | uint64_t condition_value; /* contents of the DVC register */ | |
6ffbb7ab TJB |
110 | }; |
111 | ||
112 | /* Trigger type. */ | |
113 | #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1 | |
114 | #define PPC_BREAKPOINT_TRIGGER_READ 0x2 | |
115 | #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4 | |
116 | #define PPC_BREAKPOINT_TRIGGER_RW 0x6 | |
117 | ||
118 | /* Address mode. */ | |
119 | #define PPC_BREAKPOINT_MODE_EXACT 0x0 | |
120 | #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1 | |
121 | #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2 | |
122 | #define PPC_BREAKPOINT_MODE_MASK 0x3 | |
123 | ||
124 | /* Condition mode. */ | |
125 | #define PPC_BREAKPOINT_CONDITION_NONE 0x0 | |
126 | #define PPC_BREAKPOINT_CONDITION_AND 0x1 | |
127 | #define PPC_BREAKPOINT_CONDITION_EXACT 0x1 | |
128 | #define PPC_BREAKPOINT_CONDITION_OR 0x2 | |
129 | #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3 | |
130 | #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000 | |
131 | #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16 | |
132 | #define PPC_BREAKPOINT_CONDITION_BE(n) \ | |
dda83cd7 | 133 | (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT)) |
6ffbb7ab TJB |
134 | #endif /* PPC_PTRACE_GETHWDBGINFO */ |
135 | ||
e23b9d6e UW |
136 | /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider |
137 | watchpoint (up to 512 bytes). */ | |
138 | #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR | |
139 | #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10 | |
140 | #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */ | |
6ffbb7ab | 141 | |
539d71e8 RA |
142 | /* Feature defined on Linux kernel v5.1: Second watchpoint support. */ |
143 | #ifndef PPC_DEBUG_FEATURE_DATA_BP_ARCH_31 | |
144 | #define PPC_DEBUG_FEATURE_DATA_BP_ARCH_31 0x20 | |
145 | #endif /* PPC_DEBUG_FEATURE_DATA_BP_ARCH_31 */ | |
146 | ||
227c0bf4 PFC |
147 | /* The version of the PowerPC HWDEBUG kernel interface that we will use, if |
148 | available. */ | |
149 | #define PPC_DEBUG_CURRENT_VERSION 1 | |
150 | ||
1dfe79e8 SDJ |
151 | /* Similarly for the general-purpose (gp0 -- gp31) |
152 | and floating-point registers (fp0 -- fp31). */ | |
153 | #ifndef PTRACE_GETREGS | |
154 | #define PTRACE_GETREGS 12 | |
155 | #endif | |
156 | #ifndef PTRACE_SETREGS | |
157 | #define PTRACE_SETREGS 13 | |
158 | #endif | |
159 | #ifndef PTRACE_GETFPREGS | |
160 | #define PTRACE_GETFPREGS 14 | |
161 | #endif | |
162 | #ifndef PTRACE_SETFPREGS | |
163 | #define PTRACE_SETFPREGS 15 | |
164 | #endif | |
165 | ||
9abe5450 EZ |
166 | /* This oddity is because the Linux kernel defines elf_vrregset_t as |
167 | an array of 33 16 bytes long elements. I.e. it leaves out vrsave. | |
168 | However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return | |
169 | the vrsave as an extra 4 bytes at the end. I opted for creating a | |
170 | flat array of chars, so that it is easier to manipulate for gdb. | |
171 | ||
172 | There are 32 vector registers 16 bytes longs, plus a VSCR register | |
173 | which is only 4 bytes long, but is fetched as a 16 bytes | |
0df8b418 | 174 | quantity. Up to here we have the elf_vrregset_t structure. |
9abe5450 EZ |
175 | Appended to this there is space for the VRSAVE register: 4 bytes. |
176 | Even though this vrsave register is not included in the regset | |
177 | typedef, it is handled by the ptrace requests. | |
178 | ||
9abe5450 EZ |
179 | The layout is like this (where x is the actual value of the vscr reg): */ |
180 | ||
9abe5450 | 181 | /* |
1d75a658 | 182 | Big-Endian: |
9abe5450 EZ |
183 | |.|.|.|.|.....|.|.|.|.||.|.|.|x||.| |
184 | <-------> <-------><-------><-> | |
185 | VR0 VR31 VSCR VRSAVE | |
1d75a658 PFC |
186 | Little-Endian: |
187 | |.|.|.|.|.....|.|.|.|.||X|.|.|.||.| | |
188 | <-------> <-------><-------><-> | |
189 | VR0 VR31 VSCR VRSAVE | |
9abe5450 | 190 | */ |
9abe5450 | 191 | |
d078308a | 192 | typedef char gdb_vrregset_t[PPC_LINUX_SIZEOF_VRREGSET]; |
9abe5450 | 193 | |
604c2f83 LM |
194 | /* This is the layout of the POWER7 VSX registers and the way they overlap |
195 | with the existing FPR and VMX registers. | |
196 | ||
dda83cd7 SM |
197 | VSR doubleword 0 VSR doubleword 1 |
198 | ---------------------------------------------------------------- | |
604c2f83 | 199 | VSR[0] | FPR[0] | | |
dda83cd7 | 200 | ---------------------------------------------------------------- |
604c2f83 | 201 | VSR[1] | FPR[1] | | |
dda83cd7 SM |
202 | ---------------------------------------------------------------- |
203 | | ... | | | |
204 | | ... | | | |
205 | ---------------------------------------------------------------- | |
604c2f83 | 206 | VSR[30] | FPR[30] | | |
dda83cd7 | 207 | ---------------------------------------------------------------- |
604c2f83 | 208 | VSR[31] | FPR[31] | | |
dda83cd7 | 209 | ---------------------------------------------------------------- |
604c2f83 | 210 | VSR[32] | VR[0] | |
dda83cd7 | 211 | ---------------------------------------------------------------- |
604c2f83 | 212 | VSR[33] | VR[1] | |
dda83cd7 SM |
213 | ---------------------------------------------------------------- |
214 | | ... | | |
215 | | ... | | |
216 | ---------------------------------------------------------------- | |
604c2f83 | 217 | VSR[62] | VR[30] | |
dda83cd7 | 218 | ---------------------------------------------------------------- |
604c2f83 | 219 | VSR[63] | VR[31] | |
dda83cd7 | 220 | ---------------------------------------------------------------- |
604c2f83 LM |
221 | |
222 | VSX has 64 128bit registers. The first 32 registers overlap with | |
223 | the FP registers (doubleword 0) and hence extend them with additional | |
224 | 64 bits (doubleword 1). The other 32 regs overlap with the VMX | |
225 | registers. */ | |
d078308a | 226 | typedef char gdb_vsxregset_t[PPC_LINUX_SIZEOF_VSXREGSET]; |
01904826 | 227 | |
b021a221 | 228 | /* On PPC processors that support the Signal Processing Extension |
01904826 | 229 | (SPE) APU, the general-purpose registers are 64 bits long. |
411cb3f9 PG |
230 | However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER |
231 | ptrace calls only access the lower half of each register, to allow | |
232 | them to behave the same way they do on non-SPE systems. There's a | |
233 | separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that | |
234 | read and write the top halves of all the general-purpose registers | |
235 | at once, along with some SPE-specific registers. | |
01904826 JB |
236 | |
237 | GDB itself continues to claim the general-purpose registers are 32 | |
6ced10dd | 238 | bits long. It has unnamed raw registers that hold the upper halves |
b021a221 | 239 | of the gprs, and the full 64-bit SIMD views of the registers, |
6ced10dd JB |
240 | 'ev0' -- 'ev31', are pseudo-registers that splice the top and |
241 | bottom halves together. | |
01904826 JB |
242 | |
243 | This is the structure filled in by PTRACE_GETEVRREGS and written to | |
244 | the inferior's registers by PTRACE_SETEVRREGS. */ | |
245 | struct gdb_evrregset_t | |
246 | { | |
247 | unsigned long evr[32]; | |
248 | unsigned long long acc; | |
249 | unsigned long spefscr; | |
250 | }; | |
251 | ||
604c2f83 LM |
252 | /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and |
253 | PTRACE_SETVSXREGS requests, for reading and writing the VSX | |
254 | POWER7 registers 0 through 31. Zero if we've tried one of them and | |
255 | gotten an error. Note that VSX registers 32 through 63 overlap | |
256 | with VR registers 0 through 31. */ | |
257 | int have_ptrace_getsetvsxregs = 1; | |
01904826 JB |
258 | |
259 | /* Non-zero if our kernel may support the PTRACE_GETVRREGS and | |
260 | PTRACE_SETVRREGS requests, for reading and writing the Altivec | |
261 | registers. Zero if we've tried one of them and gotten an | |
262 | error. */ | |
9abe5450 EZ |
263 | int have_ptrace_getvrregs = 1; |
264 | ||
01904826 JB |
265 | /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and |
266 | PTRACE_SETEVRREGS requests, for reading and writing the SPE | |
267 | registers. Zero if we've tried one of them and gotten an | |
268 | error. */ | |
269 | int have_ptrace_getsetevrregs = 1; | |
270 | ||
1dfe79e8 SDJ |
271 | /* Non-zero if our kernel may support the PTRACE_GETREGS and |
272 | PTRACE_SETREGS requests, for reading and writing the | |
273 | general-purpose registers. Zero if we've tried one of | |
274 | them and gotten an error. */ | |
275 | int have_ptrace_getsetregs = 1; | |
276 | ||
277 | /* Non-zero if our kernel may support the PTRACE_GETFPREGS and | |
278 | PTRACE_SETFPREGS requests, for reading and writing the | |
279 | floating-pointers registers. Zero if we've tried one of | |
280 | them and gotten an error. */ | |
281 | int have_ptrace_getsetfpregs = 1; | |
282 | ||
227c0bf4 PFC |
283 | /* Private arch info associated with each thread lwp_info object, used |
284 | for debug register handling. */ | |
285 | ||
286 | struct arch_lwp_info | |
287 | { | |
288 | /* When true, indicates that the debug registers installed in the | |
289 | thread no longer correspond to the watchpoints and breakpoints | |
290 | requested by GDB. */ | |
291 | bool debug_regs_stale; | |
292 | ||
293 | /* We need a back-reference to the PTID of the thread so that we can | |
294 | cleanup the debug register state of the thread in | |
295 | low_delete_thread. */ | |
296 | ptid_t lwp_ptid; | |
297 | }; | |
298 | ||
299 | /* Class used to detect which set of ptrace requests that | |
300 | ppc_linux_nat_target will use to install and remove hardware | |
301 | breakpoints and watchpoints. | |
302 | ||
303 | The interface is only detected once, testing the ptrace calls. The | |
304 | result can indicate that no interface is available. | |
305 | ||
306 | The Linux kernel provides two different sets of ptrace requests to | |
307 | handle hardware watchpoints and breakpoints for Power: | |
308 | ||
309 | - PPC_PTRACE_GETHWDBGINFO, PPC_PTRACE_SETHWDEBUG, and | |
310 | PPC_PTRACE_DELHWDEBUG. | |
311 | ||
312 | Or | |
313 | ||
314 | - PTRACE_SET_DEBUGREG and PTRACE_GET_DEBUGREG | |
315 | ||
316 | The first set is the more flexible one and allows setting watchpoints | |
317 | with a variable watched region length and, for BookE processors, | |
318 | multiple types of debug registers (e.g. hardware breakpoints and | |
319 | hardware-assisted conditions for watchpoints). The second one only | |
320 | allows setting one debug register, a watchpoint, so we only use it if | |
321 | the first one is not available. */ | |
322 | ||
323 | class ppc_linux_dreg_interface | |
324 | { | |
325 | public: | |
326 | ||
327 | ppc_linux_dreg_interface () | |
328 | : m_interface (), m_hwdebug_info () | |
329 | { | |
330 | }; | |
331 | ||
332 | DISABLE_COPY_AND_ASSIGN (ppc_linux_dreg_interface); | |
333 | ||
334 | /* One and only one of these three functions returns true, indicating | |
335 | whether the corresponding interface is the one we detected. The | |
3bfdcabb | 336 | interface must already have been detected as a precondition. */ |
227c0bf4 PFC |
337 | |
338 | bool hwdebug_p () | |
339 | { | |
340 | gdb_assert (detected_p ()); | |
341 | return *m_interface == HWDEBUG; | |
342 | } | |
343 | ||
344 | bool debugreg_p () | |
345 | { | |
346 | gdb_assert (detected_p ()); | |
347 | return *m_interface == DEBUGREG; | |
348 | } | |
349 | ||
350 | bool unavailable_p () | |
351 | { | |
352 | gdb_assert (detected_p ()); | |
353 | return *m_interface == UNAVAILABLE; | |
354 | } | |
355 | ||
356 | /* Returns the debug register capabilities of the target. Should only | |
357 | be called if the interface is HWDEBUG. */ | |
358 | const struct ppc_debug_info &hwdebug_info () | |
359 | { | |
360 | gdb_assert (hwdebug_p ()); | |
361 | ||
362 | return m_hwdebug_info; | |
363 | } | |
364 | ||
365 | /* Returns true if the interface has already been detected. This is | |
366 | useful for cases when we know there is no work to be done if the | |
367 | interface hasn't been detected yet. */ | |
368 | bool detected_p () | |
369 | { | |
370 | return m_interface.has_value (); | |
371 | } | |
372 | ||
373 | /* Detect the available interface, if any, if it hasn't been detected | |
374 | before, using PTID for the necessary ptrace calls. */ | |
375 | ||
376 | void detect (const ptid_t &ptid) | |
377 | { | |
378 | if (m_interface.has_value ()) | |
379 | return; | |
380 | ||
381 | gdb_assert (ptid.lwp_p ()); | |
382 | ||
383 | bool no_features = false; | |
384 | ||
385 | if (ptrace (PPC_PTRACE_GETHWDBGINFO, ptid.lwp (), 0, &m_hwdebug_info) | |
6e562fa3 | 386 | >= 0) |
227c0bf4 PFC |
387 | { |
388 | /* If there are no advertised features, we don't use the | |
389 | HWDEBUG interface and try the DEBUGREG interface instead. | |
390 | It shouldn't be necessary to do this, however, when the | |
391 | kernel is configured without CONFIG_HW_BREAKPOINTS (selected | |
392 | by CONFIG_PERF_EVENTS), there is a bug that causes | |
393 | watchpoints installed with the HWDEBUG interface not to | |
394 | trigger. When this is the case, features will be zero, | |
395 | which we use as an indicator to fall back to the DEBUGREG | |
396 | interface. */ | |
397 | if (m_hwdebug_info.features != 0) | |
398 | { | |
399 | m_interface.emplace (HWDEBUG); | |
400 | return; | |
401 | } | |
402 | else | |
403 | no_features = true; | |
404 | } | |
405 | ||
406 | /* EIO indicates that the request is invalid, so we try DEBUGREG | |
407 | next. Technically, it can also indicate other failures, but we | |
408 | can't differentiate those. | |
409 | ||
410 | Other errors could happen for various reasons. We could get an | |
411 | ESRCH if the traced thread was killed by a signal. Trying to | |
412 | detect the interface with another thread in the future would be | |
413 | complicated, as callers would have to handle an "unknown | |
414 | interface" case. It's also unclear if raising an exception | |
415 | here would be safe. | |
416 | ||
417 | Other errors, such as ENODEV, could be more permanent and cause | |
418 | a failure for any thread. | |
419 | ||
420 | For simplicity, with all errors other than EIO, we set the | |
421 | interface to UNAVAILABLE and don't try DEBUGREG. If DEBUGREG | |
422 | fails too, we'll also set the interface to UNAVAILABLE. It's | |
423 | unlikely that trying the DEBUGREG interface with this same thread | |
424 | would work, for errors other than EIO. This means that these | |
425 | errors will cause hardware watchpoints and breakpoints to become | |
426 | unavailable throughout a GDB session. */ | |
427 | ||
428 | if (no_features || errno == EIO) | |
429 | { | |
430 | unsigned long wp; | |
431 | ||
6e562fa3 | 432 | if (ptrace (PTRACE_GET_DEBUGREG, ptid.lwp (), 0, &wp) >= 0) |
227c0bf4 PFC |
433 | { |
434 | m_interface.emplace (DEBUGREG); | |
435 | return; | |
436 | } | |
437 | } | |
438 | ||
439 | if (errno != EIO) | |
440 | warning (_("Error when detecting the debug register interface. " | |
441 | "Debug registers will be unavailable.")); | |
442 | ||
443 | m_interface.emplace (UNAVAILABLE); | |
444 | return; | |
445 | } | |
446 | ||
447 | private: | |
448 | ||
449 | /* HWDEBUG represents the set of calls PPC_PTRACE_GETHWDBGINFO, | |
450 | PPC_PTRACE_SETHWDEBUG and PPC_PTRACE_DELHWDEBUG. | |
451 | ||
452 | DEBUGREG represents the set of calls PTRACE_SET_DEBUGREG and | |
453 | PTRACE_GET_DEBUGREG. | |
454 | ||
455 | UNAVAILABLE can indicate that the kernel doesn't support any of the | |
456 | two sets of requests or that there was an error when we tried to | |
33b5899f | 457 | detect which interface is available. */ |
227c0bf4 PFC |
458 | |
459 | enum debug_reg_interface | |
460 | { | |
461 | UNAVAILABLE, | |
462 | HWDEBUG, | |
463 | DEBUGREG | |
464 | }; | |
465 | ||
466 | /* The interface option. Initialized if has_value () returns true. */ | |
6b09f134 | 467 | std::optional<enum debug_reg_interface> m_interface; |
227c0bf4 PFC |
468 | |
469 | /* The info returned by the kernel with PPC_PTRACE_GETHWDBGINFO. Only | |
470 | valid if we determined that the interface is HWDEBUG. */ | |
471 | struct ppc_debug_info m_hwdebug_info; | |
472 | }; | |
473 | ||
474 | /* Per-process information. This includes the hardware watchpoints and | |
475 | breakpoints that GDB requested to this target. */ | |
476 | ||
477 | struct ppc_linux_process_info | |
478 | { | |
479 | /* The list of hardware watchpoints and breakpoints that GDB requested | |
480 | for this process. | |
481 | ||
482 | Only used when the interface is HWDEBUG. */ | |
483 | std::list<struct ppc_hw_breakpoint> requested_hw_bps; | |
484 | ||
485 | /* The watchpoint value that GDB requested for this process. | |
486 | ||
487 | Only used when the interface is DEBUGREG. */ | |
6b09f134 | 488 | std::optional<long> requested_wp_val; |
227c0bf4 PFC |
489 | }; |
490 | ||
f6ac5f3d PA |
491 | struct ppc_linux_nat_target final : public linux_nat_target |
492 | { | |
493 | /* Add our register access methods. */ | |
494 | void fetch_registers (struct regcache *, int) override; | |
495 | void store_registers (struct regcache *, int) override; | |
496 | ||
497 | /* Add our breakpoint/watchpoint methods. */ | |
498 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
499 | ||
500 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) | |
501 | override; | |
502 | ||
503 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) | |
504 | override; | |
505 | ||
506 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
507 | ||
508 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
509 | struct expression *) override; | |
510 | ||
511 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
512 | struct expression *) override; | |
513 | ||
514 | int insert_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) | |
515 | override; | |
516 | ||
517 | int remove_mask_watchpoint (CORE_ADDR, CORE_ADDR, enum target_hw_bp_type) | |
518 | override; | |
519 | ||
57810aa7 | 520 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; |
f6ac5f3d | 521 | |
57810aa7 | 522 | bool can_accel_watchpoint_condition (CORE_ADDR, int, int, struct expression *) |
f6ac5f3d PA |
523 | override; |
524 | ||
525 | int masked_watch_num_registers (CORE_ADDR, CORE_ADDR) override; | |
526 | ||
527 | int ranged_break_num_registers () override; | |
528 | ||
529 | const struct target_desc *read_description () override; | |
530 | ||
3fe639b8 SM |
531 | int auxv_parse (const gdb_byte **readptr, |
532 | const gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp) | |
f6ac5f3d | 533 | override; |
135340af PA |
534 | |
535 | /* Override linux_nat_target low methods. */ | |
227c0bf4 PFC |
536 | bool low_stopped_by_watchpoint () override; |
537 | ||
538 | bool low_stopped_data_address (CORE_ADDR *) override; | |
539 | ||
135340af | 540 | void low_new_thread (struct lwp_info *lp) override; |
227c0bf4 PFC |
541 | |
542 | void low_delete_thread (arch_lwp_info *) override; | |
543 | ||
544 | void low_new_fork (struct lwp_info *, pid_t) override; | |
545 | ||
546 | void low_new_clone (struct lwp_info *, pid_t) override; | |
547 | ||
548 | void low_forget_process (pid_t pid) override; | |
549 | ||
550 | void low_prepare_to_resume (struct lwp_info *) override; | |
551 | ||
552 | private: | |
553 | ||
554 | void copy_thread_dreg_state (const ptid_t &parent_ptid, | |
555 | const ptid_t &child_ptid); | |
556 | ||
557 | void mark_thread_stale (struct lwp_info *lp); | |
558 | ||
559 | void mark_debug_registers_changed (pid_t pid); | |
560 | ||
561 | void register_hw_breakpoint (pid_t pid, | |
562 | const struct ppc_hw_breakpoint &bp); | |
563 | ||
564 | void clear_hw_breakpoint (pid_t pid, | |
565 | const struct ppc_hw_breakpoint &a); | |
566 | ||
567 | void register_wp (pid_t pid, long wp_value); | |
568 | ||
569 | void clear_wp (pid_t pid); | |
570 | ||
571 | bool can_use_watchpoint_cond_accel (void); | |
572 | ||
573 | void calculate_dvc (CORE_ADDR addr, int len, | |
574 | CORE_ADDR data_value, | |
575 | uint32_t *condition_mode, | |
576 | uint64_t *condition_value); | |
577 | ||
578 | int check_condition (CORE_ADDR watch_addr, | |
579 | struct expression *cond, | |
580 | CORE_ADDR *data_value, int *len); | |
581 | ||
582 | int num_memory_accesses (const std::vector<value_ref_ptr> &chain); | |
583 | ||
584 | int get_trigger_type (enum target_hw_bp_type type); | |
585 | ||
586 | void create_watchpoint_request (struct ppc_hw_breakpoint *p, | |
587 | CORE_ADDR addr, | |
588 | int len, | |
589 | enum target_hw_bp_type type, | |
590 | struct expression *cond, | |
591 | int insert); | |
592 | ||
593 | bool hwdebug_point_cmp (const struct ppc_hw_breakpoint &a, | |
594 | const struct ppc_hw_breakpoint &b); | |
595 | ||
596 | void init_arch_lwp_info (struct lwp_info *lp); | |
597 | ||
598 | arch_lwp_info *get_arch_lwp_info (struct lwp_info *lp); | |
599 | ||
600 | /* The ptrace interface we'll use to install hardware watchpoints and | |
601 | breakpoints (debug registers). */ | |
602 | ppc_linux_dreg_interface m_dreg_interface; | |
603 | ||
604 | /* A map from pids to structs containing info specific to each | |
605 | process. */ | |
606 | std::unordered_map<pid_t, ppc_linux_process_info> m_process_info; | |
607 | ||
608 | /* Callable object to hash ptids by their lwp number. */ | |
609 | struct ptid_hash | |
610 | { | |
611 | std::size_t operator() (const ptid_t &ptid) const | |
612 | { | |
613 | return std::hash<long>{} (ptid.lwp ()); | |
614 | } | |
615 | }; | |
616 | ||
617 | /* A map from ptid_t objects to a list of pairs of slots and hardware | |
618 | breakpoint objects. This keeps track of which hardware breakpoints | |
619 | and watchpoints were last installed in each slot of each thread. | |
620 | ||
621 | Only used when the interface is HWDEBUG. */ | |
622 | std::unordered_map <ptid_t, | |
623 | std::list<std::pair<long, ppc_hw_breakpoint>>, | |
624 | ptid_hash> m_installed_hw_bps; | |
f6ac5f3d PA |
625 | }; |
626 | ||
627 | static ppc_linux_nat_target the_ppc_linux_nat_target; | |
628 | ||
16333c4f EZ |
629 | /* registers layout, as presented by the ptrace interface: |
630 | PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7, | |
631 | PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15, | |
632 | PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23, | |
633 | PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31, | |
0df8b418 MS |
634 | PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, |
635 | PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14, | |
636 | PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, | |
637 | PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30, | |
638 | PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, | |
639 | PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46, | |
640 | PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, | |
641 | PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62, | |
16333c4f | 642 | PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */ |
c877c8e6 | 643 | |
45229ea4 | 644 | static int |
e101270f | 645 | ppc_register_u_addr (struct gdbarch *gdbarch, int regno) |
c877c8e6 | 646 | { |
16333c4f | 647 | int u_addr = -1; |
08106042 | 648 | ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); |
56d0d96a AC |
649 | /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace |
650 | interface, and not the wordsize of the program's ABI. */ | |
411cb3f9 | 651 | int wordsize = sizeof (long); |
16333c4f | 652 | |
0df8b418 | 653 | /* General purpose registers occupy 1 slot each in the buffer. */ |
8bf659e8 JB |
654 | if (regno >= tdep->ppc_gp0_regnum |
655 | && regno < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
26e75e5c | 656 | u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize); |
16333c4f | 657 | |
49ff75ad JB |
658 | /* Floating point regs: eight bytes each in both 32- and 64-bit |
659 | ptrace interfaces. Thus, two slots each in 32-bit interface, one | |
660 | slot each in 64-bit interface. */ | |
383f0f5b JB |
661 | if (tdep->ppc_fp0_regnum >= 0 |
662 | && regno >= tdep->ppc_fp0_regnum | |
366f009f JB |
663 | && regno < tdep->ppc_fp0_regnum + ppc_num_fprs) |
664 | u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8); | |
16333c4f | 665 | |
0df8b418 | 666 | /* UISA special purpose registers: 1 slot each. */ |
e101270f | 667 | if (regno == gdbarch_pc_regnum (gdbarch)) |
49ff75ad | 668 | u_addr = PT_NIP * wordsize; |
dc5cfeb6 | 669 | if (regno == tdep->ppc_lr_regnum) |
49ff75ad | 670 | u_addr = PT_LNK * wordsize; |
dc5cfeb6 | 671 | if (regno == tdep->ppc_cr_regnum) |
49ff75ad | 672 | u_addr = PT_CCR * wordsize; |
dc5cfeb6 | 673 | if (regno == tdep->ppc_xer_regnum) |
49ff75ad | 674 | u_addr = PT_XER * wordsize; |
dc5cfeb6 | 675 | if (regno == tdep->ppc_ctr_regnum) |
49ff75ad | 676 | u_addr = PT_CTR * wordsize; |
f8c59253 | 677 | #ifdef PT_MQ |
dc5cfeb6 | 678 | if (regno == tdep->ppc_mq_regnum) |
49ff75ad | 679 | u_addr = PT_MQ * wordsize; |
f8c59253 | 680 | #endif |
dc5cfeb6 | 681 | if (regno == tdep->ppc_ps_regnum) |
49ff75ad | 682 | u_addr = PT_MSR * wordsize; |
7284e1be UW |
683 | if (regno == PPC_ORIG_R3_REGNUM) |
684 | u_addr = PT_ORIG_R3 * wordsize; | |
685 | if (regno == PPC_TRAP_REGNUM) | |
686 | u_addr = PT_TRAP * wordsize; | |
383f0f5b JB |
687 | if (tdep->ppc_fpscr_regnum >= 0 |
688 | && regno == tdep->ppc_fpscr_regnum) | |
8f135812 AC |
689 | { |
690 | /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the | |
691 | kernel headers incorrectly contained the 32-bit definition of | |
692 | PT_FPSCR. For the 32-bit definition, floating-point | |
693 | registers occupy two 32-bit "slots", and the FPSCR lives in | |
69abc51c | 694 | the second half of such a slot-pair (hence +1). For 64-bit, |
8f135812 AC |
695 | the FPSCR instead occupies the full 64-bit 2-word-slot and |
696 | hence no adjustment is necessary. Hack around this. */ | |
697 | if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1)) | |
698 | u_addr = (48 + 32) * wordsize; | |
69abc51c TJB |
699 | /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit |
700 | slot and not just its second word. The PT_FPSCR supplied when | |
701 | GDB is compiled as a 32-bit app doesn't reflect this. */ | |
702 | else if (wordsize == 4 && register_size (gdbarch, regno) == 8 | |
703 | && PT_FPSCR == (48 + 2*32 + 1)) | |
704 | u_addr = (48 + 2*32) * wordsize; | |
8f135812 AC |
705 | else |
706 | u_addr = PT_FPSCR * wordsize; | |
707 | } | |
16333c4f | 708 | return u_addr; |
c877c8e6 KB |
709 | } |
710 | ||
604c2f83 LM |
711 | /* The Linux kernel ptrace interface for POWER7 VSX registers uses the |
712 | registers set mechanism, as opposed to the interface for all the | |
713 | other registers, that stores/fetches each register individually. */ | |
714 | static void | |
2c3305f6 | 715 | fetch_vsx_registers (struct regcache *regcache, int tid, int regno) |
604c2f83 LM |
716 | { |
717 | int ret; | |
718 | gdb_vsxregset_t regs; | |
2c3305f6 | 719 | const struct regset *vsxregset = ppc_linux_vsxregset (); |
604c2f83 LM |
720 | |
721 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); | |
722 | if (ret < 0) | |
723 | { | |
724 | if (errno == EIO) | |
725 | { | |
726 | have_ptrace_getsetvsxregs = 0; | |
727 | return; | |
728 | } | |
2c3305f6 | 729 | perror_with_name (_("Unable to fetch VSX registers")); |
604c2f83 LM |
730 | } |
731 | ||
2c3305f6 PFC |
732 | vsxregset->supply_regset (vsxregset, regcache, regno, ®s, |
733 | PPC_LINUX_SIZEOF_VSXREGSET); | |
604c2f83 LM |
734 | } |
735 | ||
9abe5450 EZ |
736 | /* The Linux kernel ptrace interface for AltiVec registers uses the |
737 | registers set mechanism, as opposed to the interface for all the | |
738 | other registers, that stores/fetches each register individually. */ | |
739 | static void | |
1d75a658 PFC |
740 | fetch_altivec_registers (struct regcache *regcache, int tid, |
741 | int regno) | |
9abe5450 EZ |
742 | { |
743 | int ret; | |
9abe5450 | 744 | gdb_vrregset_t regs; |
ac7936df | 745 | struct gdbarch *gdbarch = regcache->arch (); |
1d75a658 | 746 | const struct regset *vrregset = ppc_linux_vrregset (gdbarch); |
9abe5450 EZ |
747 | |
748 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
749 | if (ret < 0) | |
750 | { | |
751 | if (errno == EIO) | |
dda83cd7 SM |
752 | { |
753 | have_ptrace_getvrregs = 0; | |
754 | return; | |
755 | } | |
1d75a658 | 756 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 | 757 | } |
1d75a658 PFC |
758 | |
759 | vrregset->supply_regset (vrregset, regcache, regno, ®s, | |
760 | PPC_LINUX_SIZEOF_VRREGSET); | |
9abe5450 EZ |
761 | } |
762 | ||
01904826 JB |
763 | /* Fetch the top 32 bits of TID's general-purpose registers and the |
764 | SPE-specific registers, and place the results in EVRREGSET. If we | |
765 | don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with | |
766 | zeros. | |
767 | ||
768 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
769 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
770 | set_spe_registers. */ | |
771 | static void | |
772 | get_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
773 | { | |
774 | if (have_ptrace_getsetevrregs) | |
775 | { | |
776 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0) | |
dda83cd7 | 777 | return; |
01904826 | 778 | else |
dda83cd7 SM |
779 | { |
780 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported; | |
781 | we just return zeros. */ | |
782 | if (errno == EIO) | |
783 | have_ptrace_getsetevrregs = 0; | |
784 | else | |
785 | /* Anything else needs to be reported. */ | |
786 | perror_with_name (_("Unable to fetch SPE registers")); | |
787 | } | |
01904826 JB |
788 | } |
789 | ||
790 | memset (evrregset, 0, sizeof (*evrregset)); | |
791 | } | |
792 | ||
6ced10dd JB |
793 | /* Supply values from TID for SPE-specific raw registers: the upper |
794 | halves of the GPRs, the accumulator, and the spefscr. REGNO must | |
795 | be the number of an upper half register, acc, spefscr, or -1 to | |
796 | supply the values of all registers. */ | |
01904826 | 797 | static void |
56be3814 | 798 | fetch_spe_register (struct regcache *regcache, int tid, int regno) |
01904826 | 799 | { |
ac7936df | 800 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 801 | ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); |
01904826 JB |
802 | struct gdb_evrregset_t evrregs; |
803 | ||
6ced10dd | 804 | gdb_assert (sizeof (evrregs.evr[0]) |
dda83cd7 | 805 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 806 | gdb_assert (sizeof (evrregs.acc) |
dda83cd7 | 807 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 808 | gdb_assert (sizeof (evrregs.spefscr) |
dda83cd7 | 809 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
6ced10dd | 810 | |
01904826 JB |
811 | get_spe_registers (tid, &evrregs); |
812 | ||
6ced10dd | 813 | if (regno == -1) |
01904826 | 814 | { |
6ced10dd JB |
815 | int i; |
816 | ||
817 | for (i = 0; i < ppc_num_gprs; i++) | |
dda83cd7 | 818 | regcache->raw_supply (tdep->ppc_ev0_upper_regnum + i, &evrregs.evr[i]); |
01904826 | 819 | } |
6ced10dd | 820 | else if (tdep->ppc_ev0_upper_regnum <= regno |
dda83cd7 | 821 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) |
73e1c03f SM |
822 | regcache->raw_supply (regno, |
823 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); | |
6ced10dd JB |
824 | |
825 | if (regno == -1 | |
826 | || regno == tdep->ppc_acc_regnum) | |
73e1c03f | 827 | regcache->raw_supply (tdep->ppc_acc_regnum, &evrregs.acc); |
6ced10dd JB |
828 | |
829 | if (regno == -1 | |
830 | || regno == tdep->ppc_spefscr_regnum) | |
73e1c03f | 831 | regcache->raw_supply (tdep->ppc_spefscr_regnum, &evrregs.spefscr); |
01904826 JB |
832 | } |
833 | ||
7ca18ed6 EBM |
834 | /* Use ptrace to fetch all registers from the register set with note |
835 | type REGSET_ID, size REGSIZE, and layout described by REGSET, from | |
836 | process/thread TID and supply their values to REGCACHE. If ptrace | |
837 | returns ENODATA to indicate the regset is unavailable, mark the | |
838 | registers as unavailable in REGCACHE. */ | |
839 | ||
840 | static void | |
841 | fetch_regset (struct regcache *regcache, int tid, | |
842 | int regset_id, int regsetsize, const struct regset *regset) | |
843 | { | |
844 | void *buf = alloca (regsetsize); | |
845 | struct iovec iov; | |
846 | ||
847 | iov.iov_base = buf; | |
848 | iov.iov_len = regsetsize; | |
849 | ||
850 | if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) < 0) | |
851 | { | |
852 | if (errno == ENODATA) | |
853 | regset->supply_regset (regset, regcache, -1, NULL, regsetsize); | |
854 | else | |
855 | perror_with_name (_("Couldn't get register set")); | |
856 | } | |
857 | else | |
858 | regset->supply_regset (regset, regcache, -1, buf, regsetsize); | |
859 | } | |
860 | ||
861 | /* Use ptrace to store register REGNUM of the regset with note type | |
862 | REGSET_ID, size REGSETSIZE, and layout described by REGSET, from | |
863 | REGCACHE back to process/thread TID. If REGNUM is -1 all registers | |
864 | in the set are collected and stored. */ | |
865 | ||
866 | static void | |
867 | store_regset (const struct regcache *regcache, int tid, int regnum, | |
868 | int regset_id, int regsetsize, const struct regset *regset) | |
869 | { | |
870 | void *buf = alloca (regsetsize); | |
871 | struct iovec iov; | |
872 | ||
873 | iov.iov_base = buf; | |
874 | iov.iov_len = regsetsize; | |
875 | ||
876 | /* Make sure that the buffer that will be stored has up to date values | |
877 | for the registers that won't be collected. */ | |
878 | if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) < 0) | |
879 | perror_with_name (_("Couldn't get register set")); | |
880 | ||
881 | regset->collect_regset (regset, regcache, regnum, buf, regsetsize); | |
882 | ||
883 | if (ptrace (PTRACE_SETREGSET, tid, regset_id, &iov) < 0) | |
884 | perror_with_name (_("Couldn't set register set")); | |
885 | } | |
886 | ||
887 | /* Check whether the kernel provides a register set with number | |
888 | REGSET_ID of size REGSETSIZE for process/thread TID. */ | |
889 | ||
890 | static bool | |
891 | check_regset (int tid, int regset_id, int regsetsize) | |
892 | { | |
893 | void *buf = alloca (regsetsize); | |
894 | struct iovec iov; | |
895 | ||
896 | iov.iov_base = buf; | |
897 | iov.iov_len = regsetsize; | |
898 | ||
899 | if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0 | |
900 | || errno == ENODATA) | |
901 | return true; | |
902 | else | |
903 | return false; | |
904 | } | |
905 | ||
45229ea4 | 906 | static void |
56be3814 | 907 | fetch_register (struct regcache *regcache, int tid, int regno) |
45229ea4 | 908 | { |
ac7936df | 909 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 910 | ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); |
45229ea4 | 911 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 912 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
4a19ea35 | 913 | int bytes_transferred; |
0f068fb5 | 914 | gdb_byte buf[PPC_MAX_REGISTER_SIZE]; |
45229ea4 | 915 | |
be8626e0 | 916 | if (altivec_register_p (gdbarch, regno)) |
9abe5450 EZ |
917 | { |
918 | /* If this is the first time through, or if it is not the first | |
dda83cd7 SM |
919 | time through, and we have confirmed that there is kernel |
920 | support for such a ptrace request, then go and fetch the | |
921 | register. */ | |
9abe5450 EZ |
922 | if (have_ptrace_getvrregs) |
923 | { | |
dda83cd7 SM |
924 | fetch_altivec_registers (regcache, tid, regno); |
925 | return; | |
9abe5450 EZ |
926 | } |
927 | /* If we have discovered that there is no ptrace support for | |
dda83cd7 SM |
928 | AltiVec registers, fall through and return zeroes, because |
929 | regaddr will be -1 in this case. */ | |
9abe5450 | 930 | } |
3d907528 | 931 | else if (vsx_register_p (gdbarch, regno)) |
604c2f83 LM |
932 | { |
933 | if (have_ptrace_getsetvsxregs) | |
934 | { | |
2c3305f6 | 935 | fetch_vsx_registers (regcache, tid, regno); |
604c2f83 LM |
936 | return; |
937 | } | |
938 | } | |
be8626e0 | 939 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 940 | { |
56be3814 | 941 | fetch_spe_register (regcache, tid, regno); |
01904826 JB |
942 | return; |
943 | } | |
7ca18ed6 EBM |
944 | else if (regno == PPC_DSCR_REGNUM) |
945 | { | |
946 | gdb_assert (tdep->ppc_dscr_regnum != -1); | |
947 | ||
948 | fetch_regset (regcache, tid, NT_PPC_DSCR, | |
949 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
950 | &ppc32_linux_dscrregset); | |
951 | return; | |
952 | } | |
953 | else if (regno == PPC_PPR_REGNUM) | |
954 | { | |
955 | gdb_assert (tdep->ppc_ppr_regnum != -1); | |
956 | ||
957 | fetch_regset (regcache, tid, NT_PPC_PPR, | |
958 | PPC_LINUX_SIZEOF_PPRREGSET, | |
959 | &ppc32_linux_pprregset); | |
960 | return; | |
961 | } | |
f2cf6173 EBM |
962 | else if (regno == PPC_TAR_REGNUM) |
963 | { | |
964 | gdb_assert (tdep->ppc_tar_regnum != -1); | |
965 | ||
966 | fetch_regset (regcache, tid, NT_PPC_TAR, | |
967 | PPC_LINUX_SIZEOF_TARREGSET, | |
968 | &ppc32_linux_tarregset); | |
969 | return; | |
970 | } | |
232bfb86 EBM |
971 | else if (PPC_IS_EBB_REGNUM (regno)) |
972 | { | |
973 | gdb_assert (tdep->have_ebb); | |
974 | ||
975 | fetch_regset (regcache, tid, NT_PPC_EBB, | |
976 | PPC_LINUX_SIZEOF_EBBREGSET, | |
977 | &ppc32_linux_ebbregset); | |
978 | return; | |
979 | } | |
980 | else if (PPC_IS_PMU_REGNUM (regno)) | |
981 | { | |
982 | gdb_assert (tdep->ppc_mmcr0_regnum != -1); | |
983 | ||
984 | fetch_regset (regcache, tid, NT_PPC_PMU, | |
985 | PPC_LINUX_SIZEOF_PMUREGSET, | |
986 | &ppc32_linux_pmuregset); | |
987 | return; | |
988 | } | |
8d619c01 EBM |
989 | else if (PPC_IS_TMSPR_REGNUM (regno)) |
990 | { | |
991 | gdb_assert (tdep->have_htm_spr); | |
992 | ||
993 | fetch_regset (regcache, tid, NT_PPC_TM_SPR, | |
994 | PPC_LINUX_SIZEOF_TM_SPRREGSET, | |
995 | &ppc32_linux_tm_sprregset); | |
996 | return; | |
997 | } | |
998 | else if (PPC_IS_CKPTGP_REGNUM (regno)) | |
999 | { | |
1000 | gdb_assert (tdep->have_htm_core); | |
1001 | ||
1002 | const struct regset *cgprregset = ppc_linux_cgprregset (gdbarch); | |
1003 | fetch_regset (regcache, tid, NT_PPC_TM_CGPR, | |
1004 | (tdep->wordsize == 4? | |
1005 | PPC32_LINUX_SIZEOF_CGPRREGSET | |
1006 | : PPC64_LINUX_SIZEOF_CGPRREGSET), | |
1007 | cgprregset); | |
1008 | return; | |
1009 | } | |
1010 | else if (PPC_IS_CKPTFP_REGNUM (regno)) | |
1011 | { | |
1012 | gdb_assert (tdep->have_htm_fpu); | |
1013 | ||
1014 | fetch_regset (regcache, tid, NT_PPC_TM_CFPR, | |
1015 | PPC_LINUX_SIZEOF_CFPRREGSET, | |
1016 | &ppc32_linux_cfprregset); | |
1017 | return; | |
1018 | } | |
1019 | else if (PPC_IS_CKPTVMX_REGNUM (regno)) | |
1020 | { | |
1021 | gdb_assert (tdep->have_htm_altivec); | |
1022 | ||
1023 | const struct regset *cvmxregset = ppc_linux_cvmxregset (gdbarch); | |
1024 | fetch_regset (regcache, tid, NT_PPC_TM_CVMX, | |
1025 | PPC_LINUX_SIZEOF_CVMXREGSET, | |
1026 | cvmxregset); | |
1027 | return; | |
1028 | } | |
1029 | else if (PPC_IS_CKPTVSX_REGNUM (regno)) | |
1030 | { | |
1031 | gdb_assert (tdep->have_htm_vsx); | |
1032 | ||
1033 | fetch_regset (regcache, tid, NT_PPC_TM_CVSX, | |
1034 | PPC_LINUX_SIZEOF_CVSXREGSET, | |
1035 | &ppc32_linux_cvsxregset); | |
1036 | return; | |
1037 | } | |
1038 | else if (regno == PPC_CPPR_REGNUM) | |
1039 | { | |
1040 | gdb_assert (tdep->ppc_cppr_regnum != -1); | |
1041 | ||
1042 | fetch_regset (regcache, tid, NT_PPC_TM_CPPR, | |
1043 | PPC_LINUX_SIZEOF_CPPRREGSET, | |
1044 | &ppc32_linux_cpprregset); | |
1045 | return; | |
1046 | } | |
1047 | else if (regno == PPC_CDSCR_REGNUM) | |
1048 | { | |
1049 | gdb_assert (tdep->ppc_cdscr_regnum != -1); | |
1050 | ||
1051 | fetch_regset (regcache, tid, NT_PPC_TM_CDSCR, | |
1052 | PPC_LINUX_SIZEOF_CDSCRREGSET, | |
1053 | &ppc32_linux_cdscrregset); | |
1054 | return; | |
1055 | } | |
1056 | else if (regno == PPC_CTAR_REGNUM) | |
1057 | { | |
1058 | gdb_assert (tdep->ppc_ctar_regnum != -1); | |
1059 | ||
1060 | fetch_regset (regcache, tid, NT_PPC_TM_CTAR, | |
1061 | PPC_LINUX_SIZEOF_CTARREGSET, | |
1062 | &ppc32_linux_ctarregset); | |
1063 | return; | |
1064 | } | |
9abe5450 | 1065 | |
45229ea4 EZ |
1066 | if (regaddr == -1) |
1067 | { | |
40a6adc1 | 1068 | memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */ |
73e1c03f | 1069 | regcache->raw_supply (regno, buf); |
45229ea4 EZ |
1070 | return; |
1071 | } | |
1072 | ||
411cb3f9 | 1073 | /* Read the raw register using sizeof(long) sized chunks. On a |
56d0d96a AC |
1074 | 32-bit platform, 64-bit floating-point registers will require two |
1075 | transfers. */ | |
4a19ea35 | 1076 | for (bytes_transferred = 0; |
40a6adc1 | 1077 | bytes_transferred < register_size (gdbarch, regno); |
411cb3f9 | 1078 | bytes_transferred += sizeof (long)) |
45229ea4 | 1079 | { |
11fde611 JK |
1080 | long l; |
1081 | ||
45229ea4 | 1082 | errno = 0; |
11fde611 | 1083 | l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0); |
411cb3f9 | 1084 | regaddr += sizeof (long); |
45229ea4 EZ |
1085 | if (errno != 0) |
1086 | { | |
dda83cd7 | 1087 | char message[128]; |
8c042590 PM |
1088 | xsnprintf (message, sizeof (message), "reading register %s (#%d)", |
1089 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 1090 | perror_with_name (message); |
45229ea4 | 1091 | } |
11fde611 | 1092 | memcpy (&buf[bytes_transferred], &l, sizeof (l)); |
45229ea4 | 1093 | } |
56d0d96a | 1094 | |
4a19ea35 JB |
1095 | /* Now supply the register. Keep in mind that the regcache's idea |
1096 | of the register's size may not be a multiple of sizeof | |
411cb3f9 | 1097 | (long). */ |
40a6adc1 | 1098 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
4a19ea35 JB |
1099 | { |
1100 | /* Little-endian values are always found at the left end of the | |
dda83cd7 | 1101 | bytes transferred. */ |
73e1c03f | 1102 | regcache->raw_supply (regno, buf); |
4a19ea35 | 1103 | } |
40a6adc1 | 1104 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
1105 | { |
1106 | /* Big-endian values are found at the right end of the bytes | |
dda83cd7 | 1107 | transferred. */ |
40a6adc1 | 1108 | size_t padding = (bytes_transferred - register_size (gdbarch, regno)); |
73e1c03f | 1109 | regcache->raw_supply (regno, buf + padding); |
4a19ea35 JB |
1110 | } |
1111 | else | |
f34652de | 1112 | internal_error (_("fetch_register: unexpected byte order: %d"), |
dda83cd7 | 1113 | gdbarch_byte_order (gdbarch)); |
45229ea4 EZ |
1114 | } |
1115 | ||
1dfe79e8 SDJ |
1116 | /* This function actually issues the request to ptrace, telling |
1117 | it to get all general-purpose registers and put them into the | |
1118 | specified regset. | |
1119 | ||
1120 | If the ptrace request does not exist, this function returns 0 | |
1121 | and properly sets the have_ptrace_* flag. If the request fails, | |
1122 | this function calls perror_with_name. Otherwise, if the request | |
1123 | succeeds, then the regcache gets filled and 1 is returned. */ | |
1124 | static int | |
1125 | fetch_all_gp_regs (struct regcache *regcache, int tid) | |
1126 | { | |
1dfe79e8 SDJ |
1127 | gdb_gregset_t gregset; |
1128 | ||
1129 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
1130 | { | |
1131 | if (errno == EIO) | |
dda83cd7 SM |
1132 | { |
1133 | have_ptrace_getsetregs = 0; | |
1134 | return 0; | |
1135 | } | |
deb70aa0 | 1136 | perror_with_name (_("Couldn't get general-purpose registers")); |
1dfe79e8 SDJ |
1137 | } |
1138 | ||
1139 | supply_gregset (regcache, (const gdb_gregset_t *) &gregset); | |
1140 | ||
1141 | return 1; | |
1142 | } | |
1143 | ||
1144 | /* This is a wrapper for the fetch_all_gp_regs function. It is | |
1145 | responsible for verifying if this target has the ptrace request | |
1146 | that can be used to fetch all general-purpose registers at one | |
1147 | shot. If it doesn't, then we should fetch them using the | |
1148 | old-fashioned way, which is to iterate over the registers and | |
1149 | request them one by one. */ | |
1150 | static void | |
1151 | fetch_gp_regs (struct regcache *regcache, int tid) | |
1152 | { | |
ac7936df | 1153 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 1154 | ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); |
1dfe79e8 SDJ |
1155 | int i; |
1156 | ||
1157 | if (have_ptrace_getsetregs) | |
1158 | if (fetch_all_gp_regs (regcache, tid)) | |
1159 | return; | |
1160 | ||
1161 | /* If we've hit this point, it doesn't really matter which | |
1162 | architecture we are using. We just need to read the | |
1163 | registers in the "old-fashioned way". */ | |
1164 | for (i = 0; i < ppc_num_gprs; i++) | |
1165 | fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i); | |
1166 | } | |
1167 | ||
1168 | /* This function actually issues the request to ptrace, telling | |
1169 | it to get all floating-point registers and put them into the | |
1170 | specified regset. | |
1171 | ||
1172 | If the ptrace request does not exist, this function returns 0 | |
1173 | and properly sets the have_ptrace_* flag. If the request fails, | |
1174 | this function calls perror_with_name. Otherwise, if the request | |
1175 | succeeds, then the regcache gets filled and 1 is returned. */ | |
1176 | static int | |
1177 | fetch_all_fp_regs (struct regcache *regcache, int tid) | |
1178 | { | |
1179 | gdb_fpregset_t fpregs; | |
1180 | ||
1181 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1182 | { | |
1183 | if (errno == EIO) | |
dda83cd7 SM |
1184 | { |
1185 | have_ptrace_getsetfpregs = 0; | |
1186 | return 0; | |
1187 | } | |
deb70aa0 | 1188 | perror_with_name (_("Couldn't get floating-point registers")); |
1dfe79e8 SDJ |
1189 | } |
1190 | ||
1191 | supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs); | |
1192 | ||
1193 | return 1; | |
1194 | } | |
1195 | ||
1196 | /* This is a wrapper for the fetch_all_fp_regs function. It is | |
1197 | responsible for verifying if this target has the ptrace request | |
1198 | that can be used to fetch all floating-point registers at one | |
1199 | shot. If it doesn't, then we should fetch them using the | |
1200 | old-fashioned way, which is to iterate over the registers and | |
1201 | request them one by one. */ | |
1202 | static void | |
1203 | fetch_fp_regs (struct regcache *regcache, int tid) | |
1204 | { | |
ac7936df | 1205 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 1206 | ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); |
1dfe79e8 SDJ |
1207 | int i; |
1208 | ||
1209 | if (have_ptrace_getsetfpregs) | |
1210 | if (fetch_all_fp_regs (regcache, tid)) | |
1211 | return; | |
1212 | ||
1213 | /* If we've hit this point, it doesn't really matter which | |
1214 | architecture we are using. We just need to read the | |
1215 | registers in the "old-fashioned way". */ | |
1216 | for (i = 0; i < ppc_num_fprs; i++) | |
1217 | fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
1218 | } | |
1219 | ||
45229ea4 | 1220 | static void |
56be3814 | 1221 | fetch_ppc_registers (struct regcache *regcache, int tid) |
45229ea4 | 1222 | { |
ac7936df | 1223 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 1224 | ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); |
9abe5450 | 1225 | |
1dfe79e8 | 1226 | fetch_gp_regs (regcache, tid); |
32b99774 | 1227 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 1228 | fetch_fp_regs (regcache, tid); |
40a6adc1 | 1229 | fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 1230 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 1231 | fetch_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 1232 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 1233 | fetch_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 1234 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 1235 | fetch_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 1236 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 1237 | fetch_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 1238 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 1239 | fetch_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 1240 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 1241 | fetch_register (regcache, tid, tdep->ppc_mq_regnum); |
7284e1be UW |
1242 | if (ppc_linux_trap_reg_p (gdbarch)) |
1243 | { | |
1244 | fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
1245 | fetch_register (regcache, tid, PPC_TRAP_REGNUM); | |
1246 | } | |
32b99774 | 1247 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 1248 | fetch_register (regcache, tid, tdep->ppc_fpscr_regnum); |
9abe5450 EZ |
1249 | if (have_ptrace_getvrregs) |
1250 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
1d75a658 | 1251 | fetch_altivec_registers (regcache, tid, -1); |
604c2f83 LM |
1252 | if (have_ptrace_getsetvsxregs) |
1253 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
2c3305f6 | 1254 | fetch_vsx_registers (regcache, tid, -1); |
6ced10dd | 1255 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 1256 | fetch_spe_register (regcache, tid, -1); |
7ca18ed6 EBM |
1257 | if (tdep->ppc_ppr_regnum != -1) |
1258 | fetch_regset (regcache, tid, NT_PPC_PPR, | |
1259 | PPC_LINUX_SIZEOF_PPRREGSET, | |
1260 | &ppc32_linux_pprregset); | |
1261 | if (tdep->ppc_dscr_regnum != -1) | |
1262 | fetch_regset (regcache, tid, NT_PPC_DSCR, | |
1263 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
1264 | &ppc32_linux_dscrregset); | |
f2cf6173 EBM |
1265 | if (tdep->ppc_tar_regnum != -1) |
1266 | fetch_regset (regcache, tid, NT_PPC_TAR, | |
1267 | PPC_LINUX_SIZEOF_TARREGSET, | |
1268 | &ppc32_linux_tarregset); | |
232bfb86 EBM |
1269 | if (tdep->have_ebb) |
1270 | fetch_regset (regcache, tid, NT_PPC_EBB, | |
1271 | PPC_LINUX_SIZEOF_EBBREGSET, | |
1272 | &ppc32_linux_ebbregset); | |
1273 | if (tdep->ppc_mmcr0_regnum != -1) | |
1274 | fetch_regset (regcache, tid, NT_PPC_PMU, | |
1275 | PPC_LINUX_SIZEOF_PMUREGSET, | |
1276 | &ppc32_linux_pmuregset); | |
8d619c01 EBM |
1277 | if (tdep->have_htm_spr) |
1278 | fetch_regset (regcache, tid, NT_PPC_TM_SPR, | |
1279 | PPC_LINUX_SIZEOF_TM_SPRREGSET, | |
1280 | &ppc32_linux_tm_sprregset); | |
1281 | if (tdep->have_htm_core) | |
1282 | { | |
1283 | const struct regset *cgprregset = ppc_linux_cgprregset (gdbarch); | |
1284 | fetch_regset (regcache, tid, NT_PPC_TM_CGPR, | |
1285 | (tdep->wordsize == 4? | |
1286 | PPC32_LINUX_SIZEOF_CGPRREGSET | |
1287 | : PPC64_LINUX_SIZEOF_CGPRREGSET), | |
1288 | cgprregset); | |
1289 | } | |
1290 | if (tdep->have_htm_fpu) | |
1291 | fetch_regset (regcache, tid, NT_PPC_TM_CFPR, | |
1292 | PPC_LINUX_SIZEOF_CFPRREGSET, | |
1293 | &ppc32_linux_cfprregset); | |
1294 | if (tdep->have_htm_altivec) | |
1295 | { | |
1296 | const struct regset *cvmxregset = ppc_linux_cvmxregset (gdbarch); | |
1297 | fetch_regset (regcache, tid, NT_PPC_TM_CVMX, | |
1298 | PPC_LINUX_SIZEOF_CVMXREGSET, | |
1299 | cvmxregset); | |
1300 | } | |
1301 | if (tdep->have_htm_vsx) | |
1302 | fetch_regset (regcache, tid, NT_PPC_TM_CVSX, | |
1303 | PPC_LINUX_SIZEOF_CVSXREGSET, | |
1304 | &ppc32_linux_cvsxregset); | |
1305 | if (tdep->ppc_cppr_regnum != -1) | |
1306 | fetch_regset (regcache, tid, NT_PPC_TM_CPPR, | |
1307 | PPC_LINUX_SIZEOF_CPPRREGSET, | |
1308 | &ppc32_linux_cpprregset); | |
1309 | if (tdep->ppc_cdscr_regnum != -1) | |
1310 | fetch_regset (regcache, tid, NT_PPC_TM_CDSCR, | |
1311 | PPC_LINUX_SIZEOF_CDSCRREGSET, | |
1312 | &ppc32_linux_cdscrregset); | |
1313 | if (tdep->ppc_ctar_regnum != -1) | |
1314 | fetch_regset (regcache, tid, NT_PPC_TM_CTAR, | |
1315 | PPC_LINUX_SIZEOF_CTARREGSET, | |
1316 | &ppc32_linux_ctarregset); | |
45229ea4 EZ |
1317 | } |
1318 | ||
1319 | /* Fetch registers from the child process. Fetch all registers if | |
1320 | regno == -1, otherwise fetch all general registers or all floating | |
1321 | point registers depending upon the value of regno. */ | |
f6ac5f3d PA |
1322 | void |
1323 | ppc_linux_nat_target::fetch_registers (struct regcache *regcache, int regno) | |
45229ea4 | 1324 | { |
222312d3 | 1325 | pid_t tid = get_ptrace_pid (regcache->ptid ()); |
05f13b9c | 1326 | |
9abe5450 | 1327 | if (regno == -1) |
56be3814 | 1328 | fetch_ppc_registers (regcache, tid); |
45229ea4 | 1329 | else |
56be3814 | 1330 | fetch_register (regcache, tid, regno); |
45229ea4 EZ |
1331 | } |
1332 | ||
604c2f83 | 1333 | static void |
2c3305f6 | 1334 | store_vsx_registers (const struct regcache *regcache, int tid, int regno) |
604c2f83 LM |
1335 | { |
1336 | int ret; | |
1337 | gdb_vsxregset_t regs; | |
2c3305f6 | 1338 | const struct regset *vsxregset = ppc_linux_vsxregset (); |
604c2f83 | 1339 | |
9fe70b4f | 1340 | ret = ptrace (PTRACE_GETVSXREGS, tid, 0, ®s); |
604c2f83 LM |
1341 | if (ret < 0) |
1342 | { | |
1343 | if (errno == EIO) | |
1344 | { | |
1345 | have_ptrace_getsetvsxregs = 0; | |
1346 | return; | |
1347 | } | |
2c3305f6 | 1348 | perror_with_name (_("Unable to fetch VSX registers")); |
604c2f83 LM |
1349 | } |
1350 | ||
2c3305f6 PFC |
1351 | vsxregset->collect_regset (vsxregset, regcache, regno, ®s, |
1352 | PPC_LINUX_SIZEOF_VSXREGSET); | |
604c2f83 LM |
1353 | |
1354 | ret = ptrace (PTRACE_SETVSXREGS, tid, 0, ®s); | |
1355 | if (ret < 0) | |
2c3305f6 | 1356 | perror_with_name (_("Unable to store VSX registers")); |
604c2f83 LM |
1357 | } |
1358 | ||
9abe5450 | 1359 | static void |
1d75a658 PFC |
1360 | store_altivec_registers (const struct regcache *regcache, int tid, |
1361 | int regno) | |
9abe5450 EZ |
1362 | { |
1363 | int ret; | |
9abe5450 | 1364 | gdb_vrregset_t regs; |
ac7936df | 1365 | struct gdbarch *gdbarch = regcache->arch (); |
1d75a658 | 1366 | const struct regset *vrregset = ppc_linux_vrregset (gdbarch); |
9abe5450 EZ |
1367 | |
1368 | ret = ptrace (PTRACE_GETVRREGS, tid, 0, ®s); | |
1369 | if (ret < 0) | |
1370 | { | |
1371 | if (errno == EIO) | |
dda83cd7 SM |
1372 | { |
1373 | have_ptrace_getvrregs = 0; | |
1374 | return; | |
1375 | } | |
1d75a658 | 1376 | perror_with_name (_("Unable to fetch AltiVec registers")); |
9abe5450 EZ |
1377 | } |
1378 | ||
1d75a658 PFC |
1379 | vrregset->collect_regset (vrregset, regcache, regno, ®s, |
1380 | PPC_LINUX_SIZEOF_VRREGSET); | |
9abe5450 EZ |
1381 | |
1382 | ret = ptrace (PTRACE_SETVRREGS, tid, 0, ®s); | |
1383 | if (ret < 0) | |
1d75a658 | 1384 | perror_with_name (_("Unable to store AltiVec registers")); |
9abe5450 EZ |
1385 | } |
1386 | ||
85102364 | 1387 | /* Assuming TID refers to an SPE process, set the top halves of TID's |
01904826 JB |
1388 | general-purpose registers and its SPE-specific registers to the |
1389 | values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do | |
1390 | nothing. | |
1391 | ||
1392 | All the logic to deal with whether or not the PTRACE_GETEVRREGS and | |
1393 | PTRACE_SETEVRREGS requests are supported is isolated here, and in | |
1394 | get_spe_registers. */ | |
1395 | static void | |
1396 | set_spe_registers (int tid, struct gdb_evrregset_t *evrregset) | |
1397 | { | |
1398 | if (have_ptrace_getsetevrregs) | |
1399 | { | |
1400 | if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0) | |
dda83cd7 | 1401 | return; |
01904826 | 1402 | else |
dda83cd7 SM |
1403 | { |
1404 | /* EIO means that the PTRACE_SETEVRREGS request isn't | |
1405 | supported; we fail silently, and don't try the call | |
1406 | again. */ | |
1407 | if (errno == EIO) | |
1408 | have_ptrace_getsetevrregs = 0; | |
1409 | else | |
1410 | /* Anything else needs to be reported. */ | |
1411 | perror_with_name (_("Unable to set SPE registers")); | |
1412 | } | |
01904826 JB |
1413 | } |
1414 | } | |
1415 | ||
6ced10dd JB |
1416 | /* Write GDB's value for the SPE-specific raw register REGNO to TID. |
1417 | If REGNO is -1, write the values of all the SPE-specific | |
1418 | registers. */ | |
01904826 | 1419 | static void |
56be3814 | 1420 | store_spe_register (const struct regcache *regcache, int tid, int regno) |
01904826 | 1421 | { |
ac7936df | 1422 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 1423 | ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); |
01904826 JB |
1424 | struct gdb_evrregset_t evrregs; |
1425 | ||
6ced10dd | 1426 | gdb_assert (sizeof (evrregs.evr[0]) |
dda83cd7 | 1427 | == register_size (gdbarch, tdep->ppc_ev0_upper_regnum)); |
6ced10dd | 1428 | gdb_assert (sizeof (evrregs.acc) |
dda83cd7 | 1429 | == register_size (gdbarch, tdep->ppc_acc_regnum)); |
6ced10dd | 1430 | gdb_assert (sizeof (evrregs.spefscr) |
dda83cd7 | 1431 | == register_size (gdbarch, tdep->ppc_spefscr_regnum)); |
01904826 | 1432 | |
6ced10dd JB |
1433 | if (regno == -1) |
1434 | /* Since we're going to write out every register, the code below | |
1435 | should store to every field of evrregs; if that doesn't happen, | |
1436 | make it obvious by initializing it with suspicious values. */ | |
1437 | memset (&evrregs, 42, sizeof (evrregs)); | |
1438 | else | |
1439 | /* We can only read and write the entire EVR register set at a | |
1440 | time, so to write just a single register, we do a | |
1441 | read-modify-write maneuver. */ | |
1442 | get_spe_registers (tid, &evrregs); | |
1443 | ||
1444 | if (regno == -1) | |
01904826 | 1445 | { |
6ced10dd JB |
1446 | int i; |
1447 | ||
1448 | for (i = 0; i < ppc_num_gprs; i++) | |
34a79281 SM |
1449 | regcache->raw_collect (tdep->ppc_ev0_upper_regnum + i, |
1450 | &evrregs.evr[i]); | |
01904826 | 1451 | } |
6ced10dd | 1452 | else if (tdep->ppc_ev0_upper_regnum <= regno |
dda83cd7 | 1453 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) |
34a79281 SM |
1454 | regcache->raw_collect (regno, |
1455 | &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]); | |
6ced10dd JB |
1456 | |
1457 | if (regno == -1 | |
1458 | || regno == tdep->ppc_acc_regnum) | |
34a79281 SM |
1459 | regcache->raw_collect (tdep->ppc_acc_regnum, |
1460 | &evrregs.acc); | |
6ced10dd JB |
1461 | |
1462 | if (regno == -1 | |
1463 | || regno == tdep->ppc_spefscr_regnum) | |
34a79281 SM |
1464 | regcache->raw_collect (tdep->ppc_spefscr_regnum, |
1465 | &evrregs.spefscr); | |
01904826 JB |
1466 | |
1467 | /* Write back the modified register set. */ | |
1468 | set_spe_registers (tid, &evrregs); | |
1469 | } | |
1470 | ||
45229ea4 | 1471 | static void |
56be3814 | 1472 | store_register (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1473 | { |
ac7936df | 1474 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 1475 | ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); |
45229ea4 | 1476 | /* This isn't really an address. But ptrace thinks of it as one. */ |
e101270f | 1477 | CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno); |
52f0bd74 | 1478 | int i; |
4a19ea35 | 1479 | size_t bytes_to_transfer; |
0f068fb5 | 1480 | gdb_byte buf[PPC_MAX_REGISTER_SIZE]; |
45229ea4 | 1481 | |
be8626e0 | 1482 | if (altivec_register_p (gdbarch, regno)) |
45229ea4 | 1483 | { |
1d75a658 | 1484 | store_altivec_registers (regcache, tid, regno); |
45229ea4 EZ |
1485 | return; |
1486 | } | |
3d907528 | 1487 | else if (vsx_register_p (gdbarch, regno)) |
604c2f83 | 1488 | { |
2c3305f6 | 1489 | store_vsx_registers (regcache, tid, regno); |
604c2f83 LM |
1490 | return; |
1491 | } | |
be8626e0 | 1492 | else if (spe_register_p (gdbarch, regno)) |
01904826 | 1493 | { |
56be3814 | 1494 | store_spe_register (regcache, tid, regno); |
01904826 JB |
1495 | return; |
1496 | } | |
7ca18ed6 EBM |
1497 | else if (regno == PPC_DSCR_REGNUM) |
1498 | { | |
1499 | gdb_assert (tdep->ppc_dscr_regnum != -1); | |
1500 | ||
1501 | store_regset (regcache, tid, regno, NT_PPC_DSCR, | |
1502 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
1503 | &ppc32_linux_dscrregset); | |
1504 | return; | |
1505 | } | |
1506 | else if (regno == PPC_PPR_REGNUM) | |
1507 | { | |
1508 | gdb_assert (tdep->ppc_ppr_regnum != -1); | |
1509 | ||
1510 | store_regset (regcache, tid, regno, NT_PPC_PPR, | |
1511 | PPC_LINUX_SIZEOF_PPRREGSET, | |
1512 | &ppc32_linux_pprregset); | |
1513 | return; | |
1514 | } | |
f2cf6173 EBM |
1515 | else if (regno == PPC_TAR_REGNUM) |
1516 | { | |
1517 | gdb_assert (tdep->ppc_tar_regnum != -1); | |
1518 | ||
1519 | store_regset (regcache, tid, regno, NT_PPC_TAR, | |
1520 | PPC_LINUX_SIZEOF_TARREGSET, | |
1521 | &ppc32_linux_tarregset); | |
1522 | return; | |
1523 | } | |
232bfb86 EBM |
1524 | else if (PPC_IS_EBB_REGNUM (regno)) |
1525 | { | |
1526 | gdb_assert (tdep->have_ebb); | |
1527 | ||
1528 | store_regset (regcache, tid, regno, NT_PPC_EBB, | |
1529 | PPC_LINUX_SIZEOF_EBBREGSET, | |
1530 | &ppc32_linux_ebbregset); | |
1531 | return; | |
1532 | } | |
1533 | else if (PPC_IS_PMU_REGNUM (regno)) | |
1534 | { | |
1535 | gdb_assert (tdep->ppc_mmcr0_regnum != -1); | |
1536 | ||
1537 | store_regset (regcache, tid, regno, NT_PPC_PMU, | |
1538 | PPC_LINUX_SIZEOF_PMUREGSET, | |
1539 | &ppc32_linux_pmuregset); | |
1540 | return; | |
1541 | } | |
8d619c01 EBM |
1542 | else if (PPC_IS_TMSPR_REGNUM (regno)) |
1543 | { | |
1544 | gdb_assert (tdep->have_htm_spr); | |
1545 | ||
1546 | store_regset (regcache, tid, regno, NT_PPC_TM_SPR, | |
1547 | PPC_LINUX_SIZEOF_TM_SPRREGSET, | |
1548 | &ppc32_linux_tm_sprregset); | |
1549 | return; | |
1550 | } | |
1551 | else if (PPC_IS_CKPTGP_REGNUM (regno)) | |
1552 | { | |
1553 | gdb_assert (tdep->have_htm_core); | |
1554 | ||
1555 | const struct regset *cgprregset = ppc_linux_cgprregset (gdbarch); | |
1556 | store_regset (regcache, tid, regno, NT_PPC_TM_CGPR, | |
1557 | (tdep->wordsize == 4? | |
1558 | PPC32_LINUX_SIZEOF_CGPRREGSET | |
1559 | : PPC64_LINUX_SIZEOF_CGPRREGSET), | |
1560 | cgprregset); | |
1561 | return; | |
1562 | } | |
1563 | else if (PPC_IS_CKPTFP_REGNUM (regno)) | |
1564 | { | |
1565 | gdb_assert (tdep->have_htm_fpu); | |
1566 | ||
1567 | store_regset (regcache, tid, regno, NT_PPC_TM_CFPR, | |
1568 | PPC_LINUX_SIZEOF_CFPRREGSET, | |
1569 | &ppc32_linux_cfprregset); | |
1570 | return; | |
1571 | } | |
1572 | else if (PPC_IS_CKPTVMX_REGNUM (regno)) | |
1573 | { | |
1574 | gdb_assert (tdep->have_htm_altivec); | |
1575 | ||
1576 | const struct regset *cvmxregset = ppc_linux_cvmxregset (gdbarch); | |
1577 | store_regset (regcache, tid, regno, NT_PPC_TM_CVMX, | |
1578 | PPC_LINUX_SIZEOF_CVMXREGSET, | |
1579 | cvmxregset); | |
1580 | return; | |
1581 | } | |
1582 | else if (PPC_IS_CKPTVSX_REGNUM (regno)) | |
1583 | { | |
1584 | gdb_assert (tdep->have_htm_vsx); | |
1585 | ||
1586 | store_regset (regcache, tid, regno, NT_PPC_TM_CVSX, | |
1587 | PPC_LINUX_SIZEOF_CVSXREGSET, | |
1588 | &ppc32_linux_cvsxregset); | |
1589 | return; | |
1590 | } | |
1591 | else if (regno == PPC_CPPR_REGNUM) | |
1592 | { | |
1593 | gdb_assert (tdep->ppc_cppr_regnum != -1); | |
1594 | ||
1595 | store_regset (regcache, tid, regno, NT_PPC_TM_CPPR, | |
1596 | PPC_LINUX_SIZEOF_CPPRREGSET, | |
1597 | &ppc32_linux_cpprregset); | |
1598 | return; | |
1599 | } | |
1600 | else if (regno == PPC_CDSCR_REGNUM) | |
1601 | { | |
1602 | gdb_assert (tdep->ppc_cdscr_regnum != -1); | |
1603 | ||
1604 | store_regset (regcache, tid, regno, NT_PPC_TM_CDSCR, | |
1605 | PPC_LINUX_SIZEOF_CDSCRREGSET, | |
1606 | &ppc32_linux_cdscrregset); | |
1607 | return; | |
1608 | } | |
1609 | else if (regno == PPC_CTAR_REGNUM) | |
1610 | { | |
1611 | gdb_assert (tdep->ppc_ctar_regnum != -1); | |
1612 | ||
1613 | store_regset (regcache, tid, regno, NT_PPC_TM_CTAR, | |
1614 | PPC_LINUX_SIZEOF_CTARREGSET, | |
1615 | &ppc32_linux_ctarregset); | |
1616 | return; | |
1617 | } | |
45229ea4 | 1618 | |
9abe5450 EZ |
1619 | if (regaddr == -1) |
1620 | return; | |
1621 | ||
4a19ea35 JB |
1622 | /* First collect the register. Keep in mind that the regcache's |
1623 | idea of the register's size may not be a multiple of sizeof | |
411cb3f9 | 1624 | (long). */ |
56d0d96a | 1625 | memset (buf, 0, sizeof buf); |
40a6adc1 MD |
1626 | bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long)); |
1627 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
4a19ea35 JB |
1628 | { |
1629 | /* Little-endian values always sit at the left end of the buffer. */ | |
34a79281 | 1630 | regcache->raw_collect (regno, buf); |
4a19ea35 | 1631 | } |
40a6adc1 | 1632 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
4a19ea35 JB |
1633 | { |
1634 | /* Big-endian values sit at the right end of the buffer. */ | |
40a6adc1 | 1635 | size_t padding = (bytes_to_transfer - register_size (gdbarch, regno)); |
34a79281 | 1636 | regcache->raw_collect (regno, buf + padding); |
4a19ea35 JB |
1637 | } |
1638 | ||
411cb3f9 | 1639 | for (i = 0; i < bytes_to_transfer; i += sizeof (long)) |
45229ea4 | 1640 | { |
11fde611 JK |
1641 | long l; |
1642 | ||
1643 | memcpy (&l, &buf[i], sizeof (l)); | |
45229ea4 | 1644 | errno = 0; |
11fde611 | 1645 | ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l); |
411cb3f9 | 1646 | regaddr += sizeof (long); |
e3f36dbd KB |
1647 | |
1648 | if (errno == EIO | |
dda83cd7 | 1649 | && (regno == tdep->ppc_fpscr_regnum |
7284e1be UW |
1650 | || regno == PPC_ORIG_R3_REGNUM |
1651 | || regno == PPC_TRAP_REGNUM)) | |
e3f36dbd | 1652 | { |
7284e1be UW |
1653 | /* Some older kernel versions don't allow fpscr, orig_r3 |
1654 | or trap to be written. */ | |
e3f36dbd KB |
1655 | continue; |
1656 | } | |
1657 | ||
45229ea4 EZ |
1658 | if (errno != 0) |
1659 | { | |
dda83cd7 | 1660 | char message[128]; |
8c042590 PM |
1661 | xsnprintf (message, sizeof (message), "writing register %s (#%d)", |
1662 | gdbarch_register_name (gdbarch, regno), regno); | |
bc97b3ba | 1663 | perror_with_name (message); |
45229ea4 EZ |
1664 | } |
1665 | } | |
1666 | } | |
1667 | ||
1dfe79e8 SDJ |
1668 | /* This function actually issues the request to ptrace, telling |
1669 | it to store all general-purpose registers present in the specified | |
1670 | regset. | |
1671 | ||
1672 | If the ptrace request does not exist, this function returns 0 | |
1673 | and properly sets the have_ptrace_* flag. If the request fails, | |
1674 | this function calls perror_with_name. Otherwise, if the request | |
1675 | succeeds, then the regcache is stored and 1 is returned. */ | |
1676 | static int | |
1677 | store_all_gp_regs (const struct regcache *regcache, int tid, int regno) | |
1678 | { | |
1dfe79e8 SDJ |
1679 | gdb_gregset_t gregset; |
1680 | ||
1681 | if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0) | |
1682 | { | |
1683 | if (errno == EIO) | |
dda83cd7 SM |
1684 | { |
1685 | have_ptrace_getsetregs = 0; | |
1686 | return 0; | |
1687 | } | |
deb70aa0 | 1688 | perror_with_name (_("Couldn't get general-purpose registers")); |
1dfe79e8 SDJ |
1689 | } |
1690 | ||
1691 | fill_gregset (regcache, &gregset, regno); | |
1692 | ||
1693 | if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0) | |
1694 | { | |
1695 | if (errno == EIO) | |
dda83cd7 SM |
1696 | { |
1697 | have_ptrace_getsetregs = 0; | |
1698 | return 0; | |
1699 | } | |
deb70aa0 | 1700 | perror_with_name (_("Couldn't set general-purpose registers")); |
1dfe79e8 SDJ |
1701 | } |
1702 | ||
1703 | return 1; | |
1704 | } | |
1705 | ||
1706 | /* This is a wrapper for the store_all_gp_regs function. It is | |
1707 | responsible for verifying if this target has the ptrace request | |
1708 | that can be used to store all general-purpose registers at one | |
1709 | shot. If it doesn't, then we should store them using the | |
1710 | old-fashioned way, which is to iterate over the registers and | |
1711 | store them one by one. */ | |
45229ea4 | 1712 | static void |
1dfe79e8 | 1713 | store_gp_regs (const struct regcache *regcache, int tid, int regno) |
45229ea4 | 1714 | { |
ac7936df | 1715 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 1716 | ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); |
1dfe79e8 SDJ |
1717 | int i; |
1718 | ||
1719 | if (have_ptrace_getsetregs) | |
1720 | if (store_all_gp_regs (regcache, tid, regno)) | |
1721 | return; | |
1722 | ||
1723 | /* If we hit this point, it doesn't really matter which | |
1724 | architecture we are using. We just need to store the | |
1725 | registers in the "old-fashioned way". */ | |
6ced10dd | 1726 | for (i = 0; i < ppc_num_gprs; i++) |
56be3814 | 1727 | store_register (regcache, tid, tdep->ppc_gp0_regnum + i); |
1dfe79e8 SDJ |
1728 | } |
1729 | ||
1730 | /* This function actually issues the request to ptrace, telling | |
1731 | it to store all floating-point registers present in the specified | |
1732 | regset. | |
1733 | ||
1734 | If the ptrace request does not exist, this function returns 0 | |
1735 | and properly sets the have_ptrace_* flag. If the request fails, | |
1736 | this function calls perror_with_name. Otherwise, if the request | |
1737 | succeeds, then the regcache is stored and 1 is returned. */ | |
1738 | static int | |
1739 | store_all_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1740 | { | |
1741 | gdb_fpregset_t fpregs; | |
1742 | ||
1743 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1744 | { | |
1745 | if (errno == EIO) | |
dda83cd7 SM |
1746 | { |
1747 | have_ptrace_getsetfpregs = 0; | |
1748 | return 0; | |
1749 | } | |
deb70aa0 | 1750 | perror_with_name (_("Couldn't get floating-point registers")); |
1dfe79e8 SDJ |
1751 | } |
1752 | ||
1753 | fill_fpregset (regcache, &fpregs, regno); | |
1754 | ||
1755 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0) | |
1756 | { | |
1757 | if (errno == EIO) | |
dda83cd7 SM |
1758 | { |
1759 | have_ptrace_getsetfpregs = 0; | |
1760 | return 0; | |
1761 | } | |
deb70aa0 | 1762 | perror_with_name (_("Couldn't set floating-point registers")); |
1dfe79e8 SDJ |
1763 | } |
1764 | ||
1765 | return 1; | |
1766 | } | |
1767 | ||
1768 | /* This is a wrapper for the store_all_fp_regs function. It is | |
1769 | responsible for verifying if this target has the ptrace request | |
1770 | that can be used to store all floating-point registers at one | |
1771 | shot. If it doesn't, then we should store them using the | |
1772 | old-fashioned way, which is to iterate over the registers and | |
1773 | store them one by one. */ | |
1774 | static void | |
1775 | store_fp_regs (const struct regcache *regcache, int tid, int regno) | |
1776 | { | |
ac7936df | 1777 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 1778 | ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); |
1dfe79e8 SDJ |
1779 | int i; |
1780 | ||
1781 | if (have_ptrace_getsetfpregs) | |
1782 | if (store_all_fp_regs (regcache, tid, regno)) | |
1783 | return; | |
1784 | ||
1785 | /* If we hit this point, it doesn't really matter which | |
1786 | architecture we are using. We just need to store the | |
1787 | registers in the "old-fashioned way". */ | |
1788 | for (i = 0; i < ppc_num_fprs; i++) | |
1789 | store_register (regcache, tid, tdep->ppc_fp0_regnum + i); | |
1790 | } | |
1791 | ||
1792 | static void | |
1793 | store_ppc_registers (const struct regcache *regcache, int tid) | |
1794 | { | |
ac7936df | 1795 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 1796 | ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); |
1dfe79e8 SDJ |
1797 | |
1798 | store_gp_regs (regcache, tid, -1); | |
32b99774 | 1799 | if (tdep->ppc_fp0_regnum >= 0) |
1dfe79e8 | 1800 | store_fp_regs (regcache, tid, -1); |
40a6adc1 | 1801 | store_register (regcache, tid, gdbarch_pc_regnum (gdbarch)); |
32b99774 | 1802 | if (tdep->ppc_ps_regnum != -1) |
56be3814 | 1803 | store_register (regcache, tid, tdep->ppc_ps_regnum); |
32b99774 | 1804 | if (tdep->ppc_cr_regnum != -1) |
56be3814 | 1805 | store_register (regcache, tid, tdep->ppc_cr_regnum); |
32b99774 | 1806 | if (tdep->ppc_lr_regnum != -1) |
56be3814 | 1807 | store_register (regcache, tid, tdep->ppc_lr_regnum); |
32b99774 | 1808 | if (tdep->ppc_ctr_regnum != -1) |
56be3814 | 1809 | store_register (regcache, tid, tdep->ppc_ctr_regnum); |
32b99774 | 1810 | if (tdep->ppc_xer_regnum != -1) |
56be3814 | 1811 | store_register (regcache, tid, tdep->ppc_xer_regnum); |
e3f36dbd | 1812 | if (tdep->ppc_mq_regnum != -1) |
56be3814 | 1813 | store_register (regcache, tid, tdep->ppc_mq_regnum); |
32b99774 | 1814 | if (tdep->ppc_fpscr_regnum != -1) |
56be3814 | 1815 | store_register (regcache, tid, tdep->ppc_fpscr_regnum); |
7284e1be UW |
1816 | if (ppc_linux_trap_reg_p (gdbarch)) |
1817 | { | |
1818 | store_register (regcache, tid, PPC_ORIG_R3_REGNUM); | |
1819 | store_register (regcache, tid, PPC_TRAP_REGNUM); | |
1820 | } | |
9abe5450 EZ |
1821 | if (have_ptrace_getvrregs) |
1822 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
1d75a658 | 1823 | store_altivec_registers (regcache, tid, -1); |
604c2f83 LM |
1824 | if (have_ptrace_getsetvsxregs) |
1825 | if (tdep->ppc_vsr0_upper_regnum != -1) | |
2c3305f6 | 1826 | store_vsx_registers (regcache, tid, -1); |
6ced10dd | 1827 | if (tdep->ppc_ev0_upper_regnum >= 0) |
56be3814 | 1828 | store_spe_register (regcache, tid, -1); |
7ca18ed6 EBM |
1829 | if (tdep->ppc_ppr_regnum != -1) |
1830 | store_regset (regcache, tid, -1, NT_PPC_PPR, | |
1831 | PPC_LINUX_SIZEOF_PPRREGSET, | |
1832 | &ppc32_linux_pprregset); | |
1833 | if (tdep->ppc_dscr_regnum != -1) | |
1834 | store_regset (regcache, tid, -1, NT_PPC_DSCR, | |
1835 | PPC_LINUX_SIZEOF_DSCRREGSET, | |
1836 | &ppc32_linux_dscrregset); | |
f2cf6173 EBM |
1837 | if (tdep->ppc_tar_regnum != -1) |
1838 | store_regset (regcache, tid, -1, NT_PPC_TAR, | |
1839 | PPC_LINUX_SIZEOF_TARREGSET, | |
1840 | &ppc32_linux_tarregset); | |
232bfb86 EBM |
1841 | |
1842 | if (tdep->ppc_mmcr0_regnum != -1) | |
1843 | store_regset (regcache, tid, -1, NT_PPC_PMU, | |
1844 | PPC_LINUX_SIZEOF_PMUREGSET, | |
1845 | &ppc32_linux_pmuregset); | |
1846 | ||
8d619c01 EBM |
1847 | if (tdep->have_htm_spr) |
1848 | store_regset (regcache, tid, -1, NT_PPC_TM_SPR, | |
1849 | PPC_LINUX_SIZEOF_TM_SPRREGSET, | |
1850 | &ppc32_linux_tm_sprregset); | |
1851 | ||
1852 | /* Because the EBB and checkpointed HTM registers can be | |
1853 | unavailable, attempts to store them here would cause this | |
1854 | function to fail most of the time, so we ignore them. */ | |
45229ea4 EZ |
1855 | } |
1856 | ||
4db10d8f PFC |
1857 | void |
1858 | ppc_linux_nat_target::store_registers (struct regcache *regcache, int regno) | |
1859 | { | |
1860 | pid_t tid = get_ptrace_pid (regcache->ptid ()); | |
1861 | ||
1862 | if (regno >= 0) | |
1863 | store_register (regcache, tid, regno); | |
1864 | else | |
1865 | store_ppc_registers (regcache, tid); | |
1866 | } | |
1867 | ||
1868 | /* Functions for transferring registers between a gregset_t or fpregset_t | |
1869 | (see sys/ucontext.h) and gdb's regcache. The word size is that used | |
1870 | by the ptrace interface, not the current program's ABI. Eg. if a | |
1871 | powerpc64-linux gdb is being used to debug a powerpc32-linux app, we | |
1872 | read or write 64-bit gregsets. This is to suit the host libthread_db. */ | |
1873 | ||
1874 | void | |
1875 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) | |
1876 | { | |
1877 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); | |
1878 | ||
1879 | ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp)); | |
1880 | } | |
1881 | ||
1882 | void | |
1883 | fill_gregset (const struct regcache *regcache, | |
1884 | gdb_gregset_t *gregsetp, int regno) | |
1885 | { | |
1886 | const struct regset *regset = ppc_linux_gregset (sizeof (long)); | |
1887 | ||
1888 | if (regno == -1) | |
1889 | memset (gregsetp, 0, sizeof (*gregsetp)); | |
1890 | ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp)); | |
1891 | } | |
1892 | ||
1893 | void | |
1894 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp) | |
1895 | { | |
1896 | const struct regset *regset = ppc_linux_fpregset (); | |
1897 | ||
1898 | ppc_supply_fpregset (regset, regcache, -1, | |
1899 | fpregsetp, sizeof (*fpregsetp)); | |
1900 | } | |
1901 | ||
1902 | void | |
1903 | fill_fpregset (const struct regcache *regcache, | |
1904 | gdb_fpregset_t *fpregsetp, int regno) | |
1905 | { | |
1906 | const struct regset *regset = ppc_linux_fpregset (); | |
1907 | ||
1908 | ppc_collect_fpregset (regset, regcache, regno, | |
1909 | fpregsetp, sizeof (*fpregsetp)); | |
1910 | } | |
1911 | ||
1912 | int | |
3fe639b8 SM |
1913 | ppc_linux_nat_target::auxv_parse (const gdb_byte **readptr, |
1914 | const gdb_byte *endptr, CORE_ADDR *typep, | |
4db10d8f PFC |
1915 | CORE_ADDR *valp) |
1916 | { | |
14414227 TV |
1917 | gdb_assert (inferior_ptid != null_ptid); |
1918 | ||
4db10d8f PFC |
1919 | int tid = inferior_ptid.lwp (); |
1920 | if (tid == 0) | |
1921 | tid = inferior_ptid.pid (); | |
1922 | ||
1923 | int sizeof_auxv_field = ppc_linux_target_wordsize (tid); | |
1924 | ||
99d9c3b9 | 1925 | bfd_endian byte_order = gdbarch_byte_order (current_inferior ()->arch ()); |
3fe639b8 | 1926 | const gdb_byte *ptr = *readptr; |
4db10d8f PFC |
1927 | |
1928 | if (endptr == ptr) | |
1929 | return 0; | |
1930 | ||
1931 | if (endptr - ptr < sizeof_auxv_field * 2) | |
1932 | return -1; | |
1933 | ||
1934 | *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); | |
1935 | ptr += sizeof_auxv_field; | |
1936 | *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order); | |
1937 | ptr += sizeof_auxv_field; | |
1938 | ||
1939 | *readptr = ptr; | |
1940 | return 1; | |
1941 | } | |
1942 | ||
1943 | const struct target_desc * | |
1944 | ppc_linux_nat_target::read_description () | |
1945 | { | |
a4a688ff JB |
1946 | if (inferior_ptid == null_ptid) |
1947 | return this->beneath ()->read_description (); | |
1948 | ||
fbf3c4b9 | 1949 | int tid = inferior_ptid.pid (); |
4db10d8f PFC |
1950 | |
1951 | if (have_ptrace_getsetevrregs) | |
1952 | { | |
1953 | struct gdb_evrregset_t evrregset; | |
1954 | ||
1955 | if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0) | |
dda83cd7 | 1956 | return tdesc_powerpc_e500l; |
4db10d8f PFC |
1957 | |
1958 | /* EIO means that the PTRACE_GETEVRREGS request isn't supported. | |
1959 | Anything else needs to be reported. */ | |
1960 | else if (errno != EIO) | |
1961 | perror_with_name (_("Unable to fetch SPE registers")); | |
1962 | } | |
1963 | ||
1964 | struct ppc_linux_features features = ppc_linux_no_features; | |
1965 | ||
1966 | features.wordsize = ppc_linux_target_wordsize (tid); | |
1967 | ||
82d23ca8 SM |
1968 | CORE_ADDR hwcap = linux_get_hwcap (); |
1969 | CORE_ADDR hwcap2 = linux_get_hwcap2 (); | |
4db10d8f PFC |
1970 | |
1971 | if (have_ptrace_getsetvsxregs | |
1972 | && (hwcap & PPC_FEATURE_HAS_VSX)) | |
1973 | { | |
1974 | gdb_vsxregset_t vsxregset; | |
1975 | ||
1976 | if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0) | |
1977 | features.vsx = true; | |
1978 | ||
1979 | /* EIO means that the PTRACE_GETVSXREGS request isn't supported. | |
1980 | Anything else needs to be reported. */ | |
1981 | else if (errno != EIO) | |
1982 | perror_with_name (_("Unable to fetch VSX registers")); | |
1983 | } | |
1984 | ||
1985 | if (have_ptrace_getvrregs | |
1986 | && (hwcap & PPC_FEATURE_HAS_ALTIVEC)) | |
1987 | { | |
1988 | gdb_vrregset_t vrregset; | |
1989 | ||
1990 | if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0) | |
dda83cd7 | 1991 | features.altivec = true; |
4db10d8f PFC |
1992 | |
1993 | /* EIO means that the PTRACE_GETVRREGS request isn't supported. | |
1994 | Anything else needs to be reported. */ | |
1995 | else if (errno != EIO) | |
1996 | perror_with_name (_("Unable to fetch AltiVec registers")); | |
1997 | } | |
1998 | ||
1999 | features.isa205 = ppc_linux_has_isa205 (hwcap); | |
2000 | ||
2001 | if ((hwcap2 & PPC_FEATURE2_DSCR) | |
2002 | && check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET) | |
2003 | && check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)) | |
2004 | { | |
2005 | features.ppr_dscr = true; | |
2006 | if ((hwcap2 & PPC_FEATURE2_ARCH_2_07) | |
2007 | && (hwcap2 & PPC_FEATURE2_TAR) | |
2008 | && (hwcap2 & PPC_FEATURE2_EBB) | |
2009 | && check_regset (tid, NT_PPC_TAR, PPC_LINUX_SIZEOF_TARREGSET) | |
2010 | && check_regset (tid, NT_PPC_EBB, PPC_LINUX_SIZEOF_EBBREGSET) | |
2011 | && check_regset (tid, NT_PPC_PMU, PPC_LINUX_SIZEOF_PMUREGSET)) | |
2012 | { | |
2013 | features.isa207 = true; | |
2014 | if ((hwcap2 & PPC_FEATURE2_HTM) | |
2015 | && check_regset (tid, NT_PPC_TM_SPR, | |
2016 | PPC_LINUX_SIZEOF_TM_SPRREGSET)) | |
2017 | features.htm = true; | |
2018 | } | |
2019 | } | |
2020 | ||
2021 | return ppc_linux_match_description (features); | |
2022 | } | |
2023 | ||
227c0bf4 PFC |
2024 | /* Routines for installing hardware watchpoints and breakpoints. When |
2025 | GDB requests a hardware watchpoint or breakpoint to be installed, we | |
2026 | register the request for the pid of inferior_ptid in a map with one | |
2027 | entry per process. We then issue a stop request to all the threads of | |
2028 | this process, and mark a per-thread flag indicating that their debug | |
2029 | registers should be updated. Right before they are next resumed, we | |
2030 | remove all previously installed debug registers and install all the | |
2031 | ones GDB requested. We then update a map with one entry per thread | |
2032 | that keeps track of what debug registers were last installed in each | |
2033 | thread. | |
2034 | ||
2035 | We use this second map to remove installed registers before installing | |
2036 | the ones requested by GDB, and to copy the debug register state after | |
2037 | a thread clones or forks, since depending on the kernel configuration, | |
2038 | debug registers can be inherited. */ | |
2039 | ||
2040 | /* Check if we support and have enough resources to install a hardware | |
2041 | watchpoint or breakpoint. See the description in target.h. */ | |
e0d24f8d | 2042 | |
f6ac5f3d | 2043 | int |
227c0bf4 PFC |
2044 | ppc_linux_nat_target::can_use_hw_breakpoint (enum bptype type, int cnt, |
2045 | int ot) | |
b7622095 | 2046 | { |
6ffbb7ab | 2047 | int total_hw_wp, total_hw_bp; |
b7622095 | 2048 | |
227c0bf4 PFC |
2049 | m_dreg_interface.detect (inferior_ptid); |
2050 | ||
2051 | if (m_dreg_interface.unavailable_p ()) | |
2052 | return 0; | |
2053 | ||
2054 | if (m_dreg_interface.hwdebug_p ()) | |
6ffbb7ab | 2055 | { |
926bf92d UW |
2056 | /* When PowerPC HWDEBUG ptrace interface is available, the number of |
2057 | available hardware watchpoints and breakpoints is stored at the | |
2058 | hwdebug_info struct. */ | |
227c0bf4 PFC |
2059 | total_hw_bp = m_dreg_interface.hwdebug_info ().num_instruction_bps; |
2060 | total_hw_wp = m_dreg_interface.hwdebug_info ().num_data_bps; | |
6ffbb7ab TJB |
2061 | } |
2062 | else | |
2063 | { | |
227c0bf4 PFC |
2064 | gdb_assert (m_dreg_interface.debugreg_p ()); |
2065 | ||
2066 | /* With the DEBUGREG ptrace interface, we should consider having 1 | |
2067 | hardware watchpoint and no hardware breakpoints. */ | |
6ffbb7ab TJB |
2068 | total_hw_bp = 0; |
2069 | total_hw_wp = 1; | |
2070 | } | |
b7622095 | 2071 | |
6ffbb7ab TJB |
2072 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
2073 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
2074 | { | |
227c0bf4 PFC |
2075 | if (total_hw_wp == 0) |
2076 | return 0; | |
2077 | else if (cnt + ot > total_hw_wp) | |
6ffbb7ab | 2078 | return -1; |
227c0bf4 PFC |
2079 | else |
2080 | return 1; | |
6ffbb7ab TJB |
2081 | } |
2082 | else if (type == bp_hardware_breakpoint) | |
2083 | { | |
572f6555 | 2084 | if (total_hw_bp == 0) |
6ffbb7ab | 2085 | return 0; |
227c0bf4 PFC |
2086 | else if (cnt > total_hw_bp) |
2087 | return -1; | |
2088 | else | |
2089 | return 1; | |
6ffbb7ab TJB |
2090 | } |
2091 | ||
227c0bf4 | 2092 | return 0; |
b7622095 LM |
2093 | } |
2094 | ||
227c0bf4 PFC |
2095 | /* Returns 1 if we can watch LEN bytes at address ADDR, 0 otherwise. */ |
2096 | ||
f6ac5f3d PA |
2097 | int |
2098 | ppc_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
e0d24f8d WZ |
2099 | { |
2100 | /* Handle sub-8-byte quantities. */ | |
2101 | if (len <= 0) | |
2102 | return 0; | |
2103 | ||
227c0bf4 PFC |
2104 | m_dreg_interface.detect (inferior_ptid); |
2105 | ||
2106 | if (m_dreg_interface.unavailable_p ()) | |
2107 | return 0; | |
2108 | ||
926bf92d UW |
2109 | /* The PowerPC HWDEBUG ptrace interface tells if there are alignment |
2110 | restrictions for watchpoints in the processors. In that case, we use that | |
2111 | information to determine the hardcoded watchable region for | |
2112 | watchpoints. */ | |
227c0bf4 | 2113 | if (m_dreg_interface.hwdebug_p ()) |
6ffbb7ab | 2114 | { |
227c0bf4 PFC |
2115 | const struct ppc_debug_info &hwdebug_info = (m_dreg_interface |
2116 | .hwdebug_info ()); | |
539d71e8 RA |
2117 | int region_size = hwdebug_info.data_bp_alignment; |
2118 | int region_align = region_size; | |
227c0bf4 | 2119 | |
4feebbdd EBM |
2120 | /* Embedded DAC-based processors, like the PowerPC 440 have ranged |
2121 | watchpoints and can watch any access within an arbitrary memory | |
2122 | region. This is useful to watch arrays and structs, for instance. It | |
dda83cd7 | 2123 | takes two hardware watchpoints though. */ |
e09342b5 | 2124 | if (len > 1 |
926bf92d | 2125 | && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE |
82d23ca8 | 2126 | && (linux_get_hwcap () & PPC_FEATURE_BOOKE)) |
e09342b5 | 2127 | return 2; |
e23b9d6e UW |
2128 | /* Check if the processor provides DAWR interface. */ |
2129 | if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR) | |
539d71e8 RA |
2130 | { |
2131 | /* DAWR interface allows to watch up to 512 byte wide ranges. */ | |
2132 | region_size = 512; | |
2133 | /* DAWR interface allows to watch up to 512 byte wide ranges which | |
f4afd6cb | 2134 | can't cross a 512 byte boundary on machines that don't have a |
539d71e8 RA |
2135 | second DAWR (P9 or less). */ |
2136 | if (!(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_ARCH_31)) | |
2137 | region_align = 512; | |
2138 | } | |
4feebbdd | 2139 | /* Server processors provide one hardware watchpoint and addr+len should |
dda83cd7 | 2140 | fall in the watchable region provided by the ptrace interface. */ |
539d71e8 RA |
2141 | if (region_align |
2142 | && (addr + len > (addr & ~(region_align - 1)) + region_size)) | |
0cf6dd15 | 2143 | return 0; |
6ffbb7ab | 2144 | } |
b7622095 | 2145 | /* addr+len must fall in the 8 byte watchable region for DABR-based |
926bf92d UW |
2146 | processors (i.e., server processors). Without the new PowerPC HWDEBUG |
2147 | ptrace interface, DAC-based processors (i.e., embedded processors) will | |
2148 | use addresses aligned to 4-bytes due to the way the read/write flags are | |
6ffbb7ab | 2149 | passed in the old ptrace interface. */ |
227c0bf4 | 2150 | else |
6ffbb7ab | 2151 | { |
227c0bf4 | 2152 | gdb_assert (m_dreg_interface.debugreg_p ()); |
6ffbb7ab | 2153 | |
82d23ca8 | 2154 | if (((linux_get_hwcap () & PPC_FEATURE_BOOKE) |
227c0bf4 PFC |
2155 | && (addr + len) > (addr & ~3) + 4) |
2156 | || (addr + len) > (addr & ~7) + 8) | |
2157 | return 0; | |
5da01df5 | 2158 | } |
6ffbb7ab | 2159 | |
227c0bf4 | 2160 | return 1; |
6ffbb7ab TJB |
2161 | } |
2162 | ||
227c0bf4 PFC |
2163 | /* This function compares two ppc_hw_breakpoint structs |
2164 | field-by-field. */ | |
6ffbb7ab | 2165 | |
227c0bf4 PFC |
2166 | bool |
2167 | ppc_linux_nat_target::hwdebug_point_cmp (const struct ppc_hw_breakpoint &a, | |
2168 | const struct ppc_hw_breakpoint &b) | |
2169 | { | |
2170 | return (a.trigger_type == b.trigger_type | |
2171 | && a.addr_mode == b.addr_mode | |
2172 | && a.condition_mode == b.condition_mode | |
2173 | && a.addr == b.addr | |
2174 | && a.addr2 == b.addr2 | |
2175 | && a.condition_value == b.condition_value); | |
6ffbb7ab | 2176 | } |
9f0bdab8 | 2177 | |
f1310107 TJB |
2178 | /* Return the number of registers needed for a ranged breakpoint. */ |
2179 | ||
f6ac5f3d PA |
2180 | int |
2181 | ppc_linux_nat_target::ranged_break_num_registers () | |
f1310107 | 2182 | { |
227c0bf4 PFC |
2183 | m_dreg_interface.detect (inferior_ptid); |
2184 | ||
2185 | return ((m_dreg_interface.hwdebug_p () | |
2186 | && (m_dreg_interface.hwdebug_info ().features | |
2187 | & PPC_DEBUG_FEATURE_INSN_BP_RANGE))? | |
f1310107 TJB |
2188 | 2 : -1); |
2189 | } | |
2190 | ||
227c0bf4 PFC |
2191 | /* Register the hardware breakpoint described by BP_TGT, to be inserted |
2192 | when the threads of inferior_ptid are resumed. Returns 0 for success, | |
2193 | or -1 if the HWDEBUG interface that we need for hardware breakpoints | |
2194 | is not available. */ | |
f1310107 | 2195 | |
f6ac5f3d PA |
2196 | int |
2197 | ppc_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
2198 | struct bp_target_info *bp_tgt) | |
e0d24f8d | 2199 | { |
6ffbb7ab TJB |
2200 | struct ppc_hw_breakpoint p; |
2201 | ||
227c0bf4 PFC |
2202 | m_dreg_interface.detect (inferior_ptid); |
2203 | ||
2204 | if (!m_dreg_interface.hwdebug_p ()) | |
6ffbb7ab TJB |
2205 | return -1; |
2206 | ||
ad422571 TJB |
2207 | p.version = PPC_DEBUG_CURRENT_VERSION; |
2208 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 | 2209 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
0d5ed153 | 2210 | p.addr = (uint64_t) (bp_tgt->placed_address = bp_tgt->reqstd_address); |
6ffbb7ab TJB |
2211 | p.condition_value = 0; |
2212 | ||
f1310107 TJB |
2213 | if (bp_tgt->length) |
2214 | { | |
2215 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
2216 | ||
2217 | /* The breakpoint will trigger if the address of the instruction is | |
2218 | within the defined range, as follows: p.addr <= address < p.addr2. */ | |
2219 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
2220 | } | |
2221 | else | |
2222 | { | |
2223 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
2224 | p.addr2 = 0; | |
2225 | } | |
2226 | ||
227c0bf4 | 2227 | register_hw_breakpoint (inferior_ptid.pid (), p); |
6ffbb7ab TJB |
2228 | |
2229 | return 0; | |
2230 | } | |
2231 | ||
227c0bf4 PFC |
2232 | /* Clear a registration for the hardware breakpoint given by type BP_TGT. |
2233 | It will be removed from the threads of inferior_ptid when they are | |
2234 | next resumed. Returns 0 for success, or -1 if the HWDEBUG interface | |
2235 | that we need for hardware breakpoints is not available. */ | |
2236 | ||
f6ac5f3d PA |
2237 | int |
2238 | ppc_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
2239 | struct bp_target_info *bp_tgt) | |
6ffbb7ab | 2240 | { |
6ffbb7ab | 2241 | struct ppc_hw_breakpoint p; |
b7622095 | 2242 | |
227c0bf4 PFC |
2243 | m_dreg_interface.detect (inferior_ptid); |
2244 | ||
2245 | if (!m_dreg_interface.hwdebug_p ()) | |
6ffbb7ab TJB |
2246 | return -1; |
2247 | ||
ad422571 TJB |
2248 | p.version = PPC_DEBUG_CURRENT_VERSION; |
2249 | p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE; | |
ad422571 TJB |
2250 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; |
2251 | p.addr = (uint64_t) bp_tgt->placed_address; | |
6ffbb7ab TJB |
2252 | p.condition_value = 0; |
2253 | ||
f1310107 TJB |
2254 | if (bp_tgt->length) |
2255 | { | |
2256 | p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
2257 | ||
2258 | /* The breakpoint will trigger if the address of the instruction is within | |
2259 | the defined range, as follows: p.addr <= address < p.addr2. */ | |
2260 | p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length; | |
2261 | } | |
2262 | else | |
2263 | { | |
2264 | p.addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
2265 | p.addr2 = 0; | |
2266 | } | |
2267 | ||
227c0bf4 | 2268 | clear_hw_breakpoint (inferior_ptid.pid (), p); |
6ffbb7ab TJB |
2269 | |
2270 | return 0; | |
2271 | } | |
2272 | ||
227c0bf4 PFC |
2273 | /* Return the trigger value to set in a ppc_hw_breakpoint object for a |
2274 | given hardware watchpoint TYPE. We assume type is not hw_execute. */ | |
2275 | ||
2276 | int | |
2277 | ppc_linux_nat_target::get_trigger_type (enum target_hw_bp_type type) | |
6ffbb7ab TJB |
2278 | { |
2279 | int t; | |
2280 | ||
e76460db | 2281 | if (type == hw_read) |
6ffbb7ab | 2282 | t = PPC_BREAKPOINT_TRIGGER_READ; |
e76460db | 2283 | else if (type == hw_write) |
6ffbb7ab | 2284 | t = PPC_BREAKPOINT_TRIGGER_WRITE; |
b7622095 | 2285 | else |
6ffbb7ab TJB |
2286 | t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE; |
2287 | ||
2288 | return t; | |
2289 | } | |
2290 | ||
227c0bf4 PFC |
2291 | /* Register a new masked watchpoint at ADDR using the mask MASK, to be |
2292 | inserted when the threads of inferior_ptid are resumed. RW may be | |
2293 | hw_read for a read watchpoint, hw_write for a write watchpoint or | |
2294 | hw_access for an access watchpoint. */ | |
9c06b0b4 | 2295 | |
f6ac5f3d PA |
2296 | int |
2297 | ppc_linux_nat_target::insert_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, | |
2298 | target_hw_bp_type rw) | |
9c06b0b4 | 2299 | { |
9c06b0b4 TJB |
2300 | struct ppc_hw_breakpoint p; |
2301 | ||
227c0bf4 | 2302 | gdb_assert (m_dreg_interface.hwdebug_p ()); |
9c06b0b4 TJB |
2303 | |
2304 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
2305 | p.trigger_type = get_trigger_type (rw); | |
2306 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
2307 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2308 | p.addr = addr; | |
2309 | p.addr2 = mask; | |
2310 | p.condition_value = 0; | |
2311 | ||
227c0bf4 | 2312 | register_hw_breakpoint (inferior_ptid.pid (), p); |
9c06b0b4 TJB |
2313 | |
2314 | return 0; | |
2315 | } | |
2316 | ||
227c0bf4 PFC |
2317 | /* Clear a registration for a masked watchpoint at ADDR with the mask |
2318 | MASK. It will be removed from the threads of inferior_ptid when they | |
2319 | are next resumed. RW may be hw_read for a read watchpoint, hw_write | |
2320 | for a write watchpoint or hw_access for an access watchpoint. */ | |
9c06b0b4 | 2321 | |
f6ac5f3d PA |
2322 | int |
2323 | ppc_linux_nat_target::remove_mask_watchpoint (CORE_ADDR addr, CORE_ADDR mask, | |
2324 | target_hw_bp_type rw) | |
9c06b0b4 | 2325 | { |
9c06b0b4 TJB |
2326 | struct ppc_hw_breakpoint p; |
2327 | ||
227c0bf4 | 2328 | gdb_assert (m_dreg_interface.hwdebug_p ()); |
9c06b0b4 TJB |
2329 | |
2330 | p.version = PPC_DEBUG_CURRENT_VERSION; | |
2331 | p.trigger_type = get_trigger_type (rw); | |
2332 | p.addr_mode = PPC_BREAKPOINT_MODE_MASK; | |
2333 | p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2334 | p.addr = addr; | |
2335 | p.addr2 = mask; | |
2336 | p.condition_value = 0; | |
2337 | ||
227c0bf4 | 2338 | clear_hw_breakpoint (inferior_ptid.pid (), p); |
9c06b0b4 TJB |
2339 | |
2340 | return 0; | |
2341 | } | |
2342 | ||
227c0bf4 PFC |
2343 | /* Check whether we have at least one free DVC register for the threads |
2344 | of the pid of inferior_ptid. */ | |
2345 | ||
2346 | bool | |
2347 | ppc_linux_nat_target::can_use_watchpoint_cond_accel (void) | |
0cf6dd15 | 2348 | { |
227c0bf4 | 2349 | m_dreg_interface.detect (inferior_ptid); |
0cf6dd15 | 2350 | |
227c0bf4 PFC |
2351 | if (!m_dreg_interface.hwdebug_p ()) |
2352 | return false; | |
0cf6dd15 | 2353 | |
227c0bf4 | 2354 | int cnt = m_dreg_interface.hwdebug_info ().num_condition_regs; |
0cf6dd15 | 2355 | |
227c0bf4 PFC |
2356 | if (cnt == 0) |
2357 | return false; | |
0cf6dd15 | 2358 | |
227c0bf4 | 2359 | auto process_it = m_process_info.find (inferior_ptid.pid ()); |
0cf6dd15 | 2360 | |
227c0bf4 PFC |
2361 | /* No breakpoints or watchpoints have been requested for this process, |
2362 | we have at least one free DVC register. */ | |
2363 | if (process_it == m_process_info.end ()) | |
2364 | return true; | |
2365 | ||
2366 | for (const ppc_hw_breakpoint &bp : process_it->second.requested_hw_bps) | |
2367 | if (bp.condition_mode != PPC_BREAKPOINT_CONDITION_NONE) | |
2368 | cnt--; | |
2369 | ||
2370 | if (cnt <= 0) | |
2371 | return false; | |
2372 | ||
2373 | return true; | |
0cf6dd15 TJB |
2374 | } |
2375 | ||
2376 | /* Calculate the enable bits and the contents of the Data Value Compare | |
2377 | debug register present in BookE processors. | |
2378 | ||
2379 | ADDR is the address to be watched, LEN is the length of watched data | |
2380 | and DATA_VALUE is the value which will trigger the watchpoint. | |
2381 | On exit, CONDITION_MODE will hold the enable bits for the DVC, and | |
2382 | CONDITION_VALUE will hold the value which should be put in the | |
2383 | DVC register. */ | |
227c0bf4 PFC |
2384 | |
2385 | void | |
2386 | ppc_linux_nat_target::calculate_dvc (CORE_ADDR addr, int len, | |
2387 | CORE_ADDR data_value, | |
2388 | uint32_t *condition_mode, | |
2389 | uint64_t *condition_value) | |
0cf6dd15 | 2390 | { |
227c0bf4 PFC |
2391 | const struct ppc_debug_info &hwdebug_info = (m_dreg_interface. |
2392 | hwdebug_info ()); | |
2393 | ||
0cf6dd15 TJB |
2394 | int i, num_byte_enable, align_offset, num_bytes_off_dvc, |
2395 | rightmost_enabled_byte; | |
2396 | CORE_ADDR addr_end_data, addr_end_dvc; | |
2397 | ||
2398 | /* The DVC register compares bytes within fixed-length windows which | |
2399 | are word-aligned, with length equal to that of the DVC register. | |
2400 | We need to calculate where our watch region is relative to that | |
2401 | window and enable comparison of the bytes which fall within it. */ | |
2402 | ||
926bf92d | 2403 | align_offset = addr % hwdebug_info.sizeof_condition; |
0cf6dd15 TJB |
2404 | addr_end_data = addr + len; |
2405 | addr_end_dvc = (addr - align_offset | |
926bf92d | 2406 | + hwdebug_info.sizeof_condition); |
0cf6dd15 TJB |
2407 | num_bytes_off_dvc = (addr_end_data > addr_end_dvc)? |
2408 | addr_end_data - addr_end_dvc : 0; | |
2409 | num_byte_enable = len - num_bytes_off_dvc; | |
2410 | /* Here, bytes are numbered from right to left. */ | |
2411 | rightmost_enabled_byte = (addr_end_data < addr_end_dvc)? | |
2412 | addr_end_dvc - addr_end_data : 0; | |
2413 | ||
2414 | *condition_mode = PPC_BREAKPOINT_CONDITION_AND; | |
2415 | for (i = 0; i < num_byte_enable; i++) | |
0df8b418 MS |
2416 | *condition_mode |
2417 | |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte); | |
0cf6dd15 TJB |
2418 | |
2419 | /* Now we need to match the position within the DVC of the comparison | |
2420 | value with where the watch region is relative to the window | |
2421 | (i.e., the ALIGN_OFFSET). */ | |
2422 | ||
2423 | *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8 | |
2424 | << rightmost_enabled_byte * 8); | |
2425 | } | |
2426 | ||
2427 | /* Return the number of memory locations that need to be accessed to | |
2428 | evaluate the expression which generated the given value chain. | |
2429 | Returns -1 if there's any register access involved, or if there are | |
2430 | other kinds of values which are not acceptable in a condition | |
2431 | expression (e.g., lval_computed or lval_internalvar). */ | |
227c0bf4 PFC |
2432 | |
2433 | int | |
2434 | ppc_linux_nat_target::num_memory_accesses (const std::vector<value_ref_ptr> | |
2435 | &chain) | |
0cf6dd15 TJB |
2436 | { |
2437 | int found_memory_cnt = 0; | |
0cf6dd15 TJB |
2438 | |
2439 | /* The idea here is that evaluating an expression generates a series | |
2440 | of values, one holding the value of every subexpression. (The | |
2441 | expression a*b+c has five subexpressions: a, b, a*b, c, and | |
2442 | a*b+c.) GDB's values hold almost enough information to establish | |
2443 | the criteria given above --- they identify memory lvalues, | |
2444 | register lvalues, computed values, etcetera. So we can evaluate | |
2445 | the expression, and then scan the chain of values that leaves | |
2446 | behind to determine the memory locations involved in the evaluation | |
2447 | of an expression. | |
2448 | ||
2449 | However, I don't think that the values returned by inferior | |
2450 | function calls are special in any way. So this function may not | |
2451 | notice that an expression contains an inferior function call. | |
2452 | FIXME. */ | |
2453 | ||
a6535de1 | 2454 | for (const value_ref_ptr &iter : chain) |
0cf6dd15 | 2455 | { |
a6535de1 TT |
2456 | struct value *v = iter.get (); |
2457 | ||
0cf6dd15 | 2458 | /* Constants and values from the history are fine. */ |
b2227e67 | 2459 | if (v->lval () == not_lval || !v->deprecated_modifiable ()) |
0cf6dd15 | 2460 | continue; |
736355f2 | 2461 | else if (v->lval () == lval_memory) |
0cf6dd15 TJB |
2462 | { |
2463 | /* A lazy memory lvalue is one that GDB never needed to fetch; | |
2464 | we either just used its address (e.g., `a' in `a.b') or | |
2465 | we never needed it at all (e.g., `a' in `a,b'). */ | |
3ee3b270 | 2466 | if (!v->lazy ()) |
0cf6dd15 TJB |
2467 | found_memory_cnt++; |
2468 | } | |
0df8b418 | 2469 | /* Other kinds of values are not fine. */ |
0cf6dd15 TJB |
2470 | else |
2471 | return -1; | |
2472 | } | |
2473 | ||
2474 | return found_memory_cnt; | |
2475 | } | |
2476 | ||
2477 | /* Verifies whether the expression COND can be implemented using the | |
2478 | DVC (Data Value Compare) register in BookE processors. The expression | |
2479 | must test the watch value for equality with a constant expression. | |
2480 | If the function returns 1, DATA_VALUE will contain the constant against | |
e7db58ea TJB |
2481 | which the watch value should be compared and LEN will contain the size |
2482 | of the constant. */ | |
227c0bf4 PFC |
2483 | |
2484 | int | |
2485 | ppc_linux_nat_target::check_condition (CORE_ADDR watch_addr, | |
2486 | struct expression *cond, | |
2487 | CORE_ADDR *data_value, int *len) | |
0cf6dd15 | 2488 | { |
1eaebe02 | 2489 | int num_accesses_left, num_accesses_right; |
a6535de1 TT |
2490 | struct value *left_val, *right_val; |
2491 | std::vector<value_ref_ptr> left_chain, right_chain; | |
0cf6dd15 | 2492 | |
1eaebe02 TT |
2493 | expr::equal_operation *eqop |
2494 | = dynamic_cast<expr::equal_operation *> (cond->op.get ()); | |
2495 | if (eqop == nullptr) | |
0cf6dd15 | 2496 | return 0; |
1eaebe02 TT |
2497 | expr::operation *lhs = eqop->get_lhs (); |
2498 | expr::operation *rhs = eqop->get_rhs (); | |
0cf6dd15 | 2499 | |
1eaebe02 | 2500 | fetch_subexp_value (cond, lhs, &left_val, NULL, &left_chain, false); |
0cf6dd15 TJB |
2501 | num_accesses_left = num_memory_accesses (left_chain); |
2502 | ||
2503 | if (left_val == NULL || num_accesses_left < 0) | |
a6535de1 | 2504 | return 0; |
0cf6dd15 | 2505 | |
1eaebe02 | 2506 | fetch_subexp_value (cond, rhs, &right_val, NULL, &right_chain, false); |
0cf6dd15 TJB |
2507 | num_accesses_right = num_memory_accesses (right_chain); |
2508 | ||
2509 | if (right_val == NULL || num_accesses_right < 0) | |
a6535de1 | 2510 | return 0; |
0cf6dd15 TJB |
2511 | |
2512 | if (num_accesses_left == 1 && num_accesses_right == 0 | |
736355f2 | 2513 | && left_val->lval () == lval_memory |
9feb2d07 | 2514 | && left_val->address () == watch_addr) |
e7db58ea TJB |
2515 | { |
2516 | *data_value = value_as_long (right_val); | |
2517 | ||
2518 | /* DATA_VALUE is the constant in RIGHT_VAL, but actually has | |
2519 | the same type as the memory region referenced by LEFT_VAL. */ | |
d0c97917 | 2520 | *len = check_typedef (left_val->type ())->length (); |
e7db58ea | 2521 | } |
0cf6dd15 | 2522 | else if (num_accesses_left == 0 && num_accesses_right == 1 |
736355f2 | 2523 | && right_val->lval () == lval_memory |
9feb2d07 | 2524 | && right_val->address () == watch_addr) |
e7db58ea TJB |
2525 | { |
2526 | *data_value = value_as_long (left_val); | |
2527 | ||
2528 | /* DATA_VALUE is the constant in LEFT_VAL, but actually has | |
2529 | the same type as the memory region referenced by RIGHT_VAL. */ | |
d0c97917 | 2530 | *len = check_typedef (right_val->type ())->length (); |
e7db58ea | 2531 | } |
0cf6dd15 | 2532 | else |
a6535de1 | 2533 | return 0; |
0cf6dd15 TJB |
2534 | |
2535 | return 1; | |
2536 | } | |
2537 | ||
227c0bf4 PFC |
2538 | /* Return true if the target is capable of using hardware to evaluate the |
2539 | condition expression, thus only triggering the watchpoint when it is | |
0cf6dd15 | 2540 | true. */ |
227c0bf4 | 2541 | |
57810aa7 | 2542 | bool |
227c0bf4 PFC |
2543 | ppc_linux_nat_target::can_accel_watchpoint_condition (CORE_ADDR addr, |
2544 | int len, int rw, | |
f6ac5f3d | 2545 | struct expression *cond) |
0cf6dd15 TJB |
2546 | { |
2547 | CORE_ADDR data_value; | |
2548 | ||
227c0bf4 PFC |
2549 | m_dreg_interface.detect (inferior_ptid); |
2550 | ||
2551 | return (m_dreg_interface.hwdebug_p () | |
2552 | && (m_dreg_interface.hwdebug_info ().num_condition_regs > 0) | |
e7db58ea | 2553 | && check_condition (addr, cond, &data_value, &len)); |
0cf6dd15 TJB |
2554 | } |
2555 | ||
e09342b5 TJB |
2556 | /* Set up P with the parameters necessary to request a watchpoint covering |
2557 | LEN bytes starting at ADDR and if possible with condition expression COND | |
2558 | evaluated by hardware. INSERT tells if we are creating a request for | |
2559 | inserting or removing the watchpoint. */ | |
2560 | ||
227c0bf4 PFC |
2561 | void |
2562 | ppc_linux_nat_target::create_watchpoint_request (struct ppc_hw_breakpoint *p, | |
2563 | CORE_ADDR addr, int len, | |
2564 | enum target_hw_bp_type type, | |
2565 | struct expression *cond, | |
2566 | int insert) | |
e09342b5 | 2567 | { |
227c0bf4 PFC |
2568 | const struct ppc_debug_info &hwdebug_info = (m_dreg_interface |
2569 | .hwdebug_info ()); | |
2570 | ||
f16c4e8b | 2571 | if (len == 1 |
926bf92d | 2572 | || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE)) |
e09342b5 TJB |
2573 | { |
2574 | int use_condition; | |
2575 | CORE_ADDR data_value; | |
2576 | ||
2577 | use_condition = (insert? can_use_watchpoint_cond_accel () | |
926bf92d | 2578 | : hwdebug_info.num_condition_regs > 0); |
e7db58ea TJB |
2579 | if (cond && use_condition && check_condition (addr, cond, |
2580 | &data_value, &len)) | |
e09342b5 TJB |
2581 | calculate_dvc (addr, len, data_value, &p->condition_mode, |
2582 | &p->condition_value); | |
2583 | else | |
2584 | { | |
2585 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2586 | p->condition_value = 0; | |
2587 | } | |
2588 | ||
2589 | p->addr_mode = PPC_BREAKPOINT_MODE_EXACT; | |
2590 | p->addr2 = 0; | |
2591 | } | |
2592 | else | |
2593 | { | |
2594 | p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE; | |
2595 | p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE; | |
2596 | p->condition_value = 0; | |
2597 | ||
2598 | /* The watchpoint will trigger if the address of the memory access is | |
2599 | within the defined range, as follows: p->addr <= address < p->addr2. | |
2600 | ||
2601 | Note that the above sentence just documents how ptrace interprets | |
2602 | its arguments; the watchpoint is set to watch the range defined by | |
2603 | the user _inclusively_, as specified by the user interface. */ | |
2604 | p->addr2 = (uint64_t) addr + len; | |
2605 | } | |
2606 | ||
2607 | p->version = PPC_DEBUG_CURRENT_VERSION; | |
e76460db | 2608 | p->trigger_type = get_trigger_type (type); |
e09342b5 TJB |
2609 | p->addr = (uint64_t) addr; |
2610 | } | |
2611 | ||
227c0bf4 PFC |
2612 | /* Register a watchpoint, to be inserted when the threads of the group of |
2613 | inferior_ptid are next resumed. Returns 0 on success, and -1 if there | |
2614 | is no ptrace interface available to install the watchpoint. */ | |
2615 | ||
f6ac5f3d PA |
2616 | int |
2617 | ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
2618 | enum target_hw_bp_type type, | |
2619 | struct expression *cond) | |
6ffbb7ab | 2620 | { |
227c0bf4 PFC |
2621 | m_dreg_interface.detect (inferior_ptid); |
2622 | ||
2623 | if (m_dreg_interface.unavailable_p ()) | |
2624 | return -1; | |
6ffbb7ab | 2625 | |
227c0bf4 | 2626 | if (m_dreg_interface.hwdebug_p ()) |
e0d24f8d | 2627 | { |
6ffbb7ab TJB |
2628 | struct ppc_hw_breakpoint p; |
2629 | ||
e76460db | 2630 | create_watchpoint_request (&p, addr, len, type, cond, 1); |
6ffbb7ab | 2631 | |
227c0bf4 | 2632 | register_hw_breakpoint (inferior_ptid.pid (), p); |
e0d24f8d | 2633 | } |
6ffbb7ab TJB |
2634 | else |
2635 | { | |
227c0bf4 PFC |
2636 | gdb_assert (m_dreg_interface.debugreg_p ()); |
2637 | ||
2638 | long wp_value; | |
6ffbb7ab | 2639 | long read_mode, write_mode; |
e0d24f8d | 2640 | |
82d23ca8 | 2641 | if (linux_get_hwcap () & PPC_FEATURE_BOOKE) |
6ffbb7ab TJB |
2642 | { |
2643 | /* PowerPC 440 requires only the read/write flags to be passed | |
2644 | to the kernel. */ | |
ad422571 | 2645 | read_mode = 1; |
6ffbb7ab TJB |
2646 | write_mode = 2; |
2647 | } | |
2648 | else | |
2649 | { | |
2650 | /* PowerPC 970 and other DABR-based processors are required to pass | |
2651 | the Breakpoint Translation bit together with the flags. */ | |
ad422571 | 2652 | read_mode = 5; |
6ffbb7ab TJB |
2653 | write_mode = 6; |
2654 | } | |
1c86e440 | 2655 | |
227c0bf4 | 2656 | wp_value = addr & ~(read_mode | write_mode); |
e76460db | 2657 | switch (type) |
6ffbb7ab TJB |
2658 | { |
2659 | case hw_read: | |
2660 | /* Set read and translate bits. */ | |
227c0bf4 | 2661 | wp_value |= read_mode; |
6ffbb7ab TJB |
2662 | break; |
2663 | case hw_write: | |
2664 | /* Set write and translate bits. */ | |
227c0bf4 | 2665 | wp_value |= write_mode; |
6ffbb7ab TJB |
2666 | break; |
2667 | case hw_access: | |
2668 | /* Set read, write and translate bits. */ | |
227c0bf4 | 2669 | wp_value |= read_mode | write_mode; |
6ffbb7ab TJB |
2670 | break; |
2671 | } | |
1c86e440 | 2672 | |
227c0bf4 | 2673 | register_wp (inferior_ptid.pid (), wp_value); |
6ffbb7ab TJB |
2674 | } |
2675 | ||
227c0bf4 | 2676 | return 0; |
e0d24f8d WZ |
2677 | } |
2678 | ||
227c0bf4 PFC |
2679 | /* Clear a registration for a hardware watchpoint. It will be removed |
2680 | from the threads of the group of inferior_ptid when they are next | |
2681 | resumed. */ | |
2682 | ||
f6ac5f3d PA |
2683 | int |
2684 | ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, | |
2685 | enum target_hw_bp_type type, | |
2686 | struct expression *cond) | |
e0d24f8d | 2687 | { |
227c0bf4 | 2688 | gdb_assert (!m_dreg_interface.unavailable_p ()); |
9f0bdab8 | 2689 | |
227c0bf4 | 2690 | if (m_dreg_interface.hwdebug_p ()) |
6ffbb7ab TJB |
2691 | { |
2692 | struct ppc_hw_breakpoint p; | |
2693 | ||
e76460db | 2694 | create_watchpoint_request (&p, addr, len, type, cond, 0); |
6ffbb7ab | 2695 | |
227c0bf4 | 2696 | clear_hw_breakpoint (inferior_ptid.pid (), p); |
6ffbb7ab TJB |
2697 | } |
2698 | else | |
2699 | { | |
227c0bf4 | 2700 | gdb_assert (m_dreg_interface.debugreg_p ()); |
6ffbb7ab | 2701 | |
227c0bf4 | 2702 | clear_wp (inferior_ptid.pid ()); |
6ffbb7ab TJB |
2703 | } |
2704 | ||
227c0bf4 | 2705 | return 0; |
e0d24f8d WZ |
2706 | } |
2707 | ||
227c0bf4 PFC |
2708 | /* Clean up the per-process info associated with PID. When using the |
2709 | HWDEBUG interface, we also erase the per-thread state of installed | |
2710 | debug registers for all the threads that belong to the group of PID. | |
2711 | ||
2712 | Usually the thread state is cleaned up by low_delete_thread. We also | |
2713 | do it here because low_new_thread is not called for the initial LWP, | |
2714 | so low_delete_thread won't be able to clean up this state. */ | |
2715 | ||
135340af | 2716 | void |
227c0bf4 | 2717 | ppc_linux_nat_target::low_forget_process (pid_t pid) |
e0d24f8d | 2718 | { |
227c0bf4 PFC |
2719 | if ((!m_dreg_interface.detected_p ()) |
2720 | || (m_dreg_interface.unavailable_p ())) | |
2721 | return; | |
6ffbb7ab | 2722 | |
227c0bf4 PFC |
2723 | ptid_t pid_ptid (pid, 0, 0); |
2724 | ||
2725 | m_process_info.erase (pid); | |
2726 | ||
2727 | if (m_dreg_interface.hwdebug_p ()) | |
6ffbb7ab | 2728 | { |
227c0bf4 PFC |
2729 | for (auto it = m_installed_hw_bps.begin (); |
2730 | it != m_installed_hw_bps.end ();) | |
2731 | { | |
2732 | if (it->first.matches (pid_ptid)) | |
2733 | it = m_installed_hw_bps.erase (it); | |
2734 | else | |
2735 | it++; | |
2736 | } | |
2737 | } | |
2738 | } | |
6ffbb7ab | 2739 | |
227c0bf4 | 2740 | /* Copy the per-process state associated with the pid of PARENT to the |
3bfdcabb | 2741 | state of CHILD_PID. GDB expects that a forked process will have the |
227c0bf4 | 2742 | same hardware breakpoints and watchpoints as the parent. |
6ffbb7ab | 2743 | |
227c0bf4 PFC |
2744 | If we're using the HWDEBUG interface, also copy the thread debug |
2745 | register state for the ptid of PARENT to the state for CHILD_PID. | |
6ffbb7ab | 2746 | |
227c0bf4 PFC |
2747 | Like for clone events, we assume the kernel will copy the debug |
2748 | registers from the parent thread to the child. The | |
2749 | low_prepare_to_resume function is made to work even if it doesn't. | |
aacbb8a5 | 2750 | |
227c0bf4 PFC |
2751 | We copy the thread state here and not in low_new_thread since we don't |
2752 | have the pid of the parent in low_new_thread. Even if we did, | |
2753 | low_new_thread might not be called immediately after the fork event is | |
2754 | detected. For instance, with the checkpointing system (see | |
2755 | linux-fork.c), the thread won't be added until GDB decides to switch | |
2756 | to a new checkpointed process. At that point, the debug register | |
2757 | state of the parent thread is unlikely to correspond to the state it | |
2758 | had at the point when it forked. */ | |
aacbb8a5 | 2759 | |
227c0bf4 PFC |
2760 | void |
2761 | ppc_linux_nat_target::low_new_fork (struct lwp_info *parent, | |
2762 | pid_t child_pid) | |
2763 | { | |
2764 | if ((!m_dreg_interface.detected_p ()) | |
2765 | || (m_dreg_interface.unavailable_p ())) | |
2766 | return; | |
2767 | ||
2768 | auto process_it = m_process_info.find (parent->ptid.pid ()); | |
2769 | ||
2770 | if (process_it != m_process_info.end ()) | |
2771 | m_process_info[child_pid] = m_process_info[parent->ptid.pid ()]; | |
2772 | ||
2773 | if (m_dreg_interface.hwdebug_p ()) | |
2774 | { | |
2775 | ptid_t child_ptid (child_pid, child_pid, 0); | |
2776 | ||
2777 | copy_thread_dreg_state (parent->ptid, child_ptid); | |
6ffbb7ab | 2778 | } |
6ffbb7ab TJB |
2779 | } |
2780 | ||
227c0bf4 PFC |
2781 | /* Copy the thread debug register state from the PARENT thread to the the |
2782 | state for CHILD_LWP, if we're using the HWDEBUG interface. We assume | |
2783 | the kernel copies the debug registers from one thread to another after | |
2784 | a clone event. The low_prepare_to_resume function is made to work | |
2785 | even if it doesn't. */ | |
2786 | ||
2787 | void | |
2788 | ppc_linux_nat_target::low_new_clone (struct lwp_info *parent, | |
2789 | pid_t child_lwp) | |
6ffbb7ab | 2790 | { |
227c0bf4 PFC |
2791 | if ((!m_dreg_interface.detected_p ()) |
2792 | || (m_dreg_interface.unavailable_p ())) | |
2793 | return; | |
2794 | ||
2795 | if (m_dreg_interface.hwdebug_p ()) | |
2796 | { | |
2797 | ptid_t child_ptid (parent->ptid.pid (), child_lwp, 0); | |
2798 | ||
2799 | copy_thread_dreg_state (parent->ptid, child_ptid); | |
2800 | } | |
2801 | } | |
2802 | ||
2803 | /* Initialize the arch-specific thread state for LP so that it contains | |
2804 | the ptid for lp, so that we can use it in low_delete_thread. Mark the | |
2805 | new thread LP as stale so that we update its debug registers before | |
2806 | resuming it. This is not called for the initial thread. */ | |
2807 | ||
2808 | void | |
2809 | ppc_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
2810 | { | |
2811 | init_arch_lwp_info (lp); | |
2812 | ||
2813 | mark_thread_stale (lp); | |
2814 | } | |
2815 | ||
2816 | /* Delete the per-thread debug register stale flag. */ | |
2817 | ||
2818 | void | |
2819 | ppc_linux_nat_target::low_delete_thread (struct arch_lwp_info | |
2820 | *lp_arch_info) | |
2821 | { | |
2822 | if (lp_arch_info != NULL) | |
2823 | { | |
2824 | if (m_dreg_interface.detected_p () | |
2825 | && m_dreg_interface.hwdebug_p ()) | |
2826 | m_installed_hw_bps.erase (lp_arch_info->lwp_ptid); | |
2827 | ||
2828 | xfree (lp_arch_info); | |
2829 | } | |
2830 | } | |
2831 | ||
2832 | /* Install or delete debug registers in thread LP so that it matches what | |
2833 | GDB requested before it is resumed. */ | |
2834 | ||
2835 | void | |
2836 | ppc_linux_nat_target::low_prepare_to_resume (struct lwp_info *lp) | |
2837 | { | |
2838 | if ((!m_dreg_interface.detected_p ()) | |
2839 | || (m_dreg_interface.unavailable_p ())) | |
2840 | return; | |
2841 | ||
2842 | /* We have to re-install or clear the debug registers if we set the | |
2843 | stale flag. | |
2844 | ||
2845 | In addition, some kernels configurations can disable a hardware | |
2846 | watchpoint after it is hit. Usually, GDB will remove and re-install | |
2847 | a hardware watchpoint when the thread stops if "breakpoint | |
2848 | always-inserted" is off, or to single-step a watchpoint. But so | |
2849 | that we don't rely on this behavior, if we stop due to a hardware | |
2850 | breakpoint or watchpoint, we also refresh our debug registers. */ | |
2851 | ||
2852 | arch_lwp_info *lp_arch_info = get_arch_lwp_info (lp); | |
6ffbb7ab | 2853 | |
227c0bf4 PFC |
2854 | bool stale_dregs = (lp->stop_reason == TARGET_STOPPED_BY_WATCHPOINT |
2855 | || lp->stop_reason == TARGET_STOPPED_BY_HW_BREAKPOINT | |
2856 | || lp_arch_info->debug_regs_stale); | |
2857 | ||
2858 | if (!stale_dregs) | |
6ffbb7ab TJB |
2859 | return; |
2860 | ||
227c0bf4 PFC |
2861 | gdb_assert (lp->ptid.lwp_p ()); |
2862 | ||
2863 | auto process_it = m_process_info.find (lp->ptid.pid ()); | |
2864 | ||
2865 | if (m_dreg_interface.hwdebug_p ()) | |
5da01df5 | 2866 | { |
227c0bf4 PFC |
2867 | /* First, delete any hardware watchpoint or breakpoint installed in |
2868 | the inferior and update the thread state. */ | |
2869 | auto installed_it = m_installed_hw_bps.find (lp->ptid); | |
2870 | ||
2871 | if (installed_it != m_installed_hw_bps.end ()) | |
5da01df5 | 2872 | { |
227c0bf4 PFC |
2873 | auto &bp_list = installed_it->second; |
2874 | ||
2875 | for (auto bp_it = bp_list.begin (); bp_it != bp_list.end ();) | |
2876 | { | |
2877 | /* We ignore ENOENT to account for various possible kernel | |
2878 | behaviors, e.g. the kernel might or might not copy debug | |
2879 | registers across forks and clones, and we always copy | |
2880 | the debug register state when fork and clone events are | |
2881 | detected. */ | |
2882 | if (ptrace (PPC_PTRACE_DELHWDEBUG, lp->ptid.lwp (), 0, | |
6e562fa3 | 2883 | bp_it->first) < 0) |
227c0bf4 PFC |
2884 | if (errno != ENOENT) |
2885 | perror_with_name (_("Error deleting hardware " | |
2886 | "breakpoint or watchpoint")); | |
2887 | ||
33b5899f | 2888 | /* We erase the entries one at a time after successfully |
227c0bf4 PFC |
2889 | removing the corresponding slot form the thread so that |
2890 | if we throw an exception above in a future iteration the | |
2891 | map remains consistent. */ | |
2892 | bp_it = bp_list.erase (bp_it); | |
2893 | } | |
2894 | ||
2895 | gdb_assert (bp_list.empty ()); | |
2896 | } | |
2897 | ||
2898 | /* Now we install all the requested hardware breakpoints and | |
2899 | watchpoints and update the thread state. */ | |
2900 | ||
2901 | if (process_it != m_process_info.end ()) | |
2902 | { | |
2903 | auto &bp_list = m_installed_hw_bps[lp->ptid]; | |
2904 | ||
2905 | for (ppc_hw_breakpoint bp | |
2906 | : process_it->second.requested_hw_bps) | |
2907 | { | |
2908 | long slot = ptrace (PPC_PTRACE_SETHWDEBUG, lp->ptid.lwp (), | |
2909 | 0, &bp); | |
2910 | ||
2911 | if (slot < 0) | |
2912 | perror_with_name (_("Error setting hardware " | |
2913 | "breakpoint or watchpoint")); | |
2914 | ||
2915 | /* Keep track of which slots we installed in this | |
2916 | thread. */ | |
2917 | bp_list.emplace (bp_list.begin (), slot, bp); | |
2918 | } | |
5da01df5 TT |
2919 | } |
2920 | } | |
227c0bf4 PFC |
2921 | else |
2922 | { | |
2923 | gdb_assert (m_dreg_interface.debugreg_p ()); | |
6ffbb7ab | 2924 | |
6ea815e7 PFC |
2925 | /* Passing 0 to PTRACE_SET_DEBUGREG will clear the watchpoint. We |
2926 | always clear the watchpoint instead of just overwriting it, in | |
2927 | case there is a request for a new watchpoint, because on some | |
2928 | older kernel versions and configurations simply overwriting the | |
2929 | watchpoint after it was hit would not re-enable it. */ | |
2930 | if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, 0) < 0) | |
2931 | perror_with_name (_("Error clearing hardware watchpoint")); | |
6ffbb7ab | 2932 | |
227c0bf4 PFC |
2933 | /* GDB requested a watchpoint to be installed. */ |
2934 | if (process_it != m_process_info.end () | |
2935 | && process_it->second.requested_wp_val.has_value ()) | |
6ea815e7 PFC |
2936 | { |
2937 | long wp = *(process_it->second.requested_wp_val); | |
6ffbb7ab | 2938 | |
6ea815e7 PFC |
2939 | if (ptrace (PTRACE_SET_DEBUGREG, lp->ptid.lwp (), 0, wp) < 0) |
2940 | perror_with_name (_("Error setting hardware watchpoint")); | |
2941 | } | |
227c0bf4 | 2942 | } |
6ffbb7ab | 2943 | |
227c0bf4 | 2944 | lp_arch_info->debug_regs_stale = false; |
e0d24f8d WZ |
2945 | } |
2946 | ||
227c0bf4 PFC |
2947 | /* Return true if INFERIOR_PTID is known to have been stopped by a |
2948 | hardware watchpoint, false otherwise. If true is returned, write the | |
2949 | address that the kernel reported as causing the SIGTRAP in ADDR_P. */ | |
2950 | ||
57810aa7 | 2951 | bool |
227c0bf4 | 2952 | ppc_linux_nat_target::low_stopped_data_address (CORE_ADDR *addr_p) |
e0d24f8d | 2953 | { |
f865ee35 | 2954 | siginfo_t siginfo; |
e0d24f8d | 2955 | |
f865ee35 | 2956 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) |
57810aa7 | 2957 | return false; |
e0d24f8d | 2958 | |
f865ee35 JK |
2959 | if (siginfo.si_signo != SIGTRAP |
2960 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
57810aa7 | 2961 | return false; |
e0d24f8d | 2962 | |
227c0bf4 PFC |
2963 | gdb_assert (!m_dreg_interface.unavailable_p ()); |
2964 | ||
2965 | /* Check if this signal corresponds to a hardware breakpoint. We only | |
2966 | need to check this if we're using the HWDEBUG interface, since the | |
2967 | DEBUGREG interface only allows setting one hardware watchpoint. */ | |
2968 | if (m_dreg_interface.hwdebug_p ()) | |
6ffbb7ab | 2969 | { |
227c0bf4 PFC |
2970 | /* The index (or slot) of the *point is passed in the si_errno |
2971 | field. Currently, this is only the case if the kernel was | |
2972 | configured with CONFIG_PPC_ADV_DEBUG_REGS. If not, we assume | |
2973 | the kernel will set si_errno to a value that doesn't correspond | |
2974 | to any real slot. */ | |
f865ee35 | 2975 | int slot = siginfo.si_errno; |
6ffbb7ab | 2976 | |
227c0bf4 | 2977 | auto installed_it = m_installed_hw_bps.find (inferior_ptid); |
6ffbb7ab | 2978 | |
227c0bf4 PFC |
2979 | /* We must have installed slots for the thread if it got a |
2980 | TRAP_HWBKPT signal. */ | |
2981 | gdb_assert (installed_it != m_installed_hw_bps.end ()); | |
2982 | ||
2983 | for (const auto & slot_bp_pair : installed_it->second) | |
2984 | if (slot_bp_pair.first == slot | |
2985 | && (slot_bp_pair.second.trigger_type | |
2986 | == PPC_BREAKPOINT_TRIGGER_EXECUTE)) | |
2987 | return false; | |
6ffbb7ab TJB |
2988 | } |
2989 | ||
f865ee35 | 2990 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
57810aa7 | 2991 | return true; |
e0d24f8d WZ |
2992 | } |
2993 | ||
227c0bf4 PFC |
2994 | /* Return true if INFERIOR_PTID is known to have been stopped by a |
2995 | hardware watchpoint, false otherwise. */ | |
2996 | ||
57810aa7 | 2997 | bool |
227c0bf4 | 2998 | ppc_linux_nat_target::low_stopped_by_watchpoint () |
9f0bdab8 DJ |
2999 | { |
3000 | CORE_ADDR addr; | |
227c0bf4 | 3001 | return low_stopped_data_address (&addr); |
9f0bdab8 DJ |
3002 | } |
3003 | ||
57810aa7 | 3004 | bool |
f6ac5f3d PA |
3005 | ppc_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
3006 | CORE_ADDR start, | |
3007 | int length) | |
5009afc5 | 3008 | { |
227c0bf4 PFC |
3009 | gdb_assert (!m_dreg_interface.unavailable_p ()); |
3010 | ||
b7622095 LM |
3011 | int mask; |
3012 | ||
227c0bf4 | 3013 | if (m_dreg_interface.hwdebug_p () |
82d23ca8 | 3014 | && (linux_get_hwcap () & PPC_FEATURE_BOOKE)) |
6ffbb7ab | 3015 | return start <= addr && start + length >= addr; |
82d23ca8 | 3016 | else if (linux_get_hwcap () & PPC_FEATURE_BOOKE) |
b7622095 LM |
3017 | mask = 3; |
3018 | else | |
3019 | mask = 7; | |
3020 | ||
3021 | addr &= ~mask; | |
3022 | ||
0df8b418 | 3023 | /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */ |
b7622095 | 3024 | return start <= addr + mask && start + length - 1 >= addr; |
5009afc5 AS |
3025 | } |
3026 | ||
9c06b0b4 TJB |
3027 | /* Return the number of registers needed for a masked hardware watchpoint. */ |
3028 | ||
f6ac5f3d | 3029 | int |
227c0bf4 PFC |
3030 | ppc_linux_nat_target::masked_watch_num_registers (CORE_ADDR addr, |
3031 | CORE_ADDR mask) | |
9c06b0b4 | 3032 | { |
227c0bf4 PFC |
3033 | m_dreg_interface.detect (inferior_ptid); |
3034 | ||
3035 | if (!m_dreg_interface.hwdebug_p () | |
3036 | || (m_dreg_interface.hwdebug_info ().features | |
3037 | & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0) | |
9c06b0b4 TJB |
3038 | return -1; |
3039 | else if ((mask & 0xC0000000) != 0xC0000000) | |
3040 | { | |
3041 | warning (_("The given mask covers kernel address space " | |
3042 | "and cannot be used.\n")); | |
3043 | ||
3044 | return -2; | |
3045 | } | |
3046 | else | |
3047 | return 2; | |
3048 | } | |
3049 | ||
227c0bf4 PFC |
3050 | /* Copy the per-thread debug register state, if any, from thread |
3051 | PARENT_PTID to thread CHILD_PTID, if the debug register being used is | |
3052 | HWDEBUG. */ | |
3053 | ||
3054 | void | |
3055 | ppc_linux_nat_target::copy_thread_dreg_state (const ptid_t &parent_ptid, | |
3056 | const ptid_t &child_ptid) | |
3057 | { | |
3058 | gdb_assert (m_dreg_interface.hwdebug_p ()); | |
3059 | ||
3060 | auto installed_it = m_installed_hw_bps.find (parent_ptid); | |
3061 | ||
3062 | if (installed_it != m_installed_hw_bps.end ()) | |
3063 | m_installed_hw_bps[child_ptid] = m_installed_hw_bps[parent_ptid]; | |
3064 | } | |
3065 | ||
3066 | /* Mark the debug register stale flag for the new thread, if we have | |
3067 | already detected which debug register interface we use. */ | |
3068 | ||
3069 | void | |
3070 | ppc_linux_nat_target::mark_thread_stale (struct lwp_info *lp) | |
3071 | { | |
3072 | if ((!m_dreg_interface.detected_p ()) | |
3073 | || (m_dreg_interface.unavailable_p ())) | |
3074 | return; | |
3075 | ||
3076 | arch_lwp_info *lp_arch_info = get_arch_lwp_info (lp); | |
3077 | ||
3078 | lp_arch_info->debug_regs_stale = true; | |
3079 | } | |
3080 | ||
3081 | /* Mark all the threads of the group of PID as stale with respect to | |
3082 | debug registers and issue a stop request to each such thread that | |
3083 | isn't already stopped. */ | |
3084 | ||
3085 | void | |
3086 | ppc_linux_nat_target::mark_debug_registers_changed (pid_t pid) | |
3087 | { | |
3088 | /* We do this in two passes to make sure all threads are marked even if | |
3089 | we get an exception when stopping one of them. */ | |
3090 | ||
3091 | iterate_over_lwps (ptid_t (pid), | |
3092 | [this] (struct lwp_info *lp) -> int { | |
3093 | this->mark_thread_stale (lp); | |
3094 | return 0; | |
3095 | }); | |
3096 | ||
3097 | iterate_over_lwps (ptid_t (pid), | |
3098 | [] (struct lwp_info *lp) -> int { | |
3099 | if (!lwp_is_stopped (lp)) | |
3100 | linux_stop_lwp (lp); | |
3101 | return 0; | |
3102 | }); | |
3103 | } | |
3104 | ||
3105 | /* Register a hardware breakpoint or watchpoint BP for the pid PID, then | |
3106 | mark the stale flag for all threads of the group of PID, and issue a | |
3107 | stop request for them. The breakpoint or watchpoint will be installed | |
3108 | the next time each thread is resumed. Should only be used if the | |
3109 | debug register interface is HWDEBUG. */ | |
3110 | ||
3111 | void | |
3112 | ppc_linux_nat_target::register_hw_breakpoint (pid_t pid, | |
3113 | const struct | |
3114 | ppc_hw_breakpoint &bp) | |
3115 | { | |
3116 | gdb_assert (m_dreg_interface.hwdebug_p ()); | |
3117 | ||
3118 | m_process_info[pid].requested_hw_bps.push_back (bp); | |
3119 | ||
3120 | mark_debug_registers_changed (pid); | |
3121 | } | |
3122 | ||
3123 | /* Clear a registration for a hardware breakpoint or watchpoint BP for | |
3124 | the pid PID, then mark the stale flag for all threads of the group of | |
3125 | PID, and issue a stop request for them. The breakpoint or watchpoint | |
3126 | will be removed the next time each thread is resumed. Should only be | |
3127 | used if the debug register interface is HWDEBUG. */ | |
3128 | ||
3129 | void | |
3130 | ppc_linux_nat_target::clear_hw_breakpoint (pid_t pid, | |
3131 | const struct ppc_hw_breakpoint &bp) | |
3132 | { | |
3133 | gdb_assert (m_dreg_interface.hwdebug_p ()); | |
3134 | ||
3135 | auto process_it = m_process_info.find (pid); | |
3136 | ||
3137 | gdb_assert (process_it != m_process_info.end ()); | |
3138 | ||
3139 | auto bp_it = std::find_if (process_it->second.requested_hw_bps.begin (), | |
3140 | process_it->second.requested_hw_bps.end (), | |
3141 | [&bp, this] | |
3142 | (const struct ppc_hw_breakpoint &curr) | |
3143 | { return hwdebug_point_cmp (bp, curr); } | |
3144 | ); | |
3145 | ||
3146 | /* If GDB is removing a watchpoint, it must have been inserted. */ | |
3147 | gdb_assert (bp_it != process_it->second.requested_hw_bps.end ()); | |
3148 | ||
3149 | process_it->second.requested_hw_bps.erase (bp_it); | |
3150 | ||
3151 | mark_debug_registers_changed (pid); | |
3152 | } | |
3153 | ||
3154 | /* Register the hardware watchpoint value WP_VALUE for the pid PID, | |
3155 | then mark the stale flag for all threads of the group of PID, and | |
3156 | issue a stop request for them. The breakpoint or watchpoint will be | |
3157 | installed the next time each thread is resumed. Should only be used | |
3158 | if the debug register interface is DEBUGREG. */ | |
3159 | ||
3160 | void | |
3161 | ppc_linux_nat_target::register_wp (pid_t pid, long wp_value) | |
3162 | { | |
3163 | gdb_assert (m_dreg_interface.debugreg_p ()); | |
3164 | ||
3165 | /* Our other functions should have told GDB that we only have one | |
3166 | hardware watchpoint with this interface. */ | |
3167 | gdb_assert (!m_process_info[pid].requested_wp_val.has_value ()); | |
3168 | ||
3169 | m_process_info[pid].requested_wp_val.emplace (wp_value); | |
3170 | ||
3171 | mark_debug_registers_changed (pid); | |
3172 | } | |
3173 | ||
3174 | /* Clear the hardware watchpoint registration for the pid PID, then mark | |
3175 | the stale flag for all threads of the group of PID, and issue a stop | |
3176 | request for them. The breakpoint or watchpoint will be installed the | |
3177 | next time each thread is resumed. Should only be used if the debug | |
3178 | register interface is DEBUGREG. */ | |
3179 | ||
3180 | void | |
3181 | ppc_linux_nat_target::clear_wp (pid_t pid) | |
3182 | { | |
3183 | gdb_assert (m_dreg_interface.debugreg_p ()); | |
3184 | ||
3185 | auto process_it = m_process_info.find (pid); | |
3186 | ||
3187 | gdb_assert (process_it != m_process_info.end ()); | |
3188 | gdb_assert (process_it->second.requested_wp_val.has_value ()); | |
3189 | ||
3190 | process_it->second.requested_wp_val.reset (); | |
3191 | ||
3192 | mark_debug_registers_changed (pid); | |
3193 | } | |
3194 | ||
3195 | /* Initialize the arch-specific thread state for LWP, if it not already | |
3196 | created. */ | |
3197 | ||
3198 | void | |
3199 | ppc_linux_nat_target::init_arch_lwp_info (struct lwp_info *lp) | |
3200 | { | |
3201 | if (lwp_arch_private_info (lp) == NULL) | |
3202 | { | |
3203 | lwp_set_arch_private_info (lp, XCNEW (struct arch_lwp_info)); | |
3204 | lwp_arch_private_info (lp)->debug_regs_stale = false; | |
3205 | lwp_arch_private_info (lp)->lwp_ptid = lp->ptid; | |
3206 | } | |
3207 | } | |
3208 | ||
3209 | /* Get the arch-specific thread state for LWP, creating it if | |
3210 | necessary. */ | |
3211 | ||
3212 | arch_lwp_info * | |
3213 | ppc_linux_nat_target::get_arch_lwp_info (struct lwp_info *lp) | |
3214 | { | |
3215 | init_arch_lwp_info (lp); | |
3216 | ||
3217 | return lwp_arch_private_info (lp); | |
3218 | } | |
3219 | ||
6c265988 | 3220 | void _initialize_ppc_linux_nat (); |
10d6c8cd | 3221 | void |
6c265988 | 3222 | _initialize_ppc_linux_nat () |
10d6c8cd | 3223 | { |
f6ac5f3d | 3224 | linux_target = &the_ppc_linux_nat_target; |
310a98e1 | 3225 | |
10d6c8cd | 3226 | /* Register the target. */ |
d9f719f1 | 3227 | add_inf_child_target (linux_target); |
10d6c8cd | 3228 | } |