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Control powerpc64-ld provision of register save/restore
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9abe5450 1/* PPC GNU/Linux native support.
2555fe1a 2
ecd75fc8 3 Copyright (C) 1988-2014 Free Software Foundation, Inc.
c877c8e6
KB
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
c877c8e6
KB
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c877c8e6
KB
19
20#include "defs.h"
0e9f083f 21#include <string.h>
6ffbb7ab 22#include "observer.h"
c877c8e6
KB
23#include "frame.h"
24#include "inferior.h"
6ffbb7ab 25#include "gdbthread.h"
c877c8e6 26#include "gdbcore.h"
4e052eda 27#include "regcache.h"
383f0f5b 28#include "gdb_assert.h"
10d6c8cd
DJ
29#include "target.h"
30#include "linux-nat.h"
c877c8e6 31
411cb3f9 32#include <stdint.h>
c877c8e6 33#include <sys/types.h>
c877c8e6
KB
34#include <signal.h>
35#include <sys/user.h>
36#include <sys/ioctl.h>
2555fe1a 37#include "gdb_wait.h"
c877c8e6
KB
38#include <fcntl.h>
39#include <sys/procfs.h>
45229ea4 40#include <sys/ptrace.h>
c877c8e6 41
0df8b418 42/* Prototypes for supply_gregset etc. */
c60c0f5f 43#include "gregset.h"
16333c4f 44#include "ppc-tdep.h"
7284e1be
UW
45#include "ppc-linux-tdep.h"
46
b7622095
LM
47/* Required when using the AUXV. */
48#include "elf/common.h"
49#include "auxv.h"
50
7284e1be
UW
51/* This sometimes isn't defined. */
52#ifndef PT_ORIG_R3
53#define PT_ORIG_R3 34
54#endif
55#ifndef PT_TRAP
56#define PT_TRAP 40
57#endif
c60c0f5f 58
69abc51c
TJB
59/* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>.
60 If they aren't, we can provide them ourselves (their values are fixed
61 because they are part of the kernel ABI). They are used in the AT_HWCAP
62 entry of the AUXV. */
f4d9bade
UW
63#ifndef PPC_FEATURE_CELL
64#define PPC_FEATURE_CELL 0x00010000
65#endif
b7622095
LM
66#ifndef PPC_FEATURE_BOOKE
67#define PPC_FEATURE_BOOKE 0x00008000
68#endif
f04c6d38
TJB
69#ifndef PPC_FEATURE_HAS_DFP
70#define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */
69abc51c 71#endif
b7622095 72
9abe5450
EZ
73/* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
74 configure time check. Some older glibc's (for instance 2.2.1)
75 don't have a specific powerpc version of ptrace.h, and fall back on
76 a generic one. In such cases, sys/ptrace.h defines
77 PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
78 ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
79 PTRACE_SETVRREGS to be. This also makes a configury check pretty
80 much useless. */
81
82/* These definitions should really come from the glibc header files,
83 but Glibc doesn't know about the vrregs yet. */
84#ifndef PTRACE_GETVRREGS
85#define PTRACE_GETVRREGS 18
86#define PTRACE_SETVRREGS 19
87#endif
88
604c2f83
LM
89/* PTRACE requests for POWER7 VSX registers. */
90#ifndef PTRACE_GETVSXREGS
91#define PTRACE_GETVSXREGS 27
92#define PTRACE_SETVSXREGS 28
93#endif
01904826
JB
94
95/* Similarly for the ptrace requests for getting / setting the SPE
96 registers (ev0 -- ev31, acc, and spefscr). See the description of
97 gdb_evrregset_t for details. */
98#ifndef PTRACE_GETEVRREGS
99#define PTRACE_GETEVRREGS 20
100#define PTRACE_SETEVRREGS 21
101#endif
102
6ffbb7ab 103/* Similarly for the hardware watchpoint support. These requests are used
926bf92d 104 when the PowerPC HWDEBUG ptrace interface is not available. */
e0d24f8d
WZ
105#ifndef PTRACE_GET_DEBUGREG
106#define PTRACE_GET_DEBUGREG 25
107#endif
108#ifndef PTRACE_SET_DEBUGREG
109#define PTRACE_SET_DEBUGREG 26
110#endif
111#ifndef PTRACE_GETSIGINFO
112#define PTRACE_GETSIGINFO 0x4202
113#endif
01904826 114
926bf92d
UW
115/* These requests are used when the PowerPC HWDEBUG ptrace interface is
116 available. It exposes the debug facilities of PowerPC processors, as well
117 as additional features of BookE processors, such as ranged breakpoints and
118 watchpoints and hardware-accelerated condition evaluation. */
6ffbb7ab
TJB
119#ifndef PPC_PTRACE_GETHWDBGINFO
120
926bf92d
UW
121/* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG
122 ptrace interface is not present in ptrace.h, so we'll have to pretty much
123 include it all here so that the code at least compiles on older systems. */
6ffbb7ab
TJB
124#define PPC_PTRACE_GETHWDBGINFO 0x89
125#define PPC_PTRACE_SETHWDEBUG 0x88
126#define PPC_PTRACE_DELHWDEBUG 0x87
127
128struct ppc_debug_info
129{
0df8b418 130 uint32_t version; /* Only version 1 exists to date. */
6ffbb7ab
TJB
131 uint32_t num_instruction_bps;
132 uint32_t num_data_bps;
133 uint32_t num_condition_regs;
134 uint32_t data_bp_alignment;
0df8b418 135 uint32_t sizeof_condition; /* size of the DVC register. */
6ffbb7ab
TJB
136 uint64_t features;
137};
138
139/* Features will have bits indicating whether there is support for: */
140#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
141#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
142#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
143#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
144
145struct ppc_hw_breakpoint
146{
147 uint32_t version; /* currently, version must be 1 */
148 uint32_t trigger_type; /* only some combinations allowed */
149 uint32_t addr_mode; /* address match mode */
150 uint32_t condition_mode; /* break/watchpoint condition flags */
151 uint64_t addr; /* break/watchpoint address */
152 uint64_t addr2; /* range end or mask */
153 uint64_t condition_value; /* contents of the DVC register */
154};
155
156/* Trigger type. */
157#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
158#define PPC_BREAKPOINT_TRIGGER_READ 0x2
159#define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
160#define PPC_BREAKPOINT_TRIGGER_RW 0x6
161
162/* Address mode. */
163#define PPC_BREAKPOINT_MODE_EXACT 0x0
164#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
165#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
166#define PPC_BREAKPOINT_MODE_MASK 0x3
167
168/* Condition mode. */
169#define PPC_BREAKPOINT_CONDITION_NONE 0x0
170#define PPC_BREAKPOINT_CONDITION_AND 0x1
171#define PPC_BREAKPOINT_CONDITION_EXACT 0x1
172#define PPC_BREAKPOINT_CONDITION_OR 0x2
173#define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
174#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
175#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
176#define PPC_BREAKPOINT_CONDITION_BE(n) \
177 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
178#endif /* PPC_PTRACE_GETHWDBGINFO */
179
e23b9d6e
UW
180/* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider
181 watchpoint (up to 512 bytes). */
182#ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR
183#define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10
184#endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */
6ffbb7ab 185
1dfe79e8
SDJ
186/* Similarly for the general-purpose (gp0 -- gp31)
187 and floating-point registers (fp0 -- fp31). */
188#ifndef PTRACE_GETREGS
189#define PTRACE_GETREGS 12
190#endif
191#ifndef PTRACE_SETREGS
192#define PTRACE_SETREGS 13
193#endif
194#ifndef PTRACE_GETFPREGS
195#define PTRACE_GETFPREGS 14
196#endif
197#ifndef PTRACE_SETFPREGS
198#define PTRACE_SETFPREGS 15
199#endif
200
9abe5450
EZ
201/* This oddity is because the Linux kernel defines elf_vrregset_t as
202 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
203 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
204 the vrsave as an extra 4 bytes at the end. I opted for creating a
205 flat array of chars, so that it is easier to manipulate for gdb.
206
207 There are 32 vector registers 16 bytes longs, plus a VSCR register
208 which is only 4 bytes long, but is fetched as a 16 bytes
0df8b418 209 quantity. Up to here we have the elf_vrregset_t structure.
9abe5450
EZ
210 Appended to this there is space for the VRSAVE register: 4 bytes.
211 Even though this vrsave register is not included in the regset
212 typedef, it is handled by the ptrace requests.
213
214 Note that GNU/Linux doesn't support little endian PPC hardware,
215 therefore the offset at which the real value of the VSCR register
216 is located will be always 12 bytes.
217
218 The layout is like this (where x is the actual value of the vscr reg): */
219
220/* *INDENT-OFF* */
221/*
222 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
223 <-------> <-------><-------><->
224 VR0 VR31 VSCR VRSAVE
225*/
226/* *INDENT-ON* */
227
228#define SIZEOF_VRREGS 33*16+4
229
230typedef char gdb_vrregset_t[SIZEOF_VRREGS];
231
604c2f83
LM
232/* This is the layout of the POWER7 VSX registers and the way they overlap
233 with the existing FPR and VMX registers.
234
235 VSR doubleword 0 VSR doubleword 1
236 ----------------------------------------------------------------
237 VSR[0] | FPR[0] | |
238 ----------------------------------------------------------------
239 VSR[1] | FPR[1] | |
240 ----------------------------------------------------------------
241 | ... | |
242 | ... | |
243 ----------------------------------------------------------------
244 VSR[30] | FPR[30] | |
245 ----------------------------------------------------------------
246 VSR[31] | FPR[31] | |
247 ----------------------------------------------------------------
248 VSR[32] | VR[0] |
249 ----------------------------------------------------------------
250 VSR[33] | VR[1] |
251 ----------------------------------------------------------------
252 | ... |
253 | ... |
254 ----------------------------------------------------------------
255 VSR[62] | VR[30] |
256 ----------------------------------------------------------------
257 VSR[63] | VR[31] |
258 ----------------------------------------------------------------
259
260 VSX has 64 128bit registers. The first 32 registers overlap with
261 the FP registers (doubleword 0) and hence extend them with additional
262 64 bits (doubleword 1). The other 32 regs overlap with the VMX
263 registers. */
264#define SIZEOF_VSXREGS 32*8
265
266typedef char gdb_vsxregset_t[SIZEOF_VSXREGS];
01904826 267
b021a221 268/* On PPC processors that support the Signal Processing Extension
01904826 269 (SPE) APU, the general-purpose registers are 64 bits long.
411cb3f9
PG
270 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
271 ptrace calls only access the lower half of each register, to allow
272 them to behave the same way they do on non-SPE systems. There's a
273 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
274 read and write the top halves of all the general-purpose registers
275 at once, along with some SPE-specific registers.
01904826
JB
276
277 GDB itself continues to claim the general-purpose registers are 32
6ced10dd 278 bits long. It has unnamed raw registers that hold the upper halves
b021a221 279 of the gprs, and the full 64-bit SIMD views of the registers,
6ced10dd
JB
280 'ev0' -- 'ev31', are pseudo-registers that splice the top and
281 bottom halves together.
01904826
JB
282
283 This is the structure filled in by PTRACE_GETEVRREGS and written to
284 the inferior's registers by PTRACE_SETEVRREGS. */
285struct gdb_evrregset_t
286{
287 unsigned long evr[32];
288 unsigned long long acc;
289 unsigned long spefscr;
290};
291
604c2f83
LM
292/* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
293 PTRACE_SETVSXREGS requests, for reading and writing the VSX
294 POWER7 registers 0 through 31. Zero if we've tried one of them and
295 gotten an error. Note that VSX registers 32 through 63 overlap
296 with VR registers 0 through 31. */
297int have_ptrace_getsetvsxregs = 1;
01904826
JB
298
299/* Non-zero if our kernel may support the PTRACE_GETVRREGS and
300 PTRACE_SETVRREGS requests, for reading and writing the Altivec
301 registers. Zero if we've tried one of them and gotten an
302 error. */
9abe5450
EZ
303int have_ptrace_getvrregs = 1;
304
01904826
JB
305/* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
306 PTRACE_SETEVRREGS requests, for reading and writing the SPE
307 registers. Zero if we've tried one of them and gotten an
308 error. */
309int have_ptrace_getsetevrregs = 1;
310
1dfe79e8
SDJ
311/* Non-zero if our kernel may support the PTRACE_GETREGS and
312 PTRACE_SETREGS requests, for reading and writing the
313 general-purpose registers. Zero if we've tried one of
314 them and gotten an error. */
315int have_ptrace_getsetregs = 1;
316
317/* Non-zero if our kernel may support the PTRACE_GETFPREGS and
318 PTRACE_SETFPREGS requests, for reading and writing the
319 floating-pointers registers. Zero if we've tried one of
320 them and gotten an error. */
321int have_ptrace_getsetfpregs = 1;
322
16333c4f
EZ
323/* *INDENT-OFF* */
324/* registers layout, as presented by the ptrace interface:
325PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
326PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
327PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
328PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
0df8b418
MS
329PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
330PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
331PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
332PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
333PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
334PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
335PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
336PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
16333c4f
EZ
337PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
338/* *INDENT_ON * */
c877c8e6 339
45229ea4 340static int
e101270f 341ppc_register_u_addr (struct gdbarch *gdbarch, int regno)
c877c8e6 342{
16333c4f 343 int u_addr = -1;
e101270f 344 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
56d0d96a
AC
345 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
346 interface, and not the wordsize of the program's ABI. */
411cb3f9 347 int wordsize = sizeof (long);
16333c4f 348
0df8b418 349 /* General purpose registers occupy 1 slot each in the buffer. */
8bf659e8
JB
350 if (regno >= tdep->ppc_gp0_regnum
351 && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
26e75e5c 352 u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
16333c4f 353
49ff75ad
JB
354 /* Floating point regs: eight bytes each in both 32- and 64-bit
355 ptrace interfaces. Thus, two slots each in 32-bit interface, one
356 slot each in 64-bit interface. */
383f0f5b
JB
357 if (tdep->ppc_fp0_regnum >= 0
358 && regno >= tdep->ppc_fp0_regnum
366f009f
JB
359 && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
360 u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
16333c4f 361
0df8b418 362 /* UISA special purpose registers: 1 slot each. */
e101270f 363 if (regno == gdbarch_pc_regnum (gdbarch))
49ff75ad 364 u_addr = PT_NIP * wordsize;
dc5cfeb6 365 if (regno == tdep->ppc_lr_regnum)
49ff75ad 366 u_addr = PT_LNK * wordsize;
dc5cfeb6 367 if (regno == tdep->ppc_cr_regnum)
49ff75ad 368 u_addr = PT_CCR * wordsize;
dc5cfeb6 369 if (regno == tdep->ppc_xer_regnum)
49ff75ad 370 u_addr = PT_XER * wordsize;
dc5cfeb6 371 if (regno == tdep->ppc_ctr_regnum)
49ff75ad 372 u_addr = PT_CTR * wordsize;
f8c59253 373#ifdef PT_MQ
dc5cfeb6 374 if (regno == tdep->ppc_mq_regnum)
49ff75ad 375 u_addr = PT_MQ * wordsize;
f8c59253 376#endif
dc5cfeb6 377 if (regno == tdep->ppc_ps_regnum)
49ff75ad 378 u_addr = PT_MSR * wordsize;
7284e1be
UW
379 if (regno == PPC_ORIG_R3_REGNUM)
380 u_addr = PT_ORIG_R3 * wordsize;
381 if (regno == PPC_TRAP_REGNUM)
382 u_addr = PT_TRAP * wordsize;
383f0f5b
JB
383 if (tdep->ppc_fpscr_regnum >= 0
384 && regno == tdep->ppc_fpscr_regnum)
8f135812
AC
385 {
386 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
387 kernel headers incorrectly contained the 32-bit definition of
388 PT_FPSCR. For the 32-bit definition, floating-point
389 registers occupy two 32-bit "slots", and the FPSCR lives in
69abc51c 390 the second half of such a slot-pair (hence +1). For 64-bit,
8f135812
AC
391 the FPSCR instead occupies the full 64-bit 2-word-slot and
392 hence no adjustment is necessary. Hack around this. */
393 if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))
394 u_addr = (48 + 32) * wordsize;
69abc51c
TJB
395 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
396 slot and not just its second word. The PT_FPSCR supplied when
397 GDB is compiled as a 32-bit app doesn't reflect this. */
398 else if (wordsize == 4 && register_size (gdbarch, regno) == 8
399 && PT_FPSCR == (48 + 2*32 + 1))
400 u_addr = (48 + 2*32) * wordsize;
8f135812
AC
401 else
402 u_addr = PT_FPSCR * wordsize;
403 }
16333c4f 404 return u_addr;
c877c8e6
KB
405}
406
604c2f83
LM
407/* The Linux kernel ptrace interface for POWER7 VSX registers uses the
408 registers set mechanism, as opposed to the interface for all the
409 other registers, that stores/fetches each register individually. */
410static void
411fetch_vsx_register (struct regcache *regcache, int tid, int regno)
412{
413 int ret;
414 gdb_vsxregset_t regs;
415 struct gdbarch *gdbarch = get_regcache_arch (regcache);
416 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
417 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
418
419 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
420 if (ret < 0)
421 {
422 if (errno == EIO)
423 {
424 have_ptrace_getsetvsxregs = 0;
425 return;
426 }
427 perror_with_name (_("Unable to fetch VSX register"));
428 }
429
430 regcache_raw_supply (regcache, regno,
431 regs + (regno - tdep->ppc_vsr0_upper_regnum)
432 * vsxregsize);
433}
434
9abe5450
EZ
435/* The Linux kernel ptrace interface for AltiVec registers uses the
436 registers set mechanism, as opposed to the interface for all the
437 other registers, that stores/fetches each register individually. */
438static void
56be3814 439fetch_altivec_register (struct regcache *regcache, int tid, int regno)
9abe5450
EZ
440{
441 int ret;
442 int offset = 0;
443 gdb_vrregset_t regs;
40a6adc1
MD
444 struct gdbarch *gdbarch = get_regcache_arch (regcache);
445 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
446 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
9abe5450
EZ
447
448 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
449 if (ret < 0)
450 {
451 if (errno == EIO)
452 {
453 have_ptrace_getvrregs = 0;
454 return;
455 }
e2e0b3e5 456 perror_with_name (_("Unable to fetch AltiVec register"));
9abe5450
EZ
457 }
458
459 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
460 long on the hardware. We deal only with the lower 4 bytes of the
461 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
462 there is no need to define an offset for it. */
463 if (regno == (tdep->ppc_vrsave_regnum - 1))
40a6adc1 464 offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
9abe5450 465
56be3814 466 regcache_raw_supply (regcache, regno,
0df8b418
MS
467 regs + (regno
468 - tdep->ppc_vr0_regnum) * vrregsize + offset);
9abe5450
EZ
469}
470
01904826
JB
471/* Fetch the top 32 bits of TID's general-purpose registers and the
472 SPE-specific registers, and place the results in EVRREGSET. If we
473 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
474 zeros.
475
476 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
477 PTRACE_SETEVRREGS requests are supported is isolated here, and in
478 set_spe_registers. */
479static void
480get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
481{
482 if (have_ptrace_getsetevrregs)
483 {
484 if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)
485 return;
486 else
487 {
488 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
489 we just return zeros. */
490 if (errno == EIO)
491 have_ptrace_getsetevrregs = 0;
492 else
493 /* Anything else needs to be reported. */
e2e0b3e5 494 perror_with_name (_("Unable to fetch SPE registers"));
01904826
JB
495 }
496 }
497
498 memset (evrregset, 0, sizeof (*evrregset));
499}
500
6ced10dd
JB
501/* Supply values from TID for SPE-specific raw registers: the upper
502 halves of the GPRs, the accumulator, and the spefscr. REGNO must
503 be the number of an upper half register, acc, spefscr, or -1 to
504 supply the values of all registers. */
01904826 505static void
56be3814 506fetch_spe_register (struct regcache *regcache, int tid, int regno)
01904826 507{
40a6adc1
MD
508 struct gdbarch *gdbarch = get_regcache_arch (regcache);
509 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
01904826
JB
510 struct gdb_evrregset_t evrregs;
511
6ced10dd 512 gdb_assert (sizeof (evrregs.evr[0])
40a6adc1 513 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
6ced10dd 514 gdb_assert (sizeof (evrregs.acc)
40a6adc1 515 == register_size (gdbarch, tdep->ppc_acc_regnum));
6ced10dd 516 gdb_assert (sizeof (evrregs.spefscr)
40a6adc1 517 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
6ced10dd 518
01904826
JB
519 get_spe_registers (tid, &evrregs);
520
6ced10dd 521 if (regno == -1)
01904826 522 {
6ced10dd
JB
523 int i;
524
525 for (i = 0; i < ppc_num_gprs; i++)
56be3814 526 regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i,
6ced10dd 527 &evrregs.evr[i]);
01904826 528 }
6ced10dd
JB
529 else if (tdep->ppc_ev0_upper_regnum <= regno
530 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
56be3814 531 regcache_raw_supply (regcache, regno,
6ced10dd
JB
532 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
533
534 if (regno == -1
535 || regno == tdep->ppc_acc_regnum)
56be3814 536 regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc);
6ced10dd
JB
537
538 if (regno == -1
539 || regno == tdep->ppc_spefscr_regnum)
56be3814 540 regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum,
6ced10dd 541 &evrregs.spefscr);
01904826
JB
542}
543
45229ea4 544static void
56be3814 545fetch_register (struct regcache *regcache, int tid, int regno)
45229ea4 546{
40a6adc1
MD
547 struct gdbarch *gdbarch = get_regcache_arch (regcache);
548 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
45229ea4 549 /* This isn't really an address. But ptrace thinks of it as one. */
e101270f 550 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
4a19ea35 551 int bytes_transferred;
0df8b418 552 unsigned int offset; /* Offset of registers within the u area. */
e362b510 553 gdb_byte buf[MAX_REGISTER_SIZE];
45229ea4 554
be8626e0 555 if (altivec_register_p (gdbarch, regno))
9abe5450
EZ
556 {
557 /* If this is the first time through, or if it is not the first
558 time through, and we have comfirmed that there is kernel
559 support for such a ptrace request, then go and fetch the
560 register. */
561 if (have_ptrace_getvrregs)
562 {
56be3814 563 fetch_altivec_register (regcache, tid, regno);
9abe5450
EZ
564 return;
565 }
566 /* If we have discovered that there is no ptrace support for
567 AltiVec registers, fall through and return zeroes, because
568 regaddr will be -1 in this case. */
569 }
604c2f83
LM
570 if (vsx_register_p (gdbarch, regno))
571 {
572 if (have_ptrace_getsetvsxregs)
573 {
574 fetch_vsx_register (regcache, tid, regno);
575 return;
576 }
577 }
be8626e0 578 else if (spe_register_p (gdbarch, regno))
01904826 579 {
56be3814 580 fetch_spe_register (regcache, tid, regno);
01904826
JB
581 return;
582 }
9abe5450 583
45229ea4
EZ
584 if (regaddr == -1)
585 {
40a6adc1 586 memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
56be3814 587 regcache_raw_supply (regcache, regno, buf);
45229ea4
EZ
588 return;
589 }
590
411cb3f9 591 /* Read the raw register using sizeof(long) sized chunks. On a
56d0d96a
AC
592 32-bit platform, 64-bit floating-point registers will require two
593 transfers. */
4a19ea35 594 for (bytes_transferred = 0;
40a6adc1 595 bytes_transferred < register_size (gdbarch, regno);
411cb3f9 596 bytes_transferred += sizeof (long))
45229ea4 597 {
11fde611
JK
598 long l;
599
45229ea4 600 errno = 0;
11fde611 601 l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
411cb3f9 602 regaddr += sizeof (long);
45229ea4
EZ
603 if (errno != 0)
604 {
bc97b3ba 605 char message[128];
8c042590
PM
606 xsnprintf (message, sizeof (message), "reading register %s (#%d)",
607 gdbarch_register_name (gdbarch, regno), regno);
bc97b3ba 608 perror_with_name (message);
45229ea4 609 }
11fde611 610 memcpy (&buf[bytes_transferred], &l, sizeof (l));
45229ea4 611 }
56d0d96a 612
4a19ea35
JB
613 /* Now supply the register. Keep in mind that the regcache's idea
614 of the register's size may not be a multiple of sizeof
411cb3f9 615 (long). */
40a6adc1 616 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
4a19ea35
JB
617 {
618 /* Little-endian values are always found at the left end of the
619 bytes transferred. */
56be3814 620 regcache_raw_supply (regcache, regno, buf);
4a19ea35 621 }
40a6adc1 622 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4a19ea35
JB
623 {
624 /* Big-endian values are found at the right end of the bytes
625 transferred. */
40a6adc1 626 size_t padding = (bytes_transferred - register_size (gdbarch, regno));
56be3814 627 regcache_raw_supply (regcache, regno, buf + padding);
4a19ea35
JB
628 }
629 else
a44bddec 630 internal_error (__FILE__, __LINE__,
e2e0b3e5 631 _("fetch_register: unexpected byte order: %d"),
40a6adc1 632 gdbarch_byte_order (gdbarch));
45229ea4
EZ
633}
634
604c2f83
LM
635static void
636supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
637{
638 int i;
639 struct gdbarch *gdbarch = get_regcache_arch (regcache);
640 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
641 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
642
643 for (i = 0; i < ppc_num_vshrs; i++)
644 {
645 regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i,
646 *vsxregsetp + i * vsxregsize);
647 }
648}
649
9abe5450 650static void
56be3814 651supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp)
9abe5450
EZ
652{
653 int i;
40a6adc1
MD
654 struct gdbarch *gdbarch = get_regcache_arch (regcache);
655 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9abe5450 656 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
40a6adc1
MD
657 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
658 int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
9abe5450
EZ
659
660 for (i = 0; i < num_of_vrregs; i++)
661 {
662 /* The last 2 registers of this set are only 32 bit long, not
663 128. However an offset is necessary only for VSCR because it
664 occupies a whole vector, while VRSAVE occupies a full 4 bytes
665 slot. */
666 if (i == (num_of_vrregs - 2))
56be3814 667 regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
23a6d369 668 *vrregsetp + i * vrregsize + offset);
9abe5450 669 else
56be3814 670 regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
23a6d369 671 *vrregsetp + i * vrregsize);
9abe5450
EZ
672 }
673}
674
604c2f83
LM
675static void
676fetch_vsx_registers (struct regcache *regcache, int tid)
677{
678 int ret;
679 gdb_vsxregset_t regs;
680
681 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
682 if (ret < 0)
683 {
684 if (errno == EIO)
685 {
686 have_ptrace_getsetvsxregs = 0;
687 return;
688 }
689 perror_with_name (_("Unable to fetch VSX registers"));
690 }
691 supply_vsxregset (regcache, &regs);
692}
693
9abe5450 694static void
56be3814 695fetch_altivec_registers (struct regcache *regcache, int tid)
9abe5450
EZ
696{
697 int ret;
698 gdb_vrregset_t regs;
699
700 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
701 if (ret < 0)
702 {
703 if (errno == EIO)
704 {
705 have_ptrace_getvrregs = 0;
706 return;
707 }
e2e0b3e5 708 perror_with_name (_("Unable to fetch AltiVec registers"));
9abe5450 709 }
56be3814 710 supply_vrregset (regcache, &regs);
9abe5450
EZ
711}
712
1dfe79e8
SDJ
713/* This function actually issues the request to ptrace, telling
714 it to get all general-purpose registers and put them into the
715 specified regset.
716
717 If the ptrace request does not exist, this function returns 0
718 and properly sets the have_ptrace_* flag. If the request fails,
719 this function calls perror_with_name. Otherwise, if the request
720 succeeds, then the regcache gets filled and 1 is returned. */
721static int
722fetch_all_gp_regs (struct regcache *regcache, int tid)
723{
724 struct gdbarch *gdbarch = get_regcache_arch (regcache);
725 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
726 gdb_gregset_t gregset;
727
728 if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
729 {
730 if (errno == EIO)
731 {
732 have_ptrace_getsetregs = 0;
733 return 0;
734 }
735 perror_with_name (_("Couldn't get general-purpose registers."));
736 }
737
738 supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
739
740 return 1;
741}
742
743/* This is a wrapper for the fetch_all_gp_regs function. It is
744 responsible for verifying if this target has the ptrace request
745 that can be used to fetch all general-purpose registers at one
746 shot. If it doesn't, then we should fetch them using the
747 old-fashioned way, which is to iterate over the registers and
748 request them one by one. */
749static void
750fetch_gp_regs (struct regcache *regcache, int tid)
751{
752 struct gdbarch *gdbarch = get_regcache_arch (regcache);
753 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
754 int i;
755
756 if (have_ptrace_getsetregs)
757 if (fetch_all_gp_regs (regcache, tid))
758 return;
759
760 /* If we've hit this point, it doesn't really matter which
761 architecture we are using. We just need to read the
762 registers in the "old-fashioned way". */
763 for (i = 0; i < ppc_num_gprs; i++)
764 fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i);
765}
766
767/* This function actually issues the request to ptrace, telling
768 it to get all floating-point registers and put them into the
769 specified regset.
770
771 If the ptrace request does not exist, this function returns 0
772 and properly sets the have_ptrace_* flag. If the request fails,
773 this function calls perror_with_name. Otherwise, if the request
774 succeeds, then the regcache gets filled and 1 is returned. */
775static int
776fetch_all_fp_regs (struct regcache *regcache, int tid)
777{
778 gdb_fpregset_t fpregs;
779
780 if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
781 {
782 if (errno == EIO)
783 {
784 have_ptrace_getsetfpregs = 0;
785 return 0;
786 }
787 perror_with_name (_("Couldn't get floating-point registers."));
788 }
789
790 supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs);
791
792 return 1;
793}
794
795/* This is a wrapper for the fetch_all_fp_regs function. It is
796 responsible for verifying if this target has the ptrace request
797 that can be used to fetch all floating-point registers at one
798 shot. If it doesn't, then we should fetch them using the
799 old-fashioned way, which is to iterate over the registers and
800 request them one by one. */
801static void
802fetch_fp_regs (struct regcache *regcache, int tid)
803{
804 struct gdbarch *gdbarch = get_regcache_arch (regcache);
805 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
806 int i;
807
808 if (have_ptrace_getsetfpregs)
809 if (fetch_all_fp_regs (regcache, tid))
810 return;
811
812 /* If we've hit this point, it doesn't really matter which
813 architecture we are using. We just need to read the
814 registers in the "old-fashioned way". */
815 for (i = 0; i < ppc_num_fprs; i++)
816 fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i);
817}
818
45229ea4 819static void
56be3814 820fetch_ppc_registers (struct regcache *regcache, int tid)
45229ea4
EZ
821{
822 int i;
40a6adc1
MD
823 struct gdbarch *gdbarch = get_regcache_arch (regcache);
824 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9abe5450 825
1dfe79e8 826 fetch_gp_regs (regcache, tid);
32b99774 827 if (tdep->ppc_fp0_regnum >= 0)
1dfe79e8 828 fetch_fp_regs (regcache, tid);
40a6adc1 829 fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
32b99774 830 if (tdep->ppc_ps_regnum != -1)
56be3814 831 fetch_register (regcache, tid, tdep->ppc_ps_regnum);
32b99774 832 if (tdep->ppc_cr_regnum != -1)
56be3814 833 fetch_register (regcache, tid, tdep->ppc_cr_regnum);
32b99774 834 if (tdep->ppc_lr_regnum != -1)
56be3814 835 fetch_register (regcache, tid, tdep->ppc_lr_regnum);
32b99774 836 if (tdep->ppc_ctr_regnum != -1)
56be3814 837 fetch_register (regcache, tid, tdep->ppc_ctr_regnum);
32b99774 838 if (tdep->ppc_xer_regnum != -1)
56be3814 839 fetch_register (regcache, tid, tdep->ppc_xer_regnum);
e3f36dbd 840 if (tdep->ppc_mq_regnum != -1)
56be3814 841 fetch_register (regcache, tid, tdep->ppc_mq_regnum);
7284e1be
UW
842 if (ppc_linux_trap_reg_p (gdbarch))
843 {
844 fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM);
845 fetch_register (regcache, tid, PPC_TRAP_REGNUM);
846 }
32b99774 847 if (tdep->ppc_fpscr_regnum != -1)
56be3814 848 fetch_register (regcache, tid, tdep->ppc_fpscr_regnum);
9abe5450
EZ
849 if (have_ptrace_getvrregs)
850 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
56be3814 851 fetch_altivec_registers (regcache, tid);
604c2f83
LM
852 if (have_ptrace_getsetvsxregs)
853 if (tdep->ppc_vsr0_upper_regnum != -1)
854 fetch_vsx_registers (regcache, tid);
6ced10dd 855 if (tdep->ppc_ev0_upper_regnum >= 0)
56be3814 856 fetch_spe_register (regcache, tid, -1);
45229ea4
EZ
857}
858
859/* Fetch registers from the child process. Fetch all registers if
860 regno == -1, otherwise fetch all general registers or all floating
861 point registers depending upon the value of regno. */
10d6c8cd 862static void
28439f5e
PA
863ppc_linux_fetch_inferior_registers (struct target_ops *ops,
864 struct regcache *regcache, int regno)
45229ea4 865{
0df8b418 866 /* Overload thread id onto process id. */
dfd4cc63 867 int tid = ptid_get_lwp (inferior_ptid);
05f13b9c 868
0df8b418 869 /* No thread id, just use process id. */
05f13b9c 870 if (tid == 0)
dfd4cc63 871 tid = ptid_get_pid (inferior_ptid);
05f13b9c 872
9abe5450 873 if (regno == -1)
56be3814 874 fetch_ppc_registers (regcache, tid);
45229ea4 875 else
56be3814 876 fetch_register (regcache, tid, regno);
45229ea4
EZ
877}
878
0df8b418 879/* Store one VSX register. */
604c2f83
LM
880static void
881store_vsx_register (const struct regcache *regcache, int tid, int regno)
882{
883 int ret;
884 gdb_vsxregset_t regs;
885 struct gdbarch *gdbarch = get_regcache_arch (regcache);
886 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
887 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
888
9fe70b4f 889 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
604c2f83
LM
890 if (ret < 0)
891 {
892 if (errno == EIO)
893 {
894 have_ptrace_getsetvsxregs = 0;
895 return;
896 }
897 perror_with_name (_("Unable to fetch VSX register"));
898 }
899
900 regcache_raw_collect (regcache, regno, regs +
901 (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize);
902
903 ret = ptrace (PTRACE_SETVSXREGS, tid, 0, &regs);
904 if (ret < 0)
905 perror_with_name (_("Unable to store VSX register"));
906}
907
0df8b418 908/* Store one register. */
9abe5450 909static void
56be3814 910store_altivec_register (const struct regcache *regcache, int tid, int regno)
9abe5450
EZ
911{
912 int ret;
913 int offset = 0;
914 gdb_vrregset_t regs;
40a6adc1
MD
915 struct gdbarch *gdbarch = get_regcache_arch (regcache);
916 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
917 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
9abe5450
EZ
918
919 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
920 if (ret < 0)
921 {
922 if (errno == EIO)
923 {
924 have_ptrace_getvrregs = 0;
925 return;
926 }
e2e0b3e5 927 perror_with_name (_("Unable to fetch AltiVec register"));
9abe5450
EZ
928 }
929
930 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
931 long on the hardware. */
932 if (regno == (tdep->ppc_vrsave_regnum - 1))
40a6adc1 933 offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
9abe5450 934
56be3814 935 regcache_raw_collect (regcache, regno,
0df8b418
MS
936 regs + (regno
937 - tdep->ppc_vr0_regnum) * vrregsize + offset);
9abe5450
EZ
938
939 ret = ptrace (PTRACE_SETVRREGS, tid, 0, &regs);
940 if (ret < 0)
e2e0b3e5 941 perror_with_name (_("Unable to store AltiVec register"));
9abe5450
EZ
942}
943
01904826
JB
944/* Assuming TID referrs to an SPE process, set the top halves of TID's
945 general-purpose registers and its SPE-specific registers to the
946 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
947 nothing.
948
949 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
950 PTRACE_SETEVRREGS requests are supported is isolated here, and in
951 get_spe_registers. */
952static void
953set_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
954{
955 if (have_ptrace_getsetevrregs)
956 {
957 if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0)
958 return;
959 else
960 {
961 /* EIO means that the PTRACE_SETEVRREGS request isn't
962 supported; we fail silently, and don't try the call
963 again. */
964 if (errno == EIO)
965 have_ptrace_getsetevrregs = 0;
966 else
967 /* Anything else needs to be reported. */
e2e0b3e5 968 perror_with_name (_("Unable to set SPE registers"));
01904826
JB
969 }
970 }
971}
972
6ced10dd
JB
973/* Write GDB's value for the SPE-specific raw register REGNO to TID.
974 If REGNO is -1, write the values of all the SPE-specific
975 registers. */
01904826 976static void
56be3814 977store_spe_register (const struct regcache *regcache, int tid, int regno)
01904826 978{
40a6adc1
MD
979 struct gdbarch *gdbarch = get_regcache_arch (regcache);
980 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
01904826
JB
981 struct gdb_evrregset_t evrregs;
982
6ced10dd 983 gdb_assert (sizeof (evrregs.evr[0])
40a6adc1 984 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
6ced10dd 985 gdb_assert (sizeof (evrregs.acc)
40a6adc1 986 == register_size (gdbarch, tdep->ppc_acc_regnum));
6ced10dd 987 gdb_assert (sizeof (evrregs.spefscr)
40a6adc1 988 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
01904826 989
6ced10dd
JB
990 if (regno == -1)
991 /* Since we're going to write out every register, the code below
992 should store to every field of evrregs; if that doesn't happen,
993 make it obvious by initializing it with suspicious values. */
994 memset (&evrregs, 42, sizeof (evrregs));
995 else
996 /* We can only read and write the entire EVR register set at a
997 time, so to write just a single register, we do a
998 read-modify-write maneuver. */
999 get_spe_registers (tid, &evrregs);
1000
1001 if (regno == -1)
01904826 1002 {
6ced10dd
JB
1003 int i;
1004
1005 for (i = 0; i < ppc_num_gprs; i++)
56be3814 1006 regcache_raw_collect (regcache,
6ced10dd
JB
1007 tdep->ppc_ev0_upper_regnum + i,
1008 &evrregs.evr[i]);
01904826 1009 }
6ced10dd
JB
1010 else if (tdep->ppc_ev0_upper_regnum <= regno
1011 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
56be3814 1012 regcache_raw_collect (regcache, regno,
6ced10dd
JB
1013 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
1014
1015 if (regno == -1
1016 || regno == tdep->ppc_acc_regnum)
56be3814 1017 regcache_raw_collect (regcache,
6ced10dd
JB
1018 tdep->ppc_acc_regnum,
1019 &evrregs.acc);
1020
1021 if (regno == -1
1022 || regno == tdep->ppc_spefscr_regnum)
56be3814 1023 regcache_raw_collect (regcache,
6ced10dd
JB
1024 tdep->ppc_spefscr_regnum,
1025 &evrregs.spefscr);
01904826
JB
1026
1027 /* Write back the modified register set. */
1028 set_spe_registers (tid, &evrregs);
1029}
1030
45229ea4 1031static void
56be3814 1032store_register (const struct regcache *regcache, int tid, int regno)
45229ea4 1033{
40a6adc1
MD
1034 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1035 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
45229ea4 1036 /* This isn't really an address. But ptrace thinks of it as one. */
e101270f 1037 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
52f0bd74 1038 int i;
4a19ea35 1039 size_t bytes_to_transfer;
e362b510 1040 gdb_byte buf[MAX_REGISTER_SIZE];
45229ea4 1041
be8626e0 1042 if (altivec_register_p (gdbarch, regno))
45229ea4 1043 {
56be3814 1044 store_altivec_register (regcache, tid, regno);
45229ea4
EZ
1045 return;
1046 }
604c2f83
LM
1047 if (vsx_register_p (gdbarch, regno))
1048 {
1049 store_vsx_register (regcache, tid, regno);
1050 return;
1051 }
be8626e0 1052 else if (spe_register_p (gdbarch, regno))
01904826 1053 {
56be3814 1054 store_spe_register (regcache, tid, regno);
01904826
JB
1055 return;
1056 }
45229ea4 1057
9abe5450
EZ
1058 if (regaddr == -1)
1059 return;
1060
4a19ea35
JB
1061 /* First collect the register. Keep in mind that the regcache's
1062 idea of the register's size may not be a multiple of sizeof
411cb3f9 1063 (long). */
56d0d96a 1064 memset (buf, 0, sizeof buf);
40a6adc1
MD
1065 bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
1066 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
4a19ea35
JB
1067 {
1068 /* Little-endian values always sit at the left end of the buffer. */
56be3814 1069 regcache_raw_collect (regcache, regno, buf);
4a19ea35 1070 }
40a6adc1 1071 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
4a19ea35
JB
1072 {
1073 /* Big-endian values sit at the right end of the buffer. */
40a6adc1 1074 size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
56be3814 1075 regcache_raw_collect (regcache, regno, buf + padding);
4a19ea35
JB
1076 }
1077
411cb3f9 1078 for (i = 0; i < bytes_to_transfer; i += sizeof (long))
45229ea4 1079 {
11fde611
JK
1080 long l;
1081
1082 memcpy (&l, &buf[i], sizeof (l));
45229ea4 1083 errno = 0;
11fde611 1084 ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
411cb3f9 1085 regaddr += sizeof (long);
e3f36dbd
KB
1086
1087 if (errno == EIO
7284e1be
UW
1088 && (regno == tdep->ppc_fpscr_regnum
1089 || regno == PPC_ORIG_R3_REGNUM
1090 || regno == PPC_TRAP_REGNUM))
e3f36dbd 1091 {
7284e1be
UW
1092 /* Some older kernel versions don't allow fpscr, orig_r3
1093 or trap to be written. */
e3f36dbd
KB
1094 continue;
1095 }
1096
45229ea4
EZ
1097 if (errno != 0)
1098 {
bc97b3ba 1099 char message[128];
8c042590
PM
1100 xsnprintf (message, sizeof (message), "writing register %s (#%d)",
1101 gdbarch_register_name (gdbarch, regno), regno);
bc97b3ba 1102 perror_with_name (message);
45229ea4
EZ
1103 }
1104 }
1105}
1106
604c2f83
LM
1107static void
1108fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
1109{
1110 int i;
1111 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1112 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1113 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
1114
1115 for (i = 0; i < ppc_num_vshrs; i++)
1116 regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i,
1117 *vsxregsetp + i * vsxregsize);
1118}
1119
9abe5450 1120static void
56be3814 1121fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp)
9abe5450
EZ
1122{
1123 int i;
40a6adc1
MD
1124 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1125 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9abe5450 1126 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
40a6adc1
MD
1127 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
1128 int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
9abe5450
EZ
1129
1130 for (i = 0; i < num_of_vrregs; i++)
1131 {
1132 /* The last 2 registers of this set are only 32 bit long, not
1133 128, but only VSCR is fetched as a 16 bytes quantity. */
1134 if (i == (num_of_vrregs - 2))
56be3814 1135 regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
822c9732 1136 *vrregsetp + i * vrregsize + offset);
9abe5450 1137 else
56be3814 1138 regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
822c9732 1139 *vrregsetp + i * vrregsize);
9abe5450
EZ
1140 }
1141}
1142
604c2f83
LM
1143static void
1144store_vsx_registers (const struct regcache *regcache, int tid)
1145{
1146 int ret;
1147 gdb_vsxregset_t regs;
1148
1149 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
1150 if (ret < 0)
1151 {
1152 if (errno == EIO)
1153 {
1154 have_ptrace_getsetvsxregs = 0;
1155 return;
1156 }
1157 perror_with_name (_("Couldn't get VSX registers"));
1158 }
1159
1160 fill_vsxregset (regcache, &regs);
1161
1162 if (ptrace (PTRACE_SETVSXREGS, tid, 0, &regs) < 0)
1163 perror_with_name (_("Couldn't write VSX registers"));
1164}
1165
9abe5450 1166static void
56be3814 1167store_altivec_registers (const struct regcache *regcache, int tid)
9abe5450
EZ
1168{
1169 int ret;
1170 gdb_vrregset_t regs;
1171
0897f59b 1172 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
9abe5450
EZ
1173 if (ret < 0)
1174 {
1175 if (errno == EIO)
1176 {
1177 have_ptrace_getvrregs = 0;
1178 return;
1179 }
e2e0b3e5 1180 perror_with_name (_("Couldn't get AltiVec registers"));
9abe5450
EZ
1181 }
1182
56be3814 1183 fill_vrregset (regcache, &regs);
9abe5450 1184
0897f59b 1185 if (ptrace (PTRACE_SETVRREGS, tid, 0, &regs) < 0)
e2e0b3e5 1186 perror_with_name (_("Couldn't write AltiVec registers"));
9abe5450
EZ
1187}
1188
1dfe79e8
SDJ
1189/* This function actually issues the request to ptrace, telling
1190 it to store all general-purpose registers present in the specified
1191 regset.
1192
1193 If the ptrace request does not exist, this function returns 0
1194 and properly sets the have_ptrace_* flag. If the request fails,
1195 this function calls perror_with_name. Otherwise, if the request
1196 succeeds, then the regcache is stored and 1 is returned. */
1197static int
1198store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
1199{
1200 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1201 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1202 gdb_gregset_t gregset;
1203
1204 if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
1205 {
1206 if (errno == EIO)
1207 {
1208 have_ptrace_getsetregs = 0;
1209 return 0;
1210 }
1211 perror_with_name (_("Couldn't get general-purpose registers."));
1212 }
1213
1214 fill_gregset (regcache, &gregset, regno);
1215
1216 if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
1217 {
1218 if (errno == EIO)
1219 {
1220 have_ptrace_getsetregs = 0;
1221 return 0;
1222 }
1223 perror_with_name (_("Couldn't set general-purpose registers."));
1224 }
1225
1226 return 1;
1227}
1228
1229/* This is a wrapper for the store_all_gp_regs function. It is
1230 responsible for verifying if this target has the ptrace request
1231 that can be used to store all general-purpose registers at one
1232 shot. If it doesn't, then we should store them using the
1233 old-fashioned way, which is to iterate over the registers and
1234 store them one by one. */
45229ea4 1235static void
1dfe79e8 1236store_gp_regs (const struct regcache *regcache, int tid, int regno)
45229ea4 1237{
40a6adc1
MD
1238 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1239 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1dfe79e8
SDJ
1240 int i;
1241
1242 if (have_ptrace_getsetregs)
1243 if (store_all_gp_regs (regcache, tid, regno))
1244 return;
1245
1246 /* If we hit this point, it doesn't really matter which
1247 architecture we are using. We just need to store the
1248 registers in the "old-fashioned way". */
6ced10dd 1249 for (i = 0; i < ppc_num_gprs; i++)
56be3814 1250 store_register (regcache, tid, tdep->ppc_gp0_regnum + i);
1dfe79e8
SDJ
1251}
1252
1253/* This function actually issues the request to ptrace, telling
1254 it to store all floating-point registers present in the specified
1255 regset.
1256
1257 If the ptrace request does not exist, this function returns 0
1258 and properly sets the have_ptrace_* flag. If the request fails,
1259 this function calls perror_with_name. Otherwise, if the request
1260 succeeds, then the regcache is stored and 1 is returned. */
1261static int
1262store_all_fp_regs (const struct regcache *regcache, int tid, int regno)
1263{
1264 gdb_fpregset_t fpregs;
1265
1266 if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
1267 {
1268 if (errno == EIO)
1269 {
1270 have_ptrace_getsetfpregs = 0;
1271 return 0;
1272 }
1273 perror_with_name (_("Couldn't get floating-point registers."));
1274 }
1275
1276 fill_fpregset (regcache, &fpregs, regno);
1277
1278 if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0)
1279 {
1280 if (errno == EIO)
1281 {
1282 have_ptrace_getsetfpregs = 0;
1283 return 0;
1284 }
1285 perror_with_name (_("Couldn't set floating-point registers."));
1286 }
1287
1288 return 1;
1289}
1290
1291/* This is a wrapper for the store_all_fp_regs function. It is
1292 responsible for verifying if this target has the ptrace request
1293 that can be used to store all floating-point registers at one
1294 shot. If it doesn't, then we should store them using the
1295 old-fashioned way, which is to iterate over the registers and
1296 store them one by one. */
1297static void
1298store_fp_regs (const struct regcache *regcache, int tid, int regno)
1299{
1300 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1301 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1302 int i;
1303
1304 if (have_ptrace_getsetfpregs)
1305 if (store_all_fp_regs (regcache, tid, regno))
1306 return;
1307
1308 /* If we hit this point, it doesn't really matter which
1309 architecture we are using. We just need to store the
1310 registers in the "old-fashioned way". */
1311 for (i = 0; i < ppc_num_fprs; i++)
1312 store_register (regcache, tid, tdep->ppc_fp0_regnum + i);
1313}
1314
1315static void
1316store_ppc_registers (const struct regcache *regcache, int tid)
1317{
1318 int i;
1319 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1320 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1321
1322 store_gp_regs (regcache, tid, -1);
32b99774 1323 if (tdep->ppc_fp0_regnum >= 0)
1dfe79e8 1324 store_fp_regs (regcache, tid, -1);
40a6adc1 1325 store_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
32b99774 1326 if (tdep->ppc_ps_regnum != -1)
56be3814 1327 store_register (regcache, tid, tdep->ppc_ps_regnum);
32b99774 1328 if (tdep->ppc_cr_regnum != -1)
56be3814 1329 store_register (regcache, tid, tdep->ppc_cr_regnum);
32b99774 1330 if (tdep->ppc_lr_regnum != -1)
56be3814 1331 store_register (regcache, tid, tdep->ppc_lr_regnum);
32b99774 1332 if (tdep->ppc_ctr_regnum != -1)
56be3814 1333 store_register (regcache, tid, tdep->ppc_ctr_regnum);
32b99774 1334 if (tdep->ppc_xer_regnum != -1)
56be3814 1335 store_register (regcache, tid, tdep->ppc_xer_regnum);
e3f36dbd 1336 if (tdep->ppc_mq_regnum != -1)
56be3814 1337 store_register (regcache, tid, tdep->ppc_mq_regnum);
32b99774 1338 if (tdep->ppc_fpscr_regnum != -1)
56be3814 1339 store_register (regcache, tid, tdep->ppc_fpscr_regnum);
7284e1be
UW
1340 if (ppc_linux_trap_reg_p (gdbarch))
1341 {
1342 store_register (regcache, tid, PPC_ORIG_R3_REGNUM);
1343 store_register (regcache, tid, PPC_TRAP_REGNUM);
1344 }
9abe5450
EZ
1345 if (have_ptrace_getvrregs)
1346 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
56be3814 1347 store_altivec_registers (regcache, tid);
604c2f83
LM
1348 if (have_ptrace_getsetvsxregs)
1349 if (tdep->ppc_vsr0_upper_regnum != -1)
1350 store_vsx_registers (regcache, tid);
6ced10dd 1351 if (tdep->ppc_ev0_upper_regnum >= 0)
56be3814 1352 store_spe_register (regcache, tid, -1);
45229ea4
EZ
1353}
1354
6ffbb7ab 1355/* Fetch the AT_HWCAP entry from the aux vector. */
b261e0c5
UW
1356static unsigned long
1357ppc_linux_get_hwcap (void)
6ffbb7ab
TJB
1358{
1359 CORE_ADDR field;
1360
1361 if (target_auxv_search (&current_target, AT_HWCAP, &field))
1362 return (unsigned long) field;
1363
1364 return 0;
1365}
1366
1367/* The cached DABR value, to install in new threads.
926bf92d
UW
1368 This variable is used when the PowerPC HWDEBUG ptrace
1369 interface is not available. */
6ffbb7ab
TJB
1370static long saved_dabr_value;
1371
1372/* Global structure that will store information about the available
926bf92d
UW
1373 features provided by the PowerPC HWDEBUG ptrace interface. */
1374static struct ppc_debug_info hwdebug_info;
6ffbb7ab
TJB
1375
1376/* Global variable that holds the maximum number of slots that the
926bf92d
UW
1377 kernel will use. This is only used when PowerPC HWDEBUG ptrace interface
1378 is available. */
6ffbb7ab
TJB
1379static size_t max_slots_number = 0;
1380
1381struct hw_break_tuple
1382{
1383 long slot;
1384 struct ppc_hw_breakpoint *hw_break;
1385};
1386
1387/* This is an internal VEC created to store information about *points inserted
926bf92d
UW
1388 for each thread. This is used when PowerPC HWDEBUG ptrace interface is
1389 available. */
6ffbb7ab
TJB
1390typedef struct thread_points
1391 {
1392 /* The TID to which this *point relates. */
1393 int tid;
1394 /* Information about the *point, such as its address, type, etc.
1395
1396 Each element inside this vector corresponds to a hardware
1397 breakpoint or watchpoint in the thread represented by TID. The maximum
1398 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1399 the tuple is NULL, then the position in the vector is free. */
1400 struct hw_break_tuple *hw_breaks;
1401 } *thread_points_p;
1402DEF_VEC_P (thread_points_p);
1403
1404VEC(thread_points_p) *ppc_threads = NULL;
1405
926bf92d
UW
1406/* The version of the PowerPC HWDEBUG kernel interface that we will use, if
1407 available. */
6ffbb7ab
TJB
1408#define PPC_DEBUG_CURRENT_VERSION 1
1409
926bf92d 1410/* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */
e0d24f8d 1411static int
926bf92d 1412have_ptrace_hwdebug_interface (void)
e0d24f8d 1413{
926bf92d 1414 static int have_ptrace_hwdebug_interface = -1;
e0d24f8d 1415
926bf92d 1416 if (have_ptrace_hwdebug_interface == -1)
6ffbb7ab
TJB
1417 {
1418 int tid;
e0d24f8d 1419
dfd4cc63 1420 tid = ptid_get_lwp (inferior_ptid);
6ffbb7ab 1421 if (tid == 0)
dfd4cc63 1422 tid = ptid_get_pid (inferior_ptid);
e0d24f8d 1423
926bf92d
UW
1424 /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */
1425 if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &hwdebug_info) >= 0)
6ffbb7ab 1426 {
926bf92d 1427 /* Check whether PowerPC HWDEBUG ptrace interface is functional and
0c56f59b 1428 provides any supported feature. */
926bf92d 1429 if (hwdebug_info.features != 0)
0c56f59b 1430 {
926bf92d
UW
1431 have_ptrace_hwdebug_interface = 1;
1432 max_slots_number = hwdebug_info.num_instruction_bps
1433 + hwdebug_info.num_data_bps
1434 + hwdebug_info.num_condition_regs;
1435 return have_ptrace_hwdebug_interface;
0c56f59b 1436 }
6ffbb7ab 1437 }
926bf92d
UW
1438 /* Old school interface and no PowerPC HWDEBUG ptrace support. */
1439 have_ptrace_hwdebug_interface = 0;
1440 memset (&hwdebug_info, 0, sizeof (struct ppc_debug_info));
6ffbb7ab
TJB
1441 }
1442
926bf92d 1443 return have_ptrace_hwdebug_interface;
e0d24f8d
WZ
1444}
1445
6ffbb7ab
TJB
1446static int
1447ppc_linux_can_use_hw_breakpoint (int type, int cnt, int ot)
b7622095 1448{
6ffbb7ab 1449 int total_hw_wp, total_hw_bp;
b7622095 1450
926bf92d 1451 if (have_ptrace_hwdebug_interface ())
6ffbb7ab 1452 {
926bf92d
UW
1453 /* When PowerPC HWDEBUG ptrace interface is available, the number of
1454 available hardware watchpoints and breakpoints is stored at the
1455 hwdebug_info struct. */
1456 total_hw_bp = hwdebug_info.num_instruction_bps;
1457 total_hw_wp = hwdebug_info.num_data_bps;
6ffbb7ab
TJB
1458 }
1459 else
1460 {
926bf92d
UW
1461 /* When we do not have PowerPC HWDEBUG ptrace interface, we should
1462 consider having 1 hardware watchpoint and no hardware breakpoints. */
6ffbb7ab
TJB
1463 total_hw_bp = 0;
1464 total_hw_wp = 1;
1465 }
b7622095 1466
6ffbb7ab
TJB
1467 if (type == bp_hardware_watchpoint || type == bp_read_watchpoint
1468 || type == bp_access_watchpoint || type == bp_watchpoint)
1469 {
bb08bdbd 1470 if (cnt + ot > total_hw_wp)
6ffbb7ab
TJB
1471 return -1;
1472 }
1473 else if (type == bp_hardware_breakpoint)
1474 {
1475 if (cnt > total_hw_bp)
1476 return -1;
1477 }
1478
926bf92d 1479 if (!have_ptrace_hwdebug_interface ())
6ffbb7ab
TJB
1480 {
1481 int tid;
1482 ptid_t ptid = inferior_ptid;
1483
0df8b418
MS
1484 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1485 and whether the target has DABR. If either answer is no, the
1486 ptrace call will return -1. Fail in that case. */
dfd4cc63 1487 tid = ptid_get_lwp (ptid);
6ffbb7ab 1488 if (tid == 0)
dfd4cc63 1489 tid = ptid_get_pid (ptid);
6ffbb7ab
TJB
1490
1491 if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1)
1492 return 0;
1493 }
1494
1495 return 1;
b7622095
LM
1496}
1497
e0d24f8d
WZ
1498static int
1499ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
1500{
1501 /* Handle sub-8-byte quantities. */
1502 if (len <= 0)
1503 return 0;
1504
926bf92d
UW
1505 /* The PowerPC HWDEBUG ptrace interface tells if there are alignment
1506 restrictions for watchpoints in the processors. In that case, we use that
1507 information to determine the hardcoded watchable region for
1508 watchpoints. */
1509 if (have_ptrace_hwdebug_interface ())
6ffbb7ab 1510 {
e23b9d6e 1511 int region_size;
4feebbdd
EBM
1512 /* Embedded DAC-based processors, like the PowerPC 440 have ranged
1513 watchpoints and can watch any access within an arbitrary memory
1514 region. This is useful to watch arrays and structs, for instance. It
1515 takes two hardware watchpoints though. */
e09342b5 1516 if (len > 1
926bf92d 1517 && hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE
4feebbdd 1518 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
e09342b5 1519 return 2;
e23b9d6e
UW
1520 /* Check if the processor provides DAWR interface. */
1521 if (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_DAWR)
1522 /* DAWR interface allows to watch up to 512 byte wide ranges which
1523 can't cross a 512 byte boundary. */
1524 region_size = 512;
1525 else
1526 region_size = hwdebug_info.data_bp_alignment;
4feebbdd
EBM
1527 /* Server processors provide one hardware watchpoint and addr+len should
1528 fall in the watchable region provided by the ptrace interface. */
e23b9d6e
UW
1529 if (region_size
1530 && (addr + len > (addr & ~(region_size - 1)) + region_size))
0cf6dd15 1531 return 0;
6ffbb7ab 1532 }
b7622095 1533 /* addr+len must fall in the 8 byte watchable region for DABR-based
926bf92d
UW
1534 processors (i.e., server processors). Without the new PowerPC HWDEBUG
1535 ptrace interface, DAC-based processors (i.e., embedded processors) will
1536 use addresses aligned to 4-bytes due to the way the read/write flags are
6ffbb7ab
TJB
1537 passed in the old ptrace interface. */
1538 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1539 && (addr + len) > (addr & ~3) + 4)
1540 || (addr + len) > (addr & ~7) + 8)
e0d24f8d
WZ
1541 return 0;
1542
1543 return 1;
1544}
1545
6ffbb7ab 1546/* This function compares two ppc_hw_breakpoint structs field-by-field. */
e4166a49 1547static int
926bf92d 1548hwdebug_point_cmp (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b)
6ffbb7ab 1549{
ad422571
TJB
1550 return (a->trigger_type == b->trigger_type
1551 && a->addr_mode == b->addr_mode
1552 && a->condition_mode == b->condition_mode
1553 && a->addr == b->addr
1554 && a->addr2 == b->addr2
6ffbb7ab
TJB
1555 && a->condition_value == b->condition_value);
1556}
1557
1558/* This function can be used to retrieve a thread_points by the TID of the
1559 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1560 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1561 provided TID will be created and returned. */
1562static struct thread_points *
926bf92d 1563hwdebug_find_thread_points_by_tid (int tid, int alloc_new)
6ffbb7ab
TJB
1564{
1565 int i;
1566 struct thread_points *t;
1567
1568 for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++)
1569 if (t->tid == tid)
1570 return t;
1571
1572 t = NULL;
1573
1574 /* Do we need to allocate a new point_item
1575 if the wanted one does not exist? */
1576 if (alloc_new)
1577 {
1578 t = xmalloc (sizeof (struct thread_points));
0df8b418
MS
1579 t->hw_breaks
1580 = xzalloc (max_slots_number * sizeof (struct hw_break_tuple));
6ffbb7ab
TJB
1581 t->tid = tid;
1582 VEC_safe_push (thread_points_p, ppc_threads, t);
1583 }
1584
1585 return t;
1586}
1587
1588/* This function is a generic wrapper that is responsible for inserting a
1589 *point (i.e., calling `ptrace' in order to issue the request to the
1590 kernel) and registering it internally in GDB. */
1591static void
926bf92d 1592hwdebug_insert_point (struct ppc_hw_breakpoint *b, int tid)
6ffbb7ab
TJB
1593{
1594 int i;
1595 long slot;
1596 struct ppc_hw_breakpoint *p = xmalloc (sizeof (struct ppc_hw_breakpoint));
1597 struct hw_break_tuple *hw_breaks;
1598 struct cleanup *c = make_cleanup (xfree, p);
1599 struct thread_points *t;
1600 struct hw_break_tuple *tuple;
1601
1602 memcpy (p, b, sizeof (struct ppc_hw_breakpoint));
1603
1604 errno = 0;
1605 slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p);
1606 if (slot < 0)
1607 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1608
1609 /* Everything went fine, so we have to register this *point. */
926bf92d 1610 t = hwdebug_find_thread_points_by_tid (tid, 1);
6ffbb7ab
TJB
1611 gdb_assert (t != NULL);
1612 hw_breaks = t->hw_breaks;
1613
1614 /* Find a free element in the hw_breaks vector. */
1615 for (i = 0; i < max_slots_number; i++)
1616 if (hw_breaks[i].hw_break == NULL)
1617 {
1618 hw_breaks[i].slot = slot;
1619 hw_breaks[i].hw_break = p;
1620 break;
1621 }
1622
1623 gdb_assert (i != max_slots_number);
1624
1625 discard_cleanups (c);
1626}
1627
1628/* This function is a generic wrapper that is responsible for removing a
1629 *point (i.e., calling `ptrace' in order to issue the request to the
1630 kernel), and unregistering it internally at GDB. */
1631static void
926bf92d 1632hwdebug_remove_point (struct ppc_hw_breakpoint *b, int tid)
6ffbb7ab
TJB
1633{
1634 int i;
1635 struct hw_break_tuple *hw_breaks;
1636 struct thread_points *t;
1637
926bf92d 1638 t = hwdebug_find_thread_points_by_tid (tid, 0);
6ffbb7ab
TJB
1639 gdb_assert (t != NULL);
1640 hw_breaks = t->hw_breaks;
1641
1642 for (i = 0; i < max_slots_number; i++)
926bf92d 1643 if (hw_breaks[i].hw_break && hwdebug_point_cmp (hw_breaks[i].hw_break, b))
6ffbb7ab
TJB
1644 break;
1645
1646 gdb_assert (i != max_slots_number);
1647
1648 /* We have to ignore ENOENT errors because the kernel implements hardware
1649 breakpoints/watchpoints as "one-shot", that is, they are automatically
1650 deleted when hit. */
1651 errno = 0;
1652 if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0)
1653 if (errno != ENOENT)
0df8b418
MS
1654 perror_with_name (_("Unexpected error deleting "
1655 "breakpoint or watchpoint"));
6ffbb7ab
TJB
1656
1657 xfree (hw_breaks[i].hw_break);
1658 hw_breaks[i].hw_break = NULL;
1659}
9f0bdab8 1660
f1310107
TJB
1661/* Return the number of registers needed for a ranged breakpoint. */
1662
1663static int
1664ppc_linux_ranged_break_num_registers (struct target_ops *target)
1665{
926bf92d
UW
1666 return ((have_ptrace_hwdebug_interface ()
1667 && hwdebug_info.features & PPC_DEBUG_FEATURE_INSN_BP_RANGE)?
f1310107
TJB
1668 2 : -1);
1669}
1670
1671/* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
1672 success, 1 if hardware breakpoints are not supported or -1 for failure. */
1673
2c387241 1674static int
6ffbb7ab
TJB
1675ppc_linux_insert_hw_breakpoint (struct gdbarch *gdbarch,
1676 struct bp_target_info *bp_tgt)
e0d24f8d 1677{
9f0bdab8 1678 struct lwp_info *lp;
6ffbb7ab
TJB
1679 struct ppc_hw_breakpoint p;
1680
926bf92d 1681 if (!have_ptrace_hwdebug_interface ())
6ffbb7ab
TJB
1682 return -1;
1683
ad422571
TJB
1684 p.version = PPC_DEBUG_CURRENT_VERSION;
1685 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
ad422571
TJB
1686 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1687 p.addr = (uint64_t) bp_tgt->placed_address;
6ffbb7ab
TJB
1688 p.condition_value = 0;
1689
f1310107
TJB
1690 if (bp_tgt->length)
1691 {
1692 p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
1693
1694 /* The breakpoint will trigger if the address of the instruction is
1695 within the defined range, as follows: p.addr <= address < p.addr2. */
1696 p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
1697 }
1698 else
1699 {
1700 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1701 p.addr2 = 0;
1702 }
1703
4c38200f 1704 ALL_LWPS (lp)
dfd4cc63 1705 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
6ffbb7ab
TJB
1706
1707 return 0;
1708}
1709
1710static int
1711ppc_linux_remove_hw_breakpoint (struct gdbarch *gdbarch,
1712 struct bp_target_info *bp_tgt)
1713{
6ffbb7ab
TJB
1714 struct lwp_info *lp;
1715 struct ppc_hw_breakpoint p;
b7622095 1716
926bf92d 1717 if (!have_ptrace_hwdebug_interface ())
6ffbb7ab
TJB
1718 return -1;
1719
ad422571
TJB
1720 p.version = PPC_DEBUG_CURRENT_VERSION;
1721 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
ad422571
TJB
1722 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1723 p.addr = (uint64_t) bp_tgt->placed_address;
6ffbb7ab
TJB
1724 p.condition_value = 0;
1725
f1310107
TJB
1726 if (bp_tgt->length)
1727 {
1728 p.addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
1729
1730 /* The breakpoint will trigger if the address of the instruction is within
1731 the defined range, as follows: p.addr <= address < p.addr2. */
1732 p.addr2 = (uint64_t) bp_tgt->placed_address + bp_tgt->length;
1733 }
1734 else
1735 {
1736 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1737 p.addr2 = 0;
1738 }
1739
4c38200f 1740 ALL_LWPS (lp)
dfd4cc63 1741 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
6ffbb7ab
TJB
1742
1743 return 0;
1744}
1745
1746static int
1747get_trigger_type (int rw)
1748{
1749 int t;
1750
1751 if (rw == hw_read)
1752 t = PPC_BREAKPOINT_TRIGGER_READ;
1753 else if (rw == hw_write)
1754 t = PPC_BREAKPOINT_TRIGGER_WRITE;
b7622095 1755 else
6ffbb7ab
TJB
1756 t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE;
1757
1758 return t;
1759}
1760
9c06b0b4
TJB
1761/* Insert a new masked watchpoint at ADDR using the mask MASK.
1762 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1763 or hw_access for an access watchpoint. Returns 0 on success and throws
1764 an error on failure. */
1765
1766static int
1767ppc_linux_insert_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr,
1768 CORE_ADDR mask, int rw)
1769{
9c06b0b4
TJB
1770 struct lwp_info *lp;
1771 struct ppc_hw_breakpoint p;
1772
926bf92d 1773 gdb_assert (have_ptrace_hwdebug_interface ());
9c06b0b4
TJB
1774
1775 p.version = PPC_DEBUG_CURRENT_VERSION;
1776 p.trigger_type = get_trigger_type (rw);
1777 p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
1778 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1779 p.addr = addr;
1780 p.addr2 = mask;
1781 p.condition_value = 0;
1782
4c38200f 1783 ALL_LWPS (lp)
dfd4cc63 1784 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
9c06b0b4
TJB
1785
1786 return 0;
1787}
1788
1789/* Remove a masked watchpoint at ADDR with the mask MASK.
1790 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1791 or hw_access for an access watchpoint. Returns 0 on success and throws
1792 an error on failure. */
1793
1794static int
1795ppc_linux_remove_mask_watchpoint (struct target_ops *ops, CORE_ADDR addr,
1796 CORE_ADDR mask, int rw)
1797{
9c06b0b4
TJB
1798 struct lwp_info *lp;
1799 struct ppc_hw_breakpoint p;
1800
926bf92d 1801 gdb_assert (have_ptrace_hwdebug_interface ());
9c06b0b4
TJB
1802
1803 p.version = PPC_DEBUG_CURRENT_VERSION;
1804 p.trigger_type = get_trigger_type (rw);
1805 p.addr_mode = PPC_BREAKPOINT_MODE_MASK;
1806 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1807 p.addr = addr;
1808 p.addr2 = mask;
1809 p.condition_value = 0;
1810
4c38200f 1811 ALL_LWPS (lp)
dfd4cc63 1812 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
9c06b0b4
TJB
1813
1814 return 0;
1815}
1816
0cf6dd15
TJB
1817/* Check whether we have at least one free DVC register. */
1818static int
1819can_use_watchpoint_cond_accel (void)
1820{
1821 struct thread_points *p;
dfd4cc63 1822 int tid = ptid_get_lwp (inferior_ptid);
926bf92d 1823 int cnt = hwdebug_info.num_condition_regs, i;
0cf6dd15
TJB
1824 CORE_ADDR tmp_value;
1825
926bf92d 1826 if (!have_ptrace_hwdebug_interface () || cnt == 0)
0cf6dd15
TJB
1827 return 0;
1828
926bf92d 1829 p = hwdebug_find_thread_points_by_tid (tid, 0);
0cf6dd15
TJB
1830
1831 if (p)
1832 {
1833 for (i = 0; i < max_slots_number; i++)
1834 if (p->hw_breaks[i].hw_break != NULL
1835 && (p->hw_breaks[i].hw_break->condition_mode
1836 != PPC_BREAKPOINT_CONDITION_NONE))
1837 cnt--;
1838
1839 /* There are no available slots now. */
1840 if (cnt <= 0)
1841 return 0;
1842 }
1843
1844 return 1;
1845}
1846
1847/* Calculate the enable bits and the contents of the Data Value Compare
1848 debug register present in BookE processors.
1849
1850 ADDR is the address to be watched, LEN is the length of watched data
1851 and DATA_VALUE is the value which will trigger the watchpoint.
1852 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1853 CONDITION_VALUE will hold the value which should be put in the
1854 DVC register. */
1855static void
1856calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value,
1857 uint32_t *condition_mode, uint64_t *condition_value)
1858{
1859 int i, num_byte_enable, align_offset, num_bytes_off_dvc,
1860 rightmost_enabled_byte;
1861 CORE_ADDR addr_end_data, addr_end_dvc;
1862
1863 /* The DVC register compares bytes within fixed-length windows which
1864 are word-aligned, with length equal to that of the DVC register.
1865 We need to calculate where our watch region is relative to that
1866 window and enable comparison of the bytes which fall within it. */
1867
926bf92d 1868 align_offset = addr % hwdebug_info.sizeof_condition;
0cf6dd15
TJB
1869 addr_end_data = addr + len;
1870 addr_end_dvc = (addr - align_offset
926bf92d 1871 + hwdebug_info.sizeof_condition);
0cf6dd15
TJB
1872 num_bytes_off_dvc = (addr_end_data > addr_end_dvc)?
1873 addr_end_data - addr_end_dvc : 0;
1874 num_byte_enable = len - num_bytes_off_dvc;
1875 /* Here, bytes are numbered from right to left. */
1876 rightmost_enabled_byte = (addr_end_data < addr_end_dvc)?
1877 addr_end_dvc - addr_end_data : 0;
1878
1879 *condition_mode = PPC_BREAKPOINT_CONDITION_AND;
1880 for (i = 0; i < num_byte_enable; i++)
0df8b418
MS
1881 *condition_mode
1882 |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte);
0cf6dd15
TJB
1883
1884 /* Now we need to match the position within the DVC of the comparison
1885 value with where the watch region is relative to the window
1886 (i.e., the ALIGN_OFFSET). */
1887
1888 *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8
1889 << rightmost_enabled_byte * 8);
1890}
1891
1892/* Return the number of memory locations that need to be accessed to
1893 evaluate the expression which generated the given value chain.
1894 Returns -1 if there's any register access involved, or if there are
1895 other kinds of values which are not acceptable in a condition
1896 expression (e.g., lval_computed or lval_internalvar). */
1897static int
1898num_memory_accesses (struct value *v)
1899{
1900 int found_memory_cnt = 0;
1901 struct value *head = v;
1902
1903 /* The idea here is that evaluating an expression generates a series
1904 of values, one holding the value of every subexpression. (The
1905 expression a*b+c has five subexpressions: a, b, a*b, c, and
1906 a*b+c.) GDB's values hold almost enough information to establish
1907 the criteria given above --- they identify memory lvalues,
1908 register lvalues, computed values, etcetera. So we can evaluate
1909 the expression, and then scan the chain of values that leaves
1910 behind to determine the memory locations involved in the evaluation
1911 of an expression.
1912
1913 However, I don't think that the values returned by inferior
1914 function calls are special in any way. So this function may not
1915 notice that an expression contains an inferior function call.
1916 FIXME. */
1917
1918 for (; v; v = value_next (v))
1919 {
1920 /* Constants and values from the history are fine. */
1921 if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0)
1922 continue;
1923 else if (VALUE_LVAL (v) == lval_memory)
1924 {
1925 /* A lazy memory lvalue is one that GDB never needed to fetch;
1926 we either just used its address (e.g., `a' in `a.b') or
1927 we never needed it at all (e.g., `a' in `a,b'). */
1928 if (!value_lazy (v))
1929 found_memory_cnt++;
1930 }
0df8b418 1931 /* Other kinds of values are not fine. */
0cf6dd15
TJB
1932 else
1933 return -1;
1934 }
1935
1936 return found_memory_cnt;
1937}
1938
1939/* Verifies whether the expression COND can be implemented using the
1940 DVC (Data Value Compare) register in BookE processors. The expression
1941 must test the watch value for equality with a constant expression.
1942 If the function returns 1, DATA_VALUE will contain the constant against
e7db58ea
TJB
1943 which the watch value should be compared and LEN will contain the size
1944 of the constant. */
0cf6dd15
TJB
1945static int
1946check_condition (CORE_ADDR watch_addr, struct expression *cond,
e7db58ea 1947 CORE_ADDR *data_value, int *len)
0cf6dd15
TJB
1948{
1949 int pc = 1, num_accesses_left, num_accesses_right;
1950 struct value *left_val, *right_val, *left_chain, *right_chain;
1951
1952 if (cond->elts[0].opcode != BINOP_EQUAL)
1953 return 0;
1954
3a1115a0 1955 fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain, 0);
0cf6dd15
TJB
1956 num_accesses_left = num_memory_accesses (left_chain);
1957
1958 if (left_val == NULL || num_accesses_left < 0)
1959 {
1960 free_value_chain (left_chain);
1961
1962 return 0;
1963 }
1964
3a1115a0 1965 fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain, 0);
0cf6dd15
TJB
1966 num_accesses_right = num_memory_accesses (right_chain);
1967
1968 if (right_val == NULL || num_accesses_right < 0)
1969 {
1970 free_value_chain (left_chain);
1971 free_value_chain (right_chain);
1972
1973 return 0;
1974 }
1975
1976 if (num_accesses_left == 1 && num_accesses_right == 0
1977 && VALUE_LVAL (left_val) == lval_memory
1978 && value_address (left_val) == watch_addr)
e7db58ea
TJB
1979 {
1980 *data_value = value_as_long (right_val);
1981
1982 /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
1983 the same type as the memory region referenced by LEFT_VAL. */
1984 *len = TYPE_LENGTH (check_typedef (value_type (left_val)));
1985 }
0cf6dd15
TJB
1986 else if (num_accesses_left == 0 && num_accesses_right == 1
1987 && VALUE_LVAL (right_val) == lval_memory
1988 && value_address (right_val) == watch_addr)
e7db58ea
TJB
1989 {
1990 *data_value = value_as_long (left_val);
1991
1992 /* DATA_VALUE is the constant in LEFT_VAL, but actually has
1993 the same type as the memory region referenced by RIGHT_VAL. */
1994 *len = TYPE_LENGTH (check_typedef (value_type (right_val)));
1995 }
0cf6dd15
TJB
1996 else
1997 {
1998 free_value_chain (left_chain);
1999 free_value_chain (right_chain);
2000
2001 return 0;
2002 }
2003
2004 free_value_chain (left_chain);
2005 free_value_chain (right_chain);
2006
2007 return 1;
2008}
2009
2010/* Return non-zero if the target is capable of using hardware to evaluate
2011 the condition expression, thus only triggering the watchpoint when it is
2012 true. */
2013static int
2014ppc_linux_can_accel_watchpoint_condition (CORE_ADDR addr, int len, int rw,
2015 struct expression *cond)
2016{
2017 CORE_ADDR data_value;
2018
926bf92d
UW
2019 return (have_ptrace_hwdebug_interface ()
2020 && hwdebug_info.num_condition_regs > 0
e7db58ea 2021 && check_condition (addr, cond, &data_value, &len));
0cf6dd15
TJB
2022}
2023
e09342b5
TJB
2024/* Set up P with the parameters necessary to request a watchpoint covering
2025 LEN bytes starting at ADDR and if possible with condition expression COND
2026 evaluated by hardware. INSERT tells if we are creating a request for
2027 inserting or removing the watchpoint. */
2028
2029static void
2030create_watchpoint_request (struct ppc_hw_breakpoint *p, CORE_ADDR addr,
2031 int len, int rw, struct expression *cond,
2032 int insert)
2033{
f16c4e8b 2034 if (len == 1
926bf92d 2035 || !(hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_RANGE))
e09342b5
TJB
2036 {
2037 int use_condition;
2038 CORE_ADDR data_value;
2039
2040 use_condition = (insert? can_use_watchpoint_cond_accel ()
926bf92d 2041 : hwdebug_info.num_condition_regs > 0);
e7db58ea
TJB
2042 if (cond && use_condition && check_condition (addr, cond,
2043 &data_value, &len))
e09342b5
TJB
2044 calculate_dvc (addr, len, data_value, &p->condition_mode,
2045 &p->condition_value);
2046 else
2047 {
2048 p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
2049 p->condition_value = 0;
2050 }
2051
2052 p->addr_mode = PPC_BREAKPOINT_MODE_EXACT;
2053 p->addr2 = 0;
2054 }
2055 else
2056 {
2057 p->addr_mode = PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE;
2058 p->condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
2059 p->condition_value = 0;
2060
2061 /* The watchpoint will trigger if the address of the memory access is
2062 within the defined range, as follows: p->addr <= address < p->addr2.
2063
2064 Note that the above sentence just documents how ptrace interprets
2065 its arguments; the watchpoint is set to watch the range defined by
2066 the user _inclusively_, as specified by the user interface. */
2067 p->addr2 = (uint64_t) addr + len;
2068 }
2069
2070 p->version = PPC_DEBUG_CURRENT_VERSION;
2071 p->trigger_type = get_trigger_type (rw);
2072 p->addr = (uint64_t) addr;
2073}
2074
6ffbb7ab 2075static int
0cf6dd15
TJB
2076ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw,
2077 struct expression *cond)
6ffbb7ab
TJB
2078{
2079 struct lwp_info *lp;
6ffbb7ab
TJB
2080 int ret = -1;
2081
926bf92d 2082 if (have_ptrace_hwdebug_interface ())
e0d24f8d 2083 {
6ffbb7ab
TJB
2084 struct ppc_hw_breakpoint p;
2085
e09342b5 2086 create_watchpoint_request (&p, addr, len, rw, cond, 1);
6ffbb7ab 2087
4c38200f 2088 ALL_LWPS (lp)
dfd4cc63 2089 hwdebug_insert_point (&p, ptid_get_lwp (lp->ptid));
6ffbb7ab
TJB
2090
2091 ret = 0;
e0d24f8d 2092 }
6ffbb7ab
TJB
2093 else
2094 {
2095 long dabr_value;
2096 long read_mode, write_mode;
e0d24f8d 2097
6ffbb7ab
TJB
2098 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2099 {
2100 /* PowerPC 440 requires only the read/write flags to be passed
2101 to the kernel. */
ad422571 2102 read_mode = 1;
6ffbb7ab
TJB
2103 write_mode = 2;
2104 }
2105 else
2106 {
2107 /* PowerPC 970 and other DABR-based processors are required to pass
2108 the Breakpoint Translation bit together with the flags. */
ad422571 2109 read_mode = 5;
6ffbb7ab
TJB
2110 write_mode = 6;
2111 }
1c86e440 2112
6ffbb7ab
TJB
2113 dabr_value = addr & ~(read_mode | write_mode);
2114 switch (rw)
2115 {
2116 case hw_read:
2117 /* Set read and translate bits. */
2118 dabr_value |= read_mode;
2119 break;
2120 case hw_write:
2121 /* Set write and translate bits. */
2122 dabr_value |= write_mode;
2123 break;
2124 case hw_access:
2125 /* Set read, write and translate bits. */
2126 dabr_value |= read_mode | write_mode;
2127 break;
2128 }
1c86e440 2129
6ffbb7ab
TJB
2130 saved_dabr_value = dabr_value;
2131
4c38200f 2132 ALL_LWPS (lp)
dfd4cc63 2133 if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0,
0cf6dd15 2134 saved_dabr_value) < 0)
6ffbb7ab
TJB
2135 return -1;
2136
2137 ret = 0;
2138 }
2139
2140 return ret;
e0d24f8d
WZ
2141}
2142
2c387241 2143static int
0cf6dd15
TJB
2144ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw,
2145 struct expression *cond)
e0d24f8d 2146{
9f0bdab8 2147 struct lwp_info *lp;
6ffbb7ab 2148 int ret = -1;
9f0bdab8 2149
926bf92d 2150 if (have_ptrace_hwdebug_interface ())
6ffbb7ab
TJB
2151 {
2152 struct ppc_hw_breakpoint p;
2153
e09342b5 2154 create_watchpoint_request (&p, addr, len, rw, cond, 0);
6ffbb7ab 2155
4c38200f 2156 ALL_LWPS (lp)
dfd4cc63 2157 hwdebug_remove_point (&p, ptid_get_lwp (lp->ptid));
6ffbb7ab
TJB
2158
2159 ret = 0;
2160 }
2161 else
2162 {
2163 saved_dabr_value = 0;
4c38200f 2164 ALL_LWPS (lp)
dfd4cc63 2165 if (ptrace (PTRACE_SET_DEBUGREG, ptid_get_lwp (lp->ptid), 0,
0cf6dd15 2166 saved_dabr_value) < 0)
6ffbb7ab
TJB
2167 return -1;
2168
2169 ret = 0;
2170 }
2171
2172 return ret;
e0d24f8d
WZ
2173}
2174
9f0bdab8 2175static void
7b50312a 2176ppc_linux_new_thread (struct lwp_info *lp)
e0d24f8d 2177{
dfd4cc63 2178 int tid = ptid_get_lwp (lp->ptid);
6ffbb7ab 2179
926bf92d 2180 if (have_ptrace_hwdebug_interface ())
6ffbb7ab
TJB
2181 {
2182 int i;
2183 struct thread_points *p;
2184 struct hw_break_tuple *hw_breaks;
2185
2186 if (VEC_empty (thread_points_p, ppc_threads))
2187 return;
2188
0df8b418 2189 /* Get a list of breakpoints from any thread. */
6ffbb7ab
TJB
2190 p = VEC_last (thread_points_p, ppc_threads);
2191 hw_breaks = p->hw_breaks;
2192
0df8b418 2193 /* Copy that thread's breakpoints and watchpoints to the new thread. */
6ffbb7ab
TJB
2194 for (i = 0; i < max_slots_number; i++)
2195 if (hw_breaks[i].hw_break)
aacbb8a5
LM
2196 {
2197 /* Older kernels did not make new threads inherit their parent
2198 thread's debug state, so we always clear the slot and replicate
2199 the debug state ourselves, ensuring compatibility with all
2200 kernels. */
2201
2202 /* The ppc debug resource accounting is done through "slots".
2203 Ask the kernel the deallocate this specific *point's slot. */
2204 ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot);
2205
926bf92d 2206 hwdebug_insert_point (hw_breaks[i].hw_break, tid);
aacbb8a5 2207 }
6ffbb7ab
TJB
2208 }
2209 else
2210 ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value);
2211}
2212
2213static void
2214ppc_linux_thread_exit (struct thread_info *tp, int silent)
2215{
2216 int i;
dfd4cc63 2217 int tid = ptid_get_lwp (tp->ptid);
6ffbb7ab
TJB
2218 struct hw_break_tuple *hw_breaks;
2219 struct thread_points *t = NULL, *p;
2220
926bf92d 2221 if (!have_ptrace_hwdebug_interface ())
6ffbb7ab
TJB
2222 return;
2223
2224 for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++)
2225 if (p->tid == tid)
2226 {
2227 t = p;
2228 break;
2229 }
2230
2231 if (t == NULL)
2232 return;
2233
2234 VEC_unordered_remove (thread_points_p, ppc_threads, i);
2235
2236 hw_breaks = t->hw_breaks;
2237
2238 for (i = 0; i < max_slots_number; i++)
2239 if (hw_breaks[i].hw_break)
2240 xfree (hw_breaks[i].hw_break);
2241
2242 xfree (t->hw_breaks);
2243 xfree (t);
e0d24f8d
WZ
2244}
2245
2246static int
9f0bdab8 2247ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p)
e0d24f8d 2248{
f865ee35 2249 siginfo_t siginfo;
e0d24f8d 2250
f865ee35
JK
2251 if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
2252 return 0;
e0d24f8d 2253
f865ee35
JK
2254 if (siginfo.si_signo != SIGTRAP
2255 || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
e0d24f8d
WZ
2256 return 0;
2257
926bf92d 2258 if (have_ptrace_hwdebug_interface ())
6ffbb7ab
TJB
2259 {
2260 int i;
2261 struct thread_points *t;
2262 struct hw_break_tuple *hw_breaks;
2263 /* The index (or slot) of the *point is passed in the si_errno field. */
f865ee35 2264 int slot = siginfo.si_errno;
6ffbb7ab 2265
dfd4cc63 2266 t = hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid), 0);
6ffbb7ab
TJB
2267
2268 /* Find out if this *point is a hardware breakpoint.
2269 If so, we should return 0. */
2270 if (t)
2271 {
2272 hw_breaks = t->hw_breaks;
2273 for (i = 0; i < max_slots_number; i++)
2274 if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot
2275 && hw_breaks[i].hw_break->trigger_type
2276 == PPC_BREAKPOINT_TRIGGER_EXECUTE)
2277 return 0;
2278 }
2279 }
2280
f865ee35 2281 *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr;
e0d24f8d
WZ
2282 return 1;
2283}
2284
9f0bdab8
DJ
2285static int
2286ppc_linux_stopped_by_watchpoint (void)
2287{
2288 CORE_ADDR addr;
2289 return ppc_linux_stopped_data_address (&current_target, &addr);
2290}
2291
5009afc5
AS
2292static int
2293ppc_linux_watchpoint_addr_within_range (struct target_ops *target,
2294 CORE_ADDR addr,
2295 CORE_ADDR start, int length)
2296{
b7622095
LM
2297 int mask;
2298
926bf92d 2299 if (have_ptrace_hwdebug_interface ()
6ffbb7ab
TJB
2300 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2301 return start <= addr && start + length >= addr;
2302 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
b7622095
LM
2303 mask = 3;
2304 else
2305 mask = 7;
2306
2307 addr &= ~mask;
2308
0df8b418 2309 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
b7622095 2310 return start <= addr + mask && start + length - 1 >= addr;
5009afc5
AS
2311}
2312
9c06b0b4
TJB
2313/* Return the number of registers needed for a masked hardware watchpoint. */
2314
2315static int
2316ppc_linux_masked_watch_num_registers (struct target_ops *target,
2317 CORE_ADDR addr, CORE_ADDR mask)
2318{
926bf92d
UW
2319 if (!have_ptrace_hwdebug_interface ()
2320 || (hwdebug_info.features & PPC_DEBUG_FEATURE_DATA_BP_MASK) == 0)
9c06b0b4
TJB
2321 return -1;
2322 else if ((mask & 0xC0000000) != 0xC0000000)
2323 {
2324 warning (_("The given mask covers kernel address space "
2325 "and cannot be used.\n"));
2326
2327 return -2;
2328 }
2329 else
2330 return 2;
2331}
2332
10d6c8cd 2333static void
28439f5e
PA
2334ppc_linux_store_inferior_registers (struct target_ops *ops,
2335 struct regcache *regcache, int regno)
45229ea4 2336{
0df8b418 2337 /* Overload thread id onto process id. */
dfd4cc63 2338 int tid = ptid_get_lwp (inferior_ptid);
05f13b9c 2339
0df8b418 2340 /* No thread id, just use process id. */
05f13b9c 2341 if (tid == 0)
dfd4cc63 2342 tid = ptid_get_pid (inferior_ptid);
05f13b9c 2343
45229ea4 2344 if (regno >= 0)
56be3814 2345 store_register (regcache, tid, regno);
45229ea4 2346 else
56be3814 2347 store_ppc_registers (regcache, tid);
45229ea4
EZ
2348}
2349
f2db237a
AM
2350/* Functions for transferring registers between a gregset_t or fpregset_t
2351 (see sys/ucontext.h) and gdb's regcache. The word size is that used
0df8b418 2352 by the ptrace interface, not the current program's ABI. Eg. if a
f2db237a
AM
2353 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2354 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2355
50c9bd31 2356void
7f7fe91e 2357supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
c877c8e6 2358{
f2db237a 2359 const struct regset *regset = ppc_linux_gregset (sizeof (long));
f9be684a 2360
f2db237a 2361 ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp));
c877c8e6
KB
2362}
2363
fdb28ac4 2364void
7f7fe91e
UW
2365fill_gregset (const struct regcache *regcache,
2366 gdb_gregset_t *gregsetp, int regno)
fdb28ac4 2367{
f2db237a 2368 const struct regset *regset = ppc_linux_gregset (sizeof (long));
f9be684a 2369
f2db237a
AM
2370 if (regno == -1)
2371 memset (gregsetp, 0, sizeof (*gregsetp));
2372 ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp));
fdb28ac4
KB
2373}
2374
50c9bd31 2375void
7f7fe91e 2376supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp)
c877c8e6 2377{
f2db237a
AM
2378 const struct regset *regset = ppc_linux_fpregset ();
2379
2380 ppc_supply_fpregset (regset, regcache, -1,
2381 fpregsetp, sizeof (*fpregsetp));
c877c8e6 2382}
fdb28ac4 2383
fdb28ac4 2384void
7f7fe91e
UW
2385fill_fpregset (const struct regcache *regcache,
2386 gdb_fpregset_t *fpregsetp, int regno)
fdb28ac4 2387{
f2db237a
AM
2388 const struct regset *regset = ppc_linux_fpregset ();
2389
2390 ppc_collect_fpregset (regset, regcache, regno,
2391 fpregsetp, sizeof (*fpregsetp));
fdb28ac4 2392}
10d6c8cd 2393
409c383c
UW
2394static int
2395ppc_linux_target_wordsize (void)
2396{
2397 int wordsize = 4;
2398
2399 /* Check for 64-bit inferior process. This is the case when the host is
2400 64-bit, and in addition the top bit of the MSR register is set. */
2401#ifdef __powerpc64__
2402 long msr;
2403
dfd4cc63 2404 int tid = ptid_get_lwp (inferior_ptid);
409c383c 2405 if (tid == 0)
dfd4cc63 2406 tid = ptid_get_pid (inferior_ptid);
409c383c
UW
2407
2408 errno = 0;
2409 msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0);
2410 if (errno == 0 && msr < 0)
2411 wordsize = 8;
2412#endif
2413
2414 return wordsize;
2415}
2416
2417static int
2418ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr,
2419 gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp)
2420{
2421 int sizeof_auxv_field = ppc_linux_target_wordsize ();
f5656ead 2422 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ());
409c383c
UW
2423 gdb_byte *ptr = *readptr;
2424
2425 if (endptr == ptr)
2426 return 0;
2427
2428 if (endptr - ptr < sizeof_auxv_field * 2)
2429 return -1;
2430
e17a4113 2431 *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
409c383c 2432 ptr += sizeof_auxv_field;
e17a4113 2433 *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
409c383c
UW
2434 ptr += sizeof_auxv_field;
2435
2436 *readptr = ptr;
2437 return 1;
2438}
2439
310a98e1
DJ
2440static const struct target_desc *
2441ppc_linux_read_description (struct target_ops *ops)
2442{
7284e1be 2443 int altivec = 0;
604c2f83 2444 int vsx = 0;
69abc51c 2445 int isa205 = 0;
f4d9bade 2446 int cell = 0;
7284e1be 2447
dfd4cc63 2448 int tid = ptid_get_lwp (inferior_ptid);
7284e1be 2449 if (tid == 0)
dfd4cc63 2450 tid = ptid_get_pid (inferior_ptid);
7284e1be 2451
310a98e1
DJ
2452 if (have_ptrace_getsetevrregs)
2453 {
2454 struct gdb_evrregset_t evrregset;
310a98e1
DJ
2455
2456 if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0)
7284e1be
UW
2457 return tdesc_powerpc_e500l;
2458
2459 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2460 Anything else needs to be reported. */
2461 else if (errno != EIO)
2462 perror_with_name (_("Unable to fetch SPE registers"));
2463 }
2464
604c2f83
LM
2465 if (have_ptrace_getsetvsxregs)
2466 {
2467 gdb_vsxregset_t vsxregset;
2468
2469 if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0)
2470 vsx = 1;
2471
2472 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2473 Anything else needs to be reported. */
2474 else if (errno != EIO)
2475 perror_with_name (_("Unable to fetch VSX registers"));
2476 }
2477
7284e1be
UW
2478 if (have_ptrace_getvrregs)
2479 {
2480 gdb_vrregset_t vrregset;
2481
2482 if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0)
2483 altivec = 1;
2484
2485 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2486 Anything else needs to be reported. */
2487 else if (errno != EIO)
2488 perror_with_name (_("Unable to fetch AltiVec registers"));
310a98e1
DJ
2489 }
2490
f04c6d38 2491 /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
0df8b418 2492 the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
f04c6d38
TJB
2493 ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
2494 PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
2495 half of the register are for Decimal Floating Point, we check if that
2496 feature is available to decide the size of the FPSCR. */
2497 if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP)
69abc51c
TJB
2498 isa205 = 1;
2499
f4d9bade
UW
2500 if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL)
2501 cell = 1;
2502
409c383c
UW
2503 if (ppc_linux_target_wordsize () == 8)
2504 {
f4d9bade
UW
2505 if (cell)
2506 return tdesc_powerpc_cell64l;
2507 else if (vsx)
409c383c
UW
2508 return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l;
2509 else if (altivec)
0df8b418
MS
2510 return isa205
2511 ? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l;
409c383c
UW
2512
2513 return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l;
2514 }
7284e1be 2515
f4d9bade
UW
2516 if (cell)
2517 return tdesc_powerpc_cell32l;
2518 else if (vsx)
69abc51c 2519 return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l;
604c2f83 2520 else if (altivec)
69abc51c 2521 return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l;
604c2f83 2522
69abc51c 2523 return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l;
310a98e1
DJ
2524}
2525
10d6c8cd
DJ
2526void _initialize_ppc_linux_nat (void);
2527
2528void
2529_initialize_ppc_linux_nat (void)
2530{
2531 struct target_ops *t;
2532
2533 /* Fill in the generic GNU/Linux methods. */
2534 t = linux_target ();
2535
2536 /* Add our register access methods. */
2537 t->to_fetch_registers = ppc_linux_fetch_inferior_registers;
2538 t->to_store_registers = ppc_linux_store_inferior_registers;
2539
6ffbb7ab
TJB
2540 /* Add our breakpoint/watchpoint methods. */
2541 t->to_can_use_hw_breakpoint = ppc_linux_can_use_hw_breakpoint;
2542 t->to_insert_hw_breakpoint = ppc_linux_insert_hw_breakpoint;
2543 t->to_remove_hw_breakpoint = ppc_linux_remove_hw_breakpoint;
e0d24f8d
WZ
2544 t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint;
2545 t->to_insert_watchpoint = ppc_linux_insert_watchpoint;
2546 t->to_remove_watchpoint = ppc_linux_remove_watchpoint;
9c06b0b4
TJB
2547 t->to_insert_mask_watchpoint = ppc_linux_insert_mask_watchpoint;
2548 t->to_remove_mask_watchpoint = ppc_linux_remove_mask_watchpoint;
e0d24f8d
WZ
2549 t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint;
2550 t->to_stopped_data_address = ppc_linux_stopped_data_address;
5009afc5 2551 t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range;
0df8b418
MS
2552 t->to_can_accel_watchpoint_condition
2553 = ppc_linux_can_accel_watchpoint_condition;
9c06b0b4 2554 t->to_masked_watch_num_registers = ppc_linux_masked_watch_num_registers;
f1310107 2555 t->to_ranged_break_num_registers = ppc_linux_ranged_break_num_registers;
e0d24f8d 2556
310a98e1 2557 t->to_read_description = ppc_linux_read_description;
409c383c 2558 t->to_auxv_parse = ppc_linux_auxv_parse;
310a98e1 2559
6ffbb7ab
TJB
2560 observer_attach_thread_exit (ppc_linux_thread_exit);
2561
10d6c8cd 2562 /* Register the target. */
f973ed9c 2563 linux_nat_add_target (t);
9f0bdab8 2564 linux_nat_set_new_thread (t, ppc_linux_new_thread);
10d6c8cd 2565}