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90ad3654 | 1 | /* Target-dependent code for GNU/Linux on RISC-V processors. |
1d506c26 | 2 | Copyright (C) 2018-2024 Free Software Foundation, Inc. |
90ad3654 JW |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
18 | ||
19 | #include "defs.h" | |
20 | #include "riscv-tdep.h" | |
21 | #include "osabi.h" | |
22 | #include "glibc-tdep.h" | |
23 | #include "linux-tdep.h" | |
24 | #include "solib-svr4.h" | |
25 | #include "regset.h" | |
77c6f5fc JW |
26 | #include "tramp-frame.h" |
27 | #include "trad-frame.h" | |
0d12e84c | 28 | #include "gdbarch.h" |
90ad3654 | 29 | |
e843807b LS |
30 | /* The following value is derived from __NR_rt_sigreturn in |
31 | <include/uapi/asm-generic/unistd.h> from the Linux source tree. */ | |
32 | ||
33 | #define RISCV_NR_rt_sigreturn 139 | |
34 | ||
90ad3654 JW |
35 | /* Define the general register mapping. The kernel puts the PC at offset 0, |
36 | gdb puts it at offset 32. Register x0 is always 0 and can be ignored. | |
37 | Registers x1 to x31 are in the same place. */ | |
38 | ||
39 | static const struct regcache_map_entry riscv_linux_gregmap[] = | |
40 | { | |
41 | { 1, RISCV_PC_REGNUM, 0 }, | |
42 | { 31, RISCV_RA_REGNUM, 0 }, /* x1 to x31 */ | |
43 | { 0 } | |
44 | }; | |
45 | ||
617126bc JW |
46 | /* Define the FP register mapping. The kernel puts the 32 FP regs first, and |
47 | then FCSR. */ | |
48 | ||
49 | static const struct regcache_map_entry riscv_linux_fregmap[] = | |
50 | { | |
51 | { 32, RISCV_FIRST_FP_REGNUM, 0 }, | |
52 | { 1, RISCV_CSR_FCSR_REGNUM, 0 }, | |
53 | { 0 } | |
54 | }; | |
55 | ||
90ad3654 JW |
56 | /* Define the general register regset. */ |
57 | ||
58 | static const struct regset riscv_linux_gregset = | |
59 | { | |
6a9ad81c | 60 | riscv_linux_gregmap, riscv_supply_regset, regcache_collect_regset |
90ad3654 JW |
61 | }; |
62 | ||
617126bc JW |
63 | /* Define the FP register regset. */ |
64 | ||
65 | static const struct regset riscv_linux_fregset = | |
66 | { | |
6a9ad81c | 67 | riscv_linux_fregmap, riscv_supply_regset, regcache_collect_regset |
617126bc JW |
68 | }; |
69 | ||
90ad3654 JW |
70 | /* Define hook for core file support. */ |
71 | ||
72 | static void | |
73 | riscv_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
dda83cd7 SM |
74 | iterate_over_regset_sections_cb *cb, |
75 | void *cb_data, | |
76 | const struct regcache *regcache) | |
90ad3654 | 77 | { |
a616bb94 | 78 | cb (".reg", (32 * riscv_isa_xlen (gdbarch)), (32 * riscv_isa_xlen (gdbarch)), |
90ad3654 | 79 | &riscv_linux_gregset, NULL, cb_data); |
617126bc JW |
80 | /* The kernel is adding 8 bytes for FCSR. */ |
81 | cb (".reg2", (32 * riscv_isa_flen (gdbarch)) + 8, | |
82 | (32 * riscv_isa_flen (gdbarch)) + 8, | |
83 | &riscv_linux_fregset, NULL, cb_data); | |
90ad3654 JW |
84 | } |
85 | ||
77c6f5fc JW |
86 | /* Signal trampoline support. */ |
87 | ||
88 | static void riscv_linux_sigframe_init (const struct tramp_frame *self, | |
bd2b40ac | 89 | frame_info_ptr this_frame, |
77c6f5fc JW |
90 | struct trad_frame_cache *this_cache, |
91 | CORE_ADDR func); | |
92 | ||
93 | #define RISCV_INST_LI_A7_SIGRETURN 0x08b00893 | |
94 | #define RISCV_INST_ECALL 0x00000073 | |
95 | ||
96 | static const struct tramp_frame riscv_linux_sigframe = { | |
97 | SIGTRAMP_FRAME, | |
98 | 4, | |
99 | { | |
100 | { RISCV_INST_LI_A7_SIGRETURN, ULONGEST_MAX }, | |
101 | { RISCV_INST_ECALL, ULONGEST_MAX }, | |
102 | { TRAMP_SENTINEL_INSN } | |
103 | }, | |
104 | riscv_linux_sigframe_init, | |
105 | NULL | |
106 | }; | |
107 | ||
108 | /* Runtime signal frames look like this: | |
109 | struct rt_sigframe { | |
110 | struct siginfo info; | |
111 | struct ucontext uc; | |
112 | }; | |
113 | ||
114 | struct ucontext { | |
115 | unsigned long __uc_flags; | |
116 | struct ucontext *uclink; | |
117 | stack_t uc_stack; | |
118 | sigset_t uc_sigmask; | |
119 | char __glibc_reserved[1024 / 8 - sizeof (sigset_t)]; | |
120 | mcontext_t uc_mcontext; | |
121 | }; */ | |
122 | ||
123 | #define SIGFRAME_SIGINFO_SIZE 128 | |
124 | #define UCONTEXT_MCONTEXT_OFFSET 176 | |
125 | ||
126 | static void | |
127 | riscv_linux_sigframe_init (const struct tramp_frame *self, | |
bd2b40ac | 128 | frame_info_ptr this_frame, |
77c6f5fc JW |
129 | struct trad_frame_cache *this_cache, |
130 | CORE_ADDR func) | |
131 | { | |
132 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
133 | int xlen = riscv_isa_xlen (gdbarch); | |
134 | int flen = riscv_isa_flen (gdbarch); | |
135 | CORE_ADDR frame_sp = get_frame_sp (this_frame); | |
136 | CORE_ADDR mcontext_base; | |
137 | CORE_ADDR regs_base; | |
138 | ||
139 | mcontext_base = frame_sp + SIGFRAME_SIGINFO_SIZE + UCONTEXT_MCONTEXT_OFFSET; | |
140 | ||
141 | /* Handle the integer registers. The first one is PC, followed by x1 | |
142 | through x31. */ | |
143 | regs_base = mcontext_base; | |
144 | trad_frame_set_reg_addr (this_cache, RISCV_PC_REGNUM, regs_base); | |
145 | for (int i = 1; i < 32; i++) | |
146 | trad_frame_set_reg_addr (this_cache, RISCV_ZERO_REGNUM + i, | |
147 | regs_base + (i * xlen)); | |
148 | ||
149 | /* Handle the FP registers. First comes the 32 FP registers, followed by | |
150 | fcsr. */ | |
151 | regs_base += 32 * xlen; | |
152 | for (int i = 0; i < 32; i++) | |
153 | trad_frame_set_reg_addr (this_cache, RISCV_FIRST_FP_REGNUM + i, | |
154 | regs_base + (i * flen)); | |
155 | regs_base += 32 * flen; | |
156 | trad_frame_set_reg_addr (this_cache, RISCV_CSR_FCSR_REGNUM, regs_base); | |
157 | ||
158 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
159 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); | |
160 | } | |
161 | ||
e843807b LS |
162 | /* When FRAME is at a syscall instruction (ECALL), return the PC of the next |
163 | instruction to be executed. */ | |
164 | ||
165 | static CORE_ADDR | |
bd2b40ac | 166 | riscv_linux_syscall_next_pc (frame_info_ptr frame) |
e843807b LS |
167 | { |
168 | const CORE_ADDR pc = get_frame_pc (frame); | |
169 | const ULONGEST a7 = get_frame_register_unsigned (frame, RISCV_A7_REGNUM); | |
170 | ||
171 | if (a7 == RISCV_NR_rt_sigreturn) | |
172 | return frame_unwind_caller_pc (frame); | |
173 | ||
174 | return pc + 4 /* Length of the ECALL insn. */; | |
175 | } | |
176 | ||
90ad3654 JW |
177 | /* Initialize RISC-V Linux ABI info. */ |
178 | ||
179 | static void | |
180 | riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
181 | { | |
08106042 | 182 | riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (gdbarch); |
e843807b | 183 | |
480af54c | 184 | linux_init_abi (info, gdbarch, 0); |
90ad3654 JW |
185 | |
186 | set_gdbarch_software_single_step (gdbarch, riscv_software_single_step); | |
187 | ||
188 | set_solib_svr4_fetch_link_map_offsets (gdbarch, | |
189 | (riscv_isa_xlen (gdbarch) == 4 | |
c0154a4a L |
190 | ? linux_ilp32_fetch_link_map_offsets |
191 | : linux_lp64_fetch_link_map_offsets)); | |
90ad3654 JW |
192 | |
193 | /* GNU/Linux uses SVR4-style shared libraries. */ | |
194 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); | |
195 | ||
196 | /* GNU/Linux uses the dynamic linker included in the GNU C Library. */ | |
197 | set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver); | |
198 | ||
199 | /* Enable TLS support. */ | |
200 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
dda83cd7 | 201 | svr4_fetch_objfile_link_map); |
90ad3654 JW |
202 | |
203 | set_gdbarch_iterate_over_regset_sections | |
204 | (gdbarch, riscv_linux_iterate_over_regset_sections); | |
77c6f5fc JW |
205 | |
206 | tramp_frame_prepend_unwinder (gdbarch, &riscv_linux_sigframe); | |
e843807b LS |
207 | |
208 | tdep->syscall_next_pc = riscv_linux_syscall_next_pc; | |
90ad3654 JW |
209 | } |
210 | ||
211 | /* Initialize RISC-V Linux target support. */ | |
212 | ||
6c265988 | 213 | void _initialize_riscv_linux_tdep (); |
90ad3654 | 214 | void |
6c265988 | 215 | _initialize_riscv_linux_tdep () |
90ad3654 JW |
216 | { |
217 | gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_LINUX, | |
218 | riscv_linux_init_abi); | |
219 | } |