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dbbb1059 AB |
1 | /* Target-dependent code for the RISC-V architecture, for GDB. |
2 | ||
4a94e368 | 3 | Copyright (C) 2018-2022 Free Software Foundation, Inc. |
dbbb1059 | 4 | |
dbbb1059 AB |
5 | This file is part of GDB. |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "inferior.h" | |
23 | #include "symtab.h" | |
24 | #include "value.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "language.h" | |
27 | #include "gdbcore.h" | |
28 | #include "symfile.h" | |
29 | #include "objfiles.h" | |
30 | #include "gdbtypes.h" | |
31 | #include "target.h" | |
32 | #include "arch-utils.h" | |
33 | #include "regcache.h" | |
34 | #include "osabi.h" | |
35 | #include "riscv-tdep.h" | |
36 | #include "block.h" | |
37 | #include "reggroups.h" | |
38 | #include "opcode/riscv.h" | |
39 | #include "elf/riscv.h" | |
40 | #include "elf-bfd.h" | |
41 | #include "symcat.h" | |
42 | #include "dis-asm.h" | |
43 | #include "frame-unwind.h" | |
44 | #include "frame-base.h" | |
45 | #include "trad-frame.h" | |
46 | #include "infcall.h" | |
47 | #include "floatformat.h" | |
48 | #include "remote.h" | |
49 | #include "target-descriptions.h" | |
82ca8957 | 50 | #include "dwarf2/frame.h" |
dbbb1059 AB |
51 | #include "user-regs.h" |
52 | #include "valprint.h" | |
268a13a5 | 53 | #include "gdbsupport/common-defs.h" |
dbbb1059 AB |
54 | #include "opcode/riscv-opc.h" |
55 | #include "cli/cli-decode.h" | |
76727919 | 56 | #include "observable.h" |
78a3b0fa | 57 | #include "prologue-value.h" |
b5ffee31 | 58 | #include "arch/riscv.h" |
db3ad2f0 | 59 | #include "riscv-ravenscar-thread.h" |
dbbb1059 AB |
60 | |
61 | /* The stack must be 16-byte aligned. */ | |
62 | #define SP_ALIGNMENT 16 | |
63 | ||
ef2de9e7 JW |
64 | /* The biggest alignment that the target supports. */ |
65 | #define BIGGEST_ALIGNMENT 16 | |
66 | ||
dbbb1059 AB |
67 | /* Define a series of is_XXX_insn functions to check if the value INSN |
68 | is an instance of instruction XXX. */ | |
69 | #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \ | |
70 | static inline bool is_ ## INSN_NAME ## _insn (long insn) \ | |
71 | { \ | |
72 | return (insn & INSN_MASK) == INSN_MATCH; \ | |
73 | } | |
74 | #include "opcode/riscv-opc.h" | |
75 | #undef DECLARE_INSN | |
76 | ||
25428040 AB |
77 | /* When this is set to non-zero debugging information about breakpoint |
78 | kinds will be printed. */ | |
79 | ||
80 | static unsigned int riscv_debug_breakpoints = 0; | |
81 | ||
82 | /* When this is set to non-zero debugging information about inferior calls | |
83 | will be printed. */ | |
84 | ||
85 | static unsigned int riscv_debug_infcall = 0; | |
86 | ||
87 | /* When this is set to non-zero debugging information about stack unwinding | |
88 | will be printed. */ | |
89 | ||
90 | static unsigned int riscv_debug_unwinder = 0; | |
91 | ||
92 | /* When this is set to non-zero debugging information about gdbarch | |
93 | initialisation will be printed. */ | |
94 | ||
95 | static unsigned int riscv_debug_gdbarch = 0; | |
96 | ||
d782d24b AB |
97 | /* The names of the RISC-V target description features. */ |
98 | const char *riscv_feature_name_csr = "org.gnu.gdb.riscv.csr"; | |
99 | static const char *riscv_feature_name_cpu = "org.gnu.gdb.riscv.cpu"; | |
100 | static const char *riscv_feature_name_fpu = "org.gnu.gdb.riscv.fpu"; | |
101 | static const char *riscv_feature_name_virtual = "org.gnu.gdb.riscv.virtual"; | |
96f842cb | 102 | static const char *riscv_feature_name_vector = "org.gnu.gdb.riscv.vector"; |
d782d24b | 103 | |
61a5375b AB |
104 | /* The current set of options to be passed to the disassembler. */ |
105 | static char *riscv_disassembler_options; | |
106 | ||
78a3b0fa AB |
107 | /* Cached information about a frame. */ |
108 | ||
109 | struct riscv_unwind_cache | |
110 | { | |
111 | /* The register from which we can calculate the frame base. This is | |
112 | usually $sp or $fp. */ | |
113 | int frame_base_reg; | |
114 | ||
115 | /* The offset from the current value in register FRAME_BASE_REG to the | |
116 | actual frame base address. */ | |
117 | int frame_base_offset; | |
118 | ||
119 | /* Information about previous register values. */ | |
098caef4 | 120 | trad_frame_saved_reg *regs; |
78a3b0fa AB |
121 | |
122 | /* The id for this frame. */ | |
123 | struct frame_id this_id; | |
124 | ||
125 | /* The base (stack) address for this frame. This is the stack pointer | |
126 | value on entry to this frame before any adjustments are made. */ | |
127 | CORE_ADDR frame_base; | |
128 | }; | |
129 | ||
b5ffee31 | 130 | /* RISC-V specific register group for CSRs. */ |
dbbb1059 | 131 | |
b5ffee31 | 132 | static reggroup *csr_reggroup = NULL; |
dbbb1059 | 133 | |
3b9fce96 AB |
134 | /* Callback function for user_reg_add. */ |
135 | ||
136 | static struct value * | |
137 | value_of_riscv_user_reg (struct frame_info *frame, const void *baton) | |
138 | { | |
139 | const int *reg_p = (const int *) baton; | |
140 | return value_of_register (*reg_p, frame); | |
141 | } | |
142 | ||
143 | /* Information about a register alias that needs to be set up for this | |
144 | target. These are collected when the target's XML description is | |
145 | analysed, and then processed later, once the gdbarch has been created. */ | |
146 | ||
147 | class riscv_pending_register_alias | |
148 | { | |
149 | public: | |
150 | /* Constructor. */ | |
151 | ||
152 | riscv_pending_register_alias (const char *name, const void *baton) | |
153 | : m_name (name), | |
154 | m_baton (baton) | |
155 | { /* Nothing. */ } | |
156 | ||
157 | /* Convert this into a user register for GDBARCH. */ | |
158 | ||
159 | void create (struct gdbarch *gdbarch) const | |
160 | { | |
161 | user_reg_add (gdbarch, m_name, value_of_riscv_user_reg, m_baton); | |
162 | } | |
163 | ||
164 | private: | |
165 | /* The name for this alias. */ | |
166 | const char *m_name; | |
167 | ||
168 | /* The baton value for passing to user_reg_add. This must point to some | |
169 | data that will live for at least as long as the gdbarch object to | |
170 | which the user register is attached. */ | |
171 | const void *m_baton; | |
172 | }; | |
173 | ||
b5ffee31 AB |
174 | /* A set of registers that we expect to find in a tdesc_feature. These |
175 | are use in RISCV_GDBARCH_INIT when processing the target description. */ | |
dbbb1059 | 176 | |
b5ffee31 | 177 | struct riscv_register_feature |
dbbb1059 | 178 | { |
25428040 AB |
179 | explicit riscv_register_feature (const char *feature_name) |
180 | : m_feature_name (feature_name) | |
181 | { /* Delete. */ } | |
182 | ||
183 | riscv_register_feature () = delete; | |
184 | DISABLE_COPY_AND_ASSIGN (riscv_register_feature); | |
185 | ||
b5ffee31 AB |
186 | /* Information for a single register. */ |
187 | struct register_info | |
188 | { | |
189 | /* The GDB register number for this register. */ | |
190 | int regnum; | |
191 | ||
192 | /* List of names for this register. The first name in this list is the | |
193 | preferred name, the name GDB should use when describing this | |
194 | register. */ | |
4445e8f5 | 195 | std::vector<const char *> names; |
b5ffee31 | 196 | |
3b9fce96 AB |
197 | /* Look in FEATURE for a register with a name from this classes names |
198 | list. If the register is found then register its number with | |
25428040 AB |
199 | TDESC_DATA and add all its aliases to the ALIASES list. |
200 | PREFER_FIRST_NAME_P is used when deciding which aliases to create. */ | |
3b9fce96 AB |
201 | bool check (struct tdesc_arch_data *tdesc_data, |
202 | const struct tdesc_feature *feature, | |
25428040 | 203 | bool prefer_first_name_p, |
3b9fce96 | 204 | std::vector<riscv_pending_register_alias> *aliases) const; |
b5ffee31 AB |
205 | }; |
206 | ||
25428040 AB |
207 | /* Return the name of this feature. */ |
208 | const char *name () const | |
209 | { return m_feature_name; } | |
dbbb1059 | 210 | |
25428040 | 211 | protected: |
ed69cbc8 | 212 | |
25428040 AB |
213 | /* Return a target description feature extracted from TDESC for this |
214 | register feature. Will return nullptr if there is no feature in TDESC | |
215 | with the name M_FEATURE_NAME. */ | |
216 | const struct tdesc_feature *tdesc_feature (const struct target_desc *tdesc) const | |
217 | { | |
218 | return tdesc_find_feature (tdesc, name ()); | |
219 | } | |
ed69cbc8 | 220 | |
b5ffee31 AB |
221 | /* List of all the registers that we expect that we might find in this |
222 | register set. */ | |
25428040 AB |
223 | std::vector<struct register_info> m_registers; |
224 | ||
225 | private: | |
226 | ||
227 | /* The name for this feature. This is the name used to find this feature | |
228 | within the target description. */ | |
229 | const char *m_feature_name; | |
b5ffee31 AB |
230 | }; |
231 | ||
3b9fce96 AB |
232 | /* See description in the class declaration above. */ |
233 | ||
234 | bool | |
235 | riscv_register_feature::register_info::check | |
236 | (struct tdesc_arch_data *tdesc_data, | |
237 | const struct tdesc_feature *feature, | |
25428040 | 238 | bool prefer_first_name_p, |
3b9fce96 AB |
239 | std::vector<riscv_pending_register_alias> *aliases) const |
240 | { | |
241 | for (const char *name : this->names) | |
242 | { | |
243 | bool found = tdesc_numbered_register (feature, tdesc_data, | |
244 | this->regnum, name); | |
245 | if (found) | |
246 | { | |
247 | /* We know that the target description mentions this | |
248 | register. In RISCV_REGISTER_NAME we ensure that GDB | |
249 | always uses the first name for each register, so here we | |
250 | add aliases for all of the remaining names. */ | |
25428040 | 251 | int start_index = prefer_first_name_p ? 1 : 0; |
3b9fce96 AB |
252 | for (int i = start_index; i < this->names.size (); ++i) |
253 | { | |
254 | const char *alias = this->names[i]; | |
25428040 | 255 | if (alias == name && !prefer_first_name_p) |
3b9fce96 AB |
256 | continue; |
257 | aliases->emplace_back (alias, (void *) &this->regnum); | |
258 | } | |
259 | return true; | |
260 | } | |
261 | } | |
262 | return false; | |
263 | } | |
264 | ||
25428040 AB |
265 | /* Class representing the x-registers feature set. */ |
266 | ||
267 | struct riscv_xreg_feature : public riscv_register_feature | |
268 | { | |
269 | riscv_xreg_feature () | |
d782d24b | 270 | : riscv_register_feature (riscv_feature_name_cpu) |
25428040 AB |
271 | { |
272 | m_registers = { | |
273 | { RISCV_ZERO_REGNUM + 0, { "zero", "x0" } }, | |
274 | { RISCV_ZERO_REGNUM + 1, { "ra", "x1" } }, | |
275 | { RISCV_ZERO_REGNUM + 2, { "sp", "x2" } }, | |
276 | { RISCV_ZERO_REGNUM + 3, { "gp", "x3" } }, | |
277 | { RISCV_ZERO_REGNUM + 4, { "tp", "x4" } }, | |
278 | { RISCV_ZERO_REGNUM + 5, { "t0", "x5" } }, | |
279 | { RISCV_ZERO_REGNUM + 6, { "t1", "x6" } }, | |
280 | { RISCV_ZERO_REGNUM + 7, { "t2", "x7" } }, | |
281 | { RISCV_ZERO_REGNUM + 8, { "fp", "x8", "s0" } }, | |
282 | { RISCV_ZERO_REGNUM + 9, { "s1", "x9" } }, | |
283 | { RISCV_ZERO_REGNUM + 10, { "a0", "x10" } }, | |
284 | { RISCV_ZERO_REGNUM + 11, { "a1", "x11" } }, | |
285 | { RISCV_ZERO_REGNUM + 12, { "a2", "x12" } }, | |
286 | { RISCV_ZERO_REGNUM + 13, { "a3", "x13" } }, | |
287 | { RISCV_ZERO_REGNUM + 14, { "a4", "x14" } }, | |
288 | { RISCV_ZERO_REGNUM + 15, { "a5", "x15" } }, | |
289 | { RISCV_ZERO_REGNUM + 16, { "a6", "x16" } }, | |
290 | { RISCV_ZERO_REGNUM + 17, { "a7", "x17" } }, | |
291 | { RISCV_ZERO_REGNUM + 18, { "s2", "x18" } }, | |
292 | { RISCV_ZERO_REGNUM + 19, { "s3", "x19" } }, | |
293 | { RISCV_ZERO_REGNUM + 20, { "s4", "x20" } }, | |
294 | { RISCV_ZERO_REGNUM + 21, { "s5", "x21" } }, | |
295 | { RISCV_ZERO_REGNUM + 22, { "s6", "x22" } }, | |
296 | { RISCV_ZERO_REGNUM + 23, { "s7", "x23" } }, | |
297 | { RISCV_ZERO_REGNUM + 24, { "s8", "x24" } }, | |
298 | { RISCV_ZERO_REGNUM + 25, { "s9", "x25" } }, | |
299 | { RISCV_ZERO_REGNUM + 26, { "s10", "x26" } }, | |
300 | { RISCV_ZERO_REGNUM + 27, { "s11", "x27" } }, | |
301 | { RISCV_ZERO_REGNUM + 28, { "t3", "x28" } }, | |
302 | { RISCV_ZERO_REGNUM + 29, { "t4", "x29" } }, | |
303 | { RISCV_ZERO_REGNUM + 30, { "t5", "x30" } }, | |
304 | { RISCV_ZERO_REGNUM + 31, { "t6", "x31" } }, | |
305 | { RISCV_ZERO_REGNUM + 32, { "pc" } } | |
306 | }; | |
307 | } | |
308 | ||
309 | /* Return the preferred name for the register with gdb register number | |
310 | REGNUM, which must be in the inclusive range RISCV_ZERO_REGNUM to | |
311 | RISCV_PC_REGNUM. */ | |
312 | const char *register_name (int regnum) const | |
313 | { | |
314 | gdb_assert (regnum >= RISCV_ZERO_REGNUM && regnum <= m_registers.size ()); | |
315 | return m_registers[regnum].names[0]; | |
316 | } | |
317 | ||
318 | /* Check this feature within TDESC, record the registers from this | |
319 | feature into TDESC_DATA and update ALIASES and FEATURES. */ | |
320 | bool check (const struct target_desc *tdesc, | |
321 | struct tdesc_arch_data *tdesc_data, | |
322 | std::vector<riscv_pending_register_alias> *aliases, | |
323 | struct riscv_gdbarch_features *features) const | |
324 | { | |
325 | const struct tdesc_feature *feature_cpu = tdesc_feature (tdesc); | |
326 | ||
327 | if (feature_cpu == nullptr) | |
328 | return false; | |
329 | ||
330 | bool seen_an_optional_reg_p = false; | |
331 | for (const auto ® : m_registers) | |
332 | { | |
333 | bool found = reg.check (tdesc_data, feature_cpu, true, aliases); | |
334 | ||
335 | bool is_optional_reg_p = (reg.regnum >= RISCV_ZERO_REGNUM + 16 | |
336 | && reg.regnum < RISCV_ZERO_REGNUM + 32); | |
337 | ||
338 | if (!found && (!is_optional_reg_p || seen_an_optional_reg_p)) | |
339 | return false; | |
340 | else if (found && is_optional_reg_p) | |
341 | seen_an_optional_reg_p = true; | |
342 | } | |
343 | ||
344 | /* Check that all of the core cpu registers have the same bitsize. */ | |
345 | int xlen_bitsize = tdesc_register_bitsize (feature_cpu, "pc"); | |
346 | ||
347 | bool valid_p = true; | |
348 | for (auto &tdesc_reg : feature_cpu->registers) | |
349 | valid_p &= (tdesc_reg->bitsize == xlen_bitsize); | |
350 | ||
351 | features->xlen = (xlen_bitsize / 8); | |
352 | features->embedded = !seen_an_optional_reg_p; | |
353 | ||
354 | return valid_p; | |
355 | } | |
b5ffee31 AB |
356 | }; |
357 | ||
25428040 AB |
358 | /* An instance of the x-register feature set. */ |
359 | ||
360 | static const struct riscv_xreg_feature riscv_xreg_feature; | |
361 | ||
362 | /* Class representing the f-registers feature set. */ | |
363 | ||
364 | struct riscv_freg_feature : public riscv_register_feature | |
365 | { | |
366 | riscv_freg_feature () | |
d782d24b | 367 | : riscv_register_feature (riscv_feature_name_fpu) |
25428040 AB |
368 | { |
369 | m_registers = { | |
370 | { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" } }, | |
371 | { RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" } }, | |
372 | { RISCV_FIRST_FP_REGNUM + 2, { "ft2", "f2" } }, | |
373 | { RISCV_FIRST_FP_REGNUM + 3, { "ft3", "f3" } }, | |
374 | { RISCV_FIRST_FP_REGNUM + 4, { "ft4", "f4" } }, | |
375 | { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" } }, | |
376 | { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" } }, | |
377 | { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" } }, | |
378 | { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" } }, | |
379 | { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" } }, | |
380 | { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" } }, | |
381 | { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" } }, | |
382 | { RISCV_FIRST_FP_REGNUM + 12, { "fa2", "f12" } }, | |
383 | { RISCV_FIRST_FP_REGNUM + 13, { "fa3", "f13" } }, | |
384 | { RISCV_FIRST_FP_REGNUM + 14, { "fa4", "f14" } }, | |
385 | { RISCV_FIRST_FP_REGNUM + 15, { "fa5", "f15" } }, | |
386 | { RISCV_FIRST_FP_REGNUM + 16, { "fa6", "f16" } }, | |
387 | { RISCV_FIRST_FP_REGNUM + 17, { "fa7", "f17" } }, | |
388 | { RISCV_FIRST_FP_REGNUM + 18, { "fs2", "f18" } }, | |
389 | { RISCV_FIRST_FP_REGNUM + 19, { "fs3", "f19" } }, | |
390 | { RISCV_FIRST_FP_REGNUM + 20, { "fs4", "f20" } }, | |
391 | { RISCV_FIRST_FP_REGNUM + 21, { "fs5", "f21" } }, | |
392 | { RISCV_FIRST_FP_REGNUM + 22, { "fs6", "f22" } }, | |
393 | { RISCV_FIRST_FP_REGNUM + 23, { "fs7", "f23" } }, | |
394 | { RISCV_FIRST_FP_REGNUM + 24, { "fs8", "f24" } }, | |
395 | { RISCV_FIRST_FP_REGNUM + 25, { "fs9", "f25" } }, | |
396 | { RISCV_FIRST_FP_REGNUM + 26, { "fs10", "f26" } }, | |
397 | { RISCV_FIRST_FP_REGNUM + 27, { "fs11", "f27" } }, | |
398 | { RISCV_FIRST_FP_REGNUM + 28, { "ft8", "f28" } }, | |
399 | { RISCV_FIRST_FP_REGNUM + 29, { "ft9", "f29" } }, | |
400 | { RISCV_FIRST_FP_REGNUM + 30, { "ft10", "f30" } }, | |
401 | { RISCV_FIRST_FP_REGNUM + 31, { "ft11", "f31" } }, | |
402 | { RISCV_CSR_FFLAGS_REGNUM, { "fflags", "csr1" } }, | |
403 | { RISCV_CSR_FRM_REGNUM, { "frm", "csr2" } }, | |
404 | { RISCV_CSR_FCSR_REGNUM, { "fcsr", "csr3" } }, | |
405 | }; | |
406 | } | |
407 | ||
408 | /* Return the preferred name for the register with gdb register number | |
409 | REGNUM, which must be in the inclusive range RISCV_FIRST_FP_REGNUM to | |
410 | RISCV_LAST_FP_REGNUM. */ | |
411 | const char *register_name (int regnum) const | |
412 | { | |
413 | gdb_static_assert (RISCV_LAST_FP_REGNUM == RISCV_FIRST_FP_REGNUM + 31); | |
414 | gdb_assert (regnum >= RISCV_FIRST_FP_REGNUM | |
415 | && regnum <= RISCV_LAST_FP_REGNUM); | |
416 | regnum -= RISCV_FIRST_FP_REGNUM; | |
417 | return m_registers[regnum].names[0]; | |
418 | } | |
419 | ||
420 | /* Check this feature within TDESC, record the registers from this | |
421 | feature into TDESC_DATA and update ALIASES and FEATURES. */ | |
422 | bool check (const struct target_desc *tdesc, | |
423 | struct tdesc_arch_data *tdesc_data, | |
424 | std::vector<riscv_pending_register_alias> *aliases, | |
425 | struct riscv_gdbarch_features *features) const | |
426 | { | |
427 | const struct tdesc_feature *feature_fpu = tdesc_feature (tdesc); | |
428 | ||
429 | /* It's fine if this feature is missing. Update the architecture | |
430 | feature set and return. */ | |
431 | if (feature_fpu == nullptr) | |
432 | { | |
433 | features->flen = 0; | |
434 | return true; | |
435 | } | |
436 | ||
437 | /* Check all of the floating pointer registers are present. We also | |
438 | check that the floating point CSRs are present too, though if these | |
439 | are missing this is not fatal. */ | |
440 | for (const auto ® : m_registers) | |
441 | { | |
442 | bool found = reg.check (tdesc_data, feature_fpu, true, aliases); | |
443 | ||
444 | bool is_ctrl_reg_p = reg.regnum > RISCV_LAST_FP_REGNUM; | |
445 | ||
446 | if (!found && !is_ctrl_reg_p) | |
447 | return false; | |
448 | } | |
449 | ||
450 | /* Look through all of the floating point registers (not the FP CSRs | |
451 | though), and check they all have the same bitsize. Use this bitsize | |
452 | to update the feature set for this gdbarch. */ | |
453 | int fp_bitsize = -1; | |
454 | for (const auto ® : m_registers) | |
455 | { | |
456 | /* Stop once we get to the CSRs which are at the end of the | |
457 | M_REGISTERS list. */ | |
458 | if (reg.regnum > RISCV_LAST_FP_REGNUM) | |
459 | break; | |
460 | ||
461 | int reg_bitsize = -1; | |
462 | for (const char *name : reg.names) | |
463 | { | |
464 | if (tdesc_unnumbered_register (feature_fpu, name)) | |
465 | { | |
466 | reg_bitsize = tdesc_register_bitsize (feature_fpu, name); | |
467 | break; | |
468 | } | |
469 | } | |
470 | gdb_assert (reg_bitsize != -1); | |
471 | if (fp_bitsize == -1) | |
472 | fp_bitsize = reg_bitsize; | |
473 | else if (fp_bitsize != reg_bitsize) | |
474 | return false; | |
475 | } | |
476 | ||
477 | features->flen = (fp_bitsize / 8); | |
478 | return true; | |
479 | } | |
b5ffee31 AB |
480 | }; |
481 | ||
25428040 AB |
482 | /* An instance of the f-register feature set. */ |
483 | ||
484 | static const struct riscv_freg_feature riscv_freg_feature; | |
485 | ||
486 | /* Class representing the virtual registers. These are not physical | |
487 | registers on the hardware, but might be available from the target. | |
488 | These are not pseudo registers, reading these really does result in a | |
489 | register read from the target, it is just that there might not be a | |
490 | physical register backing the result. */ | |
b5ffee31 | 491 | |
25428040 | 492 | struct riscv_virtual_feature : public riscv_register_feature |
b5ffee31 | 493 | { |
25428040 | 494 | riscv_virtual_feature () |
d782d24b | 495 | : riscv_register_feature (riscv_feature_name_virtual) |
25428040 AB |
496 | { |
497 | m_registers = { | |
498 | { RISCV_PRIV_REGNUM, { "priv" } } | |
499 | }; | |
500 | } | |
501 | ||
502 | bool check (const struct target_desc *tdesc, | |
503 | struct tdesc_arch_data *tdesc_data, | |
504 | std::vector<riscv_pending_register_alias> *aliases, | |
505 | struct riscv_gdbarch_features *features) const | |
506 | { | |
507 | const struct tdesc_feature *feature_virtual = tdesc_feature (tdesc); | |
508 | ||
509 | /* It's fine if this feature is missing. */ | |
510 | if (feature_virtual == nullptr) | |
511 | return true; | |
512 | ||
513 | /* We don't check the return value from the call to check here, all the | |
514 | registers in this feature are optional. */ | |
515 | for (const auto ® : m_registers) | |
516 | reg.check (tdesc_data, feature_virtual, true, aliases); | |
517 | ||
518 | return true; | |
519 | } | |
dbbb1059 AB |
520 | }; |
521 | ||
25428040 | 522 | /* An instance of the virtual register feature. */ |
b5ffee31 | 523 | |
25428040 AB |
524 | static const struct riscv_virtual_feature riscv_virtual_feature; |
525 | ||
526 | /* Class representing the CSR feature. */ | |
527 | ||
528 | struct riscv_csr_feature : public riscv_register_feature | |
b5ffee31 | 529 | { |
25428040 | 530 | riscv_csr_feature () |
d782d24b | 531 | : riscv_register_feature (riscv_feature_name_csr) |
25428040 AB |
532 | { |
533 | m_registers = { | |
534 | #define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \ | |
535 | { RISCV_ ## VALUE ## _REGNUM, { # NAME } }, | |
b5ffee31 AB |
536 | #include "opcode/riscv-opc.h" |
537 | #undef DECLARE_CSR | |
25428040 AB |
538 | }; |
539 | riscv_create_csr_aliases (); | |
540 | } | |
541 | ||
542 | bool check (const struct target_desc *tdesc, | |
543 | struct tdesc_arch_data *tdesc_data, | |
544 | std::vector<riscv_pending_register_alias> *aliases, | |
545 | struct riscv_gdbarch_features *features) const | |
546 | { | |
547 | const struct tdesc_feature *feature_csr = tdesc_feature (tdesc); | |
548 | ||
549 | /* It's fine if this feature is missing. */ | |
550 | if (feature_csr == nullptr) | |
551 | return true; | |
552 | ||
553 | /* We don't check the return value from the call to check here, all the | |
554 | registers in this feature are optional. */ | |
555 | for (const auto ® : m_registers) | |
556 | reg.check (tdesc_data, feature_csr, true, aliases); | |
557 | ||
558 | return true; | |
559 | } | |
560 | ||
561 | private: | |
562 | ||
563 | /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them | |
564 | to the name list for each register. */ | |
565 | ||
566 | void | |
567 | riscv_create_csr_aliases () | |
568 | { | |
569 | for (auto ® : m_registers) | |
570 | { | |
571 | int csr_num = reg.regnum - RISCV_FIRST_CSR_REGNUM; | |
8579fd13 AB |
572 | gdb::unique_xmalloc_ptr<char> alias = xstrprintf ("csr%d", csr_num); |
573 | reg.names.push_back (alias.release ()); | |
25428040 AB |
574 | } |
575 | } | |
dbbb1059 AB |
576 | }; |
577 | ||
25428040 | 578 | /* An instance of the csr register feature. */ |
b5ffee31 | 579 | |
25428040 | 580 | static const struct riscv_csr_feature riscv_csr_feature; |
b5ffee31 | 581 | |
96f842cb AB |
582 | /* Class representing the v-registers feature set. */ |
583 | ||
584 | struct riscv_vector_feature : public riscv_register_feature | |
585 | { | |
586 | riscv_vector_feature () | |
587 | : riscv_register_feature (riscv_feature_name_vector) | |
588 | { | |
589 | m_registers = { | |
590 | { RISCV_V0_REGNUM + 0, { "v0" } }, | |
591 | { RISCV_V0_REGNUM + 1, { "v1" } }, | |
592 | { RISCV_V0_REGNUM + 2, { "v2" } }, | |
593 | { RISCV_V0_REGNUM + 3, { "v3" } }, | |
594 | { RISCV_V0_REGNUM + 4, { "v4" } }, | |
595 | { RISCV_V0_REGNUM + 5, { "v5" } }, | |
596 | { RISCV_V0_REGNUM + 6, { "v6" } }, | |
597 | { RISCV_V0_REGNUM + 7, { "v7" } }, | |
598 | { RISCV_V0_REGNUM + 8, { "v8" } }, | |
599 | { RISCV_V0_REGNUM + 9, { "v9" } }, | |
600 | { RISCV_V0_REGNUM + 10, { "v10" } }, | |
601 | { RISCV_V0_REGNUM + 11, { "v11" } }, | |
602 | { RISCV_V0_REGNUM + 12, { "v12" } }, | |
603 | { RISCV_V0_REGNUM + 13, { "v13" } }, | |
604 | { RISCV_V0_REGNUM + 14, { "v14" } }, | |
605 | { RISCV_V0_REGNUM + 15, { "v15" } }, | |
606 | { RISCV_V0_REGNUM + 16, { "v16" } }, | |
607 | { RISCV_V0_REGNUM + 17, { "v17" } }, | |
608 | { RISCV_V0_REGNUM + 18, { "v18" } }, | |
609 | { RISCV_V0_REGNUM + 19, { "v19" } }, | |
610 | { RISCV_V0_REGNUM + 20, { "v20" } }, | |
611 | { RISCV_V0_REGNUM + 21, { "v21" } }, | |
612 | { RISCV_V0_REGNUM + 22, { "v22" } }, | |
613 | { RISCV_V0_REGNUM + 23, { "v23" } }, | |
614 | { RISCV_V0_REGNUM + 24, { "v24" } }, | |
615 | { RISCV_V0_REGNUM + 25, { "v25" } }, | |
616 | { RISCV_V0_REGNUM + 26, { "v26" } }, | |
617 | { RISCV_V0_REGNUM + 27, { "v27" } }, | |
618 | { RISCV_V0_REGNUM + 28, { "v28" } }, | |
619 | { RISCV_V0_REGNUM + 29, { "v29" } }, | |
620 | { RISCV_V0_REGNUM + 30, { "v30" } }, | |
621 | { RISCV_V0_REGNUM + 31, { "v31" } }, | |
622 | }; | |
623 | } | |
624 | ||
625 | /* Return the preferred name for the register with gdb register number | |
626 | REGNUM, which must be in the inclusive range RISCV_V0_REGNUM to | |
627 | RISCV_V0_REGNUM + 31. */ | |
628 | const char *register_name (int regnum) const | |
629 | { | |
630 | gdb_assert (regnum >= RISCV_V0_REGNUM | |
631 | && regnum <= RISCV_V0_REGNUM + 31); | |
632 | regnum -= RISCV_V0_REGNUM; | |
633 | return m_registers[regnum].names[0]; | |
634 | } | |
635 | ||
636 | /* Check this feature within TDESC, record the registers from this | |
637 | feature into TDESC_DATA and update ALIASES and FEATURES. */ | |
638 | bool check (const struct target_desc *tdesc, | |
639 | struct tdesc_arch_data *tdesc_data, | |
640 | std::vector<riscv_pending_register_alias> *aliases, | |
641 | struct riscv_gdbarch_features *features) const | |
642 | { | |
643 | const struct tdesc_feature *feature_vector = tdesc_feature (tdesc); | |
644 | ||
645 | /* It's fine if this feature is missing. Update the architecture | |
646 | feature set and return. */ | |
647 | if (feature_vector == nullptr) | |
648 | { | |
649 | features->vlen = 0; | |
650 | return true; | |
651 | } | |
652 | ||
653 | /* Check all of the vector registers are present. */ | |
654 | for (const auto ® : m_registers) | |
655 | { | |
656 | if (!reg.check (tdesc_data, feature_vector, true, aliases)) | |
657 | return false; | |
658 | } | |
659 | ||
660 | /* Look through all of the vector registers and check they all have the | |
661 | same bitsize. Use this bitsize to update the feature set for this | |
662 | gdbarch. */ | |
663 | int vector_bitsize = -1; | |
664 | for (const auto ® : m_registers) | |
665 | { | |
666 | int reg_bitsize = -1; | |
667 | for (const char *name : reg.names) | |
668 | { | |
669 | if (tdesc_unnumbered_register (feature_vector, name)) | |
670 | { | |
671 | reg_bitsize = tdesc_register_bitsize (feature_vector, name); | |
672 | break; | |
673 | } | |
674 | } | |
675 | gdb_assert (reg_bitsize != -1); | |
676 | if (vector_bitsize == -1) | |
677 | vector_bitsize = reg_bitsize; | |
678 | else if (vector_bitsize != reg_bitsize) | |
679 | return false; | |
680 | } | |
681 | ||
682 | features->vlen = (vector_bitsize / 8); | |
683 | return true; | |
684 | } | |
685 | }; | |
686 | ||
687 | /* An instance of the v-register feature set. */ | |
688 | ||
689 | static const struct riscv_vector_feature riscv_vector_feature; | |
690 | ||
dbbb1059 AB |
691 | /* Controls whether we place compressed breakpoints or not. When in auto |
692 | mode GDB tries to determine if the target supports compressed | |
693 | breakpoints, and uses them if it does. */ | |
694 | ||
695 | static enum auto_boolean use_compressed_breakpoints; | |
696 | ||
697 | /* The show callback for 'show riscv use-compressed-breakpoints'. */ | |
698 | ||
699 | static void | |
700 | show_use_compressed_breakpoints (struct ui_file *file, int from_tty, | |
701 | struct cmd_list_element *c, | |
702 | const char *value) | |
703 | { | |
6cb06a8c TT |
704 | gdb_printf (file, |
705 | _("Debugger's use of compressed breakpoints is set " | |
706 | "to %s.\n"), value); | |
dbbb1059 AB |
707 | } |
708 | ||
709 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ | |
710 | ||
711 | static struct cmd_list_element *setriscvcmdlist = NULL; | |
712 | static struct cmd_list_element *showriscvcmdlist = NULL; | |
713 | ||
dbbb1059 AB |
714 | /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */ |
715 | ||
716 | static struct cmd_list_element *setdebugriscvcmdlist = NULL; | |
717 | static struct cmd_list_element *showdebugriscvcmdlist = NULL; | |
718 | ||
dbbb1059 AB |
719 | /* The show callback for all 'show debug riscv VARNAME' variables. */ |
720 | ||
721 | static void | |
722 | show_riscv_debug_variable (struct ui_file *file, int from_tty, | |
723 | struct cmd_list_element *c, | |
724 | const char *value) | |
725 | { | |
6cb06a8c TT |
726 | gdb_printf (file, |
727 | _("RiscV debug variable `%s' is set to: %s\n"), | |
728 | c->name, value); | |
dbbb1059 AB |
729 | } |
730 | ||
8a613826 | 731 | /* See riscv-tdep.h. */ |
dbbb1059 | 732 | |
411baa47 | 733 | int |
dbbb1059 AB |
734 | riscv_isa_xlen (struct gdbarch *gdbarch) |
735 | { | |
345bd07c SM |
736 | riscv_gdbarch_tdep *tdep = (riscv_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
737 | return tdep->isa_features.xlen; | |
113b7b81 AB |
738 | } |
739 | ||
740 | /* See riscv-tdep.h. */ | |
741 | ||
742 | int | |
743 | riscv_abi_xlen (struct gdbarch *gdbarch) | |
744 | { | |
345bd07c SM |
745 | riscv_gdbarch_tdep *tdep = (riscv_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
746 | return tdep->abi_features.xlen; | |
dbbb1059 AB |
747 | } |
748 | ||
8a613826 | 749 | /* See riscv-tdep.h. */ |
dbbb1059 | 750 | |
8a613826 | 751 | int |
dbbb1059 AB |
752 | riscv_isa_flen (struct gdbarch *gdbarch) |
753 | { | |
345bd07c SM |
754 | riscv_gdbarch_tdep *tdep = (riscv_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
755 | return tdep->isa_features.flen; | |
113b7b81 AB |
756 | } |
757 | ||
758 | /* See riscv-tdep.h. */ | |
759 | ||
760 | int | |
761 | riscv_abi_flen (struct gdbarch *gdbarch) | |
762 | { | |
345bd07c SM |
763 | riscv_gdbarch_tdep *tdep = (riscv_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
764 | return tdep->abi_features.flen; | |
dbbb1059 AB |
765 | } |
766 | ||
25428040 AB |
767 | /* See riscv-tdep.h. */ |
768 | ||
769 | bool | |
770 | riscv_abi_embedded (struct gdbarch *gdbarch) | |
771 | { | |
345bd07c SM |
772 | riscv_gdbarch_tdep *tdep = (riscv_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
773 | return tdep->abi_features.embedded; | |
25428040 AB |
774 | } |
775 | ||
dbbb1059 AB |
776 | /* Return true if the target for GDBARCH has floating point hardware. */ |
777 | ||
778 | static bool | |
779 | riscv_has_fp_regs (struct gdbarch *gdbarch) | |
780 | { | |
781 | return (riscv_isa_flen (gdbarch) > 0); | |
782 | } | |
783 | ||
784 | /* Return true if GDBARCH is using any of the floating point hardware ABIs. */ | |
785 | ||
786 | static bool | |
787 | riscv_has_fp_abi (struct gdbarch *gdbarch) | |
788 | { | |
345bd07c SM |
789 | riscv_gdbarch_tdep *tdep = (riscv_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
790 | return tdep->abi_features.flen > 0; | |
dbbb1059 AB |
791 | } |
792 | ||
8c49aa89 AB |
793 | /* Return true if REGNO is a floating pointer register. */ |
794 | ||
795 | static bool | |
796 | riscv_is_fp_regno_p (int regno) | |
797 | { | |
798 | return (regno >= RISCV_FIRST_FP_REGNUM | |
799 | && regno <= RISCV_LAST_FP_REGNUM); | |
800 | } | |
801 | ||
dbbb1059 AB |
802 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
803 | ||
804 | static int | |
805 | riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
806 | { | |
807 | if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) | |
808 | { | |
3ba2ee38 | 809 | bool unaligned_p = false; |
f37bc8b1 JB |
810 | gdb_byte buf[1]; |
811 | ||
3ba2ee38 JW |
812 | /* Some targets don't support unaligned reads. The address can only |
813 | be unaligned if the C extension is supported. So it is safe to | |
814 | use a compressed breakpoint in this case. */ | |
815 | if (*pcptr & 0x2) | |
816 | unaligned_p = true; | |
817 | else | |
818 | { | |
c01660c6 AB |
819 | /* Read the opcode byte to determine the instruction length. If |
820 | the read fails this may be because we tried to set the | |
821 | breakpoint at an invalid address, in this case we provide a | |
822 | fake result which will give a breakpoint length of 4. | |
823 | Hopefully when we try to actually insert the breakpoint we | |
824 | will see a failure then too which will be reported to the | |
825 | user. */ | |
826 | if (target_read_code (*pcptr, buf, 1) == -1) | |
827 | buf[0] = 0; | |
3ba2ee38 | 828 | } |
f37bc8b1 JB |
829 | |
830 | if (riscv_debug_breakpoints) | |
3ba2ee38 JW |
831 | { |
832 | const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2 | |
833 | ? "C.EBREAK" : "EBREAK"); | |
834 | ||
6cb06a8c TT |
835 | gdb_printf (gdb_stdlog, "Using %s for breakpoint at %s ", |
836 | bp, paddress (gdbarch, *pcptr)); | |
3ba2ee38 | 837 | if (unaligned_p) |
6cb06a8c | 838 | gdb_printf (gdb_stdlog, "(unaligned address)\n"); |
3ba2ee38 | 839 | else |
6cb06a8c TT |
840 | gdb_printf (gdb_stdlog, "(instruction length %d)\n", |
841 | riscv_insn_length (buf[0])); | |
3ba2ee38 JW |
842 | } |
843 | if (unaligned_p || riscv_insn_length (buf[0]) == 2) | |
dbbb1059 AB |
844 | return 2; |
845 | else | |
846 | return 4; | |
847 | } | |
848 | else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE) | |
849 | return 2; | |
850 | else | |
851 | return 4; | |
852 | } | |
853 | ||
854 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ | |
855 | ||
856 | static const gdb_byte * | |
857 | riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
858 | { | |
859 | static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, }; | |
860 | static const gdb_byte c_ebreak[] = { 0x02, 0x90 }; | |
861 | ||
862 | *size = kind; | |
863 | switch (kind) | |
864 | { | |
865 | case 2: | |
866 | return c_ebreak; | |
867 | case 4: | |
868 | return ebreak; | |
869 | default: | |
557b4d76 | 870 | gdb_assert_not_reached ("unhandled breakpoint kind"); |
dbbb1059 AB |
871 | } |
872 | } | |
873 | ||
b5ffee31 AB |
874 | /* Implement the register_name gdbarch method. This is used instead of |
875 | the function supplied by calling TDESC_USE_REGISTERS so that we can | |
ed69cbc8 | 876 | ensure the preferred names are offered for x-regs and f-regs. */ |
dbbb1059 AB |
877 | |
878 | static const char * | |
879 | riscv_register_name (struct gdbarch *gdbarch, int regnum) | |
880 | { | |
b5ffee31 AB |
881 | /* Lookup the name through the target description. If we get back NULL |
882 | then this is an unknown register. If we do get a name back then we | |
883 | look up the registers preferred name below. */ | |
884 | const char *name = tdesc_register_name (gdbarch, regnum); | |
885 | if (name == NULL || name[0] == '\0') | |
886 | return NULL; | |
887 | ||
ed69cbc8 AB |
888 | /* We want GDB to use the ABI names for registers even if the target |
889 | gives us a target description with the architectural name. For | |
890 | example we want to see 'ra' instead of 'x1' whatever the target | |
891 | description called it. */ | |
b5ffee31 | 892 | if (regnum >= RISCV_ZERO_REGNUM && regnum < RISCV_FIRST_FP_REGNUM) |
25428040 | 893 | return riscv_xreg_feature.register_name (regnum); |
b5ffee31 | 894 | |
ed69cbc8 AB |
895 | /* Like with the x-regs we prefer the abi names for the floating point |
896 | registers. */ | |
b5ffee31 | 897 | if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM) |
dbbb1059 | 898 | { |
b5ffee31 | 899 | if (riscv_has_fp_regs (gdbarch)) |
25428040 | 900 | return riscv_freg_feature.register_name (regnum); |
b5ffee31 | 901 | else |
dda83cd7 | 902 | return NULL; |
dbbb1059 AB |
903 | } |
904 | ||
2e52d038 AB |
905 | /* Some targets (QEMU) are reporting these three registers twice, once |
906 | in the FPU feature, and once in the CSR feature. Both of these read | |
907 | the same underlying state inside the target, but naming the register | |
908 | twice in the target description results in GDB having two registers | |
909 | with the same name, only one of which can ever be accessed, but both | |
910 | will show up in 'info register all'. Unless, we identify the | |
911 | duplicate copies of these registers (in riscv_tdesc_unknown_reg) and | |
912 | then hide the registers here by giving them no name. */ | |
345bd07c | 913 | riscv_gdbarch_tdep *tdep = (riscv_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
2e52d038 AB |
914 | if (tdep->duplicate_fflags_regnum == regnum) |
915 | return NULL; | |
916 | if (tdep->duplicate_frm_regnum == regnum) | |
917 | return NULL; | |
918 | if (tdep->duplicate_fcsr_regnum == regnum) | |
919 | return NULL; | |
920 | ||
ed69cbc8 AB |
921 | /* The remaining registers are different. For all other registers on the |
922 | machine we prefer to see the names that the target description | |
923 | provides. This is particularly important for CSRs which might be | |
924 | renamed over time. If GDB keeps track of the "latest" name, but a | |
925 | particular target provides an older name then we don't want to force | |
926 | users to see the newer name in register output. | |
dbbb1059 | 927 | |
ed69cbc8 AB |
928 | The other case that reaches here are any registers that the target |
929 | provided that GDB is completely unaware of. For these we have no | |
930 | choice but to accept the target description name. | |
dbbb1059 | 931 | |
ed69cbc8 | 932 | Just accept whatever name TDESC_REGISTER_NAME returned. */ |
b5ffee31 | 933 | return name; |
dbbb1059 AB |
934 | } |
935 | ||
270b9329 JW |
936 | /* Construct a type for 64-bit FP registers. */ |
937 | ||
938 | static struct type * | |
939 | riscv_fpreg_d_type (struct gdbarch *gdbarch) | |
940 | { | |
345bd07c | 941 | riscv_gdbarch_tdep *tdep = (riscv_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
270b9329 JW |
942 | |
943 | if (tdep->riscv_fpreg_d_type == nullptr) | |
944 | { | |
945 | const struct builtin_type *bt = builtin_type (gdbarch); | |
946 | ||
947 | /* The type we're building is this: */ | |
948 | #if 0 | |
949 | union __gdb_builtin_type_fpreg_d | |
950 | { | |
951 | float f; | |
952 | double d; | |
953 | }; | |
954 | #endif | |
955 | ||
956 | struct type *t; | |
957 | ||
958 | t = arch_composite_type (gdbarch, | |
959 | "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION); | |
960 | append_composite_type_field (t, "float", bt->builtin_float); | |
961 | append_composite_type_field (t, "double", bt->builtin_double); | |
2062087b | 962 | t->set_is_vector (true); |
d0e39ea2 | 963 | t->set_name ("builtin_type_fpreg_d"); |
270b9329 JW |
964 | tdep->riscv_fpreg_d_type = t; |
965 | } | |
966 | ||
967 | return tdep->riscv_fpreg_d_type; | |
968 | } | |
969 | ||
b5ffee31 AB |
970 | /* Implement the register_type gdbarch method. This is installed as an |
971 | for the override setup by TDESC_USE_REGISTERS, for most registers we | |
972 | delegate the type choice to the target description, but for a few | |
973 | registers we try to improve the types if the target description has | |
974 | taken a simplistic approach. */ | |
270b9329 JW |
975 | |
976 | static struct type * | |
b5ffee31 | 977 | riscv_register_type (struct gdbarch *gdbarch, int regnum) |
270b9329 | 978 | { |
b5ffee31 AB |
979 | struct type *type = tdesc_register_type (gdbarch, regnum); |
980 | int xlen = riscv_isa_xlen (gdbarch); | |
270b9329 | 981 | |
b5ffee31 AB |
982 | /* We want to perform some specific type "fixes" in cases where we feel |
983 | that we really can do better than the target description. For all | |
984 | other cases we just return what the target description says. */ | |
985 | if (riscv_is_fp_regno_p (regnum)) | |
270b9329 | 986 | { |
b5ffee31 | 987 | /* This spots the case for RV64 where the double is defined as |
dda83cd7 SM |
988 | either 'ieee_double' or 'float' (which is the generic name that |
989 | converts to 'double' on 64-bit). In these cases its better to | |
990 | present the registers using a union type. */ | |
b5ffee31 AB |
991 | int flen = riscv_isa_flen (gdbarch); |
992 | if (flen == 8 | |
dda83cd7 SM |
993 | && type->code () == TYPE_CODE_FLT |
994 | && TYPE_LENGTH (type) == flen | |
995 | && (strcmp (type->name (), "builtin_type_ieee_double") == 0 | |
996 | || strcmp (type->name (), "double") == 0)) | |
997 | type = riscv_fpreg_d_type (gdbarch); | |
270b9329 JW |
998 | } |
999 | ||
b5ffee31 AB |
1000 | if ((regnum == gdbarch_pc_regnum (gdbarch) |
1001 | || regnum == RISCV_RA_REGNUM | |
1002 | || regnum == RISCV_FP_REGNUM | |
1003 | || regnum == RISCV_SP_REGNUM | |
1004 | || regnum == RISCV_GP_REGNUM | |
1005 | || regnum == RISCV_TP_REGNUM) | |
78134374 | 1006 | && type->code () == TYPE_CODE_INT |
b5ffee31 | 1007 | && TYPE_LENGTH (type) == xlen) |
dbbb1059 | 1008 | { |
b5ffee31 | 1009 | /* This spots the case where some interesting registers are defined |
dda83cd7 SM |
1010 | as simple integers of the expected size, we force these registers |
1011 | to be pointers as we believe that is more useful. */ | |
dbbb1059 | 1012 | if (regnum == gdbarch_pc_regnum (gdbarch) |
dda83cd7 SM |
1013 | || regnum == RISCV_RA_REGNUM) |
1014 | type = builtin_type (gdbarch)->builtin_func_ptr; | |
b5ffee31 | 1015 | else if (regnum == RISCV_FP_REGNUM |
dda83cd7 SM |
1016 | || regnum == RISCV_SP_REGNUM |
1017 | || regnum == RISCV_GP_REGNUM | |
1018 | || regnum == RISCV_TP_REGNUM) | |
b5ffee31 | 1019 | type = builtin_type (gdbarch)->builtin_data_ptr; |
dbbb1059 | 1020 | } |
dbbb1059 | 1021 | |
b5ffee31 | 1022 | return type; |
dbbb1059 AB |
1023 | } |
1024 | ||
1025 | /* Helper for riscv_print_registers_info, prints info for a single register | |
1026 | REGNUM. */ | |
1027 | ||
1028 | static void | |
1029 | riscv_print_one_register_info (struct gdbarch *gdbarch, | |
1030 | struct ui_file *file, | |
1031 | struct frame_info *frame, | |
1032 | int regnum) | |
1033 | { | |
1034 | const char *name = gdbarch_register_name (gdbarch, regnum); | |
b5ffee31 AB |
1035 | struct value *val; |
1036 | struct type *regtype; | |
dbbb1059 AB |
1037 | int print_raw_format; |
1038 | enum tab_stops { value_column_1 = 15 }; | |
1039 | ||
0426ad51 | 1040 | gdb_puts (name, file); |
d0b1020b | 1041 | print_spaces (value_column_1 - strlen (name), file); |
dbbb1059 | 1042 | |
a70b8144 | 1043 | try |
b5ffee31 AB |
1044 | { |
1045 | val = value_of_register (regnum, frame); | |
1046 | regtype = value_type (val); | |
1047 | } | |
230d2906 | 1048 | catch (const gdb_exception_error &ex) |
b5ffee31 AB |
1049 | { |
1050 | /* Handle failure to read a register without interrupting the entire | |
dda83cd7 | 1051 | 'info registers' flow. */ |
6cb06a8c | 1052 | gdb_printf (file, "%s\n", ex.what ()); |
b5ffee31 AB |
1053 | return; |
1054 | } | |
b5ffee31 | 1055 | |
dbbb1059 AB |
1056 | print_raw_format = (value_entirely_available (val) |
1057 | && !value_optimized_out (val)); | |
1058 | ||
78134374 SM |
1059 | if (regtype->code () == TYPE_CODE_FLT |
1060 | || (regtype->code () == TYPE_CODE_UNION | |
1f704f76 | 1061 | && regtype->num_fields () == 2 |
940da03e SM |
1062 | && regtype->field (0).type ()->code () == TYPE_CODE_FLT |
1063 | && regtype->field (1).type ()->code () == TYPE_CODE_FLT) | |
78134374 | 1064 | || (regtype->code () == TYPE_CODE_UNION |
1f704f76 | 1065 | && regtype->num_fields () == 3 |
940da03e SM |
1066 | && regtype->field (0).type ()->code () == TYPE_CODE_FLT |
1067 | && regtype->field (1).type ()->code () == TYPE_CODE_FLT | |
1068 | && regtype->field (2).type ()->code () == TYPE_CODE_FLT)) | |
dbbb1059 AB |
1069 | { |
1070 | struct value_print_options opts; | |
50888e42 | 1071 | const gdb_byte *valaddr = value_contents_for_printing (val).data (); |
34877895 | 1072 | enum bfd_endian byte_order = type_byte_order (regtype); |
dbbb1059 AB |
1073 | |
1074 | get_user_print_options (&opts); | |
1075 | opts.deref_ref = 1; | |
1076 | ||
040f66bd | 1077 | common_val_print (val, file, 0, &opts, current_language); |
dbbb1059 AB |
1078 | |
1079 | if (print_raw_format) | |
1080 | { | |
6cb06a8c | 1081 | gdb_printf (file, "\t(raw "); |
dbbb1059 AB |
1082 | print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order, |
1083 | true); | |
6cb06a8c | 1084 | gdb_printf (file, ")"); |
dbbb1059 AB |
1085 | } |
1086 | } | |
1087 | else | |
1088 | { | |
1089 | struct value_print_options opts; | |
1090 | ||
1091 | /* Print the register in hex. */ | |
1092 | get_formatted_print_options (&opts, 'x'); | |
1093 | opts.deref_ref = 1; | |
040f66bd | 1094 | common_val_print (val, file, 0, &opts, current_language); |
dbbb1059 AB |
1095 | |
1096 | if (print_raw_format) | |
1097 | { | |
1098 | if (regnum == RISCV_CSR_MSTATUS_REGNUM) | |
1099 | { | |
1100 | LONGEST d; | |
1101 | int size = register_size (gdbarch, regnum); | |
1102 | unsigned xlen; | |
1103 | ||
b7c8601a JW |
1104 | /* The SD field is always in the upper bit of MSTATUS, regardless |
1105 | of the number of bits in MSTATUS. */ | |
dbbb1059 | 1106 | d = value_as_long (val); |
b7c8601a | 1107 | xlen = size * 8; |
6cb06a8c TT |
1108 | gdb_printf (file, |
1109 | "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X " | |
1110 | "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X " | |
1111 | "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X", | |
1112 | (int) ((d >> (xlen - 1)) & 0x1), | |
1113 | (int) ((d >> 24) & 0x1f), | |
1114 | (int) ((d >> 19) & 0x1), | |
1115 | (int) ((d >> 18) & 0x1), | |
1116 | (int) ((d >> 17) & 0x1), | |
1117 | (int) ((d >> 15) & 0x3), | |
1118 | (int) ((d >> 13) & 0x3), | |
1119 | (int) ((d >> 11) & 0x3), | |
1120 | (int) ((d >> 9) & 0x3), | |
1121 | (int) ((d >> 8) & 0x1), | |
1122 | (int) ((d >> 7) & 0x1), | |
1123 | (int) ((d >> 6) & 0x1), | |
1124 | (int) ((d >> 5) & 0x1), | |
1125 | (int) ((d >> 4) & 0x1), | |
1126 | (int) ((d >> 3) & 0x1), | |
1127 | (int) ((d >> 2) & 0x1), | |
1128 | (int) ((d >> 1) & 0x1), | |
1129 | (int) ((d >> 0) & 0x1)); | |
dbbb1059 AB |
1130 | } |
1131 | else if (regnum == RISCV_CSR_MISA_REGNUM) | |
1132 | { | |
1133 | int base; | |
1134 | unsigned xlen, i; | |
1135 | LONGEST d; | |
b7c8601a | 1136 | int size = register_size (gdbarch, regnum); |
dbbb1059 | 1137 | |
b7c8601a JW |
1138 | /* The MXL field is always in the upper two bits of MISA, |
1139 | regardless of the number of bits in MISA. Mask out other | |
1140 | bits to ensure we have a positive value. */ | |
dbbb1059 | 1141 | d = value_as_long (val); |
b7c8601a | 1142 | base = (d >> ((size * 8) - 2)) & 0x3; |
dbbb1059 AB |
1143 | xlen = 16; |
1144 | ||
1145 | for (; base > 0; base--) | |
1146 | xlen *= 2; | |
6cb06a8c | 1147 | gdb_printf (file, "\tRV%d", xlen); |
dbbb1059 AB |
1148 | |
1149 | for (i = 0; i < 26; i++) | |
1150 | { | |
1151 | if (d & (1 << i)) | |
6cb06a8c | 1152 | gdb_printf (file, "%c", 'A' + i); |
dbbb1059 AB |
1153 | } |
1154 | } | |
1155 | else if (regnum == RISCV_CSR_FCSR_REGNUM | |
1156 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
1157 | || regnum == RISCV_CSR_FRM_REGNUM) | |
1158 | { | |
1159 | LONGEST d; | |
1160 | ||
1161 | d = value_as_long (val); | |
1162 | ||
6cb06a8c | 1163 | gdb_printf (file, "\t"); |
dbbb1059 | 1164 | if (regnum != RISCV_CSR_FRM_REGNUM) |
6cb06a8c TT |
1165 | gdb_printf (file, |
1166 | "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d", | |
1167 | (int) ((d >> 5) & 0x7), | |
1168 | (int) ((d >> 4) & 0x1), | |
1169 | (int) ((d >> 3) & 0x1), | |
1170 | (int) ((d >> 2) & 0x1), | |
1171 | (int) ((d >> 1) & 0x1), | |
1172 | (int) ((d >> 0) & 0x1)); | |
dbbb1059 AB |
1173 | |
1174 | if (regnum != RISCV_CSR_FFLAGS_REGNUM) | |
1175 | { | |
1176 | static const char * const sfrm[] = | |
1177 | { | |
1178 | "RNE (round to nearest; ties to even)", | |
1179 | "RTZ (Round towards zero)", | |
1180 | "RDN (Round down towards -INF)", | |
1181 | "RUP (Round up towards +INF)", | |
1182 | "RMM (Round to nearest; ties to max magnitude)", | |
1183 | "INVALID[5]", | |
1184 | "INVALID[6]", | |
1185 | "dynamic rounding mode", | |
1186 | }; | |
1187 | int frm = ((regnum == RISCV_CSR_FCSR_REGNUM) | |
1188 | ? (d >> 5) : d) & 0x3; | |
1189 | ||
6cb06a8c TT |
1190 | gdb_printf (file, "%sFRM:%i [%s]", |
1191 | (regnum == RISCV_CSR_FCSR_REGNUM | |
1192 | ? " " : ""), | |
1193 | frm, sfrm[frm]); | |
dbbb1059 AB |
1194 | } |
1195 | } | |
1196 | else if (regnum == RISCV_PRIV_REGNUM) | |
1197 | { | |
1198 | LONGEST d; | |
1199 | uint8_t priv; | |
1200 | ||
1201 | d = value_as_long (val); | |
1202 | priv = d & 0xff; | |
1203 | ||
1204 | if (priv < 4) | |
1205 | { | |
1206 | static const char * const sprv[] = | |
1207 | { | |
1208 | "User/Application", | |
1209 | "Supervisor", | |
1210 | "Hypervisor", | |
1211 | "Machine" | |
1212 | }; | |
6cb06a8c TT |
1213 | gdb_printf (file, "\tprv:%d [%s]", |
1214 | priv, sprv[priv]); | |
dbbb1059 AB |
1215 | } |
1216 | else | |
6cb06a8c | 1217 | gdb_printf (file, "\tprv:%d [INVALID]", priv); |
dbbb1059 AB |
1218 | } |
1219 | else | |
1220 | { | |
1221 | /* If not a vector register, print it also according to its | |
1222 | natural format. */ | |
bd63c870 | 1223 | if (regtype->is_vector () == 0) |
dbbb1059 AB |
1224 | { |
1225 | get_user_print_options (&opts); | |
1226 | opts.deref_ref = 1; | |
6cb06a8c | 1227 | gdb_printf (file, "\t"); |
040f66bd | 1228 | common_val_print (val, file, 0, &opts, current_language); |
dbbb1059 AB |
1229 | } |
1230 | } | |
1231 | } | |
1232 | } | |
6cb06a8c | 1233 | gdb_printf (file, "\n"); |
dbbb1059 AB |
1234 | } |
1235 | ||
0dbfcfff AB |
1236 | /* Return true if REGNUM is a valid CSR register. The CSR register space |
1237 | is sparsely populated, so not every number is a named CSR. */ | |
1238 | ||
1239 | static bool | |
1240 | riscv_is_regnum_a_named_csr (int regnum) | |
1241 | { | |
1242 | gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM | |
1243 | && regnum <= RISCV_LAST_CSR_REGNUM); | |
1244 | ||
1245 | switch (regnum) | |
1246 | { | |
8f595e9b | 1247 | #define DECLARE_CSR(name, num, class, define_ver, abort_ver) case RISCV_ ## num ## _REGNUM: |
0dbfcfff AB |
1248 | #include "opcode/riscv-opc.h" |
1249 | #undef DECLARE_CSR | |
1250 | return true; | |
1251 | ||
1252 | default: | |
1253 | return false; | |
1254 | } | |
1255 | } | |
1256 | ||
e4502042 AB |
1257 | /* Return true if REGNUM is an unknown CSR identified in |
1258 | riscv_tdesc_unknown_reg for GDBARCH. */ | |
1259 | ||
1260 | static bool | |
1261 | riscv_is_unknown_csr (struct gdbarch *gdbarch, int regnum) | |
1262 | { | |
345bd07c | 1263 | riscv_gdbarch_tdep *tdep = (riscv_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
e4502042 AB |
1264 | return (regnum >= tdep->unknown_csrs_first_regnum |
1265 | && regnum < (tdep->unknown_csrs_first_regnum | |
1266 | + tdep->unknown_csrs_count)); | |
1267 | } | |
1268 | ||
dbbb1059 AB |
1269 | /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member |
1270 | of REGGROUP? */ | |
1271 | ||
1272 | static int | |
1273 | riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
1274 | struct reggroup *reggroup) | |
1275 | { | |
dbbb1059 AB |
1276 | /* Used by 'info registers' and 'info registers <groupname>'. */ |
1277 | ||
1278 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
1279 | || gdbarch_register_name (gdbarch, regnum)[0] == '\0') | |
1280 | return 0; | |
1281 | ||
b5ffee31 AB |
1282 | if (regnum > RISCV_LAST_REGNUM) |
1283 | { | |
2e52d038 AB |
1284 | /* Any extra registers from the CSR tdesc_feature (identified in |
1285 | riscv_tdesc_unknown_reg) are removed from the save/restore groups | |
e4502042 AB |
1286 | as some targets (QEMU) report CSRs which then can't be read and |
1287 | having unreadable registers in the save/restore group breaks | |
1288 | things like inferior calls. | |
1289 | ||
1290 | The unknown CSRs are also removed from the general group, and | |
1291 | added into both the csr and system group. This is inline with the | |
1292 | known CSRs (see below). */ | |
1293 | if (riscv_is_unknown_csr (gdbarch, regnum)) | |
1294 | { | |
1295 | if (reggroup == restore_reggroup || reggroup == save_reggroup | |
1296 | || reggroup == general_reggroup) | |
1297 | return 0; | |
1298 | else if (reggroup == system_reggroup || reggroup == csr_reggroup) | |
1299 | return 1; | |
1300 | } | |
2e52d038 AB |
1301 | |
1302 | /* This is some other unknown register from the target description. | |
1303 | In this case we trust whatever the target description says about | |
1304 | which groups this register should be in. */ | |
b5ffee31 AB |
1305 | int ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup); |
1306 | if (ret != -1) | |
dda83cd7 | 1307 | return ret; |
b5ffee31 AB |
1308 | |
1309 | return default_register_reggroup_p (gdbarch, regnum, reggroup); | |
1310 | } | |
1311 | ||
dbbb1059 AB |
1312 | if (reggroup == all_reggroup) |
1313 | { | |
96f842cb | 1314 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum >= RISCV_PRIV_REGNUM) |
dbbb1059 | 1315 | return 1; |
0dbfcfff | 1316 | if (riscv_is_regnum_a_named_csr (regnum)) |
dda83cd7 | 1317 | return 1; |
dbbb1059 AB |
1318 | return 0; |
1319 | } | |
1320 | else if (reggroup == float_reggroup) | |
8c49aa89 AB |
1321 | return (riscv_is_fp_regno_p (regnum) |
1322 | || regnum == RISCV_CSR_FCSR_REGNUM | |
1323 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
1324 | || regnum == RISCV_CSR_FRM_REGNUM); | |
dbbb1059 AB |
1325 | else if (reggroup == general_reggroup) |
1326 | return regnum < RISCV_FIRST_FP_REGNUM; | |
1327 | else if (reggroup == restore_reggroup || reggroup == save_reggroup) | |
1328 | { | |
1329 | if (riscv_has_fp_regs (gdbarch)) | |
ecc82c05 AB |
1330 | return (regnum <= RISCV_LAST_FP_REGNUM |
1331 | || regnum == RISCV_CSR_FCSR_REGNUM | |
1332 | || regnum == RISCV_CSR_FFLAGS_REGNUM | |
1333 | || regnum == RISCV_CSR_FRM_REGNUM); | |
dbbb1059 AB |
1334 | else |
1335 | return regnum < RISCV_FIRST_FP_REGNUM; | |
1336 | } | |
b5ffee31 | 1337 | else if (reggroup == system_reggroup || reggroup == csr_reggroup) |
dbbb1059 AB |
1338 | { |
1339 | if (regnum == RISCV_PRIV_REGNUM) | |
1340 | return 1; | |
1341 | if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM) | |
1342 | return 0; | |
0dbfcfff | 1343 | if (riscv_is_regnum_a_named_csr (regnum)) |
dda83cd7 | 1344 | return 1; |
dbbb1059 AB |
1345 | return 0; |
1346 | } | |
1347 | else if (reggroup == vector_reggroup) | |
96f842cb | 1348 | return (regnum >= RISCV_V0_REGNUM && regnum <= RISCV_V31_REGNUM); |
dbbb1059 AB |
1349 | else |
1350 | return 0; | |
1351 | } | |
1352 | ||
1353 | /* Implement the print_registers_info gdbarch method. This is used by | |
1354 | 'info registers' and 'info all-registers'. */ | |
1355 | ||
1356 | static void | |
1357 | riscv_print_registers_info (struct gdbarch *gdbarch, | |
1358 | struct ui_file *file, | |
1359 | struct frame_info *frame, | |
1360 | int regnum, int print_all) | |
1361 | { | |
1362 | if (regnum != -1) | |
1363 | { | |
1364 | /* Print one specified register. */ | |
dbbb1059 AB |
1365 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
1366 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
dda83cd7 | 1367 | error (_("Not a valid register for the current processor type")); |
dbbb1059 AB |
1368 | riscv_print_one_register_info (gdbarch, file, frame, regnum); |
1369 | } | |
1370 | else | |
1371 | { | |
1372 | struct reggroup *reggroup; | |
1373 | ||
1374 | if (print_all) | |
1375 | reggroup = all_reggroup; | |
1376 | else | |
1377 | reggroup = general_reggroup; | |
1378 | ||
6d74da72 | 1379 | for (regnum = 0; regnum < gdbarch_num_cooked_regs (gdbarch); ++regnum) |
dbbb1059 AB |
1380 | { |
1381 | /* Zero never changes, so might as well hide by default. */ | |
1382 | if (regnum == RISCV_ZERO_REGNUM && !print_all) | |
1383 | continue; | |
1384 | ||
1385 | /* Registers with no name are not valid on this ISA. */ | |
1386 | if (gdbarch_register_name (gdbarch, regnum) == NULL | |
1387 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
1388 | continue; | |
1389 | ||
1390 | /* Is the register in the group we're interested in? */ | |
b5ffee31 | 1391 | if (!gdbarch_register_reggroup_p (gdbarch, regnum, reggroup)) |
dbbb1059 AB |
1392 | continue; |
1393 | ||
1394 | riscv_print_one_register_info (gdbarch, file, frame, regnum); | |
1395 | } | |
1396 | } | |
1397 | } | |
1398 | ||
1399 | /* Class that handles one decoded RiscV instruction. */ | |
1400 | ||
1401 | class riscv_insn | |
1402 | { | |
1403 | public: | |
1404 | ||
1405 | /* Enum of all the opcodes that GDB cares about during the prologue scan. */ | |
1406 | enum opcode | |
1407 | { | |
1408 | /* Unknown value is used at initialisation time. */ | |
1409 | UNKNOWN = 0, | |
1410 | ||
1411 | /* These instructions are all the ones we are interested in during the | |
1412 | prologue scan. */ | |
1413 | ADD, | |
1414 | ADDI, | |
1415 | ADDIW, | |
1416 | ADDW, | |
1417 | AUIPC, | |
1418 | LUI, | |
1419 | SD, | |
1420 | SW, | |
a35606d9 LS |
1421 | LD, |
1422 | LW, | |
2b014cc5 | 1423 | MV, |
405feb71 | 1424 | /* These are needed for software breakpoint support. */ |
5c720ed8 JW |
1425 | JAL, |
1426 | JALR, | |
1427 | BEQ, | |
1428 | BNE, | |
1429 | BLT, | |
1430 | BGE, | |
1431 | BLTU, | |
1432 | BGEU, | |
1433 | /* These are needed for stepping over atomic sequences. */ | |
1434 | LR, | |
1435 | SC, | |
e843807b LS |
1436 | /* This instruction is used to do a syscall. */ |
1437 | ECALL, | |
dbbb1059 AB |
1438 | |
1439 | /* Other instructions are not interesting during the prologue scan, and | |
1440 | are ignored. */ | |
1441 | OTHER | |
1442 | }; | |
1443 | ||
1444 | riscv_insn () | |
1445 | : m_length (0), | |
1446 | m_opcode (OTHER), | |
1447 | m_rd (0), | |
1448 | m_rs1 (0), | |
1449 | m_rs2 (0) | |
1450 | { | |
1451 | /* Nothing. */ | |
1452 | } | |
1453 | ||
1454 | void decode (struct gdbarch *gdbarch, CORE_ADDR pc); | |
1455 | ||
1456 | /* Get the length of the instruction in bytes. */ | |
1457 | int length () const | |
1458 | { return m_length; } | |
1459 | ||
1460 | /* Get the opcode for this instruction. */ | |
1461 | enum opcode opcode () const | |
1462 | { return m_opcode; } | |
1463 | ||
1464 | /* Get destination register field for this instruction. This is only | |
1465 | valid if the OPCODE implies there is such a field for this | |
1466 | instruction. */ | |
1467 | int rd () const | |
1468 | { return m_rd; } | |
1469 | ||
1470 | /* Get the RS1 register field for this instruction. This is only valid | |
1471 | if the OPCODE implies there is such a field for this instruction. */ | |
1472 | int rs1 () const | |
1473 | { return m_rs1; } | |
1474 | ||
1475 | /* Get the RS2 register field for this instruction. This is only valid | |
1476 | if the OPCODE implies there is such a field for this instruction. */ | |
1477 | int rs2 () const | |
1478 | { return m_rs2; } | |
1479 | ||
1480 | /* Get the immediate for this instruction in signed form. This is only | |
1481 | valid if the OPCODE implies there is such a field for this | |
1482 | instruction. */ | |
1483 | int imm_signed () const | |
1484 | { return m_imm.s; } | |
1485 | ||
1486 | private: | |
1487 | ||
1488 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ | |
1489 | int decode_register_index (unsigned long opcode, int offset) | |
1490 | { | |
1491 | return (opcode >> offset) & 0x1F; | |
1492 | } | |
1493 | ||
5c720ed8 JW |
1494 | /* Extract 5 bit register field at OFFSET from instruction OPCODE. */ |
1495 | int decode_register_index_short (unsigned long opcode, int offset) | |
1496 | { | |
1497 | return ((opcode >> offset) & 0x7) + 8; | |
1498 | } | |
1499 | ||
dbbb1059 AB |
1500 | /* Helper for DECODE, decode 32-bit R-type instruction. */ |
1501 | void decode_r_type_insn (enum opcode opcode, ULONGEST ival) | |
1502 | { | |
1503 | m_opcode = opcode; | |
1504 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1505 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1506 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
1507 | } | |
1508 | ||
1509 | /* Helper for DECODE, decode 16-bit compressed R-type instruction. */ | |
1510 | void decode_cr_type_insn (enum opcode opcode, ULONGEST ival) | |
1511 | { | |
1512 | m_opcode = opcode; | |
1513 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); | |
1514 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); | |
1515 | } | |
1516 | ||
1517 | /* Helper for DECODE, decode 32-bit I-type instruction. */ | |
1518 | void decode_i_type_insn (enum opcode opcode, ULONGEST ival) | |
1519 | { | |
1520 | m_opcode = opcode; | |
1521 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1522 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1523 | m_imm.s = EXTRACT_ITYPE_IMM (ival); | |
1524 | } | |
1525 | ||
1526 | /* Helper for DECODE, decode 16-bit compressed I-type instruction. */ | |
1527 | void decode_ci_type_insn (enum opcode opcode, ULONGEST ival) | |
1528 | { | |
1529 | m_opcode = opcode; | |
1530 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S); | |
5a9f5403 | 1531 | m_imm.s = EXTRACT_CITYPE_IMM (ival); |
dbbb1059 AB |
1532 | } |
1533 | ||
a35606d9 LS |
1534 | /* Helper for DECODE, decode 16-bit compressed CL-type instruction. */ |
1535 | void decode_cl_type_insn (enum opcode opcode, ULONGEST ival) | |
1536 | { | |
1537 | m_opcode = opcode; | |
1538 | m_rd = decode_register_index_short (ival, OP_SH_CRS2S); | |
1539 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); | |
1540 | m_imm.s = EXTRACT_CLTYPE_IMM (ival); | |
1541 | } | |
1542 | ||
dbbb1059 AB |
1543 | /* Helper for DECODE, decode 32-bit S-type instruction. */ |
1544 | void decode_s_type_insn (enum opcode opcode, ULONGEST ival) | |
1545 | { | |
1546 | m_opcode = opcode; | |
1547 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1548 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
1549 | m_imm.s = EXTRACT_STYPE_IMM (ival); | |
1550 | } | |
1551 | ||
ff3a05b3 AB |
1552 | /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate |
1553 | encoding is different for each CS format instruction, so extracting | |
1554 | the immediate is left up to the caller, who should pass the extracted | |
1555 | immediate value through in IMM. */ | |
1556 | void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm) | |
1557 | { | |
1558 | m_opcode = opcode; | |
1559 | m_imm.s = imm; | |
1560 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); | |
1561 | m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S); | |
1562 | } | |
1563 | ||
1564 | /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate | |
1565 | encoding is different for each CSS format instruction, so extracting | |
1566 | the immediate is left up to the caller, who should pass the extracted | |
1567 | immediate value through in IMM. */ | |
1568 | void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm) | |
1569 | { | |
1570 | m_opcode = opcode; | |
1571 | m_imm.s = imm; | |
1572 | m_rs1 = RISCV_SP_REGNUM; | |
1573 | /* Not a compressed register number in this case. */ | |
1574 | m_rs2 = decode_register_index (ival, OP_SH_CRS2); | |
1575 | } | |
1576 | ||
dbbb1059 AB |
1577 | /* Helper for DECODE, decode 32-bit U-type instruction. */ |
1578 | void decode_u_type_insn (enum opcode opcode, ULONGEST ival) | |
1579 | { | |
1580 | m_opcode = opcode; | |
1581 | m_rd = decode_register_index (ival, OP_SH_RD); | |
1582 | m_imm.s = EXTRACT_UTYPE_IMM (ival); | |
1583 | } | |
1584 | ||
5c720ed8 JW |
1585 | /* Helper for DECODE, decode 32-bit J-type instruction. */ |
1586 | void decode_j_type_insn (enum opcode opcode, ULONGEST ival) | |
1587 | { | |
1588 | m_opcode = opcode; | |
1589 | m_rd = decode_register_index (ival, OP_SH_RD); | |
5a9f5403 | 1590 | m_imm.s = EXTRACT_JTYPE_IMM (ival); |
5c720ed8 JW |
1591 | } |
1592 | ||
1593 | /* Helper for DECODE, decode 32-bit J-type instruction. */ | |
1594 | void decode_cj_type_insn (enum opcode opcode, ULONGEST ival) | |
1595 | { | |
1596 | m_opcode = opcode; | |
5a9f5403 | 1597 | m_imm.s = EXTRACT_CJTYPE_IMM (ival); |
5c720ed8 JW |
1598 | } |
1599 | ||
1600 | void decode_b_type_insn (enum opcode opcode, ULONGEST ival) | |
1601 | { | |
1602 | m_opcode = opcode; | |
1603 | m_rs1 = decode_register_index (ival, OP_SH_RS1); | |
1604 | m_rs2 = decode_register_index (ival, OP_SH_RS2); | |
5a9f5403 | 1605 | m_imm.s = EXTRACT_BTYPE_IMM (ival); |
5c720ed8 JW |
1606 | } |
1607 | ||
1608 | void decode_cb_type_insn (enum opcode opcode, ULONGEST ival) | |
1609 | { | |
1610 | m_opcode = opcode; | |
1611 | m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S); | |
5a9f5403 | 1612 | m_imm.s = EXTRACT_CBTYPE_IMM (ival); |
5c720ed8 JW |
1613 | } |
1614 | ||
dbbb1059 AB |
1615 | /* Fetch instruction from target memory at ADDR, return the content of |
1616 | the instruction, and update LEN with the instruction length. */ | |
1617 | static ULONGEST fetch_instruction (struct gdbarch *gdbarch, | |
1618 | CORE_ADDR addr, int *len); | |
1619 | ||
1620 | /* The length of the instruction in bytes. Should be 2 or 4. */ | |
1621 | int m_length; | |
1622 | ||
1623 | /* The instruction opcode. */ | |
1624 | enum opcode m_opcode; | |
1625 | ||
1626 | /* The three possible registers an instruction might reference. Not | |
1627 | every instruction fills in all of these registers. Which fields are | |
1628 | valid depends on the opcode. The naming of these fields matches the | |
1629 | naming in the riscv isa manual. */ | |
1630 | int m_rd; | |
1631 | int m_rs1; | |
1632 | int m_rs2; | |
1633 | ||
1634 | /* Possible instruction immediate. This is only valid if the instruction | |
1635 | format contains an immediate, not all instruction, whether this is | |
1636 | valid depends on the opcode. Despite only having one format for now | |
1637 | the immediate is packed into a union, later instructions might require | |
1638 | an unsigned formatted immediate, having the union in place now will | |
1639 | reduce the need for code churn later. */ | |
1640 | union riscv_insn_immediate | |
1641 | { | |
1642 | riscv_insn_immediate () | |
1643 | : s (0) | |
1644 | { | |
1645 | /* Nothing. */ | |
1646 | } | |
1647 | ||
1648 | int s; | |
1649 | } m_imm; | |
1650 | }; | |
1651 | ||
1652 | /* Fetch instruction from target memory at ADDR, return the content of the | |
1653 | instruction, and update LEN with the instruction length. */ | |
1654 | ||
1655 | ULONGEST | |
1656 | riscv_insn::fetch_instruction (struct gdbarch *gdbarch, | |
1657 | CORE_ADDR addr, int *len) | |
1658 | { | |
1659 | enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch); | |
1660 | gdb_byte buf[8]; | |
1661 | int instlen, status; | |
1662 | ||
1663 | /* All insns are at least 16 bits. */ | |
1664 | status = target_read_memory (addr, buf, 2); | |
1665 | if (status) | |
1666 | memory_error (TARGET_XFER_E_IO, addr); | |
1667 | ||
1668 | /* If we need more, grab it now. */ | |
1669 | instlen = riscv_insn_length (buf[0]); | |
89a3b63e | 1670 | gdb_assert (instlen <= sizeof (buf)); |
dbbb1059 | 1671 | *len = instlen; |
89a3b63e AB |
1672 | |
1673 | if (instlen > 2) | |
dbbb1059 AB |
1674 | { |
1675 | status = target_read_memory (addr + 2, buf + 2, instlen - 2); | |
1676 | if (status) | |
1677 | memory_error (TARGET_XFER_E_IO, addr + 2); | |
1678 | } | |
1679 | ||
1680 | return extract_unsigned_integer (buf, instlen, byte_order); | |
1681 | } | |
1682 | ||
17cf2897 AB |
1683 | /* Fetch from target memory an instruction at PC and decode it. This can |
1684 | throw an error if the memory access fails, callers are responsible for | |
1685 | handling this error if that is appropriate. */ | |
dbbb1059 AB |
1686 | |
1687 | void | |
1688 | riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1689 | { | |
1690 | ULONGEST ival; | |
1691 | ||
1692 | /* Fetch the instruction, and the instructions length. */ | |
1693 | ival = fetch_instruction (gdbarch, pc, &m_length); | |
1694 | ||
1695 | if (m_length == 4) | |
1696 | { | |
1697 | if (is_add_insn (ival)) | |
1698 | decode_r_type_insn (ADD, ival); | |
1699 | else if (is_addw_insn (ival)) | |
1700 | decode_r_type_insn (ADDW, ival); | |
1701 | else if (is_addi_insn (ival)) | |
1702 | decode_i_type_insn (ADDI, ival); | |
1703 | else if (is_addiw_insn (ival)) | |
1704 | decode_i_type_insn (ADDIW, ival); | |
1705 | else if (is_auipc_insn (ival)) | |
1706 | decode_u_type_insn (AUIPC, ival); | |
1707 | else if (is_lui_insn (ival)) | |
1708 | decode_u_type_insn (LUI, ival); | |
1709 | else if (is_sd_insn (ival)) | |
1710 | decode_s_type_insn (SD, ival); | |
1711 | else if (is_sw_insn (ival)) | |
1712 | decode_s_type_insn (SW, ival); | |
5c720ed8 JW |
1713 | else if (is_jal_insn (ival)) |
1714 | decode_j_type_insn (JAL, ival); | |
1715 | else if (is_jalr_insn (ival)) | |
1716 | decode_i_type_insn (JALR, ival); | |
1717 | else if (is_beq_insn (ival)) | |
1718 | decode_b_type_insn (BEQ, ival); | |
1719 | else if (is_bne_insn (ival)) | |
1720 | decode_b_type_insn (BNE, ival); | |
1721 | else if (is_blt_insn (ival)) | |
1722 | decode_b_type_insn (BLT, ival); | |
1723 | else if (is_bge_insn (ival)) | |
1724 | decode_b_type_insn (BGE, ival); | |
1725 | else if (is_bltu_insn (ival)) | |
1726 | decode_b_type_insn (BLTU, ival); | |
1727 | else if (is_bgeu_insn (ival)) | |
1728 | decode_b_type_insn (BGEU, ival); | |
1729 | else if (is_lr_w_insn (ival)) | |
1730 | decode_r_type_insn (LR, ival); | |
1731 | else if (is_lr_d_insn (ival)) | |
1732 | decode_r_type_insn (LR, ival); | |
1733 | else if (is_sc_w_insn (ival)) | |
1734 | decode_r_type_insn (SC, ival); | |
1735 | else if (is_sc_d_insn (ival)) | |
1736 | decode_r_type_insn (SC, ival); | |
e843807b LS |
1737 | else if (is_ecall_insn (ival)) |
1738 | decode_i_type_insn (ECALL, ival); | |
a35606d9 LS |
1739 | else if (is_ld_insn (ival)) |
1740 | decode_i_type_insn (LD, ival); | |
1741 | else if (is_lw_insn (ival)) | |
1742 | decode_i_type_insn (LW, ival); | |
dbbb1059 AB |
1743 | else |
1744 | /* None of the other fields are valid in this case. */ | |
1745 | m_opcode = OTHER; | |
1746 | } | |
1747 | else if (m_length == 2) | |
1748 | { | |
5c720ed8 JW |
1749 | int xlen = riscv_isa_xlen (gdbarch); |
1750 | ||
1751 | /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a | |
1752 | C_JALR. So must try to match C_JALR first as it has more bits in | |
1753 | mask. */ | |
1754 | if (is_c_jalr_insn (ival)) | |
1755 | decode_cr_type_insn (JALR, ival); | |
1756 | else if (is_c_add_insn (ival)) | |
dbbb1059 | 1757 | decode_cr_type_insn (ADD, ival); |
5c720ed8 JW |
1758 | /* C_ADDW is RV64 and RV128 only. */ |
1759 | else if (xlen != 4 && is_c_addw_insn (ival)) | |
dbbb1059 AB |
1760 | decode_cr_type_insn (ADDW, ival); |
1761 | else if (is_c_addi_insn (ival)) | |
1762 | decode_ci_type_insn (ADDI, ival); | |
5c720ed8 JW |
1763 | /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128 |
1764 | only and C_JAL is RV32 only. */ | |
1765 | else if (xlen != 4 && is_c_addiw_insn (ival)) | |
dbbb1059 | 1766 | decode_ci_type_insn (ADDIW, ival); |
5c720ed8 JW |
1767 | else if (xlen == 4 && is_c_jal_insn (ival)) |
1768 | decode_cj_type_insn (JAL, ival); | |
1769 | /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a | |
1770 | C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits | |
1771 | in mask. */ | |
dbbb1059 AB |
1772 | else if (is_c_addi16sp_insn (ival)) |
1773 | { | |
1774 | m_opcode = ADDI; | |
1775 | m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD); | |
5a9f5403 | 1776 | m_imm.s = EXTRACT_CITYPE_ADDI16SP_IMM (ival); |
dbbb1059 | 1777 | } |
ff3a05b3 AB |
1778 | else if (is_c_addi4spn_insn (ival)) |
1779 | { | |
1780 | m_opcode = ADDI; | |
1781 | m_rd = decode_register_index_short (ival, OP_SH_CRS2S); | |
1782 | m_rs1 = RISCV_SP_REGNUM; | |
5a9f5403 | 1783 | m_imm.s = EXTRACT_CIWTYPE_ADDI4SPN_IMM (ival); |
ff3a05b3 | 1784 | } |
5c720ed8 | 1785 | else if (is_c_lui_insn (ival)) |
dda83cd7 SM |
1786 | { |
1787 | m_opcode = LUI; | |
1788 | m_rd = decode_register_index (ival, OP_SH_CRS1S); | |
5a9f5403 | 1789 | m_imm.s = EXTRACT_CITYPE_LUI_IMM (ival); |
dda83cd7 | 1790 | } |
5c720ed8 JW |
1791 | /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only, |
1792 | and C_FSW is RV32 only. */ | |
1793 | else if (xlen != 4 && is_c_sd_insn (ival)) | |
5a9f5403 | 1794 | decode_cs_type_insn (SD, ival, EXTRACT_CLTYPE_LD_IMM (ival)); |
5c720ed8 | 1795 | else if (is_c_sw_insn (ival)) |
5a9f5403 | 1796 | decode_cs_type_insn (SW, ival, EXTRACT_CLTYPE_LW_IMM (ival)); |
ff3a05b3 | 1797 | else if (is_c_swsp_insn (ival)) |
5a9f5403 | 1798 | decode_css_type_insn (SW, ival, EXTRACT_CSSTYPE_SWSP_IMM (ival)); |
ff3a05b3 | 1799 | else if (xlen != 4 && is_c_sdsp_insn (ival)) |
5a9f5403 | 1800 | decode_css_type_insn (SD, ival, EXTRACT_CSSTYPE_SDSP_IMM (ival)); |
5c720ed8 | 1801 | /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR. |
2b014cc5 | 1802 | So must try to match C_JR first as it has more bits in mask. */ |
5c720ed8 JW |
1803 | else if (is_c_jr_insn (ival)) |
1804 | decode_cr_type_insn (JALR, ival); | |
2b014cc5 LS |
1805 | else if (is_c_mv_insn (ival)) |
1806 | decode_cr_type_insn (MV, ival); | |
5c720ed8 JW |
1807 | else if (is_c_j_insn (ival)) |
1808 | decode_cj_type_insn (JAL, ival); | |
1809 | else if (is_c_beqz_insn (ival)) | |
1810 | decode_cb_type_insn (BEQ, ival); | |
1811 | else if (is_c_bnez_insn (ival)) | |
1812 | decode_cb_type_insn (BNE, ival); | |
a35606d9 LS |
1813 | else if (is_c_ld_insn (ival)) |
1814 | decode_cl_type_insn (LD, ival); | |
1815 | else if (is_c_lw_insn (ival)) | |
1816 | decode_cl_type_insn (LW, ival); | |
dbbb1059 AB |
1817 | else |
1818 | /* None of the other fields of INSN are valid in this case. */ | |
1819 | m_opcode = OTHER; | |
1820 | } | |
1821 | else | |
312617a3 AB |
1822 | { |
1823 | /* This must be a 6 or 8 byte instruction, we don't currently decode | |
1824 | any of these, so just ignore it. */ | |
1825 | gdb_assert (m_length == 6 || m_length == 8); | |
1826 | m_opcode = OTHER; | |
1827 | } | |
dbbb1059 AB |
1828 | } |
1829 | ||
1830 | /* The prologue scanner. This is currently only used for skipping the | |
1831 | prologue of a function when the DWARF information is not sufficient. | |
1832 | However, it is written with filling of the frame cache in mind, which | |
1833 | is why different groups of stack setup instructions are split apart | |
1834 | during the core of the inner loop. In the future, the intention is to | |
1835 | extend this function to fully support building up a frame cache that | |
1836 | can unwind register values when there is no DWARF information. */ | |
1837 | ||
1838 | static CORE_ADDR | |
1839 | riscv_scan_prologue (struct gdbarch *gdbarch, | |
78a3b0fa AB |
1840 | CORE_ADDR start_pc, CORE_ADDR end_pc, |
1841 | struct riscv_unwind_cache *cache) | |
dbbb1059 | 1842 | { |
78a3b0fa | 1843 | CORE_ADDR cur_pc, next_pc, after_prologue_pc; |
dbbb1059 AB |
1844 | CORE_ADDR end_prologue_addr = 0; |
1845 | ||
78a3b0fa AB |
1846 | /* Find an upper limit on the function prologue using the debug |
1847 | information. If the debug information could not be used to provide | |
1848 | that bound, then use an arbitrary large number as the upper bound. */ | |
1849 | after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc); | |
1850 | if (after_prologue_pc == 0) | |
1851 | after_prologue_pc = start_pc + 100; /* Arbitrary large number. */ | |
1852 | if (after_prologue_pc < end_pc) | |
1853 | end_pc = after_prologue_pc; | |
1854 | ||
1855 | pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */ | |
1856 | for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++) | |
1857 | regs[regno] = pv_register (regno, 0); | |
1858 | pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch)); | |
1859 | ||
1860 | if (riscv_debug_unwinder) | |
6cb06a8c | 1861 | gdb_printf |
78a3b0fa AB |
1862 | (gdb_stdlog, |
1863 | "Prologue scan for function starting at %s (limit %s)\n", | |
1864 | core_addr_to_string (start_pc), | |
1865 | core_addr_to_string (end_pc)); | |
1866 | ||
1867 | for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc) | |
dbbb1059 AB |
1868 | { |
1869 | struct riscv_insn insn; | |
1870 | ||
1871 | /* Decode the current instruction, and decide where the next | |
1872 | instruction lives based on the size of this instruction. */ | |
1873 | insn.decode (gdbarch, cur_pc); | |
1874 | gdb_assert (insn.length () > 0); | |
1875 | next_pc = cur_pc + insn.length (); | |
1876 | ||
1877 | /* Look for common stack adjustment insns. */ | |
1878 | if ((insn.opcode () == riscv_insn::ADDI | |
1879 | || insn.opcode () == riscv_insn::ADDIW) | |
1880 | && insn.rd () == RISCV_SP_REGNUM | |
1881 | && insn.rs1 () == RISCV_SP_REGNUM) | |
1882 | { | |
1883 | /* Handle: addi sp, sp, -i | |
1884 | or: addiw sp, sp, -i */ | |
dda83cd7 SM |
1885 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1886 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1887 | regs[insn.rd ()] | |
1888 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
dbbb1059 AB |
1889 | } |
1890 | else if ((insn.opcode () == riscv_insn::SW | |
1891 | || insn.opcode () == riscv_insn::SD) | |
1892 | && (insn.rs1 () == RISCV_SP_REGNUM | |
1893 | || insn.rs1 () == RISCV_FP_REGNUM)) | |
1894 | { | |
1895 | /* Handle: sw reg, offset(sp) | |
1896 | or: sd reg, offset(sp) | |
1897 | or: sw reg, offset(s0) | |
1898 | or: sd reg, offset(s0) */ | |
1899 | /* Instruction storing a register onto the stack. */ | |
dda83cd7 SM |
1900 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); |
1901 | gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS); | |
1902 | stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()), | |
1903 | (insn.opcode () == riscv_insn::SW ? 4 : 8), | |
1904 | regs[insn.rs2 ()]); | |
dbbb1059 AB |
1905 | } |
1906 | else if (insn.opcode () == riscv_insn::ADDI | |
1907 | && insn.rd () == RISCV_FP_REGNUM | |
1908 | && insn.rs1 () == RISCV_SP_REGNUM) | |
1909 | { | |
1910 | /* Handle: addi s0, sp, size */ | |
1911 | /* Instructions setting up the frame pointer. */ | |
dda83cd7 SM |
1912 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1913 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1914 | regs[insn.rd ()] | |
1915 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
dbbb1059 AB |
1916 | } |
1917 | else if ((insn.opcode () == riscv_insn::ADD | |
1918 | || insn.opcode () == riscv_insn::ADDW) | |
1919 | && insn.rd () == RISCV_FP_REGNUM | |
1920 | && insn.rs1 () == RISCV_SP_REGNUM | |
1921 | && insn.rs2 () == RISCV_ZERO_REGNUM) | |
1922 | { | |
1923 | /* Handle: add s0, sp, 0 | |
1924 | or: addw s0, sp, 0 */ | |
1925 | /* Instructions setting up the frame pointer. */ | |
dda83cd7 SM |
1926 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1927 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1928 | regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0); | |
dbbb1059 | 1929 | } |
d354055e | 1930 | else if ((insn.opcode () == riscv_insn::ADDI |
dda83cd7 SM |
1931 | && insn.rd () == RISCV_ZERO_REGNUM |
1932 | && insn.rs1 () == RISCV_ZERO_REGNUM | |
1933 | && insn.imm_signed () == 0)) | |
dbbb1059 | 1934 | { |
d354055e | 1935 | /* Handle: add x0, x0, 0 (NOP) */ |
dbbb1059 | 1936 | } |
d354055e | 1937 | else if (insn.opcode () == riscv_insn::AUIPC) |
dda83cd7 SM |
1938 | { |
1939 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1940 | regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ()); | |
1941 | } | |
d354055e | 1942 | else if (insn.opcode () == riscv_insn::LUI) |
dda83cd7 | 1943 | { |
d354055e | 1944 | /* Handle: lui REG, n |
dda83cd7 SM |
1945 | Where REG is not gp register. */ |
1946 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1947 | regs[insn.rd ()] = pv_constant (insn.imm_signed ()); | |
1948 | } | |
d354055e | 1949 | else if (insn.opcode () == riscv_insn::ADDI) |
dda83cd7 SM |
1950 | { |
1951 | /* Handle: addi REG1, REG2, IMM */ | |
1952 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1953 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1954 | regs[insn.rd ()] | |
1955 | = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()); | |
1956 | } | |
d354055e | 1957 | else if (insn.opcode () == riscv_insn::ADD) |
dda83cd7 | 1958 | { |
0a9bddab | 1959 | /* Handle: add REG1, REG2, REG3 */ |
dda83cd7 SM |
1960 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); |
1961 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1962 | gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS); | |
1963 | regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]); | |
1964 | } | |
a35606d9 LS |
1965 | else if (insn.opcode () == riscv_insn::LD |
1966 | || insn.opcode () == riscv_insn::LW) | |
1967 | { | |
1968 | /* Handle: ld reg, offset(rs1) | |
1969 | or: c.ld reg, offset(rs1) | |
1970 | or: lw reg, offset(rs1) | |
1971 | or: c.lw reg, offset(rs1) */ | |
1972 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1973 | gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS); | |
1974 | regs[insn.rd ()] | |
1975 | = stack.fetch (pv_add_constant (regs[insn.rs1 ()], | |
1976 | insn.imm_signed ()), | |
1977 | (insn.opcode () == riscv_insn::LW ? 4 : 8)); | |
1978 | } | |
2b014cc5 LS |
1979 | else if (insn.opcode () == riscv_insn::MV) |
1980 | { | |
1981 | /* Handle: c.mv RD, RS2 */ | |
1982 | gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS); | |
1983 | gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS); | |
1984 | gdb_assert (insn.rs2 () > 0); | |
1985 | regs[insn.rd ()] = regs[insn.rs2 ()]; | |
1986 | } | |
dbbb1059 AB |
1987 | else |
1988 | { | |
78a3b0fa AB |
1989 | end_prologue_addr = cur_pc; |
1990 | break; | |
dbbb1059 AB |
1991 | } |
1992 | } | |
1993 | ||
1994 | if (end_prologue_addr == 0) | |
1995 | end_prologue_addr = cur_pc; | |
1996 | ||
78a3b0fa | 1997 | if (riscv_debug_unwinder) |
6cb06a8c TT |
1998 | gdb_printf (gdb_stdlog, "End of prologue at %s\n", |
1999 | core_addr_to_string (end_prologue_addr)); | |
78a3b0fa AB |
2000 | |
2001 | if (cache != NULL) | |
2002 | { | |
2003 | /* Figure out if it is a frame pointer or just a stack pointer. Also | |
dda83cd7 SM |
2004 | the offset held in the pv_t is from the original register value to |
2005 | the current value, which for a grows down stack means a negative | |
2006 | value. The FRAME_BASE_OFFSET is the negation of this, how to get | |
2007 | from the current value to the original value. */ | |
78a3b0fa AB |
2008 | if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM)) |
2009 | { | |
dda83cd7 SM |
2010 | cache->frame_base_reg = RISCV_FP_REGNUM; |
2011 | cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k; | |
78a3b0fa AB |
2012 | } |
2013 | else | |
2014 | { | |
dda83cd7 SM |
2015 | cache->frame_base_reg = RISCV_SP_REGNUM; |
2016 | cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k; | |
78a3b0fa AB |
2017 | } |
2018 | ||
2019 | /* Assign offset from old SP to all saved registers. As we don't | |
dda83cd7 SM |
2020 | have the previous value for the frame base register at this |
2021 | point, we store the offset as the address in the trad_frame, and | |
2022 | then convert this to an actual address later. */ | |
78a3b0fa AB |
2023 | for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++) |
2024 | { | |
2025 | CORE_ADDR offset; | |
2026 | if (stack.find_reg (gdbarch, i, &offset)) | |
dda83cd7 SM |
2027 | { |
2028 | if (riscv_debug_unwinder) | |
a96bd1cc AB |
2029 | { |
2030 | /* Display OFFSET as a signed value, the offsets are from | |
2031 | the frame base address to the registers location on | |
2032 | the stack, with a descending stack this means the | |
2033 | offsets are always negative. */ | |
6cb06a8c TT |
2034 | gdb_printf (gdb_stdlog, |
2035 | "Register $%s at stack offset %s\n", | |
2036 | gdbarch_register_name (gdbarch, i), | |
2037 | plongest ((LONGEST) offset)); | |
a96bd1cc | 2038 | } |
a9a87d35 | 2039 | cache->regs[i].set_addr (offset); |
dda83cd7 | 2040 | } |
78a3b0fa AB |
2041 | } |
2042 | } | |
2043 | ||
dbbb1059 AB |
2044 | return end_prologue_addr; |
2045 | } | |
2046 | ||
2047 | /* Implement the riscv_skip_prologue gdbarch method. */ | |
2048 | ||
2049 | static CORE_ADDR | |
78a3b0fa | 2050 | riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
dbbb1059 | 2051 | { |
dbbb1059 AB |
2052 | CORE_ADDR func_addr; |
2053 | ||
2054 | /* See if we can determine the end of the prologue via the symbol | |
2055 | table. If so, then return either PC, or the PC after the | |
2056 | prologue, whichever is greater. */ | |
2057 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
2058 | { | |
2059 | CORE_ADDR post_prologue_pc | |
2060 | = skip_prologue_using_sal (gdbarch, func_addr); | |
2061 | ||
2062 | if (post_prologue_pc != 0) | |
2063 | return std::max (pc, post_prologue_pc); | |
2064 | } | |
2065 | ||
2066 | /* Can't determine prologue from the symbol table, need to examine | |
78a3b0fa AB |
2067 | instructions. Pass -1 for the end address to indicate the prologue |
2068 | scanner can scan as far as it needs to find the end of the prologue. */ | |
2069 | return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL); | |
dbbb1059 AB |
2070 | } |
2071 | ||
2072 | /* Implement the gdbarch push dummy code callback. */ | |
2073 | ||
2074 | static CORE_ADDR | |
2075 | riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
2076 | CORE_ADDR funaddr, struct value **args, int nargs, | |
2077 | struct type *value_type, CORE_ADDR *real_pc, | |
2078 | CORE_ADDR *bp_addr, struct regcache *regcache) | |
2079 | { | |
01e175fe AB |
2080 | /* A nop instruction is 'add x0, x0, 0'. */ |
2081 | static const gdb_byte nop_insn[] = { 0x13, 0x00, 0x00, 0x00 }; | |
2082 | ||
dbbb1059 | 2083 | /* Allocate space for a breakpoint, and keep the stack correctly |
01e175fe AB |
2084 | aligned. The space allocated here must be at least big enough to |
2085 | accommodate the NOP_INSN defined above. */ | |
dbbb1059 AB |
2086 | sp -= 16; |
2087 | *bp_addr = sp; | |
2088 | *real_pc = funaddr; | |
01e175fe AB |
2089 | |
2090 | /* When we insert a breakpoint we select whether to use a compressed | |
2091 | breakpoint or not based on the existing contents of the memory. | |
2092 | ||
2093 | If the breakpoint is being placed onto the stack as part of setting up | |
2094 | for an inferior call from GDB, then the existing stack contents may | |
2095 | randomly appear to be a compressed instruction, causing GDB to insert | |
2096 | a compressed breakpoint. If this happens on a target that does not | |
2097 | support compressed instructions then this could cause problems. | |
2098 | ||
2099 | To prevent this issue we write an uncompressed nop onto the stack at | |
2100 | the location where the breakpoint will be inserted. In this way we | |
2101 | ensure that we always use an uncompressed breakpoint, which should | |
2102 | work on all targets. | |
2103 | ||
2104 | We call TARGET_WRITE_MEMORY here so that if the write fails we don't | |
2105 | throw an exception. Instead we ignore the error and move on. The | |
2106 | assumption is that either GDB will error later when actually trying to | |
2107 | insert a software breakpoint, or GDB will use hardware breakpoints and | |
2108 | there will be no need to write to memory later. */ | |
2109 | int status = target_write_memory (*bp_addr, nop_insn, sizeof (nop_insn)); | |
2110 | ||
2111 | if (riscv_debug_breakpoints || riscv_debug_infcall) | |
6cb06a8c TT |
2112 | gdb_printf (gdb_stdlog, |
2113 | "Writing %s-byte nop instruction to %s: %s\n", | |
2114 | plongest (sizeof (nop_insn)), | |
2115 | paddress (gdbarch, *bp_addr), | |
2116 | (status == 0 ? "success" : "failed")); | |
01e175fe | 2117 | |
dbbb1059 AB |
2118 | return sp; |
2119 | } | |
2120 | ||
a9158a86 AB |
2121 | /* Implement the gdbarch type alignment method, overrides the generic |
2122 | alignment algorithm for anything that is RISC-V specific. */ | |
dbbb1059 | 2123 | |
a9158a86 AB |
2124 | static ULONGEST |
2125 | riscv_type_align (gdbarch *gdbarch, type *type) | |
dbbb1059 | 2126 | { |
a9158a86 | 2127 | type = check_typedef (type); |
bd63c870 | 2128 | if (type->code () == TYPE_CODE_ARRAY && type->is_vector ()) |
a9158a86 | 2129 | return std::min (TYPE_LENGTH (type), (ULONGEST) BIGGEST_ALIGNMENT); |
dbbb1059 | 2130 | |
a9158a86 AB |
2131 | /* Anything else will be aligned by the generic code. */ |
2132 | return 0; | |
dbbb1059 AB |
2133 | } |
2134 | ||
2135 | /* Holds information about a single argument either being passed to an | |
2136 | inferior function, or returned from an inferior function. This includes | |
2137 | information about the size, type, etc of the argument, and also | |
2138 | information about how the argument will be passed (or returned). */ | |
2139 | ||
2140 | struct riscv_arg_info | |
2141 | { | |
2142 | /* Contents of the argument. */ | |
2143 | const gdb_byte *contents; | |
2144 | ||
2145 | /* Length of argument. */ | |
2146 | int length; | |
2147 | ||
2148 | /* Alignment required for an argument of this type. */ | |
2149 | int align; | |
2150 | ||
2151 | /* The type for this argument. */ | |
2152 | struct type *type; | |
2153 | ||
2154 | /* Each argument can have either 1 or 2 locations assigned to it. Each | |
2155 | location describes where part of the argument will be placed. The | |
2156 | second location is valid based on the LOC_TYPE and C_LENGTH fields | |
2157 | of the first location (which is always valid). */ | |
2158 | struct location | |
2159 | { | |
2160 | /* What type of location this is. */ | |
2161 | enum location_type | |
2162 | { | |
2163 | /* Argument passed in a register. */ | |
2164 | in_reg, | |
2165 | ||
2166 | /* Argument passed as an on stack argument. */ | |
2167 | on_stack, | |
2168 | ||
2169 | /* Argument passed by reference. The second location is always | |
2170 | valid for a BY_REF argument, and describes where the address | |
2171 | of the BY_REF argument should be placed. */ | |
2172 | by_ref | |
2173 | } loc_type; | |
2174 | ||
2175 | /* Information that depends on the location type. */ | |
2176 | union | |
2177 | { | |
2178 | /* Which register number to use. */ | |
2179 | int regno; | |
2180 | ||
2181 | /* The offset into the stack region. */ | |
2182 | int offset; | |
2183 | } loc_data; | |
2184 | ||
2185 | /* The length of contents covered by this location. If this is less | |
2186 | than the total length of the argument, then the second location | |
2187 | will be valid, and will describe where the rest of the argument | |
2188 | will go. */ | |
2189 | int c_length; | |
2190 | ||
dd895392 AB |
2191 | /* The offset within CONTENTS for this part of the argument. This can |
2192 | be non-zero even for the first part (the first field of a struct can | |
2193 | have a non-zero offset due to padding). For the second part of the | |
dbbb1059 AB |
2194 | argument, this might be the C_LENGTH value of the first part, |
2195 | however, if we are passing a structure in two registers, and there's | |
2196 | is padding between the first and second field, then this offset | |
2197 | might be greater than the length of the first argument part. When | |
2198 | the second argument location is not holding part of the argument | |
2199 | value, but is instead holding the address of a reference argument, | |
2200 | then this offset will be set to 0. */ | |
2201 | int c_offset; | |
2202 | } argloc[2]; | |
8b2d40cb JW |
2203 | |
2204 | /* TRUE if this is an unnamed argument. */ | |
2205 | bool is_unnamed; | |
dbbb1059 AB |
2206 | }; |
2207 | ||
2208 | /* Information about a set of registers being used for passing arguments as | |
2209 | part of a function call. The register set must be numerically | |
2210 | sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be | |
2211 | disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */ | |
2212 | ||
2213 | struct riscv_arg_reg | |
2214 | { | |
2215 | riscv_arg_reg (int first, int last) | |
2216 | : next_regnum (first), | |
2217 | last_regnum (last) | |
2218 | { | |
2219 | /* Nothing. */ | |
2220 | } | |
2221 | ||
2222 | /* The GDB register number to use in this set. */ | |
2223 | int next_regnum; | |
2224 | ||
2225 | /* The last GDB register number to use in this set. */ | |
2226 | int last_regnum; | |
2227 | }; | |
2228 | ||
2229 | /* Arguments can be passed as on stack arguments, or by reference. The | |
2230 | on stack arguments must be in a continuous region starting from $sp, | |
2231 | while the by reference arguments can be anywhere, but we'll put them | |
2232 | on the stack after (at higher address) the on stack arguments. | |
2233 | ||
2234 | This might not be the right approach to take. The ABI is clear that | |
2235 | an argument passed by reference can be modified by the callee, which | |
2236 | us placing the argument (temporarily) onto the stack will not achieve | |
2237 | (changes will be lost). There's also the possibility that very large | |
2238 | arguments could overflow the stack. | |
2239 | ||
2240 | This struct is used to track offset into these two areas for where | |
2241 | arguments are to be placed. */ | |
2242 | struct riscv_memory_offsets | |
2243 | { | |
2244 | riscv_memory_offsets () | |
2245 | : arg_offset (0), | |
2246 | ref_offset (0) | |
2247 | { | |
2248 | /* Nothing. */ | |
2249 | } | |
2250 | ||
2251 | /* Offset into on stack argument area. */ | |
2252 | int arg_offset; | |
2253 | ||
2254 | /* Offset into the pass by reference area. */ | |
2255 | int ref_offset; | |
2256 | }; | |
2257 | ||
2258 | /* Holds information about where arguments to a call will be placed. This | |
2259 | is updated as arguments are added onto the call, and can be used to | |
2260 | figure out where the next argument should be placed. */ | |
2261 | ||
2262 | struct riscv_call_info | |
2263 | { | |
2264 | riscv_call_info (struct gdbarch *gdbarch) | |
2265 | : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7), | |
2266 | float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7) | |
2267 | { | |
113b7b81 AB |
2268 | xlen = riscv_abi_xlen (gdbarch); |
2269 | flen = riscv_abi_flen (gdbarch); | |
dbbb1059 | 2270 | |
25428040 AB |
2271 | /* Reduce the number of integer argument registers when using the |
2272 | embedded abi (i.e. rv32e). */ | |
2273 | if (riscv_abi_embedded (gdbarch)) | |
2274 | int_regs.last_regnum = RISCV_A0_REGNUM + 5; | |
2275 | ||
dbbb1059 AB |
2276 | /* Disable use of floating point registers if needed. */ |
2277 | if (!riscv_has_fp_abi (gdbarch)) | |
2278 | float_regs.next_regnum = float_regs.last_regnum + 1; | |
2279 | } | |
2280 | ||
2281 | /* Track the memory areas used for holding in-memory arguments to a | |
2282 | call. */ | |
2283 | struct riscv_memory_offsets memory; | |
2284 | ||
2285 | /* Holds information about the next integer register to use for passing | |
2286 | an argument. */ | |
2287 | struct riscv_arg_reg int_regs; | |
2288 | ||
2289 | /* Holds information about the next floating point register to use for | |
2290 | passing an argument. */ | |
2291 | struct riscv_arg_reg float_regs; | |
2292 | ||
2293 | /* The XLEN and FLEN are copied in to this structure for convenience, and | |
113b7b81 | 2294 | are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */ |
dbbb1059 AB |
2295 | int xlen; |
2296 | int flen; | |
2297 | }; | |
2298 | ||
2299 | /* Return the number of registers available for use as parameters in the | |
2300 | register set REG. Returned value can be 0 or more. */ | |
2301 | ||
2302 | static int | |
2303 | riscv_arg_regs_available (struct riscv_arg_reg *reg) | |
2304 | { | |
2305 | if (reg->next_regnum > reg->last_regnum) | |
2306 | return 0; | |
2307 | ||
2308 | return (reg->last_regnum - reg->next_regnum + 1); | |
2309 | } | |
2310 | ||
2311 | /* If there is at least one register available in the register set REG then | |
2312 | the next register from REG is assigned to LOC and the length field of | |
2313 | LOC is updated to LENGTH. The register set REG is updated to indicate | |
2314 | that the assigned register is no longer available and the function | |
2315 | returns true. | |
2316 | ||
2317 | If there are no registers available in REG then the function returns | |
2318 | false, and LOC and REG are unchanged. */ | |
2319 | ||
2320 | static bool | |
2321 | riscv_assign_reg_location (struct riscv_arg_info::location *loc, | |
2322 | struct riscv_arg_reg *reg, | |
2323 | int length, int offset) | |
2324 | { | |
2325 | if (reg->next_regnum <= reg->last_regnum) | |
2326 | { | |
2327 | loc->loc_type = riscv_arg_info::location::in_reg; | |
2328 | loc->loc_data.regno = reg->next_regnum; | |
2329 | reg->next_regnum++; | |
2330 | loc->c_length = length; | |
2331 | loc->c_offset = offset; | |
2332 | return true; | |
2333 | } | |
2334 | ||
2335 | return false; | |
2336 | } | |
2337 | ||
2338 | /* Assign LOC a location as the next stack parameter, and update MEMORY to | |
2339 | record that an area of stack has been used to hold the parameter | |
2340 | described by LOC. | |
2341 | ||
2342 | The length field of LOC is updated to LENGTH, the length of the | |
2343 | parameter being stored, and ALIGN is the alignment required by the | |
2344 | parameter, which will affect how memory is allocated out of MEMORY. */ | |
2345 | ||
2346 | static void | |
2347 | riscv_assign_stack_location (struct riscv_arg_info::location *loc, | |
2348 | struct riscv_memory_offsets *memory, | |
2349 | int length, int align) | |
2350 | { | |
2351 | loc->loc_type = riscv_arg_info::location::on_stack; | |
2352 | memory->arg_offset | |
2353 | = align_up (memory->arg_offset, align); | |
2354 | loc->loc_data.offset = memory->arg_offset; | |
2355 | memory->arg_offset += length; | |
2356 | loc->c_length = length; | |
2357 | ||
2358 | /* Offset is always 0, either we're the first location part, in which | |
2359 | case we're reading content from the start of the argument, or we're | |
2360 | passing the address of a reference argument, so 0. */ | |
2361 | loc->c_offset = 0; | |
2362 | } | |
2363 | ||
2364 | /* Update AINFO, which describes an argument that should be passed or | |
2365 | returned using the integer ABI. The argloc fields within AINFO are | |
2366 | updated to describe the location in which the argument will be passed to | |
2367 | a function, or returned from a function. | |
2368 | ||
2369 | The CINFO structure contains the ongoing call information, the holds | |
2370 | information such as which argument registers are remaining to be | |
2371 | assigned to parameter, and how much memory has been used by parameters | |
2372 | so far. | |
2373 | ||
2374 | By examining the state of CINFO a suitable location can be selected, | |
2375 | and assigned to AINFO. */ | |
2376 | ||
2377 | static void | |
2378 | riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo, | |
2379 | struct riscv_call_info *cinfo) | |
2380 | { | |
2381 | if (ainfo->length > (2 * cinfo->xlen)) | |
2382 | { | |
2383 | /* Argument is going to be passed by reference. */ | |
2384 | ainfo->argloc[0].loc_type | |
2385 | = riscv_arg_info::location::by_ref; | |
2386 | cinfo->memory.ref_offset | |
2387 | = align_up (cinfo->memory.ref_offset, ainfo->align); | |
2388 | ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset; | |
2389 | cinfo->memory.ref_offset += ainfo->length; | |
2390 | ainfo->argloc[0].c_length = ainfo->length; | |
2391 | ||
2392 | /* The second location for this argument is given over to holding the | |
2393 | address of the by-reference data. Pass 0 for the offset as this | |
2394 | is not part of the actual argument value. */ | |
2395 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2396 | &cinfo->int_regs, | |
2397 | cinfo->xlen, 0)) | |
2398 | riscv_assign_stack_location (&ainfo->argloc[1], | |
2399 | &cinfo->memory, cinfo->xlen, | |
2400 | cinfo->xlen); | |
2401 | } | |
2402 | else | |
2403 | { | |
174f8ac8 JW |
2404 | int len = std::min (ainfo->length, cinfo->xlen); |
2405 | int align = std::max (ainfo->align, cinfo->xlen); | |
dbbb1059 | 2406 | |
8b2d40cb JW |
2407 | /* Unnamed arguments in registers that require 2*XLEN alignment are |
2408 | passed in an aligned register pair. */ | |
2409 | if (ainfo->is_unnamed && (align == cinfo->xlen * 2) | |
2410 | && cinfo->int_regs.next_regnum & 1) | |
2411 | cinfo->int_regs.next_regnum++; | |
2412 | ||
dbbb1059 AB |
2413 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
2414 | &cinfo->int_regs, len, 0)) | |
2415 | riscv_assign_stack_location (&ainfo->argloc[0], | |
174f8ac8 | 2416 | &cinfo->memory, len, align); |
dbbb1059 AB |
2417 | |
2418 | if (len < ainfo->length) | |
2419 | { | |
2420 | len = ainfo->length - len; | |
2421 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2422 | &cinfo->int_regs, len, | |
2423 | cinfo->xlen)) | |
2424 | riscv_assign_stack_location (&ainfo->argloc[1], | |
2425 | &cinfo->memory, len, cinfo->xlen); | |
2426 | } | |
2427 | } | |
2428 | } | |
2429 | ||
2430 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
2431 | is being passed with the floating point ABI. */ | |
2432 | ||
2433 | static void | |
2434 | riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo, | |
2435 | struct riscv_call_info *cinfo) | |
2436 | { | |
4de3d8d0 | 2437 | if (ainfo->length > cinfo->flen || ainfo->is_unnamed) |
dbbb1059 AB |
2438 | return riscv_call_arg_scalar_int (ainfo, cinfo); |
2439 | else | |
2440 | { | |
2441 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
2442 | &cinfo->float_regs, | |
2443 | ainfo->length, 0)) | |
2444 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
2445 | } | |
2446 | } | |
2447 | ||
2448 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
2449 | is a complex floating point argument, and is therefore handled | |
2450 | differently to other argument types. */ | |
2451 | ||
2452 | static void | |
2453 | riscv_call_arg_complex_float (struct riscv_arg_info *ainfo, | |
2454 | struct riscv_call_info *cinfo) | |
2455 | { | |
2456 | if (ainfo->length <= (2 * cinfo->flen) | |
4de3d8d0 AB |
2457 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2 |
2458 | && !ainfo->is_unnamed) | |
dbbb1059 AB |
2459 | { |
2460 | bool result; | |
2461 | int len = ainfo->length / 2; | |
2462 | ||
2463 | result = riscv_assign_reg_location (&ainfo->argloc[0], | |
9f0272f8 | 2464 | &cinfo->float_regs, len, 0); |
dbbb1059 AB |
2465 | gdb_assert (result); |
2466 | ||
2467 | result = riscv_assign_reg_location (&ainfo->argloc[1], | |
2468 | &cinfo->float_regs, len, len); | |
2469 | gdb_assert (result); | |
2470 | } | |
2471 | else | |
2472 | return riscv_call_arg_scalar_int (ainfo, cinfo); | |
2473 | } | |
2474 | ||
2475 | /* A structure used for holding information about a structure type within | |
2476 | the inferior program. The RiscV ABI has special rules for handling some | |
2477 | structures with a single field or with two fields. The counting of | |
2478 | fields here is done after flattening out all nested structures. */ | |
2479 | ||
2480 | class riscv_struct_info | |
2481 | { | |
2482 | public: | |
2483 | riscv_struct_info () | |
2484 | : m_number_of_fields (0), | |
9f0272f8 AB |
2485 | m_types { nullptr, nullptr }, |
2486 | m_offsets { 0, 0 } | |
dbbb1059 AB |
2487 | { |
2488 | /* Nothing. */ | |
2489 | } | |
2490 | ||
2491 | /* Analyse TYPE descending into nested structures, count the number of | |
2492 | scalar fields and record the types of the first two fields found. */ | |
9f0272f8 AB |
2493 | void analyse (struct type *type) |
2494 | { | |
2495 | analyse_inner (type, 0); | |
2496 | } | |
dbbb1059 AB |
2497 | |
2498 | /* The number of scalar fields found in the analysed type. This is | |
2499 | currently only accurate if the value returned is 0, 1, or 2 as the | |
2500 | analysis stops counting when the number of fields is 3. This is | |
2501 | because the RiscV ABI only has special cases for 1 or 2 fields, | |
2502 | anything else we just don't care about. */ | |
2503 | int number_of_fields () const | |
2504 | { return m_number_of_fields; } | |
2505 | ||
2506 | /* Return the type for scalar field INDEX within the analysed type. Will | |
2507 | return nullptr if there is no field at that index. Only INDEX values | |
2508 | 0 and 1 can be requested as the RiscV ABI only has special cases for | |
2509 | structures with 1 or 2 fields. */ | |
2510 | struct type *field_type (int index) const | |
2511 | { | |
2512 | gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0]))); | |
2513 | return m_types[index]; | |
2514 | } | |
2515 | ||
9f0272f8 AB |
2516 | /* Return the offset of scalar field INDEX within the analysed type. Will |
2517 | return 0 if there is no field at that index. Only INDEX values 0 and | |
2518 | 1 can be requested as the RiscV ABI only has special cases for | |
2519 | structures with 1 or 2 fields. */ | |
2520 | int field_offset (int index) const | |
2521 | { | |
2522 | gdb_assert (index < (sizeof (m_offsets) / sizeof (m_offsets[0]))); | |
2523 | return m_offsets[index]; | |
2524 | } | |
2525 | ||
dbbb1059 AB |
2526 | private: |
2527 | /* The number of scalar fields found within the structure after recursing | |
2528 | into nested structures. */ | |
2529 | int m_number_of_fields; | |
2530 | ||
2531 | /* The types of the first two scalar fields found within the structure | |
2532 | after recursing into nested structures. */ | |
2533 | struct type *m_types[2]; | |
9f0272f8 AB |
2534 | |
2535 | /* The offsets of the first two scalar fields found within the structure | |
2536 | after recursing into nested structures. */ | |
2537 | int m_offsets[2]; | |
2538 | ||
2539 | /* Recursive core for ANALYSE, the OFFSET parameter tracks the byte | |
2540 | offset from the start of the top level structure being analysed. */ | |
2541 | void analyse_inner (struct type *type, int offset); | |
dbbb1059 AB |
2542 | }; |
2543 | ||
9f0272f8 | 2544 | /* See description in class declaration. */ |
dbbb1059 AB |
2545 | |
2546 | void | |
9f0272f8 | 2547 | riscv_struct_info::analyse_inner (struct type *type, int offset) |
dbbb1059 | 2548 | { |
1f704f76 | 2549 | unsigned int count = type->num_fields (); |
dbbb1059 AB |
2550 | unsigned int i; |
2551 | ||
2552 | for (i = 0; i < count; ++i) | |
2553 | { | |
2ad53ea1 | 2554 | if (type->field (i).loc_kind () != FIELD_LOC_KIND_BITPOS) |
dbbb1059 AB |
2555 | continue; |
2556 | ||
940da03e | 2557 | struct type *field_type = type->field (i).type (); |
dbbb1059 | 2558 | field_type = check_typedef (field_type); |
9f0272f8 | 2559 | int field_offset |
b610c045 | 2560 | = offset + type->field (i).loc_bitpos () / TARGET_CHAR_BIT; |
dbbb1059 | 2561 | |
78134374 | 2562 | switch (field_type->code ()) |
dbbb1059 AB |
2563 | { |
2564 | case TYPE_CODE_STRUCT: | |
9f0272f8 | 2565 | analyse_inner (field_type, field_offset); |
dbbb1059 AB |
2566 | break; |
2567 | ||
2568 | default: | |
2569 | /* RiscV only flattens out structures. Anything else does not | |
2570 | need to be flattened, we just record the type, and when we | |
2571 | look at the analysis results we'll realise this is not a | |
2572 | structure we can special case, and pass the structure in | |
2573 | memory. */ | |
2574 | if (m_number_of_fields < 2) | |
9f0272f8 AB |
2575 | { |
2576 | m_types[m_number_of_fields] = field_type; | |
2577 | m_offsets[m_number_of_fields] = field_offset; | |
2578 | } | |
dbbb1059 AB |
2579 | m_number_of_fields++; |
2580 | break; | |
2581 | } | |
2582 | ||
2583 | /* RiscV only has special handling for structures with 1 or 2 scalar | |
2584 | fields, any more than that and the structure is just passed in | |
2585 | memory. We can safely drop out early when we find 3 or more | |
2586 | fields then. */ | |
2587 | ||
2588 | if (m_number_of_fields > 2) | |
2589 | return; | |
2590 | } | |
2591 | } | |
2592 | ||
2593 | /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO | |
2594 | is a structure. Small structures on RiscV have some special case | |
2595 | handling in order that the structure might be passed in register. | |
2596 | Larger structures are passed in memory. After assigning location | |
2597 | information to AINFO, CINFO will have been updated. */ | |
2598 | ||
2599 | static void | |
2600 | riscv_call_arg_struct (struct riscv_arg_info *ainfo, | |
2601 | struct riscv_call_info *cinfo) | |
2602 | { | |
2603 | if (riscv_arg_regs_available (&cinfo->float_regs) >= 1) | |
2604 | { | |
2605 | struct riscv_struct_info sinfo; | |
2606 | ||
2607 | sinfo.analyse (ainfo->type); | |
2608 | if (sinfo.number_of_fields () == 1 | |
78134374 | 2609 | && sinfo.field_type(0)->code () == TYPE_CODE_COMPLEX) |
dbbb1059 | 2610 | { |
9f0272f8 AB |
2611 | /* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT, |
2612 | except we use the type of the complex field instead of the | |
2613 | type from AINFO, and the first location might be at a non-zero | |
2614 | offset. */ | |
2615 | if (TYPE_LENGTH (sinfo.field_type (0)) <= (2 * cinfo->flen) | |
2616 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2 | |
2617 | && !ainfo->is_unnamed) | |
2618 | { | |
2619 | bool result; | |
2620 | int len = TYPE_LENGTH (sinfo.field_type (0)) / 2; | |
2621 | int offset = sinfo.field_offset (0); | |
2622 | ||
2623 | result = riscv_assign_reg_location (&ainfo->argloc[0], | |
2624 | &cinfo->float_regs, len, | |
2625 | offset); | |
2626 | gdb_assert (result); | |
2627 | ||
2628 | result = riscv_assign_reg_location (&ainfo->argloc[1], | |
2629 | &cinfo->float_regs, len, | |
2630 | (offset + len)); | |
2631 | gdb_assert (result); | |
2632 | } | |
2633 | else | |
2634 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2635 | return; | |
dbbb1059 AB |
2636 | } |
2637 | ||
2638 | if (sinfo.number_of_fields () == 1 | |
78134374 | 2639 | && sinfo.field_type(0)->code () == TYPE_CODE_FLT) |
dbbb1059 | 2640 | { |
9f0272f8 AB |
2641 | /* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT, |
2642 | except we use the type of the first scalar field instead of | |
2643 | the type from AINFO. Also the location might be at a non-zero | |
2644 | offset. */ | |
2645 | if (TYPE_LENGTH (sinfo.field_type (0)) > cinfo->flen | |
2646 | || ainfo->is_unnamed) | |
2647 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2648 | else | |
2649 | { | |
2650 | int offset = sinfo.field_offset (0); | |
2651 | int len = TYPE_LENGTH (sinfo.field_type (0)); | |
2652 | ||
2653 | if (!riscv_assign_reg_location (&ainfo->argloc[0], | |
2654 | &cinfo->float_regs, | |
2655 | len, offset)) | |
2656 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2657 | } | |
2658 | return; | |
dbbb1059 AB |
2659 | } |
2660 | ||
2661 | if (sinfo.number_of_fields () == 2 | |
78134374 | 2662 | && sinfo.field_type(0)->code () == TYPE_CODE_FLT |
dbbb1059 | 2663 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen |
78134374 | 2664 | && sinfo.field_type(1)->code () == TYPE_CODE_FLT |
dbbb1059 AB |
2665 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen |
2666 | && riscv_arg_regs_available (&cinfo->float_regs) >= 2) | |
2667 | { | |
9f0272f8 AB |
2668 | int len0 = TYPE_LENGTH (sinfo.field_type (0)); |
2669 | int offset = sinfo.field_offset (0); | |
dbbb1059 | 2670 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
9f0272f8 | 2671 | &cinfo->float_regs, len0, offset)) |
dbbb1059 AB |
2672 | error (_("failed during argument setup")); |
2673 | ||
9f0272f8 AB |
2674 | int len1 = TYPE_LENGTH (sinfo.field_type (1)); |
2675 | offset = sinfo.field_offset (1); | |
dbbb1059 AB |
2676 | gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type) |
2677 | - TYPE_LENGTH (sinfo.field_type (0)))); | |
2678 | ||
2679 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2680 | &cinfo->float_regs, | |
2681 | len1, offset)) | |
2682 | error (_("failed during argument setup")); | |
2683 | return; | |
2684 | } | |
2685 | ||
2686 | if (sinfo.number_of_fields () == 2 | |
2687 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 | |
78134374 | 2688 | && (sinfo.field_type(0)->code () == TYPE_CODE_FLT |
dbbb1059 AB |
2689 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen |
2690 | && is_integral_type (sinfo.field_type (1)) | |
2691 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen)) | |
2692 | { | |
9f0272f8 AB |
2693 | int len0 = TYPE_LENGTH (sinfo.field_type (0)); |
2694 | int offset = sinfo.field_offset (0); | |
dbbb1059 | 2695 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
9f0272f8 | 2696 | &cinfo->float_regs, len0, offset)) |
dbbb1059 AB |
2697 | error (_("failed during argument setup")); |
2698 | ||
9f0272f8 AB |
2699 | int len1 = TYPE_LENGTH (sinfo.field_type (1)); |
2700 | offset = sinfo.field_offset (1); | |
dbbb1059 AB |
2701 | gdb_assert (len1 <= cinfo->xlen); |
2702 | if (!riscv_assign_reg_location (&ainfo->argloc[1], | |
2703 | &cinfo->int_regs, len1, offset)) | |
2704 | error (_("failed during argument setup")); | |
2705 | return; | |
2706 | } | |
2707 | ||
2708 | if (sinfo.number_of_fields () == 2 | |
2709 | && riscv_arg_regs_available (&cinfo->int_regs) >= 1 | |
2710 | && (is_integral_type (sinfo.field_type (0)) | |
2711 | && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen | |
78134374 | 2712 | && sinfo.field_type(1)->code () == TYPE_CODE_FLT |
dbbb1059 AB |
2713 | && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen)) |
2714 | { | |
9f0272f8 AB |
2715 | int len0 = TYPE_LENGTH (sinfo.field_type (0)); |
2716 | int len1 = TYPE_LENGTH (sinfo.field_type (1)); | |
dbbb1059 AB |
2717 | |
2718 | gdb_assert (len0 <= cinfo->xlen); | |
2719 | gdb_assert (len1 <= cinfo->flen); | |
2720 | ||
9f0272f8 | 2721 | int offset = sinfo.field_offset (0); |
dbbb1059 | 2722 | if (!riscv_assign_reg_location (&ainfo->argloc[0], |
9f0272f8 | 2723 | &cinfo->int_regs, len0, offset)) |
dbbb1059 AB |
2724 | error (_("failed during argument setup")); |
2725 | ||
9f0272f8 | 2726 | offset = sinfo.field_offset (1); |
dbbb1059 AB |
2727 | if (!riscv_assign_reg_location (&ainfo->argloc[1], |
2728 | &cinfo->float_regs, | |
2729 | len1, offset)) | |
2730 | error (_("failed during argument setup")); | |
2731 | ||
2732 | return; | |
2733 | } | |
2734 | } | |
2735 | ||
2736 | /* Non of the structure flattening cases apply, so we just pass using | |
2737 | the integer ABI. */ | |
dbbb1059 AB |
2738 | riscv_call_arg_scalar_int (ainfo, cinfo); |
2739 | } | |
2740 | ||
2741 | /* Assign a location to call (or return) argument AINFO, the location is | |
2742 | selected from CINFO which holds information about what call argument | |
2743 | locations are available for use next. The TYPE is the type of the | |
2744 | argument being passed, this information is recorded into AINFO (along | |
8b2d40cb JW |
2745 | with some additional information derived from the type). IS_UNNAMED |
2746 | is true if this is an unnamed (stdarg) argument, this info is also | |
2747 | recorded into AINFO. | |
dbbb1059 AB |
2748 | |
2749 | After assigning a location to AINFO, CINFO will have been updated. */ | |
2750 | ||
2751 | static void | |
2752 | riscv_arg_location (struct gdbarch *gdbarch, | |
2753 | struct riscv_arg_info *ainfo, | |
2754 | struct riscv_call_info *cinfo, | |
8b2d40cb | 2755 | struct type *type, bool is_unnamed) |
dbbb1059 AB |
2756 | { |
2757 | ainfo->type = type; | |
2758 | ainfo->length = TYPE_LENGTH (ainfo->type); | |
a9158a86 | 2759 | ainfo->align = type_align (ainfo->type); |
8b2d40cb | 2760 | ainfo->is_unnamed = is_unnamed; |
dbbb1059 | 2761 | ainfo->contents = nullptr; |
9f0272f8 AB |
2762 | ainfo->argloc[0].c_length = 0; |
2763 | ainfo->argloc[1].c_length = 0; | |
dbbb1059 | 2764 | |
78134374 | 2765 | switch (ainfo->type->code ()) |
dbbb1059 AB |
2766 | { |
2767 | case TYPE_CODE_INT: | |
2768 | case TYPE_CODE_BOOL: | |
2769 | case TYPE_CODE_CHAR: | |
2770 | case TYPE_CODE_RANGE: | |
2771 | case TYPE_CODE_ENUM: | |
2772 | case TYPE_CODE_PTR: | |
0abb4049 | 2773 | case TYPE_CODE_FIXED_POINT: |
dbbb1059 AB |
2774 | if (ainfo->length <= cinfo->xlen) |
2775 | { | |
2776 | ainfo->type = builtin_type (gdbarch)->builtin_long; | |
2777 | ainfo->length = cinfo->xlen; | |
2778 | } | |
2779 | else if (ainfo->length <= (2 * cinfo->xlen)) | |
2780 | { | |
2781 | ainfo->type = builtin_type (gdbarch)->builtin_long_long; | |
2782 | ainfo->length = 2 * cinfo->xlen; | |
2783 | } | |
2784 | ||
2785 | /* Recalculate the alignment requirement. */ | |
a9158a86 | 2786 | ainfo->align = type_align (ainfo->type); |
dbbb1059 AB |
2787 | riscv_call_arg_scalar_int (ainfo, cinfo); |
2788 | break; | |
2789 | ||
2790 | case TYPE_CODE_FLT: | |
2791 | riscv_call_arg_scalar_float (ainfo, cinfo); | |
2792 | break; | |
2793 | ||
2794 | case TYPE_CODE_COMPLEX: | |
2795 | riscv_call_arg_complex_float (ainfo, cinfo); | |
2796 | break; | |
2797 | ||
2798 | case TYPE_CODE_STRUCT: | |
2799 | riscv_call_arg_struct (ainfo, cinfo); | |
2800 | break; | |
2801 | ||
2802 | default: | |
2803 | riscv_call_arg_scalar_int (ainfo, cinfo); | |
2804 | break; | |
2805 | } | |
2806 | } | |
2807 | ||
cab5bb9d AB |
2808 | /* Used for printing debug information about the call argument location in |
2809 | INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base | |
2810 | addresses for the location of pass-by-reference and | |
2811 | arguments-on-the-stack memory areas. */ | |
2812 | ||
dbbb1059 | 2813 | static void |
cab5bb9d | 2814 | riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch, |
dbbb1059 AB |
2815 | struct riscv_arg_info *info, |
2816 | CORE_ADDR sp_refs, CORE_ADDR sp_args) | |
2817 | { | |
6cb06a8c TT |
2818 | gdb_printf (stream, "type: '%s', length: 0x%x, alignment: 0x%x", |
2819 | TYPE_SAFE_NAME (info->type), info->length, info->align); | |
dbbb1059 AB |
2820 | switch (info->argloc[0].loc_type) |
2821 | { | |
2822 | case riscv_arg_info::location::in_reg: | |
6cb06a8c | 2823 | gdb_printf |
cab5bb9d AB |
2824 | (stream, ", register %s", |
2825 | gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno)); | |
dbbb1059 AB |
2826 | if (info->argloc[0].c_length < info->length) |
2827 | { | |
2828 | switch (info->argloc[1].loc_type) | |
2829 | { | |
2830 | case riscv_arg_info::location::in_reg: | |
6cb06a8c | 2831 | gdb_printf |
cab5bb9d AB |
2832 | (stream, ", register %s", |
2833 | gdbarch_register_name (gdbarch, | |
2834 | info->argloc[1].loc_data.regno)); | |
dbbb1059 AB |
2835 | break; |
2836 | ||
2837 | case riscv_arg_info::location::on_stack: | |
6cb06a8c TT |
2838 | gdb_printf (stream, ", on stack at offset 0x%x", |
2839 | info->argloc[1].loc_data.offset); | |
dbbb1059 AB |
2840 | break; |
2841 | ||
2842 | case riscv_arg_info::location::by_ref: | |
2843 | default: | |
2844 | /* The second location should never be a reference, any | |
2845 | argument being passed by reference just places its address | |
2846 | in the first location and is done. */ | |
2847 | error (_("invalid argument location")); | |
2848 | break; | |
2849 | } | |
2850 | ||
2851 | if (info->argloc[1].c_offset > info->argloc[0].c_length) | |
6cb06a8c TT |
2852 | gdb_printf (stream, " (offset 0x%x)", |
2853 | info->argloc[1].c_offset); | |
dbbb1059 AB |
2854 | } |
2855 | break; | |
2856 | ||
2857 | case riscv_arg_info::location::on_stack: | |
6cb06a8c TT |
2858 | gdb_printf (stream, ", on stack at offset 0x%x", |
2859 | info->argloc[0].loc_data.offset); | |
dbbb1059 AB |
2860 | break; |
2861 | ||
2862 | case riscv_arg_info::location::by_ref: | |
6cb06a8c | 2863 | gdb_printf |
cab5bb9d AB |
2864 | (stream, ", by reference, data at offset 0x%x (%s)", |
2865 | info->argloc[0].loc_data.offset, | |
2866 | core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset)); | |
dbbb1059 AB |
2867 | if (info->argloc[1].loc_type |
2868 | == riscv_arg_info::location::in_reg) | |
6cb06a8c | 2869 | gdb_printf |
cab5bb9d AB |
2870 | (stream, ", address in register %s", |
2871 | gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno)); | |
dbbb1059 AB |
2872 | else |
2873 | { | |
2874 | gdb_assert (info->argloc[1].loc_type | |
2875 | == riscv_arg_info::location::on_stack); | |
6cb06a8c | 2876 | gdb_printf |
cab5bb9d AB |
2877 | (stream, ", address on stack at offset 0x%x (%s)", |
2878 | info->argloc[1].loc_data.offset, | |
2879 | core_addr_to_string (sp_args + info->argloc[1].loc_data.offset)); | |
dbbb1059 AB |
2880 | } |
2881 | break; | |
2882 | ||
2883 | default: | |
557b4d76 | 2884 | gdb_assert_not_reached ("unknown argument location type"); |
dbbb1059 AB |
2885 | } |
2886 | } | |
2887 | ||
dd895392 AB |
2888 | /* Wrapper around REGCACHE->cooked_write. Places the LEN bytes of DATA |
2889 | into a buffer that is at least as big as the register REGNUM, padding | |
2890 | out the DATA with either 0x00, or 0xff. For floating point registers | |
2891 | 0xff is used, for everyone else 0x00 is used. */ | |
2892 | ||
2893 | static void | |
2894 | riscv_regcache_cooked_write (int regnum, const gdb_byte *data, int len, | |
2895 | struct regcache *regcache, int flen) | |
2896 | { | |
2897 | gdb_byte tmp [sizeof (ULONGEST)]; | |
2898 | ||
2899 | /* FP values in FP registers must be NaN-boxed. */ | |
2900 | if (riscv_is_fp_regno_p (regnum) && len < flen) | |
2901 | memset (tmp, -1, sizeof (tmp)); | |
2902 | else | |
2903 | memset (tmp, 0, sizeof (tmp)); | |
2904 | memcpy (tmp, data, len); | |
2905 | regcache->cooked_write (regnum, tmp); | |
2906 | } | |
2907 | ||
dbbb1059 AB |
2908 | /* Implement the push dummy call gdbarch callback. */ |
2909 | ||
2910 | static CORE_ADDR | |
2911 | riscv_push_dummy_call (struct gdbarch *gdbarch, | |
2912 | struct value *function, | |
2913 | struct regcache *regcache, | |
2914 | CORE_ADDR bp_addr, | |
2915 | int nargs, | |
2916 | struct value **args, | |
2917 | CORE_ADDR sp, | |
cf84fa6b | 2918 | function_call_return_method return_method, |
dbbb1059 AB |
2919 | CORE_ADDR struct_addr) |
2920 | { | |
2921 | int i; | |
2922 | CORE_ADDR sp_args, sp_refs; | |
2923 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
dbbb1059 AB |
2924 | |
2925 | struct riscv_arg_info *arg_info = | |
2926 | (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info)); | |
dbbb1059 AB |
2927 | |
2928 | struct riscv_call_info call_info (gdbarch); | |
2929 | ||
2930 | CORE_ADDR osp = sp; | |
2931 | ||
8b2d40cb JW |
2932 | struct type *ftype = check_typedef (value_type (function)); |
2933 | ||
78134374 | 2934 | if (ftype->code () == TYPE_CODE_PTR) |
8b2d40cb JW |
2935 | ftype = check_typedef (TYPE_TARGET_TYPE (ftype)); |
2936 | ||
dbbb1059 | 2937 | /* We'll use register $a0 if we're returning a struct. */ |
cf84fa6b | 2938 | if (return_method == return_method_struct) |
dbbb1059 AB |
2939 | ++call_info.int_regs.next_regnum; |
2940 | ||
b926417a | 2941 | for (i = 0; i < nargs; ++i) |
dbbb1059 AB |
2942 | { |
2943 | struct value *arg_value; | |
2944 | struct type *arg_type; | |
b926417a | 2945 | struct riscv_arg_info *info = &arg_info[i]; |
dbbb1059 AB |
2946 | |
2947 | arg_value = args[i]; | |
2948 | arg_type = check_typedef (value_type (arg_value)); | |
2949 | ||
8b2d40cb | 2950 | riscv_arg_location (gdbarch, info, &call_info, arg_type, |
a409645d | 2951 | ftype->has_varargs () && i >= ftype->num_fields ()); |
dbbb1059 AB |
2952 | |
2953 | if (info->type != arg_type) | |
2954 | arg_value = value_cast (info->type, arg_value); | |
50888e42 | 2955 | info->contents = value_contents (arg_value).data (); |
dbbb1059 AB |
2956 | } |
2957 | ||
2958 | /* Adjust the stack pointer and align it. */ | |
2959 | sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT); | |
2960 | sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT); | |
2961 | ||
2962 | if (riscv_debug_infcall > 0) | |
2963 | { | |
6cb06a8c TT |
2964 | gdb_printf (gdb_stdlog, "dummy call args:\n"); |
2965 | gdb_printf (gdb_stdlog, ": floating point ABI %s in use\n", | |
2966 | (riscv_has_fp_abi (gdbarch) ? "is" : "is not")); | |
2967 | gdb_printf (gdb_stdlog, ": xlen: %d\n: flen: %d\n", | |
2968 | call_info.xlen, call_info.flen); | |
cf84fa6b | 2969 | if (return_method == return_method_struct) |
6cb06a8c TT |
2970 | gdb_printf (gdb_stdlog, |
2971 | "[*] struct return pointer in register $A0\n"); | |
dbbb1059 AB |
2972 | for (i = 0; i < nargs; ++i) |
2973 | { | |
2974 | struct riscv_arg_info *info = &arg_info [i]; | |
2975 | ||
6cb06a8c | 2976 | gdb_printf (gdb_stdlog, "[%2d] ", i); |
cab5bb9d | 2977 | riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args); |
6cb06a8c | 2978 | gdb_printf (gdb_stdlog, "\n"); |
dbbb1059 AB |
2979 | } |
2980 | if (call_info.memory.arg_offset > 0 | |
2981 | || call_info.memory.ref_offset > 0) | |
2982 | { | |
6cb06a8c TT |
2983 | gdb_printf (gdb_stdlog, " Original sp: %s\n", |
2984 | core_addr_to_string (osp)); | |
2985 | gdb_printf (gdb_stdlog, "Stack required (for args): 0x%x\n", | |
2986 | call_info.memory.arg_offset); | |
2987 | gdb_printf (gdb_stdlog, "Stack required (for refs): 0x%x\n", | |
2988 | call_info.memory.ref_offset); | |
2989 | gdb_printf (gdb_stdlog, " Stack allocated: %s\n", | |
2990 | core_addr_to_string_nz (osp - sp)); | |
dbbb1059 AB |
2991 | } |
2992 | } | |
2993 | ||
2994 | /* Now load the argument into registers, or onto the stack. */ | |
2995 | ||
cf84fa6b | 2996 | if (return_method == return_method_struct) |
dbbb1059 AB |
2997 | { |
2998 | gdb_byte buf[sizeof (LONGEST)]; | |
2999 | ||
3000 | store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr); | |
b66f5587 | 3001 | regcache->cooked_write (RISCV_A0_REGNUM, buf); |
dbbb1059 AB |
3002 | } |
3003 | ||
3004 | for (i = 0; i < nargs; ++i) | |
3005 | { | |
3006 | CORE_ADDR dst; | |
3007 | int second_arg_length = 0; | |
3008 | const gdb_byte *second_arg_data; | |
3009 | struct riscv_arg_info *info = &arg_info [i]; | |
3010 | ||
3011 | gdb_assert (info->length > 0); | |
3012 | ||
3013 | switch (info->argloc[0].loc_type) | |
3014 | { | |
3015 | case riscv_arg_info::location::in_reg: | |
3016 | { | |
dbbb1059 | 3017 | gdb_assert (info->argloc[0].c_length <= info->length); |
dd895392 AB |
3018 | |
3019 | riscv_regcache_cooked_write (info->argloc[0].loc_data.regno, | |
3020 | (info->contents | |
3021 | + info->argloc[0].c_offset), | |
3022 | info->argloc[0].c_length, | |
3023 | regcache, call_info.flen); | |
dbbb1059 | 3024 | second_arg_length = |
9f0272f8 | 3025 | (((info->argloc[0].c_length + info->argloc[0].c_offset) < info->length) |
dbbb1059 AB |
3026 | ? info->argloc[1].c_length : 0); |
3027 | second_arg_data = info->contents + info->argloc[1].c_offset; | |
3028 | } | |
3029 | break; | |
3030 | ||
3031 | case riscv_arg_info::location::on_stack: | |
3032 | dst = sp_args + info->argloc[0].loc_data.offset; | |
3033 | write_memory (dst, info->contents, info->length); | |
3034 | second_arg_length = 0; | |
3035 | break; | |
3036 | ||
3037 | case riscv_arg_info::location::by_ref: | |
3038 | dst = sp_refs + info->argloc[0].loc_data.offset; | |
3039 | write_memory (dst, info->contents, info->length); | |
3040 | ||
3041 | second_arg_length = call_info.xlen; | |
3042 | second_arg_data = (gdb_byte *) &dst; | |
3043 | break; | |
3044 | ||
3045 | default: | |
557b4d76 | 3046 | gdb_assert_not_reached ("unknown argument location type"); |
dbbb1059 AB |
3047 | } |
3048 | ||
3049 | if (second_arg_length > 0) | |
3050 | { | |
3051 | switch (info->argloc[1].loc_type) | |
3052 | { | |
3053 | case riscv_arg_info::location::in_reg: | |
3054 | { | |
8c49aa89 AB |
3055 | gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno) |
3056 | && second_arg_length <= call_info.flen) | |
3057 | || second_arg_length <= call_info.xlen); | |
dd895392 AB |
3058 | riscv_regcache_cooked_write (info->argloc[1].loc_data.regno, |
3059 | second_arg_data, | |
3060 | second_arg_length, | |
3061 | regcache, call_info.flen); | |
dbbb1059 AB |
3062 | } |
3063 | break; | |
3064 | ||
3065 | case riscv_arg_info::location::on_stack: | |
3066 | { | |
3067 | CORE_ADDR arg_addr; | |
3068 | ||
3069 | arg_addr = sp_args + info->argloc[1].loc_data.offset; | |
3070 | write_memory (arg_addr, second_arg_data, second_arg_length); | |
3071 | break; | |
3072 | } | |
3073 | ||
3074 | case riscv_arg_info::location::by_ref: | |
3075 | default: | |
3076 | /* The second location should never be a reference, any | |
3077 | argument being passed by reference just places its address | |
3078 | in the first location and is done. */ | |
3079 | error (_("invalid argument location")); | |
3080 | break; | |
3081 | } | |
3082 | } | |
3083 | } | |
3084 | ||
3085 | /* Set the dummy return value to bp_addr. | |
3086 | A dummy breakpoint will be setup to execute the call. */ | |
3087 | ||
3088 | if (riscv_debug_infcall > 0) | |
6cb06a8c TT |
3089 | gdb_printf (gdb_stdlog, ": writing $ra = %s\n", |
3090 | core_addr_to_string (bp_addr)); | |
dbbb1059 AB |
3091 | regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr); |
3092 | ||
3093 | /* Finally, update the stack pointer. */ | |
3094 | ||
3095 | if (riscv_debug_infcall > 0) | |
6cb06a8c TT |
3096 | gdb_printf (gdb_stdlog, ": writing $sp = %s\n", |
3097 | core_addr_to_string (sp)); | |
dbbb1059 AB |
3098 | regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp); |
3099 | ||
3100 | return sp; | |
3101 | } | |
3102 | ||
3103 | /* Implement the return_value gdbarch method. */ | |
3104 | ||
3105 | static enum return_value_convention | |
3106 | riscv_return_value (struct gdbarch *gdbarch, | |
3107 | struct value *function, | |
3108 | struct type *type, | |
3109 | struct regcache *regcache, | |
3110 | gdb_byte *readbuf, | |
3111 | const gdb_byte *writebuf) | |
3112 | { | |
dbbb1059 AB |
3113 | struct riscv_call_info call_info (gdbarch); |
3114 | struct riscv_arg_info info; | |
3115 | struct type *arg_type; | |
3116 | ||
3117 | arg_type = check_typedef (type); | |
8b2d40cb | 3118 | riscv_arg_location (gdbarch, &info, &call_info, arg_type, false); |
dbbb1059 AB |
3119 | |
3120 | if (riscv_debug_infcall > 0) | |
3121 | { | |
6cb06a8c TT |
3122 | gdb_printf (gdb_stdlog, "riscv return value:\n"); |
3123 | gdb_printf (gdb_stdlog, "[R] "); | |
cab5bb9d | 3124 | riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0); |
6cb06a8c | 3125 | gdb_printf (gdb_stdlog, "\n"); |
dbbb1059 AB |
3126 | } |
3127 | ||
3128 | if (readbuf != nullptr || writebuf != nullptr) | |
3129 | { | |
74e3300d AB |
3130 | unsigned int arg_len; |
3131 | struct value *abi_val; | |
3132 | gdb_byte *old_readbuf = nullptr; | |
3133 | int regnum; | |
3134 | ||
3135 | /* We only do one thing at a time. */ | |
3136 | gdb_assert (readbuf == nullptr || writebuf == nullptr); | |
3137 | ||
3138 | /* In some cases the argument is not returned as the declared type, | |
3139 | and we need to cast to or from the ABI type in order to | |
3140 | correctly access the argument. When writing to the machine we | |
3141 | do the cast here, when reading from the machine the cast occurs | |
3142 | later, after extracting the value. As the ABI type can be | |
3143 | larger than the declared type, then the read or write buffers | |
3144 | passed in might be too small. Here we ensure that we are using | |
3145 | buffers of sufficient size. */ | |
3146 | if (writebuf != nullptr) | |
3147 | { | |
0abb4049 JB |
3148 | struct value *arg_val; |
3149 | ||
3150 | if (is_fixed_point_type (arg_type)) | |
3151 | { | |
3152 | /* Convert the argument to the type used to pass | |
3153 | the return value, but being careful to preserve | |
3154 | the fact that the value needs to be returned | |
3155 | unscaled. */ | |
3156 | gdb_mpz unscaled; | |
3157 | ||
3158 | unscaled.read (gdb::make_array_view (writebuf, | |
3159 | TYPE_LENGTH (arg_type)), | |
3160 | type_byte_order (arg_type), | |
3161 | arg_type->is_unsigned ()); | |
3162 | abi_val = allocate_value (info.type); | |
3163 | unscaled.write (value_contents_raw (abi_val), | |
3164 | type_byte_order (info.type), | |
3165 | info.type->is_unsigned ()); | |
3166 | } | |
3167 | else | |
3168 | { | |
3169 | arg_val = value_from_contents (arg_type, writebuf); | |
3170 | abi_val = value_cast (info.type, arg_val); | |
3171 | } | |
50888e42 | 3172 | writebuf = value_contents_raw (abi_val).data (); |
74e3300d AB |
3173 | } |
3174 | else | |
3175 | { | |
3176 | abi_val = allocate_value (info.type); | |
3177 | old_readbuf = readbuf; | |
50888e42 | 3178 | readbuf = value_contents_raw (abi_val).data (); |
74e3300d AB |
3179 | } |
3180 | arg_len = TYPE_LENGTH (info.type); | |
dbbb1059 AB |
3181 | |
3182 | switch (info.argloc[0].loc_type) | |
3183 | { | |
3184 | /* Return value in register(s). */ | |
3185 | case riscv_arg_info::location::in_reg: | |
3186 | { | |
3187 | regnum = info.argloc[0].loc_data.regno; | |
dda83cd7 SM |
3188 | gdb_assert (info.argloc[0].c_length <= arg_len); |
3189 | gdb_assert (info.argloc[0].c_length | |
74e3300d | 3190 | <= register_size (gdbarch, regnum)); |
dbbb1059 AB |
3191 | |
3192 | if (readbuf) | |
9f0272f8 AB |
3193 | { |
3194 | gdb_byte *ptr = readbuf + info.argloc[0].c_offset; | |
3195 | regcache->cooked_read_part (regnum, 0, | |
3196 | info.argloc[0].c_length, | |
3197 | ptr); | |
3198 | } | |
dbbb1059 AB |
3199 | |
3200 | if (writebuf) | |
9f0272f8 AB |
3201 | { |
3202 | const gdb_byte *ptr = writebuf + info.argloc[0].c_offset; | |
dd895392 | 3203 | riscv_regcache_cooked_write (regnum, ptr, |
9f0272f8 | 3204 | info.argloc[0].c_length, |
dd895392 | 3205 | regcache, call_info.flen); |
9f0272f8 | 3206 | } |
dbbb1059 AB |
3207 | |
3208 | /* A return value in register can have a second part in a | |
3209 | second register. */ | |
9f0272f8 | 3210 | if (info.argloc[1].c_length > 0) |
dbbb1059 AB |
3211 | { |
3212 | switch (info.argloc[1].loc_type) | |
3213 | { | |
3214 | case riscv_arg_info::location::in_reg: | |
3215 | regnum = info.argloc[1].loc_data.regno; | |
3216 | ||
dda83cd7 | 3217 | gdb_assert ((info.argloc[0].c_length |
74e3300d | 3218 | + info.argloc[1].c_length) <= arg_len); |
dda83cd7 | 3219 | gdb_assert (info.argloc[1].c_length |
74e3300d AB |
3220 | <= register_size (gdbarch, regnum)); |
3221 | ||
dbbb1059 AB |
3222 | if (readbuf) |
3223 | { | |
3224 | readbuf += info.argloc[1].c_offset; | |
74e3300d AB |
3225 | regcache->cooked_read_part (regnum, 0, |
3226 | info.argloc[1].c_length, | |
3227 | readbuf); | |
dbbb1059 AB |
3228 | } |
3229 | ||
3230 | if (writebuf) | |
3231 | { | |
dd895392 AB |
3232 | const gdb_byte *ptr |
3233 | = writebuf + info.argloc[1].c_offset; | |
3234 | riscv_regcache_cooked_write | |
3235 | (regnum, ptr, info.argloc[1].c_length, | |
3236 | regcache, call_info.flen); | |
dbbb1059 AB |
3237 | } |
3238 | break; | |
3239 | ||
3240 | case riscv_arg_info::location::by_ref: | |
3241 | case riscv_arg_info::location::on_stack: | |
3242 | default: | |
3243 | error (_("invalid argument location")); | |
3244 | break; | |
3245 | } | |
3246 | } | |
3247 | } | |
3248 | break; | |
3249 | ||
3250 | /* Return value by reference will have its address in A0. */ | |
3251 | case riscv_arg_info::location::by_ref: | |
3252 | { | |
b2970c23 | 3253 | ULONGEST addr; |
dbbb1059 AB |
3254 | |
3255 | regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM, | |
3256 | &addr); | |
3257 | if (readbuf != nullptr) | |
3258 | read_memory (addr, readbuf, info.length); | |
3259 | if (writebuf != nullptr) | |
3260 | write_memory (addr, writebuf, info.length); | |
3261 | } | |
3262 | break; | |
3263 | ||
3264 | case riscv_arg_info::location::on_stack: | |
3265 | default: | |
3266 | error (_("invalid argument location")); | |
3267 | break; | |
3268 | } | |
74e3300d AB |
3269 | |
3270 | /* This completes the cast from abi type back to the declared type | |
3271 | in the case that we are reading from the machine. See the | |
3272 | comment at the head of this block for more details. */ | |
3273 | if (readbuf != nullptr) | |
3274 | { | |
0abb4049 JB |
3275 | struct value *arg_val; |
3276 | ||
3277 | if (is_fixed_point_type (arg_type)) | |
3278 | { | |
3279 | /* Convert abi_val to the actual return type, but | |
3280 | being careful to preserve the fact that abi_val | |
3281 | is unscaled. */ | |
3282 | gdb_mpz unscaled; | |
3283 | ||
3284 | unscaled.read (value_contents (abi_val), | |
3285 | type_byte_order (info.type), | |
3286 | info.type->is_unsigned ()); | |
3287 | arg_val = allocate_value (arg_type); | |
3288 | unscaled.write (value_contents_raw (arg_val), | |
3289 | type_byte_order (arg_type), | |
3290 | arg_type->is_unsigned ()); | |
3291 | } | |
3292 | else | |
3293 | arg_val = value_cast (arg_type, abi_val); | |
50888e42 | 3294 | memcpy (old_readbuf, value_contents_raw (arg_val).data (), |
74e3300d AB |
3295 | TYPE_LENGTH (arg_type)); |
3296 | } | |
dbbb1059 AB |
3297 | } |
3298 | ||
3299 | switch (info.argloc[0].loc_type) | |
3300 | { | |
3301 | case riscv_arg_info::location::in_reg: | |
3302 | return RETURN_VALUE_REGISTER_CONVENTION; | |
3303 | case riscv_arg_info::location::by_ref: | |
d4be21dc | 3304 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; |
dbbb1059 AB |
3305 | case riscv_arg_info::location::on_stack: |
3306 | default: | |
3307 | error (_("invalid argument location")); | |
3308 | } | |
3309 | } | |
3310 | ||
3311 | /* Implement the frame_align gdbarch method. */ | |
3312 | ||
3313 | static CORE_ADDR | |
3314 | riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
3315 | { | |
3316 | return align_down (addr, 16); | |
3317 | } | |
3318 | ||
dbbb1059 AB |
3319 | /* Generate, or return the cached frame cache for the RiscV frame |
3320 | unwinder. */ | |
3321 | ||
78a3b0fa | 3322 | static struct riscv_unwind_cache * |
dbbb1059 AB |
3323 | riscv_frame_cache (struct frame_info *this_frame, void **this_cache) |
3324 | { | |
78a3b0fa AB |
3325 | CORE_ADDR pc, start_addr; |
3326 | struct riscv_unwind_cache *cache; | |
dbbb1059 | 3327 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
78a3b0fa | 3328 | int numregs, regno; |
dbbb1059 AB |
3329 | |
3330 | if ((*this_cache) != NULL) | |
78a3b0fa | 3331 | return (struct riscv_unwind_cache *) *this_cache; |
dbbb1059 | 3332 | |
78a3b0fa AB |
3333 | cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache); |
3334 | cache->regs = trad_frame_alloc_saved_regs (this_frame); | |
3335 | (*this_cache) = cache; | |
dbbb1059 | 3336 | |
78a3b0fa AB |
3337 | /* Scan the prologue, filling in the cache. */ |
3338 | start_addr = get_frame_func (this_frame); | |
dbbb1059 | 3339 | pc = get_frame_pc (this_frame); |
78a3b0fa AB |
3340 | riscv_scan_prologue (gdbarch, start_addr, pc, cache); |
3341 | ||
3342 | /* We can now calculate the frame base address. */ | |
3343 | cache->frame_base | |
e1f57067 | 3344 | = (get_frame_register_unsigned (this_frame, cache->frame_base_reg) |
6c9d681b | 3345 | + cache->frame_base_offset); |
78a3b0fa | 3346 | if (riscv_debug_unwinder) |
6cb06a8c TT |
3347 | gdb_printf (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n", |
3348 | core_addr_to_string (cache->frame_base), | |
3349 | gdbarch_register_name (gdbarch, | |
3350 | cache->frame_base_reg), | |
3351 | cache->frame_base_offset); | |
78a3b0fa AB |
3352 | |
3353 | /* The prologue scanner sets the address of registers stored to the stack | |
3354 | as the offset of that register from the frame base. The prologue | |
3355 | scanner doesn't know the actual frame base value, and so is unable to | |
3356 | compute the exact address. We do now know the frame base value, so | |
3357 | update the address of registers stored to the stack. */ | |
3358 | numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); | |
3359 | for (regno = 0; regno < numregs; ++regno) | |
3360 | { | |
a9a87d35 | 3361 | if (cache->regs[regno].is_addr ()) |
098caef4 LM |
3362 | cache->regs[regno].set_addr (cache->regs[regno].addr () |
3363 | + cache->frame_base); | |
78a3b0fa AB |
3364 | } |
3365 | ||
3366 | /* The previous $pc can be found wherever the $ra value can be found. | |
3367 | The previous $ra value is gone, this would have been stored be the | |
3368 | previous frame if required. */ | |
3369 | cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM]; | |
a9a87d35 | 3370 | cache->regs[RISCV_RA_REGNUM].set_unknown (); |
78a3b0fa AB |
3371 | |
3372 | /* Build the frame id. */ | |
3373 | cache->this_id = frame_id_build (cache->frame_base, start_addr); | |
dbbb1059 | 3374 | |
78a3b0fa | 3375 | /* The previous $sp value is the frame base value. */ |
a9a87d35 | 3376 | cache->regs[gdbarch_sp_regnum (gdbarch)].set_value (cache->frame_base); |
dbbb1059 | 3377 | |
78a3b0fa | 3378 | return cache; |
dbbb1059 AB |
3379 | } |
3380 | ||
3381 | /* Implement the this_id callback for RiscV frame unwinder. */ | |
3382 | ||
3383 | static void | |
3384 | riscv_frame_this_id (struct frame_info *this_frame, | |
3385 | void **prologue_cache, | |
3386 | struct frame_id *this_id) | |
3387 | { | |
78a3b0fa | 3388 | struct riscv_unwind_cache *cache; |
dbbb1059 | 3389 | |
a70b8144 | 3390 | try |
17cf2897 AB |
3391 | { |
3392 | cache = riscv_frame_cache (this_frame, prologue_cache); | |
3393 | *this_id = cache->this_id; | |
3394 | } | |
230d2906 | 3395 | catch (const gdb_exception_error &ex) |
17cf2897 AB |
3396 | { |
3397 | /* Ignore errors, this leaves the frame id as the predefined outer | |
dda83cd7 | 3398 | frame id which terminates the backtrace at this point. */ |
17cf2897 | 3399 | } |
dbbb1059 AB |
3400 | } |
3401 | ||
3402 | /* Implement the prev_register callback for RiscV frame unwinder. */ | |
3403 | ||
3404 | static struct value * | |
3405 | riscv_frame_prev_register (struct frame_info *this_frame, | |
3406 | void **prologue_cache, | |
3407 | int regnum) | |
3408 | { | |
78a3b0fa | 3409 | struct riscv_unwind_cache *cache; |
dbbb1059 | 3410 | |
78a3b0fa AB |
3411 | cache = riscv_frame_cache (this_frame, prologue_cache); |
3412 | return trad_frame_get_prev_register (this_frame, cache->regs, regnum); | |
dbbb1059 AB |
3413 | } |
3414 | ||
3415 | /* Structure defining the RiscV normal frame unwind functions. Since we | |
3416 | are the fallback unwinder (DWARF unwinder is used first), we use the | |
3417 | default frame sniffer, which always accepts the frame. */ | |
3418 | ||
3419 | static const struct frame_unwind riscv_frame_unwind = | |
3420 | { | |
a154d838 | 3421 | /*.name =*/ "riscv prologue", |
dbbb1059 AB |
3422 | /*.type =*/ NORMAL_FRAME, |
3423 | /*.stop_reason =*/ default_frame_unwind_stop_reason, | |
3424 | /*.this_id =*/ riscv_frame_this_id, | |
3425 | /*.prev_register =*/ riscv_frame_prev_register, | |
3426 | /*.unwind_data =*/ NULL, | |
3427 | /*.sniffer =*/ default_frame_sniffer, | |
3428 | /*.dealloc_cache =*/ NULL, | |
3429 | /*.prev_arch =*/ NULL, | |
3430 | }; | |
3431 | ||
895b7b4e AB |
3432 | /* Extract a set of required target features out of ABFD. If ABFD is |
3433 | nullptr then a RISCV_GDBARCH_FEATURES is returned in its default state. */ | |
dbbb1059 | 3434 | |
90af0679 | 3435 | static struct riscv_gdbarch_features |
895b7b4e | 3436 | riscv_features_from_bfd (const bfd *abfd) |
dbbb1059 | 3437 | { |
b5ffee31 | 3438 | struct riscv_gdbarch_features features; |
dbbb1059 | 3439 | |
b5ffee31 AB |
3440 | /* Now try to improve on the defaults by looking at the binary we are |
3441 | going to execute. We assume the user knows what they are doing and | |
3442 | that the target will match the binary. Remember, this code path is | |
3443 | only used at all if the target hasn't given us a description, so this | |
3444 | is really a last ditched effort to do something sane before giving | |
3445 | up. */ | |
895b7b4e | 3446 | if (abfd != nullptr && bfd_get_flavour (abfd) == bfd_target_elf_flavour) |
dbbb1059 | 3447 | { |
895b7b4e AB |
3448 | unsigned char eclass = elf_elfheader (abfd)->e_ident[EI_CLASS]; |
3449 | int e_flags = elf_elfheader (abfd)->e_flags; | |
dbbb1059 AB |
3450 | |
3451 | if (eclass == ELFCLASS32) | |
b5ffee31 | 3452 | features.xlen = 4; |
dbbb1059 | 3453 | else if (eclass == ELFCLASS64) |
b5ffee31 | 3454 | features.xlen = 8; |
dbbb1059 | 3455 | else |
b5ffee31 | 3456 | internal_error (__FILE__, __LINE__, |
dbbb1059 AB |
3457 | _("unknown ELF header class %d"), eclass); |
3458 | ||
dbbb1059 | 3459 | if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE) |
113b7b81 | 3460 | features.flen = 8; |
dbbb1059 | 3461 | else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE) |
113b7b81 | 3462 | features.flen = 4; |
25428040 AB |
3463 | |
3464 | if (e_flags & EF_RISCV_RVE) | |
3465 | { | |
3466 | if (features.xlen == 8) | |
3467 | { | |
3468 | warning (_("64-bit ELF with RV32E flag set! Assuming 32-bit")); | |
3469 | features.xlen = 4; | |
3470 | } | |
3471 | features.embedded = true; | |
3472 | } | |
dbbb1059 | 3473 | } |
dbbb1059 | 3474 | |
90af0679 AB |
3475 | return features; |
3476 | } | |
3477 | ||
3478 | /* Find a suitable default target description. Use the contents of INFO, | |
3479 | specifically the bfd object being executed, to guide the selection of a | |
3480 | suitable default target description. */ | |
3481 | ||
3482 | static const struct target_desc * | |
3483 | riscv_find_default_target_description (const struct gdbarch_info info) | |
3484 | { | |
3485 | /* Extract desired feature set from INFO. */ | |
3486 | struct riscv_gdbarch_features features | |
895b7b4e | 3487 | = riscv_features_from_bfd (info.abfd); |
90af0679 | 3488 | |
895b7b4e AB |
3489 | /* If the XLEN field is still 0 then we got nothing useful from INFO.BFD, |
3490 | maybe there was no bfd object. In this case we fall back to a minimal | |
3491 | useful target with no floating point, the x-register size is selected | |
3492 | based on the architecture from INFO. */ | |
90af0679 | 3493 | if (features.xlen == 0) |
895b7b4e | 3494 | features.xlen = info.bfd_arch_info->bits_per_word == 32 ? 4 : 8; |
90af0679 | 3495 | |
b5ffee31 | 3496 | /* Now build a target description based on the feature set. */ |
d1c9b20f | 3497 | return riscv_lookup_target_description (features); |
b5ffee31 AB |
3498 | } |
3499 | ||
b5ffee31 AB |
3500 | /* Add all the expected register sets into GDBARCH. */ |
3501 | ||
3502 | static void | |
3503 | riscv_add_reggroups (struct gdbarch *gdbarch) | |
3504 | { | |
3505 | /* Add predefined register groups. */ | |
3506 | reggroup_add (gdbarch, all_reggroup); | |
3507 | reggroup_add (gdbarch, save_reggroup); | |
3508 | reggroup_add (gdbarch, restore_reggroup); | |
3509 | reggroup_add (gdbarch, system_reggroup); | |
3510 | reggroup_add (gdbarch, vector_reggroup); | |
3511 | reggroup_add (gdbarch, general_reggroup); | |
3512 | reggroup_add (gdbarch, float_reggroup); | |
3513 | ||
3514 | /* Add RISC-V specific register groups. */ | |
3515 | reggroup_add (gdbarch, csr_reggroup); | |
3516 | } | |
3517 | ||
fb44d95a AB |
3518 | /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */ |
3519 | ||
3520 | static int | |
3521 | riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) | |
3522 | { | |
3523 | if (reg < RISCV_DWARF_REGNUM_X31) | |
3524 | return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0); | |
3525 | ||
3526 | else if (reg < RISCV_DWARF_REGNUM_F31) | |
3527 | return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0); | |
3528 | ||
550820e1 AB |
3529 | else if (reg >= RISCV_DWARF_FIRST_CSR && reg <= RISCV_DWARF_LAST_CSR) |
3530 | return RISCV_FIRST_CSR_REGNUM + (reg - RISCV_DWARF_FIRST_CSR); | |
3531 | ||
96f842cb AB |
3532 | else if (reg >= RISCV_DWARF_REGNUM_V0 && reg <= RISCV_DWARF_REGNUM_V31) |
3533 | return RISCV_V0_REGNUM + (reg - RISCV_DWARF_REGNUM_V0); | |
3534 | ||
fb44d95a AB |
3535 | return -1; |
3536 | } | |
3537 | ||
ff371ec9 JW |
3538 | /* Implement the gcc_target_options method. We have to select the arch and abi |
3539 | from the feature info. We have enough feature info to select the abi, but | |
3540 | not enough info for the arch given all of the possible architecture | |
3541 | extensions. So choose reasonable defaults for now. */ | |
3542 | ||
3543 | static std::string | |
3544 | riscv_gcc_target_options (struct gdbarch *gdbarch) | |
3545 | { | |
3546 | int isa_xlen = riscv_isa_xlen (gdbarch); | |
3547 | int isa_flen = riscv_isa_flen (gdbarch); | |
3548 | int abi_xlen = riscv_abi_xlen (gdbarch); | |
3549 | int abi_flen = riscv_abi_flen (gdbarch); | |
3550 | std::string target_options; | |
3551 | ||
3552 | target_options = "-march=rv"; | |
3553 | if (isa_xlen == 8) | |
3554 | target_options += "64"; | |
3555 | else | |
3556 | target_options += "32"; | |
3557 | if (isa_flen == 8) | |
3558 | target_options += "gc"; | |
3559 | else if (isa_flen == 4) | |
3560 | target_options += "imafc"; | |
3561 | else | |
3562 | target_options += "imac"; | |
3563 | ||
3564 | target_options += " -mabi="; | |
3565 | if (abi_xlen == 8) | |
3566 | target_options += "lp64"; | |
3567 | else | |
3568 | target_options += "ilp32"; | |
3569 | if (abi_flen == 8) | |
3570 | target_options += "d"; | |
3571 | else if (abi_flen == 4) | |
3572 | target_options += "f"; | |
3573 | ||
3574 | /* The gdb loader doesn't handle link-time relaxation relocations. */ | |
3575 | target_options += " -mno-relax"; | |
3576 | ||
3577 | return target_options; | |
3578 | } | |
3579 | ||
2e52d038 AB |
3580 | /* Call back from tdesc_use_registers, called for each unknown register |
3581 | found in the target description. | |
3582 | ||
3583 | See target-description.h (typedef tdesc_unknown_register_ftype) for a | |
3584 | discussion of the arguments and return values. */ | |
3585 | ||
3586 | static int | |
3587 | riscv_tdesc_unknown_reg (struct gdbarch *gdbarch, tdesc_feature *feature, | |
3588 | const char *reg_name, int possible_regnum) | |
3589 | { | |
3590 | /* At one point in time GDB had an incorrect default target description | |
3591 | that duplicated the fflags, frm, and fcsr registers in both the FPU | |
3592 | and CSR register sets. | |
3593 | ||
3594 | Some targets (QEMU) copied these target descriptions into their source | |
3595 | tree, and so we're currently stuck working with some targets that | |
3596 | declare the same registers twice. | |
3597 | ||
3598 | There's not much we can do about this any more. Assuming the target | |
3599 | will direct a request for either register number to the correct | |
3600 | underlying hardware register then it doesn't matter which one GDB | |
3601 | uses, so long as we (GDB) are consistent (so that we don't end up with | |
3602 | invalid cache misses). | |
3603 | ||
3604 | As we always scan the FPU registers first, then the CSRs, if the | |
3605 | target has included the offending registers in both sets then we will | |
3606 | always see the FPU copies here, as the CSR versions will replace them | |
3607 | in the register list. | |
3608 | ||
3609 | To prevent these duplicates showing up in any of the register list, | |
3610 | record their register numbers here. */ | |
25428040 | 3611 | if (strcmp (tdesc_feature_name (feature), riscv_freg_feature.name ()) == 0) |
2e52d038 | 3612 | { |
345bd07c | 3613 | riscv_gdbarch_tdep *tdep = (riscv_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
2e52d038 AB |
3614 | int *regnum_ptr = nullptr; |
3615 | ||
3616 | if (strcmp (reg_name, "fflags") == 0) | |
3617 | regnum_ptr = &tdep->duplicate_fflags_regnum; | |
3618 | else if (strcmp (reg_name, "frm") == 0) | |
3619 | regnum_ptr = &tdep->duplicate_frm_regnum; | |
3620 | else if (strcmp (reg_name, "fcsr") == 0) | |
3621 | regnum_ptr = &tdep->duplicate_fcsr_regnum; | |
3622 | ||
3623 | if (regnum_ptr != nullptr) | |
3624 | { | |
3625 | /* This means the register appears more than twice in the target | |
3626 | description. Just let GDB add this as another register. | |
3627 | We'll have duplicates in the register name list, but there's | |
3628 | not much more we can do. */ | |
3629 | if (*regnum_ptr != -1) | |
3630 | return -1; | |
3631 | ||
3632 | /* Record the number assigned to this register, then return the | |
3633 | number (so it actually gets assigned to this register). */ | |
3634 | *regnum_ptr = possible_regnum; | |
3635 | return possible_regnum; | |
3636 | } | |
3637 | } | |
3638 | ||
3639 | /* Any unknown registers in the CSR feature are recorded within a single | |
3640 | block so we can easily identify these registers when making choices | |
3641 | about register groups in riscv_register_reggroup_p. */ | |
25428040 | 3642 | if (strcmp (tdesc_feature_name (feature), riscv_csr_feature.name ()) == 0) |
2e52d038 | 3643 | { |
345bd07c | 3644 | riscv_gdbarch_tdep *tdep = (riscv_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
2e52d038 AB |
3645 | if (tdep->unknown_csrs_first_regnum == -1) |
3646 | tdep->unknown_csrs_first_regnum = possible_regnum; | |
3647 | gdb_assert (tdep->unknown_csrs_first_regnum | |
3648 | + tdep->unknown_csrs_count == possible_regnum); | |
3649 | tdep->unknown_csrs_count++; | |
3650 | return possible_regnum; | |
3651 | } | |
3652 | ||
3653 | /* Some other unknown register. Don't assign this a number now, it will | |
3654 | be assigned a number automatically later by the target description | |
3655 | handling code. */ | |
3656 | return -1; | |
3657 | } | |
3658 | ||
ff371ec9 JW |
3659 | /* Implement the gnu_triplet_regexp method. A single compiler supports both |
3660 | 32-bit and 64-bit code, and may be named riscv32 or riscv64 or (not | |
3661 | recommended) riscv. */ | |
3662 | ||
3663 | static const char * | |
3664 | riscv_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
3665 | { | |
3666 | return "riscv(32|64)?"; | |
3667 | } | |
3668 | ||
b5ffee31 AB |
3669 | /* Initialize the current architecture based on INFO. If possible, |
3670 | re-use an architecture from ARCHES, which is a list of | |
3671 | architectures already created during this debugging session. | |
3672 | ||
3673 | Called e.g. at program startup, when reading a core file, and when | |
3674 | reading a binary file. */ | |
3675 | ||
3676 | static struct gdbarch * | |
3677 | riscv_gdbarch_init (struct gdbarch_info info, | |
3678 | struct gdbarch_list *arches) | |
3679 | { | |
3680 | struct gdbarch *gdbarch; | |
b5ffee31 AB |
3681 | struct riscv_gdbarch_features features; |
3682 | const struct target_desc *tdesc = info.target_desc; | |
3683 | ||
3684 | /* Ensure we always have a target description. */ | |
3685 | if (!tdesc_has_registers (tdesc)) | |
3686 | tdesc = riscv_find_default_target_description (info); | |
25428040 | 3687 | gdb_assert (tdesc != nullptr); |
b5ffee31 AB |
3688 | |
3689 | if (riscv_debug_gdbarch) | |
6cb06a8c | 3690 | gdb_printf (gdb_stdlog, "Have got a target description\n"); |
b5ffee31 | 3691 | |
c1e1314d | 3692 | tdesc_arch_data_up tdesc_data = tdesc_data_alloc (); |
767a879e | 3693 | std::vector<riscv_pending_register_alias> pending_aliases; |
b5ffee31 | 3694 | |
25428040 AB |
3695 | bool valid_p = (riscv_xreg_feature.check (tdesc, tdesc_data.get (), |
3696 | &pending_aliases, &features) | |
3697 | && riscv_freg_feature.check (tdesc, tdesc_data.get (), | |
3698 | &pending_aliases, &features) | |
3699 | && riscv_virtual_feature.check (tdesc, tdesc_data.get (), | |
3700 | &pending_aliases, &features) | |
3701 | && riscv_csr_feature.check (tdesc, tdesc_data.get (), | |
96f842cb AB |
3702 | &pending_aliases, &features) |
3703 | && riscv_vector_feature.check (tdesc, tdesc_data.get (), | |
3704 | &pending_aliases, &features)); | |
b5ffee31 AB |
3705 | if (!valid_p) |
3706 | { | |
3707 | if (riscv_debug_gdbarch) | |
6cb06a8c | 3708 | gdb_printf (gdb_stdlog, "Target description is not valid\n"); |
b5ffee31 AB |
3709 | return NULL; |
3710 | } | |
3711 | ||
90af0679 AB |
3712 | /* Have a look at what the supplied (if any) bfd object requires of the |
3713 | target, then check that this matches with what the target is | |
3714 | providing. */ | |
113b7b81 | 3715 | struct riscv_gdbarch_features abi_features |
895b7b4e | 3716 | = riscv_features_from_bfd (info.abfd); |
25428040 AB |
3717 | |
3718 | /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi | |
3719 | features from the INFO object. In this case we just treat the | |
3720 | hardware features as defining the abi. */ | |
3721 | if (abi_features.xlen == 0) | |
3722 | abi_features = features; | |
3723 | ||
113b7b81 AB |
3724 | /* In theory a binary compiled for RV32 could run on an RV64 target, |
3725 | however, this has not been tested in GDB yet, so for now we require | |
3726 | that the requested xlen match the targets xlen. */ | |
25428040 | 3727 | if (abi_features.xlen != features.xlen) |
90af0679 | 3728 | error (_("bfd requires xlen %d, but target has xlen %d"), |
dda83cd7 | 3729 | abi_features.xlen, features.xlen); |
113b7b81 AB |
3730 | /* We do support running binaries compiled for 32-bit float on targets |
3731 | with 64-bit float, so we only complain if the binary requires more | |
3732 | than the target has available. */ | |
3733 | if (abi_features.flen > features.flen) | |
90af0679 | 3734 | error (_("bfd requires flen %d, but target has flen %d"), |
dda83cd7 | 3735 | abi_features.flen, features.flen); |
90af0679 | 3736 | |
dbbb1059 AB |
3737 | /* Find a candidate among the list of pre-declared architectures. */ |
3738 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
3739 | arches != NULL; | |
3740 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
b5ffee31 AB |
3741 | { |
3742 | /* Check that the feature set of the ARCHES matches the feature set | |
dda83cd7 SM |
3743 | we are looking for. If it doesn't then we can't reuse this |
3744 | gdbarch. */ | |
345bd07c SM |
3745 | riscv_gdbarch_tdep *other_tdep |
3746 | = (riscv_gdbarch_tdep *) gdbarch_tdep (arches->gdbarch); | |
b5ffee31 | 3747 | |
113b7b81 AB |
3748 | if (other_tdep->isa_features != features |
3749 | || other_tdep->abi_features != abi_features) | |
dda83cd7 | 3750 | continue; |
b5ffee31 AB |
3751 | |
3752 | break; | |
3753 | } | |
3754 | ||
3755 | if (arches != NULL) | |
c1e1314d | 3756 | return arches->gdbarch; |
dbbb1059 AB |
3757 | |
3758 | /* None found, so create a new architecture from the information provided. */ | |
345bd07c | 3759 | riscv_gdbarch_tdep *tdep = new riscv_gdbarch_tdep; |
dbbb1059 | 3760 | gdbarch = gdbarch_alloc (&info, tdep); |
113b7b81 AB |
3761 | tdep->isa_features = features; |
3762 | tdep->abi_features = abi_features; | |
dbbb1059 AB |
3763 | |
3764 | /* Target data types. */ | |
3765 | set_gdbarch_short_bit (gdbarch, 16); | |
3766 | set_gdbarch_int_bit (gdbarch, 32); | |
3767 | set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); | |
3768 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3769 | set_gdbarch_float_bit (gdbarch, 32); | |
3770 | set_gdbarch_double_bit (gdbarch, 64); | |
3771 | set_gdbarch_long_double_bit (gdbarch, 128); | |
552f1157 | 3772 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_quad); |
dbbb1059 AB |
3773 | set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8); |
3774 | set_gdbarch_char_signed (gdbarch, 0); | |
a9158a86 | 3775 | set_gdbarch_type_align (gdbarch, riscv_type_align); |
dbbb1059 AB |
3776 | |
3777 | /* Information about the target architecture. */ | |
3778 | set_gdbarch_return_value (gdbarch, riscv_return_value); | |
3779 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc); | |
3780 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind); | |
5a77b1b4 | 3781 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
dbbb1059 | 3782 | |
dbbb1059 | 3783 | /* Functions to analyze frames. */ |
dbbb1059 AB |
3784 | set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue); |
3785 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3786 | set_gdbarch_frame_align (gdbarch, riscv_frame_align); | |
3787 | ||
dbbb1059 AB |
3788 | /* Functions handling dummy frames. */ |
3789 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
3790 | set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code); | |
3791 | set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call); | |
dbbb1059 AB |
3792 | |
3793 | /* Frame unwinders. Use DWARF debug info if available, otherwise use our own | |
3794 | unwinder. */ | |
3795 | dwarf2_append_unwinders (gdbarch); | |
3796 | frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind); | |
3797 | ||
b5ffee31 AB |
3798 | /* Register architecture. */ |
3799 | riscv_add_reggroups (gdbarch); | |
3800 | ||
fb44d95a AB |
3801 | /* Internal <-> external register number maps. */ |
3802 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, riscv_dwarf_reg_to_regnum); | |
3803 | ||
b5ffee31 AB |
3804 | /* We reserve all possible register numbers for the known registers. |
3805 | This means the target description mechanism will add any target | |
3806 | specific registers after this number. This helps make debugging GDB | |
3807 | just a little easier. */ | |
3808 | set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1); | |
3809 | ||
3810 | /* We don't have to provide the count of 0 here (its the default) but | |
3811 | include this line to make it explicit that, right now, we don't have | |
3812 | any pseudo registers on RISC-V. */ | |
3813 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
3814 | ||
3815 | /* Some specific register numbers GDB likes to know about. */ | |
3816 | set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM); | |
3817 | set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM); | |
3818 | ||
3819 | set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info); | |
3820 | ||
3821 | /* Finalise the target description registers. */ | |
c1e1314d TT |
3822 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data), |
3823 | riscv_tdesc_unknown_reg); | |
b5ffee31 AB |
3824 | |
3825 | /* Override the register type callback setup by the target description | |
3826 | mechanism. This allows us to provide special type for floating point | |
3827 | registers. */ | |
3828 | set_gdbarch_register_type (gdbarch, riscv_register_type); | |
3829 | ||
3830 | /* Override the register name callback setup by the target description | |
3831 | mechanism. This allows us to force our preferred names for the | |
3832 | registers, no matter what the target description called them. */ | |
3833 | set_gdbarch_register_name (gdbarch, riscv_register_name); | |
3834 | ||
3835 | /* Override the register group callback setup by the target description | |
3836 | mechanism. This allows us to force registers into the groups we | |
3837 | want, ignoring what the target tells us. */ | |
3838 | set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p); | |
3839 | ||
767a879e AB |
3840 | /* Create register aliases for alternative register names. We only |
3841 | create aliases for registers which were mentioned in the target | |
3842 | description. */ | |
3843 | for (const auto &alias : pending_aliases) | |
3844 | alias.create (gdbarch); | |
dbbb1059 | 3845 | |
ff371ec9 JW |
3846 | /* Compile command hooks. */ |
3847 | set_gdbarch_gcc_target_options (gdbarch, riscv_gcc_target_options); | |
3848 | set_gdbarch_gnu_triplet_regexp (gdbarch, riscv_gnu_triplet_regexp); | |
3849 | ||
61a5375b AB |
3850 | /* Disassembler options support. */ |
3851 | set_gdbarch_valid_disassembler_options (gdbarch, | |
3852 | disassembler_options_riscv ()); | |
3853 | set_gdbarch_disassembler_options (gdbarch, &riscv_disassembler_options); | |
3854 | ||
117a0e99 JW |
3855 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
3856 | gdbarch_init_osabi (info, gdbarch); | |
3857 | ||
db3ad2f0 TT |
3858 | register_riscv_ravenscar_ops (gdbarch); |
3859 | ||
dbbb1059 AB |
3860 | return gdbarch; |
3861 | } | |
3862 | ||
5c720ed8 JW |
3863 | /* This decodes the current instruction and determines the address of the |
3864 | next instruction. */ | |
3865 | ||
3866 | static CORE_ADDR | |
3867 | riscv_next_pc (struct regcache *regcache, CORE_ADDR pc) | |
3868 | { | |
3869 | struct gdbarch *gdbarch = regcache->arch (); | |
345bd07c SM |
3870 | const riscv_gdbarch_tdep *tdep |
3871 | = (riscv_gdbarch_tdep *) gdbarch_tdep (gdbarch); | |
5c720ed8 JW |
3872 | struct riscv_insn insn; |
3873 | CORE_ADDR next_pc; | |
3874 | ||
3875 | insn.decode (gdbarch, pc); | |
3876 | next_pc = pc + insn.length (); | |
3877 | ||
3878 | if (insn.opcode () == riscv_insn::JAL) | |
3879 | next_pc = pc + insn.imm_signed (); | |
3880 | else if (insn.opcode () == riscv_insn::JALR) | |
3881 | { | |
3882 | LONGEST source; | |
3883 | regcache->cooked_read (insn.rs1 (), &source); | |
3884 | next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1; | |
3885 | } | |
3886 | else if (insn.opcode () == riscv_insn::BEQ) | |
3887 | { | |
3888 | LONGEST src1, src2; | |
3889 | regcache->cooked_read (insn.rs1 (), &src1); | |
3890 | regcache->cooked_read (insn.rs2 (), &src2); | |
3891 | if (src1 == src2) | |
3892 | next_pc = pc + insn.imm_signed (); | |
3893 | } | |
3894 | else if (insn.opcode () == riscv_insn::BNE) | |
3895 | { | |
3896 | LONGEST src1, src2; | |
3897 | regcache->cooked_read (insn.rs1 (), &src1); | |
3898 | regcache->cooked_read (insn.rs2 (), &src2); | |
3899 | if (src1 != src2) | |
3900 | next_pc = pc + insn.imm_signed (); | |
3901 | } | |
3902 | else if (insn.opcode () == riscv_insn::BLT) | |
3903 | { | |
3904 | LONGEST src1, src2; | |
3905 | regcache->cooked_read (insn.rs1 (), &src1); | |
3906 | regcache->cooked_read (insn.rs2 (), &src2); | |
3907 | if (src1 < src2) | |
3908 | next_pc = pc + insn.imm_signed (); | |
3909 | } | |
3910 | else if (insn.opcode () == riscv_insn::BGE) | |
3911 | { | |
3912 | LONGEST src1, src2; | |
3913 | regcache->cooked_read (insn.rs1 (), &src1); | |
3914 | regcache->cooked_read (insn.rs2 (), &src2); | |
3915 | if (src1 >= src2) | |
3916 | next_pc = pc + insn.imm_signed (); | |
3917 | } | |
3918 | else if (insn.opcode () == riscv_insn::BLTU) | |
3919 | { | |
3920 | ULONGEST src1, src2; | |
3921 | regcache->cooked_read (insn.rs1 (), &src1); | |
3922 | regcache->cooked_read (insn.rs2 (), &src2); | |
3923 | if (src1 < src2) | |
3924 | next_pc = pc + insn.imm_signed (); | |
3925 | } | |
3926 | else if (insn.opcode () == riscv_insn::BGEU) | |
3927 | { | |
3928 | ULONGEST src1, src2; | |
3929 | regcache->cooked_read (insn.rs1 (), &src1); | |
3930 | regcache->cooked_read (insn.rs2 (), &src2); | |
3931 | if (src1 >= src2) | |
3932 | next_pc = pc + insn.imm_signed (); | |
3933 | } | |
e843807b LS |
3934 | else if (insn.opcode () == riscv_insn::ECALL) |
3935 | { | |
3936 | if (tdep->syscall_next_pc != nullptr) | |
3937 | next_pc = tdep->syscall_next_pc (get_current_frame ()); | |
3938 | } | |
5c720ed8 JW |
3939 | |
3940 | return next_pc; | |
3941 | } | |
3942 | ||
3943 | /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look | |
3944 | for the end of the sequence and put the breakpoint there. */ | |
3945 | ||
3946 | static bool | |
3947 | riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc, | |
3948 | CORE_ADDR *next_pc) | |
3949 | { | |
3950 | struct gdbarch *gdbarch = regcache->arch (); | |
3951 | struct riscv_insn insn; | |
3952 | CORE_ADDR cur_step_pc = pc; | |
3953 | CORE_ADDR last_addr = 0; | |
3954 | ||
3955 | /* First instruction has to be a load reserved. */ | |
3956 | insn.decode (gdbarch, cur_step_pc); | |
3957 | if (insn.opcode () != riscv_insn::LR) | |
3958 | return false; | |
3959 | cur_step_pc = cur_step_pc + insn.length (); | |
3960 | ||
3961 | /* Next instruction should be branch to exit. */ | |
3962 | insn.decode (gdbarch, cur_step_pc); | |
3963 | if (insn.opcode () != riscv_insn::BNE) | |
3964 | return false; | |
3965 | last_addr = cur_step_pc + insn.imm_signed (); | |
3966 | cur_step_pc = cur_step_pc + insn.length (); | |
3967 | ||
3968 | /* Next instruction should be store conditional. */ | |
3969 | insn.decode (gdbarch, cur_step_pc); | |
3970 | if (insn.opcode () != riscv_insn::SC) | |
3971 | return false; | |
3972 | cur_step_pc = cur_step_pc + insn.length (); | |
3973 | ||
3974 | /* Next instruction should be branch to start. */ | |
3975 | insn.decode (gdbarch, cur_step_pc); | |
3976 | if (insn.opcode () != riscv_insn::BNE) | |
3977 | return false; | |
3978 | if (pc != (cur_step_pc + insn.imm_signed ())) | |
3979 | return false; | |
3980 | cur_step_pc = cur_step_pc + insn.length (); | |
3981 | ||
3982 | /* We should now be at the end of the sequence. */ | |
3983 | if (cur_step_pc != last_addr) | |
3984 | return false; | |
3985 | ||
3986 | *next_pc = cur_step_pc; | |
3987 | return true; | |
3988 | } | |
3989 | ||
3990 | /* This is called just before we want to resume the inferior, if we want to | |
3991 | single-step it but there is no hardware or kernel single-step support. We | |
3992 | find the target of the coming instruction and breakpoint it. */ | |
3993 | ||
3994 | std::vector<CORE_ADDR> | |
3995 | riscv_software_single_step (struct regcache *regcache) | |
3996 | { | |
3997 | CORE_ADDR pc, next_pc; | |
3998 | ||
3999 | pc = regcache_read_pc (regcache); | |
4000 | ||
4001 | if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc)) | |
4002 | return {next_pc}; | |
4003 | ||
4004 | next_pc = riscv_next_pc (regcache, pc); | |
4005 | ||
4006 | return {next_pc}; | |
4007 | } | |
4008 | ||
b5ffee31 AB |
4009 | /* Create RISC-V specific reggroups. */ |
4010 | ||
4011 | static void | |
4012 | riscv_init_reggroups () | |
4013 | { | |
4014 | csr_reggroup = reggroup_new ("csr", USER_REGGROUP); | |
4015 | } | |
4016 | ||
6a9ad81c AB |
4017 | /* See riscv-tdep.h. */ |
4018 | ||
4019 | void | |
4020 | riscv_supply_regset (const struct regset *regset, | |
4021 | struct regcache *regcache, int regnum, | |
4022 | const void *regs, size_t len) | |
4023 | { | |
4024 | regcache->supply_regset (regset, regnum, regs, len); | |
4025 | ||
4026 | if (regnum == -1 || regnum == RISCV_ZERO_REGNUM) | |
4027 | regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM); | |
4028 | ||
4029 | if (regnum == -1 || regnum == RISCV_CSR_FFLAGS_REGNUM | |
4030 | || regnum == RISCV_CSR_FRM_REGNUM) | |
4031 | { | |
4032 | int fcsr_regnum = RISCV_CSR_FCSR_REGNUM; | |
4033 | ||
4034 | /* Ensure that FCSR has been read into REGCACHE. */ | |
4035 | if (regnum != -1) | |
4036 | regcache->supply_regset (regset, fcsr_regnum, regs, len); | |
4037 | ||
4038 | /* Grab the FCSR value if it is now in the regcache. We must check | |
4039 | the status first as, if the register was not supplied by REGSET, | |
4040 | this call will trigger a recursive attempt to fetch the | |
4041 | registers. */ | |
4042 | if (regcache->get_register_status (fcsr_regnum) == REG_VALID) | |
4043 | { | |
4044 | ULONGEST fcsr_val; | |
4045 | regcache->raw_read (fcsr_regnum, &fcsr_val); | |
4046 | ||
4047 | /* Extract the fflags and frm values. */ | |
4048 | ULONGEST fflags_val = fcsr_val & 0x1f; | |
4049 | ULONGEST frm_val = (fcsr_val >> 5) & 0x7; | |
4050 | ||
4051 | /* And supply these if needed. */ | |
4052 | if (regnum == -1 || regnum == RISCV_CSR_FFLAGS_REGNUM) | |
4053 | regcache->raw_supply_integer (RISCV_CSR_FFLAGS_REGNUM, | |
4054 | (gdb_byte *) &fflags_val, | |
4055 | sizeof (fflags_val), | |
4056 | /* is_signed */ false); | |
4057 | ||
4058 | if (regnum == -1 || regnum == RISCV_CSR_FRM_REGNUM) | |
4059 | regcache->raw_supply_integer (RISCV_CSR_FRM_REGNUM, | |
4060 | (gdb_byte *)&frm_val, | |
4061 | sizeof (fflags_val), | |
4062 | /* is_signed */ false); | |
4063 | } | |
4064 | } | |
4065 | } | |
4066 | ||
6c265988 | 4067 | void _initialize_riscv_tdep (); |
dbbb1059 | 4068 | void |
6c265988 | 4069 | _initialize_riscv_tdep () |
dbbb1059 | 4070 | { |
b5ffee31 AB |
4071 | riscv_init_reggroups (); |
4072 | ||
dbbb1059 AB |
4073 | gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL); |
4074 | ||
dbbb1059 AB |
4075 | /* Add root prefix command for all "set debug riscv" and "show debug |
4076 | riscv" commands. */ | |
f54bdb6d SM |
4077 | add_setshow_prefix_cmd ("riscv", no_class, |
4078 | _("RISC-V specific debug commands."), | |
4079 | _("RISC-V specific debug commands."), | |
4080 | &setdebugriscvcmdlist, &showdebugriscvcmdlist, | |
4081 | &setdebuglist, &showdebuglist); | |
dbbb1059 | 4082 | |
f37bc8b1 JB |
4083 | add_setshow_zuinteger_cmd ("breakpoints", class_maintenance, |
4084 | &riscv_debug_breakpoints, _("\ | |
4085 | Set riscv breakpoint debugging."), _("\ | |
4086 | Show riscv breakpoint debugging."), _("\ | |
4087 | When non-zero, print debugging information for the riscv specific parts\n\ | |
4088 | of the breakpoint mechanism."), | |
4089 | NULL, | |
4090 | show_riscv_debug_variable, | |
4091 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
4092 | ||
dbbb1059 AB |
4093 | add_setshow_zuinteger_cmd ("infcall", class_maintenance, |
4094 | &riscv_debug_infcall, _("\ | |
4095 | Set riscv inferior call debugging."), _("\ | |
4096 | Show riscv inferior call debugging."), _("\ | |
4097 | When non-zero, print debugging information for the riscv specific parts\n\ | |
4098 | of the inferior call mechanism."), | |
4099 | NULL, | |
4100 | show_riscv_debug_variable, | |
4101 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
78a3b0fa AB |
4102 | |
4103 | add_setshow_zuinteger_cmd ("unwinder", class_maintenance, | |
4104 | &riscv_debug_unwinder, _("\ | |
4105 | Set riscv stack unwinding debugging."), _("\ | |
4106 | Show riscv stack unwinding debugging."), _("\ | |
4107 | When non-zero, print debugging information for the riscv specific parts\n\ | |
4108 | of the stack unwinding mechanism."), | |
4109 | NULL, | |
4110 | show_riscv_debug_variable, | |
4111 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
b5ffee31 AB |
4112 | |
4113 | add_setshow_zuinteger_cmd ("gdbarch", class_maintenance, | |
4114 | &riscv_debug_gdbarch, _("\ | |
4115 | Set riscv gdbarch initialisation debugging."), _("\ | |
4116 | Show riscv gdbarch initialisation debugging."), _("\ | |
4117 | When non-zero, print debugging information for the riscv gdbarch\n\ | |
4118 | initialisation process."), | |
4119 | NULL, | |
4120 | show_riscv_debug_variable, | |
4121 | &setdebugriscvcmdlist, &showdebugriscvcmdlist); | |
dbbb1059 AB |
4122 | |
4123 | /* Add root prefix command for all "set riscv" and "show riscv" commands. */ | |
f54bdb6d SM |
4124 | add_setshow_prefix_cmd ("riscv", no_class, |
4125 | _("RISC-V specific commands."), | |
4126 | _("RISC-V specific commands."), | |
4127 | &setriscvcmdlist, &showriscvcmdlist, | |
4128 | &setlist, &showlist); | |
dbbb1059 AB |
4129 | |
4130 | ||
4131 | use_compressed_breakpoints = AUTO_BOOLEAN_AUTO; | |
4132 | add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class, | |
4133 | &use_compressed_breakpoints, | |
4134 | _("\ | |
4135 | Set debugger's use of compressed breakpoints."), _(" \ | |
4136 | Show debugger's use of compressed breakpoints."), _("\ | |
f37bc8b1 JB |
4137 | Debugging compressed code requires compressed breakpoints to be used. If\n\ |
4138 | left to 'auto' then gdb will use them if the existing instruction is a\n\ | |
4139 | compressed instruction. If that doesn't give the correct behavior, then\n\ | |
4140 | this option can be used."), | |
dbbb1059 AB |
4141 | NULL, |
4142 | show_use_compressed_breakpoints, | |
4143 | &setriscvcmdlist, | |
4144 | &showriscvcmdlist); | |
4145 | } |