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9058f767
KB		 1/* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
2
32d0add0 3 Copyright (C) 2011-2015 Free Software Foundation, Inc.
9058f767
KB		 4
5 Contributed by Red Hat, Inc.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22#include "defs.h"
23#include "arch-utils.h"
24#include "prologue-value.h"
25#include "target.h"
26#include "regcache.h"
27#include "opcode/rl78.h"
28#include "dis-asm.h"
29#include "gdbtypes.h"
30#include "frame.h"
31#include "frame-unwind.h"
32#include "frame-base.h"
33#include "value.h"
34#include "gdbcore.h"
35#include "dwarf2-frame.h"
c47a44f4 36#include "reggroups.h"
9058f767
KB		 37
38#include "elf/rl78.h"
39#include "elf-bfd.h"
40
41/* Register Banks. */
42
43enum
44{
45 RL78_BANK0 = 0,
46 RL78_BANK1 = 1,
47 RL78_BANK2 = 2,
48 RL78_BANK3 = 3,
49 RL78_NUMBANKS = 4,
50 RL78_REGS_PER_BANK = 8
51};
52
53/* Register Numbers. */
54
55enum
56{
57 /* All general purpose registers are 8 bits wide. */
c47a44f4
KB		 58 RL78_RAW_BANK0_R0_REGNUM = 0,
59 RL78_RAW_BANK0_R1_REGNUM,
60 RL78_RAW_BANK0_R2_REGNUM,
61 RL78_RAW_BANK0_R3_REGNUM,
62 RL78_RAW_BANK0_R4_REGNUM,
63 RL78_RAW_BANK0_R5_REGNUM,
64 RL78_RAW_BANK0_R6_REGNUM,
65 RL78_RAW_BANK0_R7_REGNUM,
66
67 RL78_RAW_BANK1_R0_REGNUM,
68 RL78_RAW_BANK1_R1_REGNUM,
69 RL78_RAW_BANK1_R2_REGNUM,
70 RL78_RAW_BANK1_R3_REGNUM,
71 RL78_RAW_BANK1_R4_REGNUM,
72 RL78_RAW_BANK1_R5_REGNUM,
73 RL78_RAW_BANK1_R6_REGNUM,
74 RL78_RAW_BANK1_R7_REGNUM,
75
76 RL78_RAW_BANK2_R0_REGNUM,
77 RL78_RAW_BANK2_R1_REGNUM,
78 RL78_RAW_BANK2_R2_REGNUM,
79 RL78_RAW_BANK2_R3_REGNUM,
80 RL78_RAW_BANK2_R4_REGNUM,
81 RL78_RAW_BANK2_R5_REGNUM,
82 RL78_RAW_BANK2_R6_REGNUM,
83 RL78_RAW_BANK2_R7_REGNUM,
84
85 RL78_RAW_BANK3_R0_REGNUM,
86 RL78_RAW_BANK3_R1_REGNUM,
87 RL78_RAW_BANK3_R2_REGNUM,
88 RL78_RAW_BANK3_R3_REGNUM,
89 RL78_RAW_BANK3_R4_REGNUM,
90 RL78_RAW_BANK3_R5_REGNUM,
91 RL78_RAW_BANK3_R6_REGNUM,
92 RL78_RAW_BANK3_R7_REGNUM,
93
94 RL78_PSW_REGNUM, /* 8 bits */
95 RL78_ES_REGNUM, /* 8 bits */
96 RL78_CS_REGNUM, /* 8 bits */
ba89f962 97 RL78_RAW_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */
c47a44f4
KB		 98
99 /* Fixed address SFRs (some of those above are SFRs too.) */
100 RL78_SPL_REGNUM, /* 8 bits; lower half of SP */
101 RL78_SPH_REGNUM, /* 8 bits; upper half of SP */
102 RL78_PMC_REGNUM, /* 8 bits */
103 RL78_MEM_REGNUM, /* 8 bits ?? */
104
105 RL78_NUM_REGS,
106
107 /* Pseudo registers. */
ba89f962
KB		 108 RL78_PC_REGNUM = RL78_NUM_REGS,
109 RL78_SP_REGNUM,
c47a44f4
KB		 110
111 RL78_X_REGNUM,
112 RL78_A_REGNUM,
113 RL78_C_REGNUM,
114 RL78_B_REGNUM,
115 RL78_E_REGNUM,
116 RL78_D_REGNUM,
117 RL78_L_REGNUM,
118 RL78_H_REGNUM,
119
120 RL78_AX_REGNUM,
121 RL78_BC_REGNUM,
122 RL78_DE_REGNUM,
123 RL78_HL_REGNUM,
124
125 RL78_BANK0_R0_REGNUM,
9058f767
KB		 126 RL78_BANK0_R1_REGNUM,
127 RL78_BANK0_R2_REGNUM,
128 RL78_BANK0_R3_REGNUM,
129 RL78_BANK0_R4_REGNUM,
130 RL78_BANK0_R5_REGNUM,
131 RL78_BANK0_R6_REGNUM,
132 RL78_BANK0_R7_REGNUM,
133
134 RL78_BANK1_R0_REGNUM,
135 RL78_BANK1_R1_REGNUM,
136 RL78_BANK1_R2_REGNUM,
137 RL78_BANK1_R3_REGNUM,
138 RL78_BANK1_R4_REGNUM,
139 RL78_BANK1_R5_REGNUM,
140 RL78_BANK1_R6_REGNUM,
141 RL78_BANK1_R7_REGNUM,
142
143 RL78_BANK2_R0_REGNUM,
144 RL78_BANK2_R1_REGNUM,
145 RL78_BANK2_R2_REGNUM,
146 RL78_BANK2_R3_REGNUM,
147 RL78_BANK2_R4_REGNUM,
148 RL78_BANK2_R5_REGNUM,
149 RL78_BANK2_R6_REGNUM,
150 RL78_BANK2_R7_REGNUM,
151
152 RL78_BANK3_R0_REGNUM,
153 RL78_BANK3_R1_REGNUM,
154 RL78_BANK3_R2_REGNUM,
155 RL78_BANK3_R3_REGNUM,
156 RL78_BANK3_R4_REGNUM,
157 RL78_BANK3_R5_REGNUM,
158 RL78_BANK3_R6_REGNUM,
159 RL78_BANK3_R7_REGNUM,
160
c47a44f4 161 RL78_BANK0_RP0_REGNUM,
9058f767
KB		 162 RL78_BANK0_RP1_REGNUM,
163 RL78_BANK0_RP2_REGNUM,
164 RL78_BANK0_RP3_REGNUM,
165
166 RL78_BANK1_RP0_REGNUM,
167 RL78_BANK1_RP1_REGNUM,
168 RL78_BANK1_RP2_REGNUM,
169 RL78_BANK1_RP3_REGNUM,
170
171 RL78_BANK2_RP0_REGNUM,
172 RL78_BANK2_RP1_REGNUM,
173 RL78_BANK2_RP2_REGNUM,
174 RL78_BANK2_RP3_REGNUM,
175
176 RL78_BANK3_RP0_REGNUM,
177 RL78_BANK3_RP1_REGNUM,
178 RL78_BANK3_RP2_REGNUM,
179 RL78_BANK3_RP3_REGNUM,
180
6d451942
KB		 181 /* These are the same as the above 16 registers, but have
182 a pointer type for use as base registers in expression
183 evaluation. These are not user visible registers. */
184 RL78_BANK0_RP0_PTR_REGNUM,
185 RL78_BANK0_RP1_PTR_REGNUM,
186 RL78_BANK0_RP2_PTR_REGNUM,
187 RL78_BANK0_RP3_PTR_REGNUM,
188
189 RL78_BANK1_RP0_PTR_REGNUM,
190 RL78_BANK1_RP1_PTR_REGNUM,
191 RL78_BANK1_RP2_PTR_REGNUM,
192 RL78_BANK1_RP3_PTR_REGNUM,
193
194 RL78_BANK2_RP0_PTR_REGNUM,
195 RL78_BANK2_RP1_PTR_REGNUM,
196 RL78_BANK2_RP2_PTR_REGNUM,
197 RL78_BANK2_RP3_PTR_REGNUM,
198
199 RL78_BANK3_RP0_PTR_REGNUM,
200 RL78_BANK3_RP1_PTR_REGNUM,
201 RL78_BANK3_RP2_PTR_REGNUM,
202 RL78_BANK3_RP3_PTR_REGNUM,
203
9058f767
KB		 204 RL78_NUM_TOTAL_REGS,
205 RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
206};
207
0bca7f99
KB		 208#define RL78_SP_ADDR 0xffff8
209
9058f767
KB		 210/* Architecture specific data. */
211
212struct gdbarch_tdep
213{
214 /* The ELF header flags specify the multilib used. */
215 int elf_flags;
216
217 struct type *rl78_void,
218 *rl78_uint8,
219 *rl78_int8,
220 *rl78_uint16,
221 *rl78_int16,
222 *rl78_uint32,
223 *rl78_int32,
224 *rl78_data_pointer,
225 *rl78_code_pointer;
226};
227
228/* This structure holds the results of a prologue analysis. */
229
230struct rl78_prologue
231{
232 /* The offset from the frame base to the stack pointer --- always
233 zero or negative.
234
235 Calling this a "size" is a bit misleading, but given that the
236 stack grows downwards, using offsets for everything keeps one
237 from going completely sign-crazy: you never change anything's
238 sign for an ADD instruction; always change the second operand's
239 sign for a SUB instruction; and everything takes care of
240 itself. */
241 int frame_size;
242
243 /* Non-zero if this function has initialized the frame pointer from
244 the stack pointer, zero otherwise. */
245 int has_frame_ptr;
246
247 /* If has_frame_ptr is non-zero, this is the offset from the frame
248 base to where the frame pointer points. This is always zero or
249 negative. */
250 int frame_ptr_offset;
251
252 /* The address of the first instruction at which the frame has been
253 set up and the arguments are where the debug info says they are
254 --- as best as we can tell. */
255 CORE_ADDR prologue_end;
256
257 /* reg_offset[R] is the offset from the CFA at which register R is
258 saved, or 1 if register R has not been saved. (Real values are
259 always zero or negative.) */
260 int reg_offset[RL78_NUM_TOTAL_REGS];
261};
262
263/* Implement the "register_type" gdbarch method. */
264
265static struct type *
266rl78_register_type (struct gdbarch *gdbarch, int reg_nr)
267{
268 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
269
270 if (reg_nr == RL78_PC_REGNUM)
271 return tdep->rl78_code_pointer;
ba89f962
KB		 272 else if (reg_nr == RL78_RAW_PC_REGNUM)
273 return tdep->rl78_uint32;
9058f767 274 else if (reg_nr <= RL78_MEM_REGNUM
c47a44f4
KB		 275 || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)
276 || (RL78_BANK0_R0_REGNUM <= reg_nr
277 && reg_nr <= RL78_BANK3_R7_REGNUM))
9058f767 278 return tdep->rl78_int8;
6d451942
KB		 279 else if (reg_nr == RL78_SP_REGNUM
280 || (RL78_BANK0_RP0_PTR_REGNUM <= reg_nr
281 && reg_nr <= RL78_BANK3_RP3_PTR_REGNUM))
9058f767 282 return tdep->rl78_data_pointer;
6d451942
KB		 283 else
284 return tdep->rl78_int16;
9058f767
KB		 285}
286
287/* Implement the "register_name" gdbarch method. */
288
289static const char *
290rl78_register_name (struct gdbarch *gdbarch, int regnr)
291{
292 static const char *const reg_names[] =
293 {
c47a44f4
KB		 294 "", /* bank0_r0 */
295 "", /* bank0_r1 */
296 "", /* bank0_r2 */
297 "", /* bank0_r3 */
298 "", /* bank0_r4 */
299 "", /* bank0_r5 */
300 "", /* bank0_r6 */
301 "", /* bank0_r7 */
302
303 "", /* bank1_r0 */
304 "", /* bank1_r1 */
305 "", /* bank1_r2 */
306 "", /* bank1_r3 */
307 "", /* bank1_r4 */
308 "", /* bank1_r5 */
309 "", /* bank1_r6 */
310 "", /* bank1_r7 */
311
312 "", /* bank2_r0 */
313 "", /* bank2_r1 */
314 "", /* bank2_r2 */
315 "", /* bank2_r3 */
316 "", /* bank2_r4 */
317 "", /* bank2_r5 */
318 "", /* bank2_r6 */
319 "", /* bank2_r7 */
320
321 "", /* bank3_r0 */
322 "", /* bank3_r1 */
323 "", /* bank3_r2 */
324 "", /* bank3_r3 */
325 "", /* bank3_r4 */
326 "", /* bank3_r5 */
327 "", /* bank3_r6 */
328 "", /* bank3_r7 */
329
330 "psw",
331 "es",
332 "cs",
ba89f962 333 "",
c47a44f4
KB		 334
335 "", /* spl */
336 "", /* sph */
337 "pmc",
338 "mem",
339
ba89f962 340 "pc",
c47a44f4
KB		 341 "sp",
342
343 "x",
344 "a",
345 "c",
346 "b",
347 "e",
348 "d",
349 "l",
350 "h",
351
352 "ax",
353 "bc",
354 "de",
355 "hl",
356
9058f767
KB		 357 "bank0_r0",
358 "bank0_r1",
359 "bank0_r2",
360 "bank0_r3",
361 "bank0_r4",
362 "bank0_r5",
363 "bank0_r6",
364 "bank0_r7",
365
366 "bank1_r0",
367 "bank1_r1",
368 "bank1_r2",
369 "bank1_r3",
370 "bank1_r4",
371 "bank1_r5",
372 "bank1_r6",
373 "bank1_r7",
374
375 "bank2_r0",
376 "bank2_r1",
377 "bank2_r2",
378 "bank2_r3",
379 "bank2_r4",
380 "bank2_r5",
381 "bank2_r6",
382 "bank2_r7",
383
384 "bank3_r0",
385 "bank3_r1",
386 "bank3_r2",
387 "bank3_r3",
388 "bank3_r4",
389 "bank3_r5",
390 "bank3_r6",
391 "bank3_r7",
392
9058f767
KB		 393 "bank0_rp0",
394 "bank0_rp1",
395 "bank0_rp2",
396 "bank0_rp3",
397
398 "bank1_rp0",
399 "bank1_rp1",
400 "bank1_rp2",
401 "bank1_rp3",
402
403 "bank2_rp0",
404 "bank2_rp1",
405 "bank2_rp2",
406 "bank2_rp3",
407
408 "bank3_rp0",
409 "bank3_rp1",
410 "bank3_rp2",
6d451942
KB		 411 "bank3_rp3",
412
413 /* The 16 register slots would be named
414 bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
415 want these to be user visible registers. */
416 "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
c47a44f4 417 };
9058f767 418
c47a44f4
KB		 419 return reg_names[regnr];
420}
9058f767 421
bc3c6b36
KB		 422/* Implement the "register_name" gdbarch method for the g10 variant. */
423
424static const char *
425rl78_g10_register_name (struct gdbarch *gdbarch, int regnr)
426{
427 static const char *const reg_names[] =
428 {
429 "", /* bank0_r0 */
430 "", /* bank0_r1 */
431 "", /* bank0_r2 */
432 "", /* bank0_r3 */
433 "", /* bank0_r4 */
434 "", /* bank0_r5 */
435 "", /* bank0_r6 */
436 "", /* bank0_r7 */
437
438 "", /* bank1_r0 */
439 "", /* bank1_r1 */
440 "", /* bank1_r2 */
441 "", /* bank1_r3 */
442 "", /* bank1_r4 */
443 "", /* bank1_r5 */
444 "", /* bank1_r6 */
445 "", /* bank1_r7 */
446
447 "", /* bank2_r0 */
448 "", /* bank2_r1 */
449 "", /* bank2_r2 */
450 "", /* bank2_r3 */
451 "", /* bank2_r4 */
452 "", /* bank2_r5 */
453 "", /* bank2_r6 */
454 "", /* bank2_r7 */
455
456 "", /* bank3_r0 */
457 "", /* bank3_r1 */
458 "", /* bank3_r2 */
459 "", /* bank3_r3 */
460 "", /* bank3_r4 */
461 "", /* bank3_r5 */
462 "", /* bank3_r6 */
463 "", /* bank3_r7 */
464
465 "psw",
466 "es",
467 "cs",
468 "",
469
470 "", /* spl */
471 "", /* sph */
472 "pmc",
473 "mem",
474
475 "pc",
476 "sp",
477
478 "x",
479 "a",
480 "c",
481 "b",
482 "e",
483 "d",
484 "l",
485 "h",
486
487 "ax",
488 "bc",
489 "de",
490 "hl",
491
492 "bank0_r0",
493 "bank0_r1",
494 "bank0_r2",
495 "bank0_r3",
496 "bank0_r4",
497 "bank0_r5",
498 "bank0_r6",
499 "bank0_r7",
500
501 "",
502 "",
503 "",
504 "",
505 "",
506 "",
507 "",
508 "",
509
510 "",
511 "",
512 "",
513 "",
514 "",
515 "",
516 "",
517 "",
518
519 "",
520 "",
521 "",
522 "",
523 "",
524 "",
525 "",
526 "",
527
528 "bank0_rp0",
529 "bank0_rp1",
530 "bank0_rp2",
531 "bank0_rp3",
532
533 "",
534 "",
535 "",
536 "",
537
538 "",
539 "",
540 "",
541 "",
542
543 "",
544 "",
545 "",
6d451942
KB		 546 "",
547
548 /* The 16 register slots would be named
549 bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
550 want these to be user visible registers. */
551 "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
bc3c6b36
KB		 552 };
553
554 return reg_names[regnr];
555}
556
c47a44f4 557/* Implement the "register_reggroup_p" gdbarch method. */
9058f767 558
c47a44f4
KB		 559static int
560rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
561 struct reggroup *group)
562{
563 if (group == all_reggroup)
564 return 1;
9058f767 565
c47a44f4
KB		 566 /* All other registers are saved and restored. */
567 if (group == save_reggroup || group == restore_reggroup)
568 {
b3ce41ea 569 if ((regnum < RL78_NUM_REGS
ba89f962
KB		 570 && regnum != RL78_SPL_REGNUM
571 && regnum != RL78_SPH_REGNUM
572 && regnum != RL78_RAW_PC_REGNUM)
573 || regnum == RL78_SP_REGNUM
574 || regnum == RL78_PC_REGNUM)
c47a44f4
KB		 575 return 1;
576 else
577 return 0;
578 }
579
580 if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM)
581 || regnum == RL78_ES_REGNUM
582 || regnum == RL78_CS_REGNUM
583 || regnum == RL78_SPL_REGNUM
584 || regnum == RL78_SPH_REGNUM
585 || regnum == RL78_PMC_REGNUM
586 || regnum == RL78_MEM_REGNUM
ba89f962 587 || regnum == RL78_RAW_PC_REGNUM
c47a44f4
KB		 588 || (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM))
589 return group == system_reggroup;
590
591 return group == general_reggroup;
9058f767
KB		 592}
593
594/* Strip bits to form an instruction address. (When fetching a
595 32-bit address from the stack, the high eight bits are garbage.
596 This function strips off those unused bits.) */
597
598static CORE_ADDR
599rl78_make_instruction_address (CORE_ADDR addr)
600{
601 return addr & 0xffffff;
602}
603
604/* Set / clear bits necessary to make a data address. */
605
606static CORE_ADDR
607rl78_make_data_address (CORE_ADDR addr)
608{
609 return (addr & 0xffff) | 0xf0000;
610}
611
612/* Implement the "pseudo_register_read" gdbarch method. */
613
614static enum register_status
615rl78_pseudo_register_read (struct gdbarch *gdbarch,
616 struct regcache *regcache,
617 int reg, gdb_byte *buffer)
618{
619 enum register_status status;
620
c47a44f4
KB		 621 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
622 {
623 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
624 + (reg - RL78_BANK0_R0_REGNUM);
625
626 status = regcache_raw_read (regcache, raw_regnum, buffer);
627 }
628 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
9058f767
KB		 629 {
630 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
c47a44f4 631 + RL78_RAW_BANK0_R0_REGNUM;
9058f767 632
6d451942
KB		 633 status = regcache_raw_read (regcache, raw_regnum, buffer);
634 if (status == REG_VALID)
635 status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
636 }
637 else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
638 {
639 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
640 + RL78_RAW_BANK0_R0_REGNUM;
641
9058f767
KB		 642 status = regcache_raw_read (regcache, raw_regnum, buffer);
643 if (status == REG_VALID)
644 status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
645 }
646 else if (reg == RL78_SP_REGNUM)
647 {
648 status = regcache_raw_read (regcache, RL78_SPL_REGNUM, buffer);
649 if (status == REG_VALID)
650 status = regcache_raw_read (regcache, RL78_SPH_REGNUM, buffer + 1);
651 }
ba89f962
KB		 652 else if (reg == RL78_PC_REGNUM)
653 {
654 gdb_byte rawbuf[4];
655
656 status = regcache_raw_read (regcache, RL78_RAW_PC_REGNUM, rawbuf);
657 memcpy (buffer, rawbuf, 3);
658 }
9058f767
KB		 659 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
660 {
661 ULONGEST psw;
662
663 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
664 if (status == REG_VALID)
665 {
666 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
667 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
c47a44f4 668 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 669 + (reg - RL78_X_REGNUM);
670 status = regcache_raw_read (regcache, raw_regnum, buffer);
671 }
672 }
673 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
674 {
675 ULONGEST psw;
676
677 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
678 if (status == REG_VALID)
679 {
680 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
681 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
c47a44f4 682 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 683 + 2 * (reg - RL78_AX_REGNUM);
684 status = regcache_raw_read (regcache, raw_regnum, buffer);
685 if (status == REG_VALID)
686 status = regcache_raw_read (regcache, raw_regnum + 1,
687 buffer + 1);
688 }
689 }
690 else
691 gdb_assert_not_reached ("invalid pseudo register number");
692 return status;
693}
694
695/* Implement the "pseudo_register_write" gdbarch method. */
696
697static void
698rl78_pseudo_register_write (struct gdbarch *gdbarch,
699 struct regcache *regcache,
700 int reg, const gdb_byte *buffer)
701{
c47a44f4
KB		 702 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
703 {
704 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
705 + (reg - RL78_BANK0_R0_REGNUM);
706
707 regcache_raw_write (regcache, raw_regnum, buffer);
708 }
709 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
9058f767
KB		 710 {
711 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
c47a44f4 712 + RL78_RAW_BANK0_R0_REGNUM;
9058f767 713
6d451942
KB		 714 regcache_raw_write (regcache, raw_regnum, buffer);
715 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
716 }
717 else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
718 {
719 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
720 + RL78_RAW_BANK0_R0_REGNUM;
721
9058f767
KB		 722 regcache_raw_write (regcache, raw_regnum, buffer);
723 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
724 }
725 else if (reg == RL78_SP_REGNUM)
726 {
727 regcache_raw_write (regcache, RL78_SPL_REGNUM, buffer);
728 regcache_raw_write (regcache, RL78_SPH_REGNUM, buffer + 1);
729 }
ba89f962
KB		 730 else if (reg == RL78_PC_REGNUM)
731 {
732 gdb_byte rawbuf[4];
733
734 memcpy (rawbuf, buffer, 3);
735 rawbuf[3] = 0;
736 regcache_raw_write (regcache, RL78_RAW_PC_REGNUM, rawbuf);
737 }
9058f767
KB		 738 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
739 {
740 ULONGEST psw;
741 int bank;
742 int raw_regnum;
743
744 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
745 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
746 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
c47a44f4 747 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 748 + (reg - RL78_X_REGNUM);
749 regcache_raw_write (regcache, raw_regnum, buffer);
750 }
751 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
752 {
753 ULONGEST psw;
754 int bank, raw_regnum;
755
756 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
757 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
758 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
c47a44f4 759 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 760 + 2 * (reg - RL78_AX_REGNUM);
761 regcache_raw_write (regcache, raw_regnum, buffer);
762 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
763 }
764 else
765 gdb_assert_not_reached ("invalid pseudo register number");
766}
767
768/* Implement the "breakpoint_from_pc" gdbarch method. */
769
693be288 770static const gdb_byte *
9058f767
KB		 771rl78_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
772 int *lenptr)
773{
774 /* The documented BRK instruction is actually a two byte sequence,
775 {0x61, 0xcc}, but instructions may be as short as one byte.
776 Correspondence with Renesas revealed that the one byte sequence
777 0xff is used when a one byte breakpoint instruction is required. */
778 static gdb_byte breakpoint[] = { 0xff };
779
780 *lenptr = sizeof breakpoint;
781 return breakpoint;
782}
783
784/* Define a "handle" struct for fetching the next opcode. */
785
786struct rl78_get_opcode_byte_handle
787{
788 CORE_ADDR pc;
789};
790
0bca7f99
KB		 791static int
792opc_reg_to_gdb_regnum (int opcreg)
793{
794 switch (opcreg)
795 {
796 case RL78_Reg_X:
797 return RL78_X_REGNUM;
798 case RL78_Reg_A:
799 return RL78_A_REGNUM;
800 case RL78_Reg_C:
801 return RL78_C_REGNUM;
802 case RL78_Reg_B:
803 return RL78_B_REGNUM;
804 case RL78_Reg_E:
805 return RL78_E_REGNUM;
806 case RL78_Reg_D:
807 return RL78_D_REGNUM;
808 case RL78_Reg_L:
809 return RL78_L_REGNUM;
810 case RL78_Reg_H:
811 return RL78_H_REGNUM;
812 case RL78_Reg_AX:
813 return RL78_AX_REGNUM;
814 case RL78_Reg_BC:
815 return RL78_BC_REGNUM;
816 case RL78_Reg_DE:
817 return RL78_DE_REGNUM;
818 case RL78_Reg_HL:
819 return RL78_HL_REGNUM;
820 case RL78_Reg_SP:
821 return RL78_SP_REGNUM;
822 case RL78_Reg_PSW:
823 return RL78_PSW_REGNUM;
824 case RL78_Reg_CS:
825 return RL78_CS_REGNUM;
826 case RL78_Reg_ES:
827 return RL78_ES_REGNUM;
828 case RL78_Reg_PMC:
829 return RL78_PMC_REGNUM;
830 case RL78_Reg_MEM:
831 return RL78_MEM_REGNUM;
832 default:
833 internal_error (__FILE__, __LINE__,
834 _("Undefined mapping for opc reg %d"),
835 opcreg);
836 }
837
838 /* Not reached. */
839 return 0;
840}
841
9058f767
KB		 842/* Fetch a byte on behalf of the opcode decoder. HANDLE contains
843 the memory address of the next byte to fetch. If successful,
844 the address in the handle is updated and the byte fetched is
845 returned as the value of the function. If not successful, -1
846 is returned. */
847
848static int
849rl78_get_opcode_byte (void *handle)
850{
851 struct rl78_get_opcode_byte_handle *opcdata = handle;
852 int status;
853 gdb_byte byte;
854
855 status = target_read_memory (opcdata->pc, &byte, 1);
856 if (status == 0)
857 {
858 opcdata->pc += 1;
859 return byte;
860 }
861 else
862 return -1;
863}
864
865/* Function for finding saved registers in a 'struct pv_area'; this
866 function is passed to pv_area_scan.
867
868 If VALUE is a saved register, ADDR says it was saved at a constant
869 offset from the frame base, and SIZE indicates that the whole
870 register was saved, record its offset. */
871
872static void
873check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size,
874 pv_t value)
875{
876 struct rl78_prologue *result = (struct rl78_prologue *) result_untyped;
877
878 if (value.kind == pvk_register
879 && value.k == 0
880 && pv_is_register (addr, RL78_SP_REGNUM)
f5656ead 881 && size == register_size (target_gdbarch (), value.reg))
9058f767
KB		 882 result->reg_offset[value.reg] = addr.k;
883}
884
885/* Analyze a prologue starting at START_PC, going no further than
886 LIMIT_PC. Fill in RESULT as appropriate. */
887
888static void
889rl78_analyze_prologue (CORE_ADDR start_pc,
890 CORE_ADDR limit_pc, struct rl78_prologue *result)
891{
892 CORE_ADDR pc, next_pc;
893 int rn;
894 pv_t reg[RL78_NUM_TOTAL_REGS];
895 struct pv_area *stack;
896 struct cleanup *back_to;
897 CORE_ADDR after_last_frame_setup_insn = start_pc;
898 int bank = 0;
899
900 memset (result, 0, sizeof (*result));
901
902 for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++)
903 {
904 reg[rn] = pv_register (rn, 0);
905 result->reg_offset[rn] = 1;
906 }
907
f5656ead 908 stack = make_pv_area (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch ()));
9058f767
KB		 909 back_to = make_cleanup_free_pv_area (stack);
910
911 /* The call instruction has saved the return address on the stack. */
912 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4);
913 pv_area_store (stack, reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]);
914
915 pc = start_pc;
916 while (pc < limit_pc)
917 {
918 int bytes_read;
919 struct rl78_get_opcode_byte_handle opcode_handle;
920 RL78_Opcode_Decoded opc;
921
922 opcode_handle.pc = pc;
923 bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
0952813b 924 &opcode_handle, RL78_ISA_DEFAULT);
9058f767
KB		 925 next_pc = pc + bytes_read;
926
927 if (opc.id == RLO_sel)
928 {
929 bank = opc.op[1].addend;
930 }
931 else if (opc.id == RLO_mov
932 && opc.op[0].type == RL78_Operand_PreDec
933 && opc.op[0].reg == RL78_Reg_SP
934 && opc.op[1].type == RL78_Operand_Register)
935 {
936 int rsrc = (bank * RL78_REGS_PER_BANK)
937 + 2 * (opc.op[1].reg - RL78_Reg_AX);
938
939 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
940 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc]);
941 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
942 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]);
943 after_last_frame_setup_insn = next_pc;
944 }
945 else if (opc.id == RLO_sub
946 && opc.op[0].type == RL78_Operand_Register
947 && opc.op[0].reg == RL78_Reg_SP
948 && opc.op[1].type == RL78_Operand_Immediate)
949 {
950 int addend = opc.op[1].addend;
951
952 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM],
953 -addend);
954 after_last_frame_setup_insn = next_pc;
955 }
0bca7f99
KB		 956 else if (opc.id == RLO_mov
957 && opc.size == RL78_Word
958 && opc.op[0].type == RL78_Operand_Register
959 && opc.op[1].type == RL78_Operand_Indirect
960 && opc.op[1].addend == RL78_SP_ADDR)
961 {
962 reg[opc_reg_to_gdb_regnum (opc.op[0].reg)]
963 = reg[RL78_SP_REGNUM];
964 }
965 else if (opc.id == RLO_sub
966 && opc.size == RL78_Word
967 && opc.op[0].type == RL78_Operand_Register
968 && opc.op[1].type == RL78_Operand_Immediate)
969 {
970 int addend = opc.op[1].addend;
971 int regnum = opc_reg_to_gdb_regnum (opc.op[0].reg);
972
973 reg[regnum] = pv_add_constant (reg[regnum], -addend);
974 }
975 else if (opc.id == RLO_mov
976 && opc.size == RL78_Word
977 && opc.op[0].type == RL78_Operand_Indirect
978 && opc.op[0].addend == RL78_SP_ADDR
979 && opc.op[1].type == RL78_Operand_Register)
980 {
981 reg[RL78_SP_REGNUM]
982 = reg[opc_reg_to_gdb_regnum (opc.op[1].reg)];
983 after_last_frame_setup_insn = next_pc;
984 }
9058f767
KB		 985 else
986 {
987 /* Terminate the prologue scan. */
988 break;
989 }
990
991 pc = next_pc;
992 }
993
994 /* Is the frame size (offset, really) a known constant? */
995 if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM))
996 result->frame_size = reg[RL78_SP_REGNUM].k;
997
998 /* Record where all the registers were saved. */
999 pv_area_scan (stack, check_for_saved, (void *) result);
1000
1001 result->prologue_end = after_last_frame_setup_insn;
1002
1003 do_cleanups (back_to);
1004}
1005
1006/* Implement the "addr_bits_remove" gdbarch method. */
1007
1008static CORE_ADDR
1009rl78_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
1010{
1011 return addr & 0xffffff;
1012}
1013
1014/* Implement the "address_to_pointer" gdbarch method. */
1015
1016static void
1017rl78_address_to_pointer (struct gdbarch *gdbarch,
1018 struct type *type, gdb_byte *buf, CORE_ADDR addr)
1019{
1020 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1021
1022 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
1023 addr & 0xffffff);
1024}
1025
1026/* Implement the "pointer_to_address" gdbarch method. */
1027
1028static CORE_ADDR
1029rl78_pointer_to_address (struct gdbarch *gdbarch,
1030 struct type *type, const gdb_byte *buf)
1031{
1032 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1033 CORE_ADDR addr
1034 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
1035
1036 /* Is it a code address? */
1037 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
1038 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
1039 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))
1040 || TYPE_LENGTH (type) == 4)
1041 return rl78_make_instruction_address (addr);
1042 else
1043 return rl78_make_data_address (addr);
1044}
1045
1046/* Implement the "skip_prologue" gdbarch method. */
1047
1048static CORE_ADDR
1049rl78_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1050{
e4569f1e 1051 const char *name;
9058f767
KB		 1052 CORE_ADDR func_addr, func_end;
1053 struct rl78_prologue p;
1054
1055 /* Try to find the extent of the function that contains PC. */
1056 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
1057 return pc;
1058
1059 rl78_analyze_prologue (pc, func_end, &p);
1060 return p.prologue_end;
1061}
1062
1063/* Implement the "unwind_pc" gdbarch method. */
1064
1065static CORE_ADDR
1066rl78_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
1067{
1068 return rl78_addr_bits_remove
1069 (arch, frame_unwind_register_unsigned (next_frame,
1070 RL78_PC_REGNUM));
1071}
1072
1073/* Implement the "unwind_sp" gdbarch method. */
1074
1075static CORE_ADDR
1076rl78_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
1077{
1078 return frame_unwind_register_unsigned (next_frame, RL78_SP_REGNUM);
1079}
1080
1081/* Given a frame described by THIS_FRAME, decode the prologue of its
1082 associated function if there is not cache entry as specified by
1083 THIS_PROLOGUE_CACHE. Save the decoded prologue in the cache and
1084 return that struct as the value of this function. */
1085
1086static struct rl78_prologue *
1087rl78_analyze_frame_prologue (struct frame_info *this_frame,
1088 void **this_prologue_cache)
1089{
1090 if (!*this_prologue_cache)
1091 {
1092 CORE_ADDR func_start, stop_addr;
1093
1094 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct rl78_prologue);
1095
1096 func_start = get_frame_func (this_frame);
1097 stop_addr = get_frame_pc (this_frame);
1098
1099 /* If we couldn't find any function containing the PC, then
1100 just initialize the prologue cache, but don't do anything. */
1101 if (!func_start)
1102 stop_addr = func_start;
1103
1104 rl78_analyze_prologue (func_start, stop_addr, *this_prologue_cache);
1105 }
1106
1107 return *this_prologue_cache;
1108}
1109
1110/* Given a frame and a prologue cache, return this frame's base. */
1111
1112static CORE_ADDR
1113rl78_frame_base (struct frame_info *this_frame, void **this_prologue_cache)
1114{
1115 struct rl78_prologue *p
1116 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
1117 CORE_ADDR sp = get_frame_register_unsigned (this_frame, RL78_SP_REGNUM);
1118
1119 return rl78_make_data_address (sp - p->frame_size);
1120}
1121
1122/* Implement the "frame_this_id" method for unwinding frames. */
1123
1124static void
1125rl78_this_id (struct frame_info *this_frame,
1126 void **this_prologue_cache, struct frame_id *this_id)
1127{
1128 *this_id = frame_id_build (rl78_frame_base (this_frame,
1129 this_prologue_cache),
1130 get_frame_func (this_frame));
1131}
1132
1133/* Implement the "frame_prev_register" method for unwinding frames. */
1134
1135static struct value *
1136rl78_prev_register (struct frame_info *this_frame,
1137 void **this_prologue_cache, int regnum)
1138{
1139 struct rl78_prologue *p
1140 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
1141 CORE_ADDR frame_base = rl78_frame_base (this_frame, this_prologue_cache);
1142
1143 if (regnum == RL78_SP_REGNUM)
1144 return frame_unwind_got_constant (this_frame, regnum, frame_base);
1145
1146 else if (regnum == RL78_SPL_REGNUM)
1147 return frame_unwind_got_constant (this_frame, regnum,
1148 (frame_base & 0xff));
1149
1150 else if (regnum == RL78_SPH_REGNUM)
1151 return frame_unwind_got_constant (this_frame, regnum,
1152 ((frame_base >> 8) & 0xff));
1153
1154 /* If prologue analysis says we saved this register somewhere,
1155 return a description of the stack slot holding it. */
1156 else if (p->reg_offset[regnum] != 1)
1157 {
1158 struct value *rv =
1159 frame_unwind_got_memory (this_frame, regnum,
1160 frame_base + p->reg_offset[regnum]);
1161
1162 if (regnum == RL78_PC_REGNUM)
1163 {
1164 ULONGEST pc = rl78_make_instruction_address (value_as_long (rv));
1165
1166 return frame_unwind_got_constant (this_frame, regnum, pc);
1167 }
1168 return rv;
1169 }
1170
1171 /* Otherwise, presume we haven't changed the value of this
1172 register, and get it from the next frame. */
1173 else
1174 return frame_unwind_got_register (this_frame, regnum, regnum);
1175}
1176
1177static const struct frame_unwind rl78_unwind =
1178{
1179 NORMAL_FRAME,
1180 default_frame_unwind_stop_reason,
1181 rl78_this_id,
1182 rl78_prev_register,
1183 NULL,
1184 default_frame_sniffer
1185};
1186
1187/* Implement the "dwarf_reg_to_regnum" gdbarch method. */
1188
1189static int
1190rl78_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1191{
1192 if (0 <= reg && reg <= 31)
1193 {
1194 if ((reg & 1) == 0)
6d451942
KB		 1195 /* Map even registers to their 16-bit counterparts which have a
1196 pointer type. This is usually what is required from the DWARF
1197 info. */
1198 return (reg >> 1) + RL78_BANK0_RP0_PTR_REGNUM;
9058f767
KB		 1199 else
1200 return reg;
1201 }
1202 else if (reg == 32)
1203 return RL78_SP_REGNUM;
1204 else if (reg == 33)
b3ce41ea
KB		 1205 return -1; /* ap */
1206 else if (reg == 34)
1207 return RL78_PSW_REGNUM;
1208 else if (reg == 35)
1209 return RL78_ES_REGNUM;
1210 else if (reg == 36)
1211 return RL78_CS_REGNUM;
1212 else if (reg == 37)
9058f767
KB		 1213 return RL78_PC_REGNUM;
1214 else
1215 internal_error (__FILE__, __LINE__,
1216 _("Undefined dwarf2 register mapping of reg %d"),
1217 reg);
1218}
1219
c47a44f4
KB		 1220/* Implement the `register_sim_regno' gdbarch method. */
1221
1222static int
1223rl78_register_sim_regno (struct gdbarch *gdbarch, int regnum)
1224{
1225 gdb_assert (regnum < RL78_NUM_REGS);
1226
1227 /* So long as regnum is in [0, RL78_NUM_REGS), it's valid. We
1228 just want to override the default here which disallows register
1229 numbers which have no names. */
1230 return regnum;
1231}
1232
9058f767
KB		 1233/* Implement the "return_value" gdbarch method. */
1234
1235static enum return_value_convention
1236rl78_return_value (struct gdbarch *gdbarch,
6a3a010b 1237 struct value *function,
9058f767
KB		 1238 struct type *valtype,
1239 struct regcache *regcache,
1240 gdb_byte *readbuf, const gdb_byte *writebuf)
1241{
1242 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1243 ULONGEST valtype_len = TYPE_LENGTH (valtype);
bc3c6b36 1244 int is_g10 = gdbarch_tdep (gdbarch)->elf_flags & E_FLAG_RL78_G10;
9058f767
KB		 1245
1246 if (valtype_len > 8)
1247 return RETURN_VALUE_STRUCT_CONVENTION;
1248
1249 if (readbuf)
1250 {
1251 ULONGEST u;
c47a44f4 1252 int argreg = RL78_RAW_BANK1_R0_REGNUM;
bc3c6b36 1253 CORE_ADDR g10_raddr = 0xffec8;
9058f767
KB		 1254 int offset = 0;
1255
1256 while (valtype_len > 0)
1257 {
bc3c6b36
KB		 1258 if (is_g10)
1259 u = read_memory_integer (g10_raddr, 1,
1260 gdbarch_byte_order (gdbarch));
1261 else
1262 regcache_cooked_read_unsigned (regcache, argreg, &u);
9058f767
KB		 1263 store_unsigned_integer (readbuf + offset, 1, byte_order, u);
1264 valtype_len -= 1;
1265 offset += 1;
1266 argreg++;
bc3c6b36 1267 g10_raddr++;
9058f767
KB		 1268 }
1269 }
1270
1271 if (writebuf)
1272 {
1273 ULONGEST u;
c47a44f4 1274 int argreg = RL78_RAW_BANK1_R0_REGNUM;
bc3c6b36 1275 CORE_ADDR g10_raddr = 0xffec8;
9058f767
KB		 1276 int offset = 0;
1277
1278 while (valtype_len > 0)
1279 {
1280 u = extract_unsigned_integer (writebuf + offset, 1, byte_order);
bc3c6b36
KB		 1281 if (is_g10) {
1282 gdb_byte b = u & 0xff;
1283 write_memory (g10_raddr, &b, 1);
1284 }
1285 else
1286 regcache_cooked_write_unsigned (regcache, argreg, u);
9058f767
KB		 1287 valtype_len -= 1;
1288 offset += 1;
1289 argreg++;
bc3c6b36 1290 g10_raddr++;
9058f767
KB		 1291 }
1292 }
1293
1294 return RETURN_VALUE_REGISTER_CONVENTION;
1295}
1296
1297
1298/* Implement the "frame_align" gdbarch method. */
1299
1300static CORE_ADDR
1301rl78_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1302{
1303 return rl78_make_data_address (align_down (sp, 2));
1304}
1305
1306
1307/* Implement the "dummy_id" gdbarch method. */
1308
1309static struct frame_id
1310rl78_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1311{
1312 return
1313 frame_id_build (rl78_make_data_address
1314 (get_frame_register_unsigned
1315 (this_frame, RL78_SP_REGNUM)),
1316 get_frame_pc (this_frame));
1317}
1318
1319
1320/* Implement the "push_dummy_call" gdbarch method. */
1321
1322static CORE_ADDR
1323rl78_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1324 struct regcache *regcache, CORE_ADDR bp_addr,
1325 int nargs, struct value **args, CORE_ADDR sp,
1326 int struct_return, CORE_ADDR struct_addr)
1327{
1328 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1329 gdb_byte buf[4];
1330 int i;
1331
1332 /* Push arguments in reverse order. */
1333 for (i = nargs - 1; i >= 0; i--)
1334 {
1335 struct type *value_type = value_enclosing_type (args[i]);
1336 int len = TYPE_LENGTH (value_type);
1337 int container_len = (len + 1) & ~1;
9058f767
KB		 1338
1339 sp -= container_len;
1340 write_memory (rl78_make_data_address (sp),
1341 value_contents_all (args[i]), len);
1342 }
1343
1344 /* Store struct value address. */
1345 if (struct_return)
1346 {
1347 store_unsigned_integer (buf, 2, byte_order, struct_addr);
1348 sp -= 2;
1349 write_memory (rl78_make_data_address (sp), buf, 2);
1350 }
1351
1352 /* Store return address. */
1353 sp -= 4;
1354 store_unsigned_integer (buf, 4, byte_order, bp_addr);
1355 write_memory (rl78_make_data_address (sp), buf, 4);
1356
1357 /* Finally, update the stack pointer... */
1358 regcache_cooked_write_unsigned (regcache, RL78_SP_REGNUM, sp);
1359
1360 /* DWARF2/GCC uses the stack address *before* the function call as a
1361 frame's CFA. */
1362 return rl78_make_data_address (sp + 4);
1363}
1364
1365/* Allocate and initialize a gdbarch object. */
1366
1367static struct gdbarch *
1368rl78_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1369{
1370 struct gdbarch *gdbarch;
1371 struct gdbarch_tdep *tdep;
1372 int elf_flags;
1373
1374 /* Extract the elf_flags if available. */
1375 if (info.abfd != NULL
1376 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1377 elf_flags = elf_elfheader (info.abfd)->e_flags;
1378 else
1379 elf_flags = 0;
1380
1381
1382 /* Try to find the architecture in the list of already defined
1383 architectures. */
1384 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1385 arches != NULL;
1386 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1387 {
1388 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
1389 continue;
1390
1391 return arches->gdbarch;
1392 }
1393
1394 /* None found, create a new architecture from the information
1395 provided. */
1396 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
1397 gdbarch = gdbarch_alloc (&info, tdep);
1398 tdep->elf_flags = elf_flags;
1399
1400 /* Initialize types. */
1401 tdep->rl78_void = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void");
1402 tdep->rl78_uint8 = arch_integer_type (gdbarch, 8, 1, "uint8_t");
1403 tdep->rl78_int8 = arch_integer_type (gdbarch, 8, 0, "int8_t");
1404 tdep->rl78_uint16 = arch_integer_type (gdbarch, 16, 1, "uint16_t");
1405 tdep->rl78_int16 = arch_integer_type (gdbarch, 16, 0, "int16_t");
1406 tdep->rl78_uint32 = arch_integer_type (gdbarch, 32, 1, "uint32_t");
1407 tdep->rl78_int32 = arch_integer_type (gdbarch, 32, 0, "int32_t");
1408
1409 tdep->rl78_data_pointer
1410 = arch_type (gdbarch, TYPE_CODE_PTR, 16 / TARGET_CHAR_BIT,
1411 xstrdup ("rl78_data_addr_t"));
1412 TYPE_TARGET_TYPE (tdep->rl78_data_pointer) = tdep->rl78_void;
1413 TYPE_UNSIGNED (tdep->rl78_data_pointer) = 1;
1414
1415 tdep->rl78_code_pointer
1416 = arch_type (gdbarch, TYPE_CODE_PTR, 32 / TARGET_CHAR_BIT,
1417 xstrdup ("rl78_code_addr_t"));
1418 TYPE_TARGET_TYPE (tdep->rl78_code_pointer) = tdep->rl78_void;
1419 TYPE_UNSIGNED (tdep->rl78_code_pointer) = 1;
1420
1421 /* Registers. */
1422 set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS);
1423 set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS);
bc3c6b36
KB		 1424 if (tdep->elf_flags & E_FLAG_RL78_G10)
1425 set_gdbarch_register_name (gdbarch, rl78_g10_register_name);
1426 else
1427 set_gdbarch_register_name (gdbarch, rl78_register_name);
9058f767
KB		 1428 set_gdbarch_register_type (gdbarch, rl78_register_type);
1429 set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM);
1430 set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM);
1431 set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read);
1432 set_gdbarch_pseudo_register_write (gdbarch, rl78_pseudo_register_write);
1433 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum);
c47a44f4
KB		 1434 set_gdbarch_register_reggroup_p (gdbarch, rl78_register_reggroup_p);
1435 set_gdbarch_register_sim_regno (gdbarch, rl78_register_sim_regno);
9058f767
KB		 1436
1437 /* Data types. */
1438 set_gdbarch_char_signed (gdbarch, 0);
1439 set_gdbarch_short_bit (gdbarch, 16);
1440 set_gdbarch_int_bit (gdbarch, 16);
1441 set_gdbarch_long_bit (gdbarch, 32);
1442 set_gdbarch_long_long_bit (gdbarch, 64);
1443 set_gdbarch_ptr_bit (gdbarch, 16);
1444 set_gdbarch_addr_bit (gdbarch, 32);
b3ce41ea 1445 set_gdbarch_dwarf2_addr_size (gdbarch, 4);
9058f767
KB		 1446 set_gdbarch_float_bit (gdbarch, 32);
1447 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1448 set_gdbarch_double_bit (gdbarch, 32);
1449 set_gdbarch_long_double_bit (gdbarch, 64);
1450 set_gdbarch_double_format (gdbarch, floatformats_ieee_single);
1451 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
1452 set_gdbarch_pointer_to_address (gdbarch, rl78_pointer_to_address);
1453 set_gdbarch_address_to_pointer (gdbarch, rl78_address_to_pointer);
1454 set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove);
1455
1456 /* Breakpoints. */
1457 set_gdbarch_breakpoint_from_pc (gdbarch, rl78_breakpoint_from_pc);
1458 set_gdbarch_decr_pc_after_break (gdbarch, 1);
1459
1460 /* Disassembly. */
1461 set_gdbarch_print_insn (gdbarch, print_insn_rl78);
1462
1463 /* Frames, prologues, etc. */
1464 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1465 set_gdbarch_skip_prologue (gdbarch, rl78_skip_prologue);
1466 set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc);
1467 set_gdbarch_unwind_sp (gdbarch, rl78_unwind_sp);
1468 set_gdbarch_frame_align (gdbarch, rl78_frame_align);
b3ce41ea
KB		 1469
1470 dwarf2_append_unwinders (gdbarch);
9058f767
KB		 1471 frame_unwind_append_unwinder (gdbarch, &rl78_unwind);
1472
1473 /* Dummy frames, return values. */
1474 set_gdbarch_dummy_id (gdbarch, rl78_dummy_id);
1475 set_gdbarch_push_dummy_call (gdbarch, rl78_push_dummy_call);
1476 set_gdbarch_return_value (gdbarch, rl78_return_value);
1477
1478 /* Virtual tables. */
1479 set_gdbarch_vbit_in_delta (gdbarch, 1);
1480
1481 return gdbarch;
1482}
1483
693be288
JK		 1484/* -Wmissing-prototypes */
1485extern initialize_file_ftype _initialize_rl78_tdep;
1486
9058f767
KB		 1487/* Register the above initialization routine. */
1488
1489void
1490_initialize_rl78_tdep (void)
1491{
1492 register_gdbarch_init (bfd_arch_rl78, rl78_gdbarch_init);
1493}
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