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2003-10-10 Kei Sakamoto <sakamoto.kei@renesas.com>
[thirdparty/binutils-gdb.git] / gdb / sh64-tdep.c
CommitLineData
55ff77ac
CV		 1/* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22/*
23 Contributed by Steve Chamberlain
24 sac@cygnus.com
25 */
26
27#include "defs.h"
28#include "frame.h"
29#include "symtab.h"
30#include "symfile.h"
31#include "gdbtypes.h"
32#include "gdbcmd.h"
33#include "gdbcore.h"
34#include "value.h"
35#include "dis-asm.h"
36#include "inferior.h"
37#include "gdb_string.h"
38#include "arch-utils.h"
39#include "floatformat.h"
40#include "regcache.h"
41#include "doublest.h"
42#include "osabi.h"
43
44#include "elf-bfd.h"
45#include "solib-svr4.h"
46
47/* sh flags */
48#include "elf/sh.h"
49/* registers numbers shared with the simulator */
50#include "gdb/sim-sh.h"
51
52/* Information that is dependent on the processor variant. */
53enum sh_abi
54 {
55 SH_ABI_UNKNOWN,
56 SH_ABI_32,
57 SH_ABI_64
58 };
59
60struct gdbarch_tdep
61 {
62 enum sh_abi sh_abi;
63 };
64
65/* Registers of SH5 */
66enum
67 {
68 R0_REGNUM = 0,
69 DEFAULT_RETURN_REGNUM = 2,
70 STRUCT_RETURN_REGNUM = 2,
71 ARG0_REGNUM = 2,
72 ARGLAST_REGNUM = 9,
73 FLOAT_ARGLAST_REGNUM = 11,
74 PR_REGNUM = 18,
75 SR_REGNUM = 65,
76 DR0_REGNUM = 141,
77 DR_LAST_REGNUM = 172,
78 /* FPP stands for Floating Point Pair, to avoid confusion with
79 GDB's FP0_REGNUM, which is the number of the first Floating
80 point register. Unfortunately on the sh5, the floating point
81 registers are called FR, and the floating point pairs are called FP. */
82 FPP0_REGNUM = 173,
83 FPP_LAST_REGNUM = 204,
84 FV0_REGNUM = 205,
85 FV_LAST_REGNUM = 220,
86 R0_C_REGNUM = 221,
87 R_LAST_C_REGNUM = 236,
88 PC_C_REGNUM = 237,
89 GBR_C_REGNUM = 238,
90 MACH_C_REGNUM = 239,
91 MACL_C_REGNUM = 240,
92 PR_C_REGNUM = 241,
93 T_C_REGNUM = 242,
94 FPSCR_C_REGNUM = 243,
95 FPUL_C_REGNUM = 244,
96 FP0_C_REGNUM = 245,
97 FP_LAST_C_REGNUM = 260,
98 DR0_C_REGNUM = 261,
99 DR_LAST_C_REGNUM = 268,
100 FV0_C_REGNUM = 269,
101 FV_LAST_C_REGNUM = 272,
102 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
103 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
104 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
105 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
106 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
107 };
108
109
110/* Define other aspects of the stack frame.
111 we keep a copy of the worked out return pc lying around, since it
112 is a useful bit of info */
113
114struct frame_extra_info
115{
116 CORE_ADDR return_pc;
117 int leaf_function;
118 int f_offset;
119};
120
121static const char *
122sh_sh64_register_name (int reg_nr)
123{
124 static char *register_names[] =
125 {
126 /* SH MEDIA MODE (ISA 32) */
127 /* general registers (64-bit) 0-63 */
128 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
129 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
130 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
131 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
132 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
133 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
134 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
135 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
136
137 /* pc (64-bit) 64 */
138 "pc",
139
140 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
141 "sr", "ssr", "spc",
142
143 /* target registers (64-bit) 68-75*/
144 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
145
146 /* floating point state control register (32-bit) 76 */
147 "fpscr",
148
149 /* single precision floating point registers (32-bit) 77-140*/
150 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
151 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
152 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
153 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
154 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
155 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
156 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
157 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
158
159 /* double precision registers (pseudo) 141-172 */
160 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
161 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
162 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
163 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
164
165 /* floating point pairs (pseudo) 173-204*/
166 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
167 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
168 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
169 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
170
171 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
172 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
173 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
174
175 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
176 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
177 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
178 "pc_c",
179 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
180 "fpscr_c", "fpul_c",
181 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
182 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
183 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
184 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
185 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
186 };
187
188 if (reg_nr < 0)
189 return NULL;
190 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
191 return NULL;
192 return register_names[reg_nr];
193}
194
195#define NUM_PSEUDO_REGS_SH_MEDIA 80
196#define NUM_PSEUDO_REGS_SH_COMPACT 51
197
198/* Macros and functions for setting and testing a bit in a minimal
199 symbol that marks it as 32-bit function. The MSB of the minimal
200 symbol's "info" field is used for this purpose. This field is
201 already being used to store the symbol size, so the assumption is
202 that the symbol size cannot exceed 2^31.
203
204 ELF_MAKE_MSYMBOL_SPECIAL
205 tests whether an ELF symbol is "special", i.e. refers
206 to a 32-bit function, and sets a "special" bit in a
207 minimal symbol to mark it as a 32-bit function
208 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
209 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
210 the "info" field with the "special" bit masked out */
211
212#define MSYMBOL_IS_SPECIAL(msym) \
213 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
214
215static void
216sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
217{
218 if (msym == NULL)
219 return;
220
221 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
222 {
223 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
224 SYMBOL_VALUE_ADDRESS (msym) |= 1;
225 }
226}
227
228/* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
229 are some macros to test, set, or clear bit 0 of addresses. */
230#define IS_ISA32_ADDR(addr) ((addr) & 1)
231#define MAKE_ISA32_ADDR(addr) ((addr) | 1)
232#define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
233
234static int
235pc_is_isa32 (bfd_vma memaddr)
236{
237 struct minimal_symbol *sym;
238
239 /* If bit 0 of the address is set, assume this is a
240 ISA32 (shmedia) address. */
241 if (IS_ISA32_ADDR (memaddr))
242 return 1;
243
244 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
245 the high bit of the info field. Use this to decide if the function is
246 ISA16 or ISA32. */
247 sym = lookup_minimal_symbol_by_pc (memaddr);
248 if (sym)
249 return MSYMBOL_IS_SPECIAL (sym);
250 else
251 return 0;
252}
253
254static const unsigned char *
255sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
256{
257 /* The BRK instruction for shmedia is
258 01101111 11110101 11111111 11110000
259 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
260 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
261
262 /* The BRK instruction for shcompact is
263 00000000 00111011
264 which translates in big endian mode to 0x0, 0x3b
265 and in little endian mode to 0x3b, 0x0*/
266
267 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
268 {
269 if (pc_is_isa32 (*pcptr))
270 {
271 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
272 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
273 *lenptr = sizeof (big_breakpoint_media);
274 return big_breakpoint_media;
275 }
276 else
277 {
278 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
279 *lenptr = sizeof (big_breakpoint_compact);
280 return big_breakpoint_compact;
281 }
282 }
283 else
284 {
285 if (pc_is_isa32 (*pcptr))
286 {
287 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
288 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
289 *lenptr = sizeof (little_breakpoint_media);
290 return little_breakpoint_media;
291 }
292 else
293 {
294 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
295 *lenptr = sizeof (little_breakpoint_compact);
296 return little_breakpoint_compact;
297 }
298 }
299}
300
301/* Prologue looks like
302 [mov.l <regs>,@-r15]...
303 [sts.l pr,@-r15]
304 [mov.l r14,@-r15]
305 [mov r15,r14]
306
307 Actually it can be more complicated than this. For instance, with
308 newer gcc's:
309
310 mov.l r14,@-r15
311 add #-12,r15
312 mov r15,r14
313 mov r4,r1
314 mov r5,r2
315 mov.l r6,@(4,r14)
316 mov.l r7,@(8,r14)
317 mov.b r1,@r14
318 mov r14,r1
319 mov r14,r1
320 add #2,r1
321 mov.w r2,@r1
322
323 */
324
325/* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
326 with l=1 and n = 18 0110101111110001010010100aaa0000 */
327#define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
328
329/* STS.L PR,@-r0 0100000000100010
330 r0-4-->r0, PR-->(r0) */
331#define IS_STS_R0(x) ((x) == 0x4022)
332
333/* STS PR, Rm 0000mmmm00101010
334 PR-->Rm */
335#define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
336
337/* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
338 Rm-->(dispx4+r15) */
339#define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
340
341/* MOV.L R14,@(disp,r15) 000111111110dddd
342 R14-->(dispx4+r15) */
343#define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
344
345/* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
346 R18-->(dispx8+R14) */
347#define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
348
349/* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
350 R18-->(dispx8+R15) */
351#define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
352
353/* ST.L R15, disp, R18 101010001111dddddddddd0100100000
354 R18-->(dispx4+R15) */
355#define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
356
357/* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
358 R14-->(dispx8+R15) */
359#define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
360
361/* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
362 R14-->(dispx4+R15) */
363#define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
364
365/* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
366 R15 + imm --> R15 */
367#define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
368
369/* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
370 R15 + imm --> R15 */
371#define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
372
373/* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
374 R15 + R63 --> R14 */
375#define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
376
377/* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
378 R15 + R63 --> R14 */
379#define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
380
381#define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
382
383/* MOV #imm, R0 1110 0000 ssss ssss
384 #imm-->R0 */
385#define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
386
387/* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
388#define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
389
390/* ADD r15,r0 0011 0000 1111 1100
391 r15+r0-->r0 */
392#define IS_ADD_SP_R0(x) ((x) == 0x30fc)
393
394/* MOV.L R14 @-R0 0010 0000 1110 0110
395 R14-->(R0-4), R0-4-->R0 */
396#define IS_MOV_R14_R0(x) ((x) == 0x20e6)
397
398/* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
399 where Rm is one of r2-r9 which are the argument registers. */
400/* FIXME: Recognize the float and double register moves too! */
401#define IS_MEDIA_IND_ARG_MOV(x) \
402((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
403
404/* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
405 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
406 where Rm is one of r2-r9 which are the argument registers. */
407#define IS_MEDIA_ARG_MOV(x) \
408(((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
409 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
410
411/* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
412/* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
413/* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
414/* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
415/* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
416#define IS_MEDIA_MOV_TO_R14(x) \
417((((x) & 0xfffffc0f) == 0xa0e00000) \
418|| (((x) & 0xfffffc0f) == 0xa4e00000) \
419|| (((x) & 0xfffffc0f) == 0xa8e00000) \
420|| (((x) & 0xfffffc0f) == 0xb4e00000) \
421|| (((x) & 0xfffffc0f) == 0xbce00000))
422
423/* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
424 where Rm is r2-r9 */
425#define IS_COMPACT_IND_ARG_MOV(x) \
426((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
427
428/* compact direct arg move!
429 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
430#define IS_COMPACT_ARG_MOV(x) \
431(((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
432
433/* MOV.B Rm, @R14 0010 1110 mmmm 0000
434 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
435#define IS_COMPACT_MOV_TO_R14(x) \
436((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
437
438#define IS_JSR_R0(x) ((x) == 0x400b)
439#define IS_NOP(x) ((x) == 0x0009)
440
441
442/* MOV r15,r14 0110111011110011
443 r15-->r14 */
444#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
445
446/* ADD #imm,r15 01111111iiiiiiii
447 r15+imm-->r15 */
448#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
449
450/* Skip any prologue before the guts of a function */
451
452/* Skip the prologue using the debug information. If this fails we'll
453 fall back on the 'guess' method below. */
454static CORE_ADDR
455after_prologue (CORE_ADDR pc)
456{
457 struct symtab_and_line sal;
458 CORE_ADDR func_addr, func_end;
459
460 /* If we can not find the symbol in the partial symbol table, then
461 there is no hope we can determine the function's start address
462 with this code. */
463 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
464 return 0;
465
466 /* Get the line associated with FUNC_ADDR. */
467 sal = find_pc_line (func_addr, 0);
468
469 /* There are only two cases to consider. First, the end of the source line
470 is within the function bounds. In that case we return the end of the
471 source line. Second is the end of the source line extends beyond the
472 bounds of the current function. We need to use the slow code to
473 examine instructions in that case. */
474 if (sal.end < func_end)
475 return sal.end;
476 else
477 return 0;
478}
479
480static CORE_ADDR
481look_for_args_moves (CORE_ADDR start_pc, int media_mode)
482{
483 CORE_ADDR here, end;
484 int w;
485 int insn_size = (media_mode ? 4 : 2);
486
487 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
488 {
489 if (media_mode)
490 {
491 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
492 here += insn_size;
493 if (IS_MEDIA_IND_ARG_MOV (w))
494 {
495 /* This must be followed by a store to r14, so the argument
496 is where the debug info says it is. This can happen after
497 the SP has been saved, unfortunately. */
498
499 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
500 insn_size);
501 here += insn_size;
502 if (IS_MEDIA_MOV_TO_R14 (next_insn))
503 start_pc = here;
504 }
505 else if (IS_MEDIA_ARG_MOV (w))
506 {
507 /* These instructions store directly the argument in r14. */
508 start_pc = here;
509 }
510 else
511 break;
512 }
513 else
514 {
515 w = read_memory_integer (here, insn_size);
516 w = w & 0xffff;
517 here += insn_size;
518 if (IS_COMPACT_IND_ARG_MOV (w))
519 {
520 /* This must be followed by a store to r14, so the argument
521 is where the debug info says it is. This can happen after
522 the SP has been saved, unfortunately. */
523
524 int next_insn = 0xffff & read_memory_integer (here, insn_size);
525 here += insn_size;
526 if (IS_COMPACT_MOV_TO_R14 (next_insn))
527 start_pc = here;
528 }
529 else if (IS_COMPACT_ARG_MOV (w))
530 {
531 /* These instructions store directly the argument in r14. */
532 start_pc = here;
533 }
534 else if (IS_MOVL_R0 (w))
535 {
536 /* There is a function that gcc calls to get the arguments
537 passed correctly to the function. Only after this
538 function call the arguments will be found at the place
539 where they are supposed to be. This happens in case the
540 argument has to be stored into a 64-bit register (for
541 instance doubles, long longs). SHcompact doesn't have
542 access to the full 64-bits, so we store the register in
543 stack slot and store the address of the stack slot in
544 the register, then do a call through a wrapper that
545 loads the memory value into the register. A SHcompact
546 callee calls an argument decoder
547 (GCC_shcompact_incoming_args) that stores the 64-bit
548 value in a stack slot and stores the address of the
549 stack slot in the register. GCC thinks the argument is
550 just passed by transparent reference, but this is only
551 true after the argument decoder is called. Such a call
552 needs to be considered part of the prologue. */
553
554 /* This must be followed by a JSR @r0 instruction and by
555 a NOP instruction. After these, the prologue is over! */
556
557 int next_insn = 0xffff & read_memory_integer (here, insn_size);
558 here += insn_size;
559 if (IS_JSR_R0 (next_insn))
560 {
561 next_insn = 0xffff & read_memory_integer (here, insn_size);
562 here += insn_size;
563
564 if (IS_NOP (next_insn))
565 start_pc = here;
566 }
567 }
568 else
569 break;
570 }
571 }
572
573 return start_pc;
574}
575
576static CORE_ADDR
577sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
578{
579 CORE_ADDR here, end;
580 int updated_fp = 0;
581 int insn_size = 4;
582 int media_mode = 1;
583
584 if (!start_pc)
585 return 0;
586
587 if (pc_is_isa32 (start_pc) == 0)
588 {
589 insn_size = 2;
590 media_mode = 0;
591 }
592
593 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
594 {
595
596 if (media_mode)
597 {
598 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
599 here += insn_size;
600 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
601 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
602 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
603 {
604 start_pc = here;
605 }
606 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
607 {
608 start_pc = here;
609 updated_fp = 1;
610 }
611 else
612 if (updated_fp)
613 {
614 /* Don't bail out yet, we may have arguments stored in
615 registers here, according to the debug info, so that
616 gdb can print the frames correctly. */
617 start_pc = look_for_args_moves (here - insn_size, media_mode);
618 break;
619 }
620 }
621 else
622 {
623 int w = 0xffff & read_memory_integer (here, insn_size);
624 here += insn_size;
625
626 if (IS_STS_R0 (w) || IS_STS_PR (w)
627 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
628 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
629 {
630 start_pc = here;
631 }
632 else if (IS_MOV_SP_FP (w))
633 {
634 start_pc = here;
635 updated_fp = 1;
636 }
637 else
638 if (updated_fp)
639 {
640 /* Don't bail out yet, we may have arguments stored in
641 registers here, according to the debug info, so that
642 gdb can print the frames correctly. */
643 start_pc = look_for_args_moves (here - insn_size, media_mode);
644 break;
645 }
646 }
647 }
648
649 return start_pc;
650}
651
652static CORE_ADDR
653sh_skip_prologue (CORE_ADDR pc)
654{
655 CORE_ADDR post_prologue_pc;
656
657 /* See if we can determine the end of the prologue via the symbol table.
658 If so, then return either PC, or the PC after the prologue, whichever
659 is greater. */
660 post_prologue_pc = after_prologue (pc);
661
662 /* If after_prologue returned a useful address, then use it. Else
663 fall back on the instruction skipping code. */
664 if (post_prologue_pc != 0)
665 return max (pc, post_prologue_pc);
666 else
667 return sh64_skip_prologue_hard_way (pc);
668}
669
670/* Immediately after a function call, return the saved pc.
671 Can't always go through the frames for this because on some machines
672 the new frame is not set up until the new function executes
673 some instructions.
674
675 The return address is the value saved in the PR register + 4 */
676static CORE_ADDR
677sh_saved_pc_after_call (struct frame_info *frame)
678{
679 return (ADDR_BITS_REMOVE (read_register (PR_REGNUM)));
680}
681
682/* Should call_function allocate stack space for a struct return? */
683static int
684sh64_use_struct_convention (int gcc_p, struct type *type)
685{
686 return (TYPE_LENGTH (type) > 8);
687}
688
689/* Store the address of the place in which to copy the structure the
690 subroutine will return. This is called from call_function.
691
692 We store structs through a pointer passed in R2 */
693static void
694sh64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
695{
696 write_register (STRUCT_RETURN_REGNUM, (addr));
697}
698
699/* Disassemble an instruction. */
700static int
701gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
702{
703 info->endian = TARGET_BYTE_ORDER;
704 return print_insn_sh (memaddr, info);
705}
706
707/* Given a register number RN as it appears in an assembly
708 instruction, find the corresponding register number in the GDB
709 scheme. */
710static int
711translate_insn_rn (int rn, int media_mode)
712{
713 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
714
715 /* FIXME: this assumes that the number rn is for a not pseudo
716 register only. */
717 if (media_mode)
718 return rn;
719 else
720 {
721 /* These registers don't have a corresponding compact one. */
722 /* FIXME: This is probably not enough. */
723#if 0
724 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
725 return rn;
726#endif
727 if (rn >= 0 && rn <= R0_C_REGNUM)
728 return R0_C_REGNUM + rn;
729 else
730 return rn;
731 }
732}
733
734/* Given a GDB frame, determine the address of the calling function's
735 frame. This will be used to create a new GDB frame struct, and
736 then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC
737 will be called for the new frame.
738
739 For us, the frame address is its stack pointer value, so we look up
740 the function prologue to determine the caller's sp value, and return it. */
741static CORE_ADDR
742sh64_frame_chain (struct frame_info *frame)
743{
744 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
745 get_frame_base (frame),
746 get_frame_base (frame)))
747 return get_frame_base (frame); /* dummy frame same as caller's frame */
627b3ba2
AC		 748 if (get_frame_pc (frame)
749 && !deprecated_inside_entry_file (get_frame_pc (frame)))
55ff77ac
CV		 750 {
751 int media_mode = pc_is_isa32 (get_frame_pc (frame));
752 int size;
753 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
754 size = 4;
755 else
12c266ea 756 size = DEPRECATED_REGISTER_RAW_SIZE (translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode));
55ff77ac
CV		 757 return read_memory_integer (get_frame_base (frame)
758 + get_frame_extra_info (frame)->f_offset,
759 size);
760 }
761 else
762 return 0;
763}
764
765static CORE_ADDR
766sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
767{
768 int media_mode = 0;
769
770 for (; fi; fi = get_next_frame (fi))
771 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
772 get_frame_base (fi)))
773 /* When the caller requests PR from the dummy frame, we return PC because
774 that's where the previous routine appears to have done a call from. */
775 return deprecated_read_register_dummy (get_frame_pc (fi),
776 get_frame_base (fi), pr_regnum);
777 else
778 {
779 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
780 if (!get_frame_pc (fi))
781 return 0;
782
783 media_mode = pc_is_isa32 (get_frame_pc (fi));
784
1b1d3794 785 if (deprecated_get_frame_saved_regs (fi)[pr_regnum] != 0)
55ff77ac
CV		 786 {
787 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
788 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
789 ? 4
12c266ea 790 : DEPRECATED_REGISTER_RAW_SIZE (gdb_reg_num));
1b1d3794 791 return read_memory_integer (deprecated_get_frame_saved_regs (fi)[pr_regnum], size);
55ff77ac
CV		 792 }
793 }
794 return read_register (pr_regnum);
795}
796
797/* For vectors of 4 floating point registers. */
798static int
799fv_reg_base_num (int fv_regnum)
800{
801 int fp_regnum;
802
803 fp_regnum = FP0_REGNUM +
804 (fv_regnum - FV0_REGNUM) * 4;
805 return fp_regnum;
806}
807
808/* For double precision floating point registers, i.e 2 fp regs.*/
809static int
810dr_reg_base_num (int dr_regnum)
811{
812 int fp_regnum;
813
814 fp_regnum = FP0_REGNUM +
815 (dr_regnum - DR0_REGNUM) * 2;
816 return fp_regnum;
817}
818
819/* For pairs of floating point registers */
820static int
821fpp_reg_base_num (int fpp_regnum)
822{
823 int fp_regnum;
824
825 fp_regnum = FP0_REGNUM +
826 (fpp_regnum - FPP0_REGNUM) * 2;
827 return fp_regnum;
828}
829
830static int
831is_media_pseudo (int rn)
832{
833 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
834
835 return (rn >= DR0_REGNUM
836 && rn <= FV_LAST_REGNUM);
837}
838
839static int
840sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc)
841{
842 return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc));
843}
844
845static int
846sh64_media_reg_base_num (int reg_nr)
847{
848 int base_regnum = -1;
849 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
850
851 if (reg_nr >= DR0_REGNUM
852 && reg_nr <= DR_LAST_REGNUM)
853 base_regnum = dr_reg_base_num (reg_nr);
854
855 else if (reg_nr >= FPP0_REGNUM
856 && reg_nr <= FPP_LAST_REGNUM)
857 base_regnum = fpp_reg_base_num (reg_nr);
858
859 else if (reg_nr >= FV0_REGNUM
860 && reg_nr <= FV_LAST_REGNUM)
861 base_regnum = fv_reg_base_num (reg_nr);
862
863 return base_regnum;
864}
865
866/* *INDENT-OFF* */
867/*
868 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
869 GDB_REGNUM BASE_REGNUM
870 r0_c 221 0
871 r1_c 222 1
872 r2_c 223 2
873 r3_c 224 3
874 r4_c 225 4
875 r5_c 226 5
876 r6_c 227 6
877 r7_c 228 7
878 r8_c 229 8
879 r9_c 230 9
880 r10_c 231 10
881 r11_c 232 11
882 r12_c 233 12
883 r13_c 234 13
884 r14_c 235 14
885 r15_c 236 15
886
887 pc_c 237 64
888 gbr_c 238 16
889 mach_c 239 17
890 macl_c 240 17
891 pr_c 241 18
892 t_c 242 19
893 fpscr_c 243 76
894 fpul_c 244 109
895
896 fr0_c 245 77
897 fr1_c 246 78
898 fr2_c 247 79
899 fr3_c 248 80
900 fr4_c 249 81
901 fr5_c 250 82
902 fr6_c 251 83
903 fr7_c 252 84
904 fr8_c 253 85
905 fr9_c 254 86
906 fr10_c 255 87
907 fr11_c 256 88
908 fr12_c 257 89
909 fr13_c 258 90
910 fr14_c 259 91
911 fr15_c 260 92
912
913 dr0_c 261 77
914 dr2_c 262 79
915 dr4_c 263 81
916 dr6_c 264 83
917 dr8_c 265 85
918 dr10_c 266 87
919 dr12_c 267 89
920 dr14_c 268 91
921
922 fv0_c 269 77
923 fv4_c 270 81
924 fv8_c 271 85
925 fv12_c 272 91
926*/
927/* *INDENT-ON* */
928static int
929sh64_compact_reg_base_num (int reg_nr)
930{
931 int base_regnum = -1;
932 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
933
934 /* general register N maps to general register N */
935 if (reg_nr >= R0_C_REGNUM
936 && reg_nr <= R_LAST_C_REGNUM)
937 base_regnum = reg_nr - R0_C_REGNUM;
938
939 /* floating point register N maps to floating point register N */
940 else if (reg_nr >= FP0_C_REGNUM
941 && reg_nr <= FP_LAST_C_REGNUM)
942 base_regnum = reg_nr - FP0_C_REGNUM + FP0_REGNUM;
943
944 /* double prec register N maps to base regnum for double prec register N */
945 else if (reg_nr >= DR0_C_REGNUM
946 && reg_nr <= DR_LAST_C_REGNUM)
947 base_regnum = dr_reg_base_num (DR0_REGNUM
948 + reg_nr - DR0_C_REGNUM);
949
950 /* vector N maps to base regnum for vector register N */
951 else if (reg_nr >= FV0_C_REGNUM
952 && reg_nr <= FV_LAST_C_REGNUM)
953 base_regnum = fv_reg_base_num (FV0_REGNUM
954 + reg_nr - FV0_C_REGNUM);
955
956 else if (reg_nr == PC_C_REGNUM)
957 base_regnum = PC_REGNUM;
958
959 else if (reg_nr == GBR_C_REGNUM)
960 base_regnum = 16;
961
962 else if (reg_nr == MACH_C_REGNUM
963 || reg_nr == MACL_C_REGNUM)
964 base_regnum = 17;
965
966 else if (reg_nr == PR_C_REGNUM)
967 base_regnum = 18;
968
969 else if (reg_nr == T_C_REGNUM)
970 base_regnum = 19;
971
972 else if (reg_nr == FPSCR_C_REGNUM)
973 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
974
975 else if (reg_nr == FPUL_C_REGNUM)
976 base_regnum = FP0_REGNUM + 32;
977
978 return base_regnum;
979}
980
981/* Given a register number RN (according to the gdb scheme) , return
982 its corresponding architectural register. In media mode, only a
983 subset of the registers is pseudo registers. For compact mode, all
984 the registers are pseudo. */
985static int
986translate_rn_to_arch_reg_num (int rn, int media_mode)
987{
988
989 if (media_mode)
990 {
991 if (!is_media_pseudo (rn))
992 return rn;
993 else
994 return sh64_media_reg_base_num (rn);
995 }
996 else
997 /* All compact registers are pseudo. */
998 return sh64_compact_reg_base_num (rn);
999}
1000
1001static int
1002sign_extend (int value, int bits)
1003{
1004 value = value & ((1 << bits) - 1);
1005 return (value & (1 << (bits - 1))
1006 ? value | (~((1 << bits) - 1))
1007 : value);
1008}
1009
1010static void
1011sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
1012{
1013 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1014 int rn;
1015 int have_fp = 0;
1016 int fp_regnum;
1017 int sp_regnum;
1018 int depth;
1019 int pc;
1020 int opc;
1021 int insn;
1022 int r0_val = 0;
1023 int media_mode = 0;
1024 int insn_size;
1025 int gdb_register_number;
1026 int register_number;
1027 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi));
1028 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1029
1b1d3794 1030 if (deprecated_get_frame_saved_regs (fi) == NULL)
55ff77ac
CV		 1031 frame_saved_regs_zalloc (fi);
1032 else
1b1d3794 1033 memset (deprecated_get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
55ff77ac
CV		 1034
1035 if (dummy_regs)
1036 {
1037 /* DANGER! This is ONLY going to work if the char buffer format of
1038 the saved registers is byte-for-byte identical to the
1039 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1b1d3794 1040 memcpy (deprecated_get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
55ff77ac
CV		 1041 return;
1042 }
1043
1044 get_frame_extra_info (fi)->leaf_function = 1;
1045 get_frame_extra_info (fi)->f_offset = 0;
1046
1047 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1048 where[rn] = -1;
1049
1050 depth = 0;
1051
1052 /* Loop around examining the prologue insns until we find something
1053 that does not appear to be part of the prologue. But give up
1054 after 20 of them, since we're getting silly then. */
1055
1056 pc = get_frame_func (fi);
1057 if (!pc)
1058 {
1059 deprecated_update_frame_pc_hack (fi, 0);
1060 return;
1061 }
1062
1063 if (pc_is_isa32 (pc))
1064 {
1065 media_mode = 1;
1066 insn_size = 4;
1067 }
1068 else
1069 {
1070 media_mode = 0;
1071 insn_size = 2;
1072 }
1073
1074 /* The frame pointer register is general register 14 in shmedia and
1075 shcompact modes. In sh compact it is a pseudo register. Same goes
1076 for the stack pointer register, which is register 15. */
1077 fp_regnum = translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode);
1078 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1079
1080 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1081 {
1082 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1083 insn_size);
1084
1085 if (media_mode == 0)
1086 {
1087 if (IS_STS_PR (insn))
1088 {
1089 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1090 if (IS_MOV_TO_R15 (next_insn))
1091 {
1092 int reg_nr = PR_C_REGNUM;
1093
1094 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1095 get_frame_extra_info (fi)->leaf_function = 0;
1096 pc += insn_size;
1097 }
1098 }
1099 else if (IS_MOV_R14 (insn))
1100 {
1101 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1102 }
1103
1104 else if (IS_MOV_R0 (insn))
1105 {
1106 /* Put in R0 the offset from SP at which to store some
1107 registers. We are interested in this value, because it
1108 will tell us where the given registers are stored within
1109 the frame. */
1110 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1111 }
1112 else if (IS_ADD_SP_R0 (insn))
1113 {
1114 /* This instruction still prepares r0, but we don't care.
1115 We already have the offset in r0_val. */
1116 }
1117 else if (IS_STS_R0 (insn))
1118 {
1119 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1120 int reg_nr = PR_C_REGNUM;
1121 where[reg_nr] = depth - (r0_val - 4);
1122 r0_val -= 4;
1123 get_frame_extra_info (fi)->leaf_function = 0;
1124 }
1125 else if (IS_MOV_R14_R0 (insn))
1126 {
1127 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1128 where[fp_regnum] = depth - (r0_val - 4);
1129 r0_val -= 4;
1130 }
1131
1132 else if (IS_ADD_SP (insn))
1133 {
1134 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1135 }
1136 else if (IS_MOV_SP_FP (insn))
1137 break;
1138 }
1139 else
1140 {
1141 if (IS_ADDIL_SP_MEDIA (insn)
1142 || IS_ADDI_SP_MEDIA (insn))
1143 {
1144 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1145 }
1146
1147 else if (IS_STQ_R18_R15 (insn))
1148 {
1149 where[PR_REGNUM] =
1150 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1151 get_frame_extra_info (fi)->leaf_function = 0;
1152 }
1153
1154 else if (IS_STL_R18_R15 (insn))
1155 {
1156 where[PR_REGNUM] =
1157 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1158 get_frame_extra_info (fi)->leaf_function = 0;
1159 }
1160
1161 else if (IS_STQ_R14_R15 (insn))
1162 {
1163 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1164 }
1165
1166 else if (IS_STL_R14_R15 (insn))
1167 {
1168 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1169 }
1170
1171 else if (IS_MOV_SP_FP_MEDIA (insn))
1172 break;
1173 }
1174 }
1175
1176 /* Now we know how deep things are, we can work out their addresses. */
1177 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1178 {
1179 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1180
1181 if (where[rn] >= 0)
1182 {
1183 if (rn == fp_regnum)
1184 have_fp = 1;
1185
1186 /* Watch out! saved_regs is only for the real registers, and
1187 doesn't include space for the pseudo registers. */
1b1d3794 1188 deprecated_get_frame_saved_regs (fi)[register_number]= get_frame_base (fi) - where[rn] + depth;
55ff77ac
CV		 1189
1190 }
1191 else
1b1d3794 1192 deprecated_get_frame_saved_regs (fi)[register_number] = 0;
55ff77ac
CV		 1193 }
1194
1195 if (have_fp)
1196 {
1197 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1198 shcompact 15 is the arch register corresponding to the pseudo
1199 register r15 which still is the SP register. */
1200 /* The place on the stack where fp is stored contains the sp of
1201 the caller. */
1202 /* Again, saved_registers contains only space for the real
1203 registers, so we store in DEPRECATED_FP_REGNUM position. */
1204 int size;
1205 if (tdep->sh_abi == SH_ABI_32)
1206 size = 4;
1207 else
12c266ea 1208 size = DEPRECATED_REGISTER_RAW_SIZE (fp_regnum);
1b1d3794 1209 deprecated_get_frame_saved_regs (fi)[sp_regnum] = read_memory_integer (deprecated_get_frame_saved_regs (fi)[fp_regnum], size);
55ff77ac
CV		 1210 }
1211 else
1b1d3794 1212 deprecated_get_frame_saved_regs (fi)[sp_regnum] = get_frame_base (fi);
55ff77ac
CV		 1213
1214 get_frame_extra_info (fi)->f_offset = depth - where[fp_regnum];
1215}
1216
1217/* Initialize the extra info saved in a FRAME */
1218static void
1219sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1220{
1221 int media_mode = pc_is_isa32 (get_frame_pc (fi));
1222
1223 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
1224
1225 if (get_next_frame (fi))
1226 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
1227
1228 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1229 get_frame_base (fi)))
1230 {
1231 /* We need to setup fi->frame here because call_function_by_hand
1232 gets it wrong by assuming it's always FP. */
1233 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), SP_REGNUM));
1234 get_frame_extra_info (fi)->return_pc =
1235 deprecated_read_register_dummy (get_frame_pc (fi),
1236 get_frame_base (fi), PC_REGNUM);
1237 get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4);
1238 get_frame_extra_info (fi)->leaf_function = 0;
1239 return;
1240 }
1241 else
1242 {
1243 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1244 get_frame_extra_info (fi)->return_pc =
1245 sh64_get_saved_pr (fi, PR_REGNUM);
1246 }
1247}
1248
1249static void
1250sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1251 struct frame_info *frame, int regnum,
1252 enum lval_type *lval)
1253{
1254 int media_mode;
1255 int live_regnum = regnum;
1256 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1257
1258 if (!target_has_registers)
1259 error ("No registers.");
1260
1261 /* Normal systems don't optimize out things with register numbers. */
1262 if (optimized != NULL)
1263 *optimized = 0;
1264
1265 if (addrp) /* default assumption: not found in memory */
1266 *addrp = 0;
1267
1268 if (raw_buffer)
1269 memset (raw_buffer, 0, sizeof (raw_buffer));
1270
1271 /* We must do this here, before the following while loop changes
1272 frame, and makes it NULL. If this is a media register number,
1273 but we are in compact mode, it will become the corresponding
1274 compact pseudo register. If there is no corresponding compact
1275 pseudo-register what do we do?*/
1276 media_mode = pc_is_isa32 (get_frame_pc (frame));
1277 live_regnum = translate_insn_rn (regnum, media_mode);
1278
1279 /* Note: since the current frame's registers could only have been
1280 saved by frames INTERIOR TO the current frame, we skip examining
1281 the current frame itself: otherwise, we would be getting the
1282 previous frame's registers which were saved by the current frame. */
1283
1284 while (frame && ((frame = get_next_frame (frame)) != NULL))
1285 {
1286 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1287 get_frame_base (frame),
1288 get_frame_base (frame)))
1289 {
1290 if (lval) /* found it in a CALL_DUMMY frame */
1291 *lval = not_lval;
1292 if (raw_buffer)
1293 memcpy (raw_buffer,
1294 (deprecated_generic_find_dummy_frame (get_frame_pc (frame), get_frame_base (frame))
62700349 1295 + DEPRECATED_REGISTER_BYTE (regnum)),
12c266ea 1296 DEPRECATED_REGISTER_RAW_SIZE (regnum));
55ff77ac
CV		 1297 return;
1298 }
1299
1300 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1b1d3794
AC		 1301 if (deprecated_get_frame_saved_regs (frame) != NULL
1302 && deprecated_get_frame_saved_regs (frame)[regnum] != 0)
55ff77ac
CV		 1303 {
1304 if (lval) /* found it saved on the stack */
1305 *lval = lval_memory;
1306 if (regnum == SP_REGNUM)
1307 {
1308 if (raw_buffer) /* SP register treated specially */
12c266ea 1309 store_unsigned_integer (raw_buffer, DEPRECATED_REGISTER_RAW_SIZE (regnum),
1b1d3794 1310 deprecated_get_frame_saved_regs (frame)[regnum]);
55ff77ac
CV		 1311 }
1312 else
1313 { /* any other register */
1314
1315 if (addrp)
1b1d3794 1316 *addrp = deprecated_get_frame_saved_regs (frame)[regnum];
55ff77ac
CV		 1317 if (raw_buffer)
1318 {
1319 int size;
1320 if (tdep->sh_abi == SH_ABI_32
1321 && (live_regnum == DEPRECATED_FP_REGNUM
1322 || live_regnum == PR_REGNUM))
1323 size = 4;
1324 else
12c266ea 1325 size = DEPRECATED_REGISTER_RAW_SIZE (live_regnum);
55ff77ac 1326 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1b1d3794 1327 read_memory (deprecated_get_frame_saved_regs (frame)[regnum], raw_buffer, size);
55ff77ac 1328 else
1b1d3794 1329 read_memory (deprecated_get_frame_saved_regs (frame)[regnum],
55ff77ac 1330 raw_buffer
12c266ea 1331 + DEPRECATED_REGISTER_RAW_SIZE (live_regnum)
55ff77ac
CV		 1332 - size,
1333 size);
1334 }
1335 }
1336 return;
1337 }
1338 }
1339
1340 /* If we get thru the loop to this point, it means the register was
1341 not saved in any frame. Return the actual live-register value. */
1342
1343 if (lval) /* found it in a live register */
1344 *lval = lval_register;
1345 if (addrp)
62700349 1346 *addrp = DEPRECATED_REGISTER_BYTE (live_regnum);
55ff77ac
CV		 1347 if (raw_buffer)
1348 deprecated_read_register_gen (live_regnum, raw_buffer);
1349}
1350
1351static CORE_ADDR
1352sh64_extract_struct_value_address (char *regbuf)
1353{
62700349 1354 return (extract_unsigned_integer ((regbuf + DEPRECATED_REGISTER_BYTE (STRUCT_RETURN_REGNUM)),
12c266ea 1355 DEPRECATED_REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM)));
55ff77ac
CV		 1356}
1357
1358static CORE_ADDR
1359sh_frame_saved_pc (struct frame_info *frame)
1360{
1361 return (get_frame_extra_info (frame)->return_pc);
1362}
1363
1364/* Discard from the stack the innermost frame, restoring all saved registers.
1365 Used in the 'return' command. */
1366static void
1367sh64_pop_frame (void)
1368{
52f0bd74
AC		 1369 struct frame_info *frame = get_current_frame ();
1370 CORE_ADDR fp;
1371 int regnum;
55ff77ac
CV		 1372 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1373
1374 int media_mode = pc_is_isa32 (get_frame_pc (frame));
1375
1376 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1377 get_frame_base (frame),
1378 get_frame_base (frame)))
1379 generic_pop_dummy_frame ();
1380 else
1381 {
1382 fp = get_frame_base (frame);
1383 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1384
1385 /* Copy regs from where they were saved in the frame */
1386 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1b1d3794 1387 if (deprecated_get_frame_saved_regs (frame)[regnum])
55ff77ac
CV		 1388 {
1389 int size;
1390 if (tdep->sh_abi == SH_ABI_32
1391 && (regnum == DEPRECATED_FP_REGNUM
1392 || regnum == PR_REGNUM))
1393 size = 4;
1394 else
12c266ea 1395 size = DEPRECATED_REGISTER_RAW_SIZE (translate_insn_rn (regnum,
55ff77ac
CV		 1396 media_mode));
1397 write_register (regnum,
1b1d3794 1398 read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum],
55ff77ac
CV		 1399 size));
1400 }
1401
1402 write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc);
1403 write_register (SP_REGNUM, fp + 8);
1404 }
1405 flush_cached_frames ();
1406}
1407
1408static CORE_ADDR
1409sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
1410{
1411 return sp & ~3;
1412}
1413
1414/* Function: push_arguments
1415 Setup the function arguments for calling a function in the inferior.
1416
1417 On the Hitachi SH architecture, there are four registers (R4 to R7)
1418 which are dedicated for passing function arguments. Up to the first
1419 four arguments (depending on size) may go into these registers.
1420 The rest go on the stack.
1421
1422 Arguments that are smaller than 4 bytes will still take up a whole
1423 register or a whole 32-bit word on the stack, and will be
1424 right-justified in the register or the stack word. This includes
1425 chars, shorts, and small aggregate types.
1426
1427 Arguments that are larger than 4 bytes may be split between two or
1428 more registers. If there are not enough registers free, an argument
1429 may be passed partly in a register (or registers), and partly on the
1430 stack. This includes doubles, long longs, and larger aggregates.
1431 As far as I know, there is no upper limit to the size of aggregates
1432 that will be passed in this way; in other words, the convention of
1433 passing a pointer to a large aggregate instead of a copy is not used.
1434
1435 An exceptional case exists for struct arguments (and possibly other
1436 aggregates such as arrays) if the size is larger than 4 bytes but
1437 not a multiple of 4 bytes. In this case the argument is never split
1438 between the registers and the stack, but instead is copied in its
1439 entirety onto the stack, AND also copied into as many registers as
1440 there is room for. In other words, space in registers permitting,
1441 two copies of the same argument are passed in. As far as I can tell,
1442 only the one on the stack is used, although that may be a function
1443 of the level of compiler optimization. I suspect this is a compiler
1444 bug. Arguments of these odd sizes are left-justified within the
1445 word (as opposed to arguments smaller than 4 bytes, which are
1446 right-justified).
1447
1448 If the function is to return an aggregate type such as a struct, it
1449 is either returned in the normal return value register R0 (if its
1450 size is no greater than one byte), or else the caller must allocate
1451 space into which the callee will copy the return value (if the size
1452 is greater than one byte). In this case, a pointer to the return
1453 value location is passed into the callee in register R2, which does
1454 not displace any of the other arguments passed in via registers R4
1455 to R7. */
1456
1457/* R2-R9 for integer types and integer equivalent (char, pointers) and
1458 non-scalar (struct, union) elements (even if the elements are
1459 floats).
1460 FR0-FR11 for single precision floating point (float)
1461 DR0-DR10 for double precision floating point (double)
1462
1463 If a float is argument number 3 (for instance) and arguments number
1464 1,2, and 4 are integer, the mapping will be:
1465 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1466
1467 If a float is argument number 10 (for instance) and arguments number
1468 1 through 10 are integer, the mapping will be:
1469 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1470 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
1471 I.e. there is hole in the stack.
1472
1473 Different rules apply for variable arguments functions, and for functions
1474 for which the prototype is not known. */
1475
1476static CORE_ADDR
1477sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
1478 int struct_return, CORE_ADDR struct_addr)
1479{
1480 int stack_offset, stack_alloc;
1481 int int_argreg;
1482 int float_argreg;
1483 int double_argreg;
1484 int float_arg_index = 0;
1485 int double_arg_index = 0;
1486 int argnum;
1487 struct type *type;
1488 CORE_ADDR regval;
1489 char *val;
1490 char valbuf[8];
1491 char valbuf_tmp[8];
1492 int len;
1493 int argreg_size;
1494 int fp_args[12];
1495 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1496
1497 memset (fp_args, 0, sizeof (fp_args));
1498
1499 /* first force sp to a 8-byte alignment */
1500 sp = sp & ~7;
1501
1502 /* The "struct return pointer" pseudo-argument has its own dedicated
1503 register */
1504
1505 if (struct_return)
1506 write_register (STRUCT_RETURN_REGNUM, struct_addr);
1507
1508 /* Now make sure there's space on the stack */
1509 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1510 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
1511 sp -= stack_alloc; /* make room on stack for args */
1512
1513 /* Now load as many as possible of the first arguments into
1514 registers, and push the rest onto the stack. There are 64 bytes
1515 in eight registers available. Loop thru args from first to last. */
1516
1517 int_argreg = ARG0_REGNUM;
1518 float_argreg = FP0_REGNUM;
1519 double_argreg = DR0_REGNUM;
1520
1521 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1522 {
1523 type = VALUE_TYPE (args[argnum]);
1524 len = TYPE_LENGTH (type);
1525 memset (valbuf, 0, sizeof (valbuf));
1526
1527 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1528 {
12c266ea 1529 argreg_size = DEPRECATED_REGISTER_RAW_SIZE (int_argreg);
55ff77ac
CV		 1530
1531 if (len < argreg_size)
1532 {
1533 /* value gets right-justified in the register or stack word */
1534 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1535 memcpy (valbuf + argreg_size - len,
1536 (char *) VALUE_CONTENTS (args[argnum]), len);
1537 else
1538 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
1539
1540 val = valbuf;
1541 }
1542 else
1543 val = (char *) VALUE_CONTENTS (args[argnum]);
1544
1545 while (len > 0)
1546 {
1547 if (int_argreg > ARGLAST_REGNUM)
1548 {
1549 /* must go on the stack */
1550 write_memory (sp + stack_offset, val, argreg_size);
1551 stack_offset += 8;/*argreg_size;*/
1552 }
1553 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1554 That's because some *&^%$ things get passed on the stack
1555 AND in the registers! */
1556 if (int_argreg <= ARGLAST_REGNUM)
1557 {
1558 /* there's room in a register */
1559 regval = extract_unsigned_integer (val, argreg_size);
1560 write_register (int_argreg, regval);
1561 }
1562 /* Store the value 8 bytes at a time. This means that
1563 things larger than 8 bytes may go partly in registers
1564 and partly on the stack. FIXME: argreg is incremented
1565 before we use its size. */
1566 len -= argreg_size;
1567 val += argreg_size;
1568 int_argreg++;
1569 }
1570 }
1571 else
1572 {
1573 val = (char *) VALUE_CONTENTS (args[argnum]);
1574 if (len == 4)
1575 {
1576 /* Where is it going to be stored? */
1577 while (fp_args[float_arg_index])
1578 float_arg_index ++;
1579
1580 /* Now float_argreg points to the register where it
1581 should be stored. Are we still within the allowed
1582 register set? */
1583 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1584 {
1585 /* Goes in FR0...FR11 */
1586 deprecated_write_register_gen (FP0_REGNUM + float_arg_index,
1587 val);
1588 fp_args[float_arg_index] = 1;
1589 /* Skip the corresponding general argument register. */
1590 int_argreg ++;
1591 }
1592 else
1593 ;
1594 /* Store it as the integers, 8 bytes at the time, if
1595 necessary spilling on the stack. */
1596
1597 }
1598 else if (len == 8)
1599 {
1600 /* Where is it going to be stored? */
1601 while (fp_args[double_arg_index])
1602 double_arg_index += 2;
1603 /* Now double_argreg points to the register
1604 where it should be stored.
1605 Are we still within the allowed register set? */
1606 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1607 {
1608 /* Goes in DR0...DR10 */
1609 /* The numbering of the DRi registers is consecutive,
1610 i.e. includes odd numbers. */
1611 int double_register_offset = double_arg_index / 2;
1612 int regnum = DR0_REGNUM +
1613 double_register_offset;
1614#if 0
1615 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1616 {
1617 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
1618 DEPRECATED_REGISTER_CONVERT_TO_VIRTUAL (regnum,
1619 type, val,
1620 valbuf_tmp);
1621 val = valbuf_tmp;
1622 }
1623#endif
1624 /* Note: must use write_register_gen here instead
1625 of regcache_raw_write, because
1626 regcache_raw_write works only for real
1627 registers, not pseudo. write_register_gen will
1628 call the gdbarch function to do register
1629 writes, and that will properly know how to deal
1630 with pseudoregs. */
1631 deprecated_write_register_gen (regnum, val);
1632 fp_args[double_arg_index] = 1;
1633 fp_args[double_arg_index + 1] = 1;
1634 /* Skip the corresponding general argument register. */
1635 int_argreg ++;
1636 }
1637 else
1638 ;
1639 /* Store it as the integers, 8 bytes at the time, if
1640 necessary spilling on the stack. */
1641 }
1642 }
1643 }
1644 return sp;
1645}
1646
1647/* Function: push_return_address (pc)
1648 Set up the return address for the inferior function call.
1649 Needed for targets where we don't actually execute a JSR/BSR instruction */
1650
1651static CORE_ADDR
1652sh64_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
1653{
e8a7b686 1654 write_register (PR_REGNUM, entry_point_address ());
55ff77ac
CV		 1655 return sp;
1656}
1657
1658/* Find a function's return value in the appropriate registers (in
1659 regbuf), and copy it into valbuf. Extract from an array REGBUF
1660 containing the (raw) register state a function return value of type
1661 TYPE, and copy that, in virtual format, into VALBUF. */
1662static void
1663sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
1664{
1665 int offset;
1666 int return_register;
1667 int len = TYPE_LENGTH (type);
1668 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1669
1670 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1671 {
1672 if (len == 4)
1673 {
1674 /* Return value stored in FP0_REGNUM */
1675 return_register = FP0_REGNUM;
62700349 1676 offset = DEPRECATED_REGISTER_BYTE (return_register);
55ff77ac
CV		 1677 memcpy (valbuf, (char *) regbuf + offset, len);
1678 }
1679 else if (len == 8)
1680 {
1681 /* return value stored in DR0_REGNUM */
1682 DOUBLEST val;
1683
1684 return_register = DR0_REGNUM;
62700349 1685 offset = DEPRECATED_REGISTER_BYTE (return_register);
55ff77ac
CV		 1686
1687 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1688 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1689 (char *) regbuf + offset, &val);
1690 else
1691 floatformat_to_doublest (&floatformat_ieee_double_big,
1692 (char *) regbuf + offset, &val);
1693 deprecated_store_floating (valbuf, len, val);
1694 }
1695 }
1696 else
1697 {
1698 if (len <= 8)
1699 {
1700 /* Result is in register 2. If smaller than 8 bytes, it is padded
1701 at the most significant end. */
1702 return_register = DEFAULT_RETURN_REGNUM;
1703 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
62700349 1704 offset = DEPRECATED_REGISTER_BYTE (return_register) +
12c266ea 1705 DEPRECATED_REGISTER_RAW_SIZE (return_register) - len;
55ff77ac 1706 else
62700349 1707 offset = DEPRECATED_REGISTER_BYTE (return_register);
55ff77ac
CV		 1708 memcpy (valbuf, (char *) regbuf + offset, len);
1709 }
1710 else
1711 error ("bad size for return value");
1712 }
1713}
1714
1715/* Write into appropriate registers a function return value
1716 of type TYPE, given in virtual format.
1717 If the architecture is sh4 or sh3e, store a function's return value
1718 in the R0 general register or in the FP0 floating point register,
1719 depending on the type of the return value. In all the other cases
1720 the result is stored in r0, left-justified. */
1721
1722static void
1723sh64_store_return_value (struct type *type, char *valbuf)
1724{
1725 char buf[64]; /* more than enough... */
1726 int len = TYPE_LENGTH (type);
1727
1728 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1729 {
1730 if (len == 4)
1731 {
1732 /* Return value stored in FP0_REGNUM */
1733 deprecated_write_register_gen (FP0_REGNUM, valbuf);
1734 }
1735 if (len == 8)
1736 {
1737 /* return value stored in DR0_REGNUM */
1738 /* FIXME: Implement */
1739 }
1740 }
1741 else
1742 {
1743 int return_register = DEFAULT_RETURN_REGNUM;
1744 int offset = 0;
1745
12c266ea 1746 if (len <= DEPRECATED_REGISTER_RAW_SIZE (return_register))
55ff77ac
CV		 1747 {
1748 /* Pad with zeros. */
12c266ea 1749 memset (buf, 0, DEPRECATED_REGISTER_RAW_SIZE (return_register));
55ff77ac 1750 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
12c266ea 1751 offset = 0; /*DEPRECATED_REGISTER_RAW_SIZE (return_register) - len;*/
55ff77ac 1752 else
12c266ea 1753 offset = DEPRECATED_REGISTER_RAW_SIZE (return_register) - len;
55ff77ac
CV		 1754
1755 memcpy (buf + offset, valbuf, len);
1756 deprecated_write_register_gen (return_register, buf);
1757 }
1758 else
1759 deprecated_write_register_gen (return_register, valbuf);
1760 }
1761}
1762
1763static void
1764sh64_show_media_regs (void)
1765{
1766 int i;
1767 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1768
1769 printf_filtered ("PC=%s SR=%016llx \n",
1770 paddr (read_register (PC_REGNUM)),
1771 (long long) read_register (SR_REGNUM));
1772
1773 printf_filtered ("SSR=%016llx SPC=%016llx \n",
1774 (long long) read_register (SSR_REGNUM),
1775 (long long) read_register (SPC_REGNUM));
1776 printf_filtered ("FPSCR=%016lx\n ",
1777 (long) read_register (FPSCR_REGNUM));
1778
1779 for (i = 0; i < 64; i = i + 4)
1780 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
1781 i, i + 3,
1782 (long long) read_register (i + 0),
1783 (long long) read_register (i + 1),
1784 (long long) read_register (i + 2),
1785 (long long) read_register (i + 3));
1786
1787 printf_filtered ("\n");
1788
1789 for (i = 0; i < 64; i = i + 8)
1790 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1791 i, i + 7,
1792 (long) read_register (FP0_REGNUM + i + 0),
1793 (long) read_register (FP0_REGNUM + i + 1),
1794 (long) read_register (FP0_REGNUM + i + 2),
1795 (long) read_register (FP0_REGNUM + i + 3),
1796 (long) read_register (FP0_REGNUM + i + 4),
1797 (long) read_register (FP0_REGNUM + i + 5),
1798 (long) read_register (FP0_REGNUM + i + 6),
1799 (long) read_register (FP0_REGNUM + i + 7));
1800}
1801
1802static void
1803sh64_show_compact_regs (void)
1804{
1805 int i;
1806 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1807
1808 printf_filtered ("PC=%s \n",
1809 paddr (read_register (PC_C_REGNUM)));
1810
1811 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1812 (long) read_register (GBR_C_REGNUM),
1813 (long) read_register (MACH_C_REGNUM),
1814 (long) read_register (MACL_C_REGNUM),
1815 (long) read_register (PR_C_REGNUM),
1816 (long) read_register (T_C_REGNUM));
1817 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
1818 (long) read_register (FPSCR_C_REGNUM),
1819 (long) read_register (FPUL_C_REGNUM));
1820
1821 for (i = 0; i < 16; i = i + 4)
1822 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1823 i, i + 3,
1824 (long) read_register (i + 0),
1825 (long) read_register (i + 1),
1826 (long) read_register (i + 2),
1827 (long) read_register (i + 3));
1828
1829 printf_filtered ("\n");
1830
1831 for (i = 0; i < 16; i = i + 8)
1832 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1833 i, i + 7,
1834 (long) read_register (FP0_REGNUM + i + 0),
1835 (long) read_register (FP0_REGNUM + i + 1),
1836 (long) read_register (FP0_REGNUM + i + 2),
1837 (long) read_register (FP0_REGNUM + i + 3),
1838 (long) read_register (FP0_REGNUM + i + 4),
1839 (long) read_register (FP0_REGNUM + i + 5),
1840 (long) read_register (FP0_REGNUM + i + 6),
1841 (long) read_register (FP0_REGNUM + i + 7));
1842}
1843
1844/*FIXME!!! This only shows the registers for shmedia, excluding the
1845 pseudo registers. */
1846void
1847sh64_show_regs (void)
1848{
1849 if (deprecated_selected_frame
1850 && pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
1851 sh64_show_media_regs ();
1852 else
1853 sh64_show_compact_regs ();
1854}
1855
1856/* *INDENT-OFF* */
1857/*
1858 SH MEDIA MODE (ISA 32)
1859 general registers (64-bit) 0-63
18600 r0, r1, r2, r3, r4, r5, r6, r7,
186164 r8, r9, r10, r11, r12, r13, r14, r15,
1862128 r16, r17, r18, r19, r20, r21, r22, r23,
1863192 r24, r25, r26, r27, r28, r29, r30, r31,
1864256 r32, r33, r34, r35, r36, r37, r38, r39,
1865320 r40, r41, r42, r43, r44, r45, r46, r47,
1866384 r48, r49, r50, r51, r52, r53, r54, r55,
1867448 r56, r57, r58, r59, r60, r61, r62, r63,
1868
1869 pc (64-bit) 64
1870512 pc,
1871
1872 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1873520 sr, ssr, spc,
1874
1875 target registers (64-bit) 68-75
1876544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1877
1878 floating point state control register (32-bit) 76
1879608 fpscr,
1880
1881 single precision floating point registers (32-bit) 77-140
1882612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1883644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1884676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1885708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1886740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1887772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1888804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1889836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1890
1891TOTAL SPACE FOR REGISTERS: 868 bytes
1892
1893From here on they are all pseudo registers: no memory allocated.
1894REGISTER_BYTE returns the register byte for the base register.
1895
1896 double precision registers (pseudo) 141-172
1897 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1898 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1899 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1900 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1901
1902 floating point pairs (pseudo) 173-204
1903 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1904 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1905 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1906 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1907
1908 floating point vectors (4 floating point regs) (pseudo) 205-220
1909 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1910 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1911
1912 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1913 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1914 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1915 pc_c,
1916 gbr_c, mach_c, macl_c, pr_c, t_c,
1917 fpscr_c, fpul_c,
1918 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1919 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1920 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1921 fv0_c, fv4_c, fv8_c, fv12_c
1922*/
1923/* *INDENT-ON* */
1924static int
1925sh_sh64_register_byte (int reg_nr)
1926{
1927 int base_regnum = -1;
1928 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1929
1930 /* If it is a pseudo register, get the number of the first floating
1931 point register that is part of it. */
1932 if (reg_nr >= DR0_REGNUM
1933 && reg_nr <= DR_LAST_REGNUM)
1934 base_regnum = dr_reg_base_num (reg_nr);
1935
1936 else if (reg_nr >= FPP0_REGNUM
1937 && reg_nr <= FPP_LAST_REGNUM)
1938 base_regnum = fpp_reg_base_num (reg_nr);
1939
1940 else if (reg_nr >= FV0_REGNUM
1941 && reg_nr <= FV_LAST_REGNUM)
1942 base_regnum = fv_reg_base_num (reg_nr);
1943
1944 /* sh compact pseudo register. FPSCR is a pathological case, need to
1945 treat it as special. */
1946 else if ((reg_nr >= R0_C_REGNUM
1947 && reg_nr <= FV_LAST_C_REGNUM)
1948 && reg_nr != FPSCR_C_REGNUM)
1949 base_regnum = sh64_compact_reg_base_num (reg_nr);
1950
1951 /* Now return the offset in bytes within the register cache. */
1952 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
1953 if (reg_nr >= DR0_REGNUM
1954 && reg_nr <= FV_LAST_REGNUM)
1955 return (base_regnum - FP0_REGNUM + 1) * 4
1956 + (TR7_REGNUM + 1) * 8;
1957
1958 /* sh compact pseudo register: general register */
1959 if ((reg_nr >= R0_C_REGNUM
1960 && reg_nr <= R_LAST_C_REGNUM))
1961 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1962 ? base_regnum * 8 + 4
1963 : base_regnum * 8);
1964
1965 /* sh compact pseudo register: */
1966 if (reg_nr == PC_C_REGNUM
1967 || reg_nr == GBR_C_REGNUM
1968 || reg_nr == MACL_C_REGNUM
1969 || reg_nr == PR_C_REGNUM)
1970 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1971 ? base_regnum * 8 + 4
1972 : base_regnum * 8);
1973
1974 if (reg_nr == MACH_C_REGNUM)
1975 return base_regnum * 8;
1976
1977 if (reg_nr == T_C_REGNUM)
1978 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
1979
1980 /* sh compact pseudo register: floating point register */
1981 else if (reg_nr >= FP0_C_REGNUM
1982 && reg_nr <= FV_LAST_C_REGNUM)
1983 return (base_regnum - FP0_REGNUM) * 4
1984 + (TR7_REGNUM + 1) * 8 + 4;
1985
1986 else if (reg_nr == FPSCR_C_REGNUM)
1987 /* This is complicated, for now return the beginning of the
1988 architectural FPSCR register. */
1989 return (TR7_REGNUM + 1) * 8;
1990
1991 else if (reg_nr == FPUL_C_REGNUM)
1992 return ((base_regnum - FP0_REGNUM) * 4 +
1993 (TR7_REGNUM + 1) * 8 + 4);
1994
1995 /* It is not a pseudo register. */
1996 /* It is a 64 bit register. */
1997 else if (reg_nr <= TR7_REGNUM)
1998 return reg_nr * 8;
1999
2000 /* It is a 32 bit register. */
2001 else if (reg_nr == FPSCR_REGNUM)
2002 return (FPSCR_REGNUM * 8);
2003
2004 /* It is floating point 32-bit register */
2005 else
2006 return ((TR7_REGNUM + 1) * 8
2007 + (reg_nr - FP0_REGNUM + 1) * 4);
2008}
2009
2010static int
2011sh_sh64_register_raw_size (int reg_nr)
2012{
2013 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2014
2015 if ((reg_nr >= DR0_REGNUM
2016 && reg_nr <= DR_LAST_REGNUM)
2017 || (reg_nr >= FPP0_REGNUM
2018 && reg_nr <= FPP_LAST_REGNUM)
2019 || (reg_nr >= DR0_C_REGNUM
2020 && reg_nr <= DR_LAST_C_REGNUM)
2021 || (reg_nr <= TR7_REGNUM))
2022 return 8;
2023
2024 else if ((reg_nr >= FV0_REGNUM
2025 && reg_nr <= FV_LAST_REGNUM)
2026 || (reg_nr >= FV0_C_REGNUM
2027 && reg_nr <= FV_LAST_C_REGNUM))
2028 return 16;
2029
2030 else /* this covers also the 32-bit SH compact registers. */
2031 return 4;
2032}
2033
2034/* ??????? FIXME */
2035static int
2036sh_sh64_register_virtual_size (int reg_nr)
2037{
2038 if (reg_nr >= FP0_REGNUM
2039 && reg_nr <= FP_LAST_REGNUM)
2040 return 4;
2041 else
2042 return 8;
2043}
2044
2045static struct type *
2046sh_sh64_build_float_register_type (int high)
2047{
2048 struct type *temp;
2049
2050 temp = create_range_type (NULL, builtin_type_int, 0, high);
2051 return create_array_type (NULL, builtin_type_float, temp);
2052}
2053
2054static struct type *
2055sh_sh64_register_virtual_type (int reg_nr)
2056{
2057 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2058
2059 if ((reg_nr >= FP0_REGNUM
2060 && reg_nr <= FP_LAST_REGNUM)
2061 || (reg_nr >= FP0_C_REGNUM
2062 && reg_nr <= FP_LAST_C_REGNUM))
2063 return builtin_type_float;
2064 else if ((reg_nr >= DR0_REGNUM
2065 && reg_nr <= DR_LAST_REGNUM)
2066 || (reg_nr >= DR0_C_REGNUM
2067 && reg_nr <= DR_LAST_C_REGNUM))
2068 return builtin_type_double;
2069 else if (reg_nr >= FPP0_REGNUM
2070 && reg_nr <= FPP_LAST_REGNUM)
2071 return sh_sh64_build_float_register_type (1);
2072 else if ((reg_nr >= FV0_REGNUM
2073 && reg_nr <= FV_LAST_REGNUM)
2074 ||(reg_nr >= FV0_C_REGNUM
2075 && reg_nr <= FV_LAST_C_REGNUM))
2076 return sh_sh64_build_float_register_type (3);
2077 else if (reg_nr == FPSCR_REGNUM)
2078 return builtin_type_int;
2079 else if (reg_nr >= R0_C_REGNUM
2080 && reg_nr < FP0_C_REGNUM)
2081 return builtin_type_int;
2082 else
2083 return builtin_type_long_long;
2084}
2085
2086static void
2087sh_sh64_register_convert_to_virtual (int regnum, struct type *type,
2088 char *from, char *to)
2089{
2090 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2091
2092 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
2093 {
2094 /* It is a no-op. */
12c266ea 2095 memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (regnum));
55ff77ac
CV		 2096 return;
2097 }
2098
2099 if ((regnum >= DR0_REGNUM
2100 && regnum <= DR_LAST_REGNUM)
2101 || (regnum >= DR0_C_REGNUM
2102 && regnum <= DR_LAST_C_REGNUM))
2103 {
2104 DOUBLEST val;
2105 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
2106 deprecated_store_floating(to, TYPE_LENGTH(type), val);
2107 }
2108 else
2109 error("sh_register_convert_to_virtual called with non DR register number");
2110}
2111
2112static void
2113sh_sh64_register_convert_to_raw (struct type *type, int regnum,
2114 const void *from, void *to)
2115{
2116 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2117
2118 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
2119 {
2120 /* It is a no-op. */
12c266ea 2121 memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (regnum));
55ff77ac
CV		 2122 return;
2123 }
2124
2125 if ((regnum >= DR0_REGNUM
2126 && regnum <= DR_LAST_REGNUM)
2127 || (regnum >= DR0_C_REGNUM
2128 && regnum <= DR_LAST_C_REGNUM))
2129 {
2130 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
2131 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
2132 }
2133 else
2134 error("sh_register_convert_to_raw called with non DR register number");
2135}
2136
2137static void
2138sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2139 int reg_nr, void *buffer)
2140{
2141 int base_regnum;
2142 int portion;
2143 int offset = 0;
2144 char temp_buffer[MAX_REGISTER_SIZE];
2145 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2146
2147 if (reg_nr >= DR0_REGNUM
2148 && reg_nr <= DR_LAST_REGNUM)
2149 {
2150 base_regnum = dr_reg_base_num (reg_nr);
2151
2152 /* Build the value in the provided buffer. */
2153 /* DR regs are double precision registers obtained by
2154 concatenating 2 single precision floating point registers. */
2155 for (portion = 0; portion < 2; portion++)
2156 regcache_raw_read (regcache, base_regnum + portion,
2157 (temp_buffer
12c266ea 2158 + DEPRECATED_REGISTER_RAW_SIZE (base_regnum) * portion));
55ff77ac
CV		 2159
2160 /* We must pay attention to the endiannes. */
2e092625 2161 sh_sh64_register_convert_to_virtual (reg_nr, DEPRECATED_REGISTER_VIRTUAL_TYPE (reg_nr),
55ff77ac
CV		 2162 temp_buffer, buffer);
2163
2164 }
2165
2166 else if (reg_nr >= FPP0_REGNUM
2167 && reg_nr <= FPP_LAST_REGNUM)
2168 {
2169 base_regnum = fpp_reg_base_num (reg_nr);
2170
2171 /* Build the value in the provided buffer. */
2172 /* FPP regs are pairs of single precision registers obtained by
2173 concatenating 2 single precision floating point registers. */
2174 for (portion = 0; portion < 2; portion++)
2175 regcache_raw_read (regcache, base_regnum + portion,
2176 ((char *) buffer
12c266ea 2177 + DEPRECATED_REGISTER_RAW_SIZE (base_regnum) * portion));
55ff77ac
CV		 2178 }
2179
2180 else if (reg_nr >= FV0_REGNUM
2181 && reg_nr <= FV_LAST_REGNUM)
2182 {
2183 base_regnum = fv_reg_base_num (reg_nr);
2184
2185 /* Build the value in the provided buffer. */
2186 /* FV regs are vectors of single precision registers obtained by
2187 concatenating 4 single precision floating point registers. */
2188 for (portion = 0; portion < 4; portion++)
2189 regcache_raw_read (regcache, base_regnum + portion,
2190 ((char *) buffer
12c266ea 2191 + DEPRECATED_REGISTER_RAW_SIZE (base_regnum) * portion));
55ff77ac
CV		 2192 }
2193
2194 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
2195 else if (reg_nr >= R0_C_REGNUM
2196 && reg_nr <= T_C_REGNUM)
2197 {
2198 base_regnum = sh64_compact_reg_base_num (reg_nr);
2199
2200 /* Build the value in the provided buffer. */
2201 regcache_raw_read (regcache, base_regnum, temp_buffer);
2202 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2203 offset = 4;
2204 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
2205 }
2206
2207 else if (reg_nr >= FP0_C_REGNUM
2208 && reg_nr <= FP_LAST_C_REGNUM)
2209 {
2210 base_regnum = sh64_compact_reg_base_num (reg_nr);
2211
2212 /* Build the value in the provided buffer. */
2213 /* Floating point registers map 1-1 to the media fp regs,
2214 they have the same size and endienness. */
2215 regcache_raw_read (regcache, base_regnum, buffer);
2216 }
2217
2218 else if (reg_nr >= DR0_C_REGNUM
2219 && reg_nr <= DR_LAST_C_REGNUM)
2220 {
2221 base_regnum = sh64_compact_reg_base_num (reg_nr);
2222
2223 /* DR_C regs are double precision registers obtained by
2224 concatenating 2 single precision floating point registers. */
2225 for (portion = 0; portion < 2; portion++)
2226 regcache_raw_read (regcache, base_regnum + portion,
2227 (temp_buffer
12c266ea 2228 + DEPRECATED_REGISTER_RAW_SIZE (base_regnum) * portion));
55ff77ac
CV		 2229
2230 /* We must pay attention to the endiannes. */
2e092625 2231 sh_sh64_register_convert_to_virtual (reg_nr, DEPRECATED_REGISTER_VIRTUAL_TYPE (reg_nr),
55ff77ac
CV		 2232 temp_buffer, buffer);
2233 }
2234
2235 else if (reg_nr >= FV0_C_REGNUM
2236 && reg_nr <= FV_LAST_C_REGNUM)
2237 {
2238 base_regnum = sh64_compact_reg_base_num (reg_nr);
2239
2240 /* Build the value in the provided buffer. */
2241 /* FV_C regs are vectors of single precision registers obtained by
2242 concatenating 4 single precision floating point registers. */
2243 for (portion = 0; portion < 4; portion++)
2244 regcache_raw_read (regcache, base_regnum + portion,
2245 ((char *) buffer
12c266ea 2246 + DEPRECATED_REGISTER_RAW_SIZE (base_regnum) * portion));
55ff77ac
CV		 2247 }
2248
2249 else if (reg_nr == FPSCR_C_REGNUM)
2250 {
2251 int fpscr_base_regnum;
2252 int sr_base_regnum;
2253 unsigned int fpscr_value;
2254 unsigned int sr_value;
2255 unsigned int fpscr_c_value;
2256 unsigned int fpscr_c_part1_value;
2257 unsigned int fpscr_c_part2_value;
2258
2259 fpscr_base_regnum = FPSCR_REGNUM;
2260 sr_base_regnum = SR_REGNUM;
2261
2262 /* Build the value in the provided buffer. */
2263 /* FPSCR_C is a very weird register that contains sparse bits
2264 from the FPSCR and the SR architectural registers.
2265 Specifically: */
2266 /* *INDENT-OFF* */
2267 /*
2268 FPSRC_C bit
2269 0 Bit 0 of FPSCR
2270 1 reserved
2271 2-17 Bit 2-18 of FPSCR
2272 18-20 Bits 12,13,14 of SR
2273 21-31 reserved
2274 */
2275 /* *INDENT-ON* */
2276 /* Get FPSCR into a local buffer */
2277 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
2278 /* Get value as an int. */
2279 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
2280 /* Get SR into a local buffer */
2281 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
2282 /* Get value as an int. */
2283 sr_value = extract_unsigned_integer (temp_buffer, 4);
2284 /* Build the new value. */
2285 fpscr_c_part1_value = fpscr_value & 0x3fffd;
2286 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
2287 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
2288 /* Store that in out buffer!!! */
2289 store_unsigned_integer (buffer, 4, fpscr_c_value);
2290 /* FIXME There is surely an endianness gotcha here. */
2291 }
2292
2293 else if (reg_nr == FPUL_C_REGNUM)
2294 {
2295 base_regnum = sh64_compact_reg_base_num (reg_nr);
2296
2297 /* FPUL_C register is floating point register 32,
2298 same size, same endianness. */
2299 regcache_raw_read (regcache, base_regnum, buffer);
2300 }
2301}
2302
2303static void
2304sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2305 int reg_nr, const void *buffer)
2306{
2307 int base_regnum, portion;
2308 int offset;
2309 char temp_buffer[MAX_REGISTER_SIZE];
2310 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2311
2312 if (reg_nr >= DR0_REGNUM
2313 && reg_nr <= DR_LAST_REGNUM)
2314 {
2315 base_regnum = dr_reg_base_num (reg_nr);
2316 /* We must pay attention to the endiannes. */
2e092625 2317 sh_sh64_register_convert_to_raw (DEPRECATED_REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
55ff77ac
CV		 2318 buffer, temp_buffer);
2319
2320
2321 /* Write the real regs for which this one is an alias. */
2322 for (portion = 0; portion < 2; portion++)
2323 regcache_raw_write (regcache, base_regnum + portion,
2324 (temp_buffer
12c266ea 2325 + DEPRECATED_REGISTER_RAW_SIZE (base_regnum) * portion));
55ff77ac
CV		 2326 }
2327
2328 else if (reg_nr >= FPP0_REGNUM
2329 && reg_nr <= FPP_LAST_REGNUM)
2330 {
2331 base_regnum = fpp_reg_base_num (reg_nr);
2332
2333 /* Write the real regs for which this one is an alias. */
2334 for (portion = 0; portion < 2; portion++)
2335 regcache_raw_write (regcache, base_regnum + portion,
2336 ((char *) buffer
12c266ea 2337 + DEPRECATED_REGISTER_RAW_SIZE (base_regnum) * portion));
55ff77ac
CV		 2338 }
2339
2340 else if (reg_nr >= FV0_REGNUM
2341 && reg_nr <= FV_LAST_REGNUM)
2342 {
2343 base_regnum = fv_reg_base_num (reg_nr);
2344
2345 /* Write the real regs for which this one is an alias. */
2346 for (portion = 0; portion < 4; portion++)
2347 regcache_raw_write (regcache, base_regnum + portion,
2348 ((char *) buffer
12c266ea 2349 + DEPRECATED_REGISTER_RAW_SIZE (base_regnum) * portion));
55ff77ac
CV		 2350 }
2351
2352 /* sh compact general pseudo registers. 1-to-1 with a shmedia
2353 register but only 4 bytes of it. */
2354 else if (reg_nr >= R0_C_REGNUM
2355 && reg_nr <= T_C_REGNUM)
2356 {
2357 base_regnum = sh64_compact_reg_base_num (reg_nr);
2358 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
2359 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2360 offset = 4;
2361 else
2362 offset = 0;
2363 /* Let's read the value of the base register into a temporary
2364 buffer, so that overwriting the last four bytes with the new
2365 value of the pseudo will leave the upper 4 bytes unchanged. */
2366 regcache_raw_read (regcache, base_regnum, temp_buffer);
2367 /* Write as an 8 byte quantity */
2368 memcpy (temp_buffer + offset, buffer, 4);
2369 regcache_raw_write (regcache, base_regnum, temp_buffer);
2370 }
2371
2372 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
2373 registers. Both are 4 bytes. */
2374 else if (reg_nr >= FP0_C_REGNUM
2375 && reg_nr <= FP_LAST_C_REGNUM)
2376 {
2377 base_regnum = sh64_compact_reg_base_num (reg_nr);
2378 regcache_raw_write (regcache, base_regnum, buffer);
2379 }
2380
2381 else if (reg_nr >= DR0_C_REGNUM
2382 && reg_nr <= DR_LAST_C_REGNUM)
2383 {
2384 base_regnum = sh64_compact_reg_base_num (reg_nr);
2385 for (portion = 0; portion < 2; portion++)
2386 {
2387 /* We must pay attention to the endiannes. */
2e092625 2388 sh_sh64_register_convert_to_raw (DEPRECATED_REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
55ff77ac
CV		 2389 buffer, temp_buffer);
2390
2391 regcache_raw_write (regcache, base_regnum + portion,
2392 (temp_buffer
12c266ea 2393 + DEPRECATED_REGISTER_RAW_SIZE (base_regnum) * portion));
55ff77ac
CV		 2394 }
2395 }
2396
2397 else if (reg_nr >= FV0_C_REGNUM
2398 && reg_nr <= FV_LAST_C_REGNUM)
2399 {
2400 base_regnum = sh64_compact_reg_base_num (reg_nr);
2401
2402 for (portion = 0; portion < 4; portion++)
2403 {
2404 regcache_raw_write (regcache, base_regnum + portion,
2405 ((char *) buffer
12c266ea 2406 + DEPRECATED_REGISTER_RAW_SIZE (base_regnum) * portion));
55ff77ac
CV		 2407 }
2408 }
2409
2410 else if (reg_nr == FPSCR_C_REGNUM)
2411 {
2412 int fpscr_base_regnum;
2413 int sr_base_regnum;
2414 unsigned int fpscr_value;
2415 unsigned int sr_value;
2416 unsigned int old_fpscr_value;
2417 unsigned int old_sr_value;
2418 unsigned int fpscr_c_value;
2419 unsigned int fpscr_mask;
2420 unsigned int sr_mask;
2421
2422 fpscr_base_regnum = FPSCR_REGNUM;
2423 sr_base_regnum = SR_REGNUM;
2424
2425 /* FPSCR_C is a very weird register that contains sparse bits
2426 from the FPSCR and the SR architectural registers.
2427 Specifically: */
2428 /* *INDENT-OFF* */
2429 /*
2430 FPSRC_C bit
2431 0 Bit 0 of FPSCR
2432 1 reserved
2433 2-17 Bit 2-18 of FPSCR
2434 18-20 Bits 12,13,14 of SR
2435 21-31 reserved
2436 */
2437 /* *INDENT-ON* */
2438 /* Get value as an int. */
2439 fpscr_c_value = extract_unsigned_integer (buffer, 4);
2440
2441 /* Build the new values. */
2442 fpscr_mask = 0x0003fffd;
2443 sr_mask = 0x001c0000;
2444
2445 fpscr_value = fpscr_c_value & fpscr_mask;
2446 sr_value = (fpscr_value & sr_mask) >> 6;
2447
2448 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
2449 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
2450 old_fpscr_value &= 0xfffc0002;
2451 fpscr_value |= old_fpscr_value;
2452 store_unsigned_integer (temp_buffer, 4, fpscr_value);
2453 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
2454
2455 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
2456 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
2457 old_sr_value &= 0xffff8fff;
2458 sr_value |= old_sr_value;
2459 store_unsigned_integer (temp_buffer, 4, sr_value);
2460 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
2461 }
2462
2463 else if (reg_nr == FPUL_C_REGNUM)
2464 {
2465 base_regnum = sh64_compact_reg_base_num (reg_nr);
2466 regcache_raw_write (regcache, base_regnum, buffer);
2467 }
2468}
2469
2470/* Floating point vector of 4 float registers. */
2471static void
2472do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
2473 int fv_regnum)
2474{
2475 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
2476 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2477 fv_regnum - FV0_REGNUM,
2478 (int) read_register (first_fp_reg_num),
2479 (int) read_register (first_fp_reg_num + 1),
2480 (int) read_register (first_fp_reg_num + 2),
2481 (int) read_register (first_fp_reg_num + 3));
2482}
2483
2484/* Floating point vector of 4 float registers, compact mode. */
2485static void
2486do_fv_c_register_info (int fv_regnum)
2487{
2488 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
2489 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2490 fv_regnum - FV0_C_REGNUM,
2491 (int) read_register (first_fp_reg_num),
2492 (int) read_register (first_fp_reg_num + 1),
2493 (int) read_register (first_fp_reg_num + 2),
2494 (int) read_register (first_fp_reg_num + 3));
2495}
2496
2497/* Pairs of single regs. The DR are instead double precision
2498 registers. */
2499static void
2500do_fpp_register_info (int fpp_regnum)
2501{
2502 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
2503
2504 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
2505 fpp_regnum - FPP0_REGNUM,
2506 (int) read_register (first_fp_reg_num),
2507 (int) read_register (first_fp_reg_num + 1));
2508}
2509
2510/* Double precision registers. */
2511static void
2512do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
2513 int dr_regnum)
2514{
2515 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
2516
2517 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
2518 dr_regnum - DR0_REGNUM,
2519 (int) read_register (first_fp_reg_num),
2520 (int) read_register (first_fp_reg_num + 1));
2521}
2522
2523/* Double precision registers, compact mode. */
2524static void
2525do_dr_c_register_info (int dr_regnum)
2526{
2527 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
2528
2529 printf_filtered ("dr%d_c\t0x%08x%08x\n",
2530 dr_regnum - DR0_C_REGNUM,
2531 (int) read_register (first_fp_reg_num),
2532 (int) read_register (first_fp_reg_num +1));
2533}
2534
2535/* General register in compact mode. */
2536static void
2537do_r_c_register_info (int r_c_regnum)
2538{
2539 int regnum = sh64_compact_reg_base_num (r_c_regnum);
2540
2541 printf_filtered ("r%d_c\t0x%08x\n",
2542 r_c_regnum - R0_C_REGNUM,
2543 /*FIXME!!!*/ (int) read_register (regnum));
2544}
2545
2546/* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
2547 shmedia REGISTERS. */
2548/* Control registers, compact mode. */
2549static void
2550do_cr_c_register_info (int cr_c_regnum)
2551{
2552 switch (cr_c_regnum)
2553 {
2554 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2555 break;
2556 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2557 break;
2558 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2559 break;
2560 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2561 break;
2562 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2563 break;
2564 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2565 break;
2566 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2567 break;
2568 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
2569 break;
2570 }
2571}
2572
2573static void
2574sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2575{ /* do values for FP (float) regs */
2576 char *raw_buffer;
2577 double flt; /* double extracted from raw hex data */
2578 int inv;
2579 int j;
2580
2581 /* Allocate space for the float. */
2582 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
2583
2584 /* Get the data in raw format. */
2585 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2586 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
2587
2588 /* Get the register as a number */
2589 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
2590
2591 /* Print the name and some spaces. */
2592 fputs_filtered (REGISTER_NAME (regnum), file);
2593 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2594
2595 /* Print the value. */
2596 if (inv)
2597 fprintf_filtered (file, "<invalid float>");
2598 else
2599 fprintf_filtered (file, "%-10.9g", flt);
2600
2601 /* Print the fp register as hex. */
2602 fprintf_filtered (file, "\t(raw 0x");
2603 for (j = 0; j < register_size (gdbarch, regnum); j++)
2604 {
aa1ee363 2605 int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
55ff77ac
CV		 2606 : register_size (gdbarch, regnum) - 1 - j;
2607 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
2608 }
2609 fprintf_filtered (file, ")");
2610 fprintf_filtered (file, "\n");
2611}
2612
2613static void
2614sh64_do_pseudo_register (int regnum)
2615{
2616 /* All the sh64-compact mode registers are pseudo registers. */
2617 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2618
2619 if (regnum < NUM_REGS
2620 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
2621 internal_error (__FILE__, __LINE__,
2622 "Invalid pseudo register number %d\n", regnum);
2623
2624 else if ((regnum >= DR0_REGNUM
2625 && regnum <= DR_LAST_REGNUM))
2626 do_dr_register_info (current_gdbarch, gdb_stdout, regnum);
2627
2628 else if ((regnum >= DR0_C_REGNUM
2629 && regnum <= DR_LAST_C_REGNUM))
2630 do_dr_c_register_info (regnum);
2631
2632 else if ((regnum >= FV0_REGNUM
2633 && regnum <= FV_LAST_REGNUM))
2634 do_fv_register_info (current_gdbarch, gdb_stdout, regnum);
2635
2636 else if ((regnum >= FV0_C_REGNUM
2637 && regnum <= FV_LAST_C_REGNUM))
2638 do_fv_c_register_info (regnum);
2639
2640 else if (regnum >= FPP0_REGNUM
2641 && regnum <= FPP_LAST_REGNUM)
2642 do_fpp_register_info (regnum);
2643
2644 else if (regnum >= R0_C_REGNUM
2645 && regnum <= R_LAST_C_REGNUM)
2646 do_r_c_register_info (regnum); /* FIXME, this function will not print the right format */
2647
2648 else if (regnum >= FP0_C_REGNUM
2649 && regnum <= FP_LAST_C_REGNUM)
2650 sh_do_fp_register (current_gdbarch, gdb_stdout, regnum); /* this should work also for pseudoregs */
2651
2652 else if (regnum >= PC_C_REGNUM
2653 && regnum <= FPUL_C_REGNUM)
2654 do_cr_c_register_info (regnum);
2655
2656}
2657
2658static void
2659sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2660{
2661 char raw_buffer[MAX_REGISTER_SIZE];
2662
2663 fputs_filtered (REGISTER_NAME (regnum), file);
2664 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2665
2666 /* Get the data in raw format. */
2667 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2668 fprintf_filtered (file, "*value not available*\n");
2669
2670 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2671 file, 'x', 1, 0, Val_pretty_default);
2672 fprintf_filtered (file, "\t");
2673 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2674 file, 0, 1, 0, Val_pretty_default);
2675 fprintf_filtered (file, "\n");
2676}
2677
2678static void
2679sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2680{
2681 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
2682 internal_error (__FILE__, __LINE__,
2683 "Invalid register number %d\n", regnum);
2684
2685 else if (regnum >= 0 && regnum < NUM_REGS)
2686 {
2687 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2688 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2689 else
2690 sh_do_register (gdbarch, file, regnum); /* All other regs */
2691 }
2692
2693 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2694 sh64_do_pseudo_register (regnum);
2695}
2696
2697static void
2698sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2699 struct frame_info *frame, int regnum, int fpregs)
2700{
2701 if (regnum != -1) /* do one specified register */
2702 {
2703 if (*(REGISTER_NAME (regnum)) == '\0')
2704 error ("Not a valid register for the current processor type");
2705
2706 sh_print_register (gdbarch, file, regnum);
2707 }
2708 else
2709 /* do all (or most) registers */
2710 {
2711 regnum = 0;
2712 while (regnum < NUM_REGS)
2713 {
2714 /* If the register name is empty, it is undefined for this
2715 processor, so don't display anything. */
2716 if (REGISTER_NAME (regnum) == NULL
2717 || *(REGISTER_NAME (regnum)) == '\0')
2718 {
2719 regnum++;
2720 continue;
2721 }
2722
2723 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2724 {
2725 if (fpregs)
2726 {
2727 /* true for "INFO ALL-REGISTERS" command */
2728 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2729 regnum ++;
2730 }
2731 else
2732 regnum += FP_LAST_REGNUM - FP0_REGNUM; /* skip FP regs */
2733 }
2734 else
2735 {
2736 sh_do_register (gdbarch, file, regnum); /* All other regs */
2737 regnum++;
2738 }
2739 }
2740
2741 if (fpregs)
2742 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2743 {
2744 sh64_do_pseudo_register (regnum);
2745 regnum++;
2746 }
2747 }
2748}
2749
2750static void
2751sh_compact_do_registers_info (int regnum, int fpregs)
2752{
2753 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2754 if (regnum != -1) /* do one specified register */
2755 {
2756 if (*(REGISTER_NAME (regnum)) == '\0')
2757 error ("Not a valid register for the current processor type");
2758
2759 if (regnum >= 0 && regnum < R0_C_REGNUM)
2760 error ("Not a valid register for the current processor mode.");
2761
2762 sh_print_register (current_gdbarch, gdb_stdout, regnum);
2763 }
2764 else
2765 /* do all compact registers */
2766 {
2767 regnum = R0_C_REGNUM;
2768 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2769 {
2770 sh64_do_pseudo_register (regnum);
2771 regnum++;
2772 }
2773 }
2774}
2775
2776static void
2777sh64_do_registers_info (int regnum, int fpregs)
2778{
2779 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
2780 sh_print_registers_info (current_gdbarch, gdb_stdout,
2781 deprecated_selected_frame, regnum, fpregs);
2782 else
2783 sh_compact_do_registers_info (regnum, fpregs);
2784}
2785
2786#ifdef SVR4_SHARED_LIBS
2787
2788/* Fetch (and possibly build) an appropriate link_map_offsets structure
2789 for native i386 linux targets using the struct offsets defined in
2790 link.h (but without actual reference to that file).
2791
2792 This makes it possible to access i386-linux shared libraries from
2793 a gdb that was not built on an i386-linux host (for cross debugging).
2794 */
2795
2796struct link_map_offsets *
2797sh_linux_svr4_fetch_link_map_offsets (void)
2798{
2799 static struct link_map_offsets lmo;
2800 static struct link_map_offsets *lmp = 0;
2801
2802 if (lmp == 0)
2803 {
2804 lmp = &lmo;
2805
2806 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
2807
2808 lmo.r_map_offset = 4;
2809 lmo.r_map_size = 4;
2810
2811 lmo.link_map_size = 20; /* 552 not actual size but all we need */
2812
2813 lmo.l_addr_offset = 0;
2814 lmo.l_addr_size = 4;
2815
2816 lmo.l_name_offset = 4;
2817 lmo.l_name_size = 4;
2818
2819 lmo.l_next_offset = 12;
2820 lmo.l_next_size = 4;
2821
2822 lmo.l_prev_offset = 16;
2823 lmo.l_prev_size = 4;
2824 }
2825
2826 return lmp;
2827}
2828#endif /* SVR4_SHARED_LIBS */
2829
2830gdbarch_init_ftype sh64_gdbarch_init;
2831
2832struct gdbarch *
2833sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2834{
2835 static LONGEST sh64_call_dummy_words[] = {0};
2836 struct gdbarch *gdbarch;
2837 struct gdbarch_tdep *tdep;
2838
2839 /* If there is already a candidate, use it. */
2840 arches = gdbarch_list_lookup_by_info (arches, &info);
2841 if (arches != NULL)
2842 return arches->gdbarch;
2843
2844 /* None found, create a new architecture from the information
2845 provided. */
2846 tdep = XMALLOC (struct gdbarch_tdep);
2847 gdbarch = gdbarch_alloc (&info, tdep);
2848
2849 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
2850 ready to unwind the PC first (see frame.c:get_prev_frame()). */
0968aa8c 2851 set_gdbarch_deprecated_init_frame_pc (gdbarch, deprecated_init_frame_pc_default);
55ff77ac
CV		 2852
2853 /* Determine the ABI */
2854 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2855 {
2856 /* If the ABI is the 64-bit one, it can only be sh-media. */
2857 tdep->sh_abi = SH_ABI_64;
2858 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2859 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2860 }
2861 else
2862 {
2863 /* If the ABI is the 32-bit one it could be either media or
2864 compact. */
2865 tdep->sh_abi = SH_ABI_32;
2866 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2867 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2868 }
2869
2870 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2871 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2872 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2873 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2874 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2875 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2876
2877 set_gdbarch_sp_regnum (gdbarch, 15);
2878 set_gdbarch_deprecated_fp_regnum (gdbarch, 14);
2879
2880 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2881 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2882
2883 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2884
2885 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2886 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2887 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2888 set_gdbarch_function_start_offset (gdbarch, 0);
2889
2890 set_gdbarch_frame_args_skip (gdbarch, 0);
2891 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
2892 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2893
2894 set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc);
2895 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
2896 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2897
2898 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
2899 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2900 set_gdbarch_pc_regnum (gdbarch, 64);
2901
2902 /* the number of real registers is the same whether we are in
2903 ISA16(compact) or ISA32(media). */
2904 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
2905 set_gdbarch_deprecated_register_size (gdbarch, 8); /*????*/
2906 set_gdbarch_deprecated_register_bytes (gdbarch,
2907 ((SIM_SH64_NR_FP_REGS + 1) * 4)
2908 + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8);
2909
2910 set_gdbarch_register_name (gdbarch, sh_sh64_register_name);
2911 set_gdbarch_deprecated_register_virtual_type (gdbarch, sh_sh64_register_virtual_type);
2912 set_gdbarch_deprecated_store_return_value (gdbarch, sh64_store_return_value);
2913 set_gdbarch_deprecated_register_raw_size (gdbarch, sh_sh64_register_raw_size);
2914 set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_sh64_register_raw_size);
2915 set_gdbarch_deprecated_register_byte (gdbarch, sh_sh64_register_byte);
2916 /* This seems awfully wrong!*/
2917 /*set_gdbarch_deprecated_max_register_raw_size (gdbarch, 8);*/
2918 /* should include the size of the pseudo regs. */
2919 set_gdbarch_deprecated_max_register_raw_size (gdbarch, 4 * 4);
2920 /* Or should that go in the virtual_size? */
2921 /*set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 8);*/
2922 set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 4 * 4);
2923 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2924 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2925
2926 set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info);
2927 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
2928 set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc);
2929 set_gdbarch_deprecated_call_dummy_words (gdbarch, sh64_call_dummy_words);
2930 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (sh64_call_dummy_words));
2931
2932 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
2933 set_gdbarch_deprecated_frame_chain (gdbarch, sh64_frame_chain);
2934 set_gdbarch_deprecated_get_saved_register (gdbarch, sh64_get_saved_register);
2935 set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value);
2936 set_gdbarch_deprecated_push_arguments (gdbarch, sh64_push_arguments);
2937 set_gdbarch_deprecated_push_return_address (gdbarch, sh64_push_return_address);
2938 set_gdbarch_deprecated_dummy_write_sp (gdbarch, deprecated_write_sp);
2939 set_gdbarch_deprecated_store_struct_return (gdbarch, sh64_store_struct_return);
2940 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
2941 set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention);
2942 set_gdbarch_deprecated_pop_frame (gdbarch, sh64_pop_frame);
2943 set_gdbarch_elf_make_msymbol_special (gdbarch,
2944 sh64_elf_make_msymbol_special);
2945
2946 /* Hook in ABI-specific overrides, if they have been registered. */
2947 gdbarch_init_osabi (info, gdbarch);
2948
2949 return gdbarch;
2950}
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