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a055a187 L |
1 | /* Helper file for i386 platform. Runtime check for MMX/SSE/SSE2/AVX |
2 | * support. Copied from gcc 4.4. | |
3 | * | |
28e7fd62 | 4 | * Copyright (C) 2007-2013 Free Software Foundation, Inc. |
a055a187 L |
5 | * |
6 | * This file is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 3, or (at your option) any | |
9 | * later version. | |
10 | * | |
11 | * This file is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * Under Section 7 of GPL version 3, you are granted additional | |
17 | * permissions described in the GCC Runtime Library Exception, version | |
18 | * 3.1, as published by the Free Software Foundation. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License and | |
21 | * a copy of the GCC Runtime Library Exception along with this program; | |
22 | * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
23 | * <http://www.gnu.org/licenses/>. | |
24 | */ | |
83ecb59f | 25 | |
a055a187 L |
26 | /* %ecx */ |
27 | #define bit_SSE3 (1 << 0) | |
28 | #define bit_PCLMUL (1 << 1) | |
29 | #define bit_SSSE3 (1 << 9) | |
30 | #define bit_FMA (1 << 12) | |
31 | #define bit_CMPXCHG16B (1 << 13) | |
32 | #define bit_SSE4_1 (1 << 19) | |
33 | #define bit_SSE4_2 (1 << 20) | |
34 | #define bit_MOVBE (1 << 22) | |
35 | #define bit_POPCNT (1 << 23) | |
36 | #define bit_AES (1 << 25) | |
37 | #define bit_XSAVE (1 << 26) | |
38 | #define bit_OSXSAVE (1 << 27) | |
39 | #define bit_AVX (1 << 28) | |
83ecb59f | 40 | |
a055a187 L |
41 | /* %edx */ |
42 | #define bit_CMPXCHG8B (1 << 8) | |
43 | #define bit_CMOV (1 << 15) | |
44 | #define bit_MMX (1 << 23) | |
45 | #define bit_FXSAVE (1 << 24) | |
46 | #define bit_SSE (1 << 25) | |
47 | #define bit_SSE2 (1 << 26) | |
83ecb59f | 48 | |
a055a187 L |
49 | /* Extended Features */ |
50 | /* %ecx */ | |
51 | #define bit_LAHF_LM (1 << 0) | |
52 | #define bit_ABM (1 << 5) | |
53 | #define bit_SSE4a (1 << 6) | |
54 | #define bit_XOP (1 << 11) | |
55 | #define bit_LWP (1 << 15) | |
56 | #define bit_FMA4 (1 << 16) | |
a9762ec7 | 57 | |
a055a187 L |
58 | /* %edx */ |
59 | #define bit_LM (1 << 29) | |
60 | #define bit_3DNOWP (1 << 30) | |
61 | #define bit_3DNOW (1 << 31) | |
a9762ec7 | 62 | |
83ecb59f | 63 | |
a055a187 L |
64 | #if defined(__i386__) && defined(__PIC__) |
65 | /* %ebx may be the PIC register. */ | |
66 | #if __GNUC__ >= 3 | |
67 | #define __cpuid(level, a, b, c, d) \ | |
68 | __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \ | |
69 | "cpuid\n\t" \ | |
70 | "xchg{l}\t{%%}ebx, %1\n\t" \ | |
71 | : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ | |
72 | : "0" (level)) | |
83ecb59f | 73 | |
a055a187 L |
74 | #define __cpuid_count(level, count, a, b, c, d) \ |
75 | __asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \ | |
76 | "cpuid\n\t" \ | |
77 | "xchg{l}\t{%%}ebx, %1\n\t" \ | |
78 | : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ | |
79 | : "0" (level), "2" (count)) | |
80 | #else | |
81 | /* Host GCCs older than 3.0 weren't supporting Intel asm syntax | |
82 | nor alternatives in i386 code. */ | |
83 | #define __cpuid(level, a, b, c, d) \ | |
84 | __asm__ ("xchgl\t%%ebx, %1\n\t" \ | |
85 | "cpuid\n\t" \ | |
86 | "xchgl\t%%ebx, %1\n\t" \ | |
87 | : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ | |
88 | : "0" (level)) | |
83ecb59f | 89 | |
a055a187 L |
90 | #define __cpuid_count(level, count, a, b, c, d) \ |
91 | __asm__ ("xchgl\t%%ebx, %1\n\t" \ | |
92 | "cpuid\n\t" \ | |
93 | "xchgl\t%%ebx, %1\n\t" \ | |
94 | : "=a" (a), "=r" (b), "=c" (c), "=d" (d) \ | |
95 | : "0" (level), "2" (count)) | |
83ecb59f | 96 | #endif |
a055a187 L |
97 | #else |
98 | #define __cpuid(level, a, b, c, d) \ | |
99 | __asm__ ("cpuid\n\t" \ | |
100 | : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ | |
101 | : "0" (level)) | |
83ecb59f | 102 | |
a055a187 L |
103 | #define __cpuid_count(level, count, a, b, c, d) \ |
104 | __asm__ ("cpuid\n\t" \ | |
105 | : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ | |
106 | : "0" (level), "2" (count)) | |
107 | #endif | |
83ecb59f | 108 | |
a055a187 L |
109 | /* Return highest supported input value for cpuid instruction. ext can |
110 | be either 0x0 or 0x8000000 to return highest supported value for | |
111 | basic or extended cpuid information. Function returns 0 if cpuid | |
112 | is not supported or whatever cpuid returns in eax register. If sig | |
113 | pointer is non-null, then first four bytes of the signature | |
114 | (as found in ebx register) are returned in location pointed by sig. */ | |
115 | ||
116 | static __inline unsigned int | |
117 | __get_cpuid_max (unsigned int __ext, unsigned int *__sig) | |
83ecb59f | 118 | { |
a055a187 | 119 | unsigned int __eax, __ebx, __ecx, __edx; |
83ecb59f JB |
120 | |
121 | #ifndef __x86_64__ | |
a055a187 | 122 | #if __GNUC__ >= 3 |
83ecb59f | 123 | /* See if we can use cpuid. On AMD64 we always can. */ |
a055a187 L |
124 | __asm__ ("pushf{l|d}\n\t" |
125 | "pushf{l|d}\n\t" | |
126 | "pop{l}\t%0\n\t" | |
127 | "mov{l}\t{%0, %1|%1, %0}\n\t" | |
128 | "xor{l}\t{%2, %0|%0, %2}\n\t" | |
129 | "push{l}\t%0\n\t" | |
130 | "popf{l|d}\n\t" | |
131 | "pushf{l|d}\n\t" | |
132 | "pop{l}\t%0\n\t" | |
133 | "popf{l|d}\n\t" | |
134 | : "=&r" (__eax), "=&r" (__ebx) | |
135 | : "i" (0x00200000)); | |
136 | #else | |
137 | /* Host GCCs older than 3.0 weren't supporting Intel asm syntax | |
138 | nor alternatives in i386 code. */ | |
139 | __asm__ ("pushfl\n\t" | |
140 | "pushfl\n\t" | |
141 | "popl\t%0\n\t" | |
142 | "movl\t%0, %1\n\t" | |
143 | "xorl\t%2, %0\n\t" | |
144 | "pushl\t%0\n\t" | |
145 | "popfl\n\t" | |
146 | "pushfl\n\t" | |
147 | "popl\t%0\n\t" | |
148 | "popfl\n\t" | |
149 | : "=&r" (__eax), "=&r" (__ebx) | |
83ecb59f | 150 | : "i" (0x00200000)); |
83ecb59f JB |
151 | #endif |
152 | ||
a055a187 L |
153 | if (!((__eax ^ __ebx) & 0x00200000)) |
154 | return 0; | |
83ecb59f | 155 | #endif |
a055a187 L |
156 | |
157 | /* Host supports cpuid. Return highest supported cpuid input value. */ | |
158 | __cpuid (__ext, __eax, __ebx, __ecx, __edx); | |
159 | ||
160 | if (__sig) | |
161 | *__sig = __ebx; | |
162 | ||
163 | return __eax; | |
164 | } | |
165 | ||
166 | /* Return cpuid data for requested cpuid level, as found in returned | |
167 | eax, ebx, ecx and edx registers. The function checks if cpuid is | |
168 | supported and returns 1 for valid cpuid information or 0 for | |
169 | unsupported cpuid level. All pointers are required to be non-null. */ | |
170 | ||
171 | static __inline int | |
172 | __get_cpuid (unsigned int __level, | |
173 | unsigned int *__eax, unsigned int *__ebx, | |
174 | unsigned int *__ecx, unsigned int *__edx) | |
175 | { | |
176 | unsigned int __ext = __level & 0x80000000; | |
177 | ||
178 | if (__get_cpuid_max (__ext, 0) < __level) | |
179 | return 0; | |
180 | ||
181 | __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx); | |
182 | return 1; | |
183 | } | |
184 | ||
185 | #ifndef NOINLINE | |
186 | #define NOINLINE __attribute__ ((noinline)) | |
83ecb59f JB |
187 | #endif |
188 | ||
a055a187 L |
189 | unsigned int i386_cpuid (void) NOINLINE; |
190 | ||
191 | unsigned int NOINLINE | |
192 | i386_cpuid (void) | |
193 | { | |
194 | unsigned int eax, ebx, ecx, edx; | |
195 | ||
196 | if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx)) | |
197 | return 0; | |
198 | ||
199 | return edx; | |
83ecb59f | 200 | } |