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42a4f53d | 1 | # Copyright (C) 2008-2019 Free Software Foundation, Inc. |
604c2f83 LM |
2 | # |
3 | # This program is free software; you can redistribute it and/or modify | |
4 | # it under the terms of the GNU General Public License as published by | |
5 | # the Free Software Foundation; either version 3 of the License, or | |
6 | # (at your option) any later version. | |
7 | # | |
8 | # This program is distributed in the hope that it will be useful, | |
9 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | # GNU General Public License for more details. | |
12 | # | |
13 | # You should have received a copy of the GNU General Public License | |
14 | # along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | # | |
604c2f83 | 16 | |
604c2f83 LM |
17 | # |
18 | # Test the use of VSX registers, for Powerpc. | |
19 | # | |
20 | ||
604c2f83 LM |
21 | |
22 | if {![istarget "powerpc*"] || [skip_vsx_tests]} then { | |
23 | verbose "Skipping vsx register tests." | |
604c2f83 LM |
24 | return |
25 | } | |
26 | ||
20c2c024 | 27 | standard_testfile |
604c2f83 LM |
28 | |
29 | set compile_flags {debug nowarnings quiet} | |
4c93b1db | 30 | if [get_compiler_info] { |
604c2f83 LM |
31 | warning "get_compiler failed" |
32 | return -1 | |
33 | } | |
34 | ||
35 | if [test_compiler_info gcc*] { | |
36 | set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec" | |
37 | } elseif [test_compiler_info xlc*] { | |
38 | set compile_flags "$compile_flags additional_flags=-qaltivec" | |
39 | } else { | |
40 | warning "unknown compiler" | |
41 | return -1 | |
42 | } | |
43 | ||
44 | if { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } { | |
5b362f04 | 45 | untested "failed to compile" |
604c2f83 LM |
46 | return -1 |
47 | } | |
48 | ||
49 | gdb_start | |
50 | gdb_reinitialize_dir $srcdir/$subdir | |
51 | gdb_load ${binfile} | |
52 | ||
53 | # Run to `main' where we begin our tests. | |
54 | ||
55 | if ![runto_main] then { | |
c8ee3f04 PW |
56 | fail "can't run to main" |
57 | return 0 | |
604c2f83 LM |
58 | } |
59 | ||
805acca0 | 60 | set endianness [get_endianness] |
084ee545 | 61 | |
604c2f83 LM |
62 | # Data sets used throughout the test |
63 | ||
084ee545 | 64 | if {$endianness == "big"} { |
7a26362d | 65 | set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.." |
084ee545 | 66 | |
7a26362d | 67 | set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." |
4572cbac | 68 | |
7a26362d | 69 | set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." |
d9492458 | 70 | |
084ee545 | 71 | set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." |
604c2f83 | 72 | |
30a25466 | 73 | set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." |
084ee545 | 74 | |
30a25466 | 75 | set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." |
084ee545 | 76 | } else { |
7a26362d | 77 | set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x1., v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.." |
d9492458 | 78 | |
7a26362d | 79 | set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.." |
604c2f83 | 80 | |
7a26362d | 81 | set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.." |
084ee545 UW |
82 | |
83 | set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.." | |
84 | ||
30a25466 | 85 | set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." |
084ee545 | 86 | |
30a25466 | 87 | set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." |
084ee545 | 88 | } |
604c2f83 LM |
89 | |
90 | set float_register ".raw 0xdeadbeefdeadbeef." | |
91 | ||
92 | # First run the F0~F31/VS0~VS31 tests | |
93 | ||
94 | # 1: Set F0~F31 registers and check if it reflects on VS0~VS31. | |
95 | for {set i 0} {$i < 32} {incr i 1} { | |
4572cbac | 96 | gdb_test_no_output "set \$f$i = 1\.3" |
604c2f83 LM |
97 | } |
98 | ||
99 | for {set i 0} {$i < 32} {incr i 1} { | |
100 | gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)" | |
101 | } | |
102 | ||
103 | # 2: Set VS0~VS31 registers and check if it reflects on F0~F31. | |
104 | for {set i 0} {$i < 32} {incr i 1} { | |
105 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 106 | gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef" |
604c2f83 LM |
107 | } |
108 | } | |
109 | ||
110 | for {set i 0} {$i < 32} {incr i 1} { | |
111 | gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i" | |
112 | } | |
113 | ||
114 | for {set i 0} {$i < 32} {incr i 1} { | |
115 | gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)" | |
116 | } | |
117 | ||
118 | # Now run the VR0~VR31/VS32~VS63 tests | |
119 | ||
120 | # 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63. | |
121 | for {set i 0} {$i < 32} {incr i 1} { | |
122 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 123 | gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1" |
604c2f83 LM |
124 | } |
125 | } | |
126 | ||
127 | for {set i 32} {$i < 64} {incr i 1} { | |
128 | gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i" | |
129 | } | |
130 | # 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31. | |
131 | for {set i 32} {$i < 64} {incr i 1} { | |
132 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 133 | gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1" |
604c2f83 LM |
134 | } |
135 | } | |
136 | ||
137 | for {set i 0} {$i < 32} {incr i 1} { | |
4572cbac | 138 | gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i" |
604c2f83 LM |
139 | } |
140 | ||
d9492458 TJB |
141 | # Create a core file. We create the core file before the F32~F63/VR0~VR31 test |
142 | # below because then we'll have more interesting register values to verify | |
143 | # later when loading the core file (i.e., different register values for different | |
144 | # vector register banks). | |
145 | ||
16c85b5d | 146 | set corefile [standard_output_file vsx-core.test] |
fac51dd9 | 147 | set core_supported [gdb_gcore_cmd "$corefile" "Save a VSX-enabled corefile"] |
604c2f83 | 148 | |
d9492458 TJB |
149 | # Now run the F32~F63/VR0~VR31 tests. |
150 | ||
151 | # 1: Set F32~F63 registers and check if it reflects on VR0~VR31. | |
152 | for {set i 32} {$i < 64} {incr i 1} { | |
153 | gdb_test_no_output "set \$f$i = 1\.3" | |
154 | } | |
155 | ||
156 | for {set i 0} {$i < 32} {incr i 1} { | |
157 | gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)" | |
158 | } | |
159 | ||
160 | # 2: Set VR0~VR31 registers and check if it reflects on F32~F63. | |
161 | for {set i 0} {$i < 32} {incr i 1} { | |
162 | for {set j 0} {$j < 4} {incr j 1} { | |
163 | gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef" | |
164 | } | |
165 | } | |
166 | ||
167 | for {set i 32} {$i < 64} {incr i 1} { | |
168 | gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i" | |
169 | } | |
170 | ||
171 | for {set i 0} {$i < 32} {incr i 1} { | |
172 | gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)" | |
173 | } | |
174 | ||
175 | # Test reading the core file. | |
176 | ||
604c2f83 LM |
177 | if {!$core_supported} { |
178 | return -1 | |
179 | } | |
180 | ||
181 | gdb_exit | |
182 | gdb_start | |
183 | gdb_reinitialize_dir $srcdir/$subdir | |
184 | gdb_load ${binfile} | |
185 | ||
fac51dd9 DE |
186 | set core_loaded [gdb_core_cmd "$corefile" "re-load generated corefile"] |
187 | if { $core_loaded == -1 } { | |
188 | # No use proceeding from here. | |
189 | return | |
604c2f83 LM |
190 | } |
191 | ||
192 | for {set i 0} {$i < 32} {incr i 1} { | |
cdc7edd7 | 193 | gdb_test "info reg vs$i" "vs$i.*$vector_register2" "restore vs$i from core file" |
604c2f83 LM |
194 | } |
195 | ||
196 | for {set i 32} {$i < 64} {incr i 1} { | |
cdc7edd7 | 197 | gdb_test "info reg vs$i" "vs$i.*$vector_register3" "restore vs$i from core file" |
604c2f83 | 198 | } |