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gdbserver/linux-low: turn 'arch_setup' into a method
[thirdparty/binutils-gdb.git] / gdbserver / linux-ppc-low.cc
CommitLineData
0a30fbc4
DJ		 1/* GNU/Linux/PowerPC specific low level interface, for the remote server for
2 GDB.
b811d2c2 3 Copyright (C) 1995-2020 Free Software Foundation, Inc.
0a30fbc4
DJ		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
0a30fbc4
DJ		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
0a30fbc4
DJ		 19
20#include "server.h"
58caa3dc 21#include "linux-low.h"
0a30fbc4 22
7ca18ed6
EBM		 23#include "elf/common.h"
24#include <sys/uio.h>
b6430ec3 25#include <elf.h>
0a30fbc4
DJ		 26#include <asm/ptrace.h>
27
bd64614e
PFC		 28#include "arch/ppc-linux-common.h"
29#include "arch/ppc-linux-tdesc.h"
514c5338 30#include "nat/ppc-linux.h"
64f57f3d 31#include "nat/linux-ptrace.h"
bd64614e 32#include "linux-ppc-tdesc-init.h"
a2174ba4
MK		 33#include "ax.h"
34#include "tracepoint.h"
35
36#define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38#define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42#define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43#define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44#define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45#define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
b6430ec3 46
ef0478f6
TBA		 47/* Linux target op definitions for the PowerPC architecture. */
48
49class ppc_target : public linux_process_target
50{
51public:
52
797bcff5
TBA		 53protected:
54
55 void low_arch_setup () override;
ef0478f6
TBA		 56};
57
58/* The singleton target ops object. */
59
60static ppc_target the_ppc_target;
61
7ca18ed6
EBM		 62/* Holds the AT_HWCAP auxv entry. */
63
b6430ec3
UW		 64static unsigned long ppc_hwcap;
65
7ca18ed6
EBM		 66/* Holds the AT_HWCAP2 auxv entry. */
67
68static unsigned long ppc_hwcap2;
69
b6430ec3 70
7284e1be
UW		 71#define ppc_num_regs 73
72
5b0a002e
UW		 73#ifdef __powerpc64__
74/* We use a constant for FPSCR instead of PT_FPSCR, because
75 many shipped PPC64 kernels had the wrong value in ptrace.h. */
76static int ppc_regmap[] =
77 {PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8,
78 PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8,
79 PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8,
80 PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8,
81 PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8,
82 PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8,
83 PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8,
84 PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8,
85 PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24,
86 PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56,
87 PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88,
88 PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120,
89 PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152,
90 PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184,
91 PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216,
92 PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248,
93 PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8,
7284e1be
UW		 94 PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256,
95 PT_ORIG_R3 * 8, PT_TRAP * 8 };
5b0a002e 96#else
0a30fbc4 97/* Currently, don't check/send MQ. */
2ec06d2e 98static int ppc_regmap[] =
0a30fbc4
DJ		 99 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
100 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
101 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
102 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
103 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
104 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
105 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
106 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
107 PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24,
108 PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56,
109 PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88,
110 PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120,
111 PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152,
112 PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184,
113 PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216,
114 PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248,
115 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 116 PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4,
117 PT_ORIG_R3 * 4, PT_TRAP * 4
b6430ec3
UW		 118 };
119
120static int ppc_regmap_e500[] =
121 {PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
122 PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
123 PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
124 PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
125 PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
126 PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
127 PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
128 PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
129 -1, -1, -1, -1,
130 -1, -1, -1, -1,
131 -1, -1, -1, -1,
132 -1, -1, -1, -1,
133 -1, -1, -1, -1,
134 -1, -1, -1, -1,
135 -1, -1, -1, -1,
136 -1, -1, -1, -1,
137 PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
7284e1be
UW		 138 PT_CTR * 4, PT_XER * 4, -1,
139 PT_ORIG_R3 * 4, PT_TRAP * 4
30ed0a8f 140 };
5b0a002e 141#endif
0a30fbc4 142
7ca18ed6
EBM		 143/* Check whether the kernel provides a register set with number
144 REGSET_ID of size REGSETSIZE for process/thread TID. */
145
146static int
147ppc_check_regset (int tid, int regset_id, int regsetsize)
148{
149 void *buf = alloca (regsetsize);
150 struct iovec iov;
151
152 iov.iov_base = buf;
153 iov.iov_len = regsetsize;
154
155 if (ptrace (PTRACE_GETREGSET, tid, regset_id, &iov) >= 0
156 || errno == ENODATA)
157 return 1;
158 return 0;
159}
160
2ec06d2e
DJ		 161static int
162ppc_cannot_store_register (int regno)
0a30fbc4 163{
3aee8918
PA		 164 const struct target_desc *tdesc = current_process ()->tdesc;
165
b6430ec3 166#ifndef __powerpc64__
bc1e36ca 167 /* Some kernels do not allow us to store fpscr. */
3aee8918
PA		 168 if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)
169 && regno == find_regno (tdesc, "fpscr"))
a5863204 170 return 1;
30ed0a8f 171#endif
bc1e36ca 172
7284e1be 173 /* Some kernels do not allow us to store orig_r3 or trap. */
3aee8918
PA		 174 if (regno == find_regno (tdesc, "orig_r3")
175 || regno == find_regno (tdesc, "trap"))
a5863204 176 return 1;
7284e1be 177
0a30fbc4
DJ		 178 return 0;
179}
180
2ec06d2e
DJ		 181static int
182ppc_cannot_fetch_register (int regno)
0a30fbc4
DJ		 183{
184 return 0;
185}
186
5b0a002e 187static void
442ea881 188ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
5b0a002e 189{
76b233dd
UW		 190 memset (buf, 0, sizeof (long));
191
2e4bb98a
EBM		 192 if (__BYTE_ORDER == __LITTLE_ENDIAN)
193 {
194 /* Little-endian values always sit at the left end of the buffer. */
195 collect_register (regcache, regno, buf);
196 }
197 else if (__BYTE_ORDER == __BIG_ENDIAN)
198 {
199 /* Big-endian values sit at the right end of the buffer. In case of
200 registers whose sizes are smaller than sizeof (long), we must use a
201 padding to access them correctly. */
202 int size = register_size (regcache->tdesc, regno);
203
204 if (size < sizeof (long))
205 collect_register (regcache, regno, buf + sizeof (long) - size);
206 else
207 collect_register (regcache, regno, buf);
208 }
5b0a002e 209 else
2e4bb98a 210 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 211}
212
213static void
442ea881
PA		 214ppc_supply_ptrace_register (struct regcache *regcache,
215 int regno, const char *buf)
5b0a002e 216{
2e4bb98a
EBM		 217 if (__BYTE_ORDER == __LITTLE_ENDIAN)
218 {
219 /* Little-endian values always sit at the left end of the buffer. */
220 supply_register (regcache, regno, buf);
221 }
222 else if (__BYTE_ORDER == __BIG_ENDIAN)
223 {
224 /* Big-endian values sit at the right end of the buffer. In case of
225 registers whose sizes are smaller than sizeof (long), we must use a
226 padding to access them correctly. */
227 int size = register_size (regcache->tdesc, regno);
228
229 if (size < sizeof (long))
230 supply_register (regcache, regno, buf + sizeof (long) - size);
231 else
232 supply_register (regcache, regno, buf);
233 }
5b0a002e 234 else
2e4bb98a 235 perror_with_name ("Unexpected byte order");
5b0a002e
UW		 236}
237
0d62e5e8 238static CORE_ADDR
442ea881 239ppc_get_pc (struct regcache *regcache)
0d62e5e8 240{
abf516c6 241 if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 242 {
243 unsigned int pc;
442ea881 244 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 245 return (CORE_ADDR) pc;
246 }
247 else
248 {
249 unsigned long pc;
442ea881 250 collect_register_by_name (regcache, "pc", &pc);
6fe305f7
UW		 251 return (CORE_ADDR) pc;
252 }
0d62e5e8
DJ		 253}
254
255static void
442ea881 256ppc_set_pc (struct regcache *regcache, CORE_ADDR pc)
0d62e5e8 257{
abf516c6 258 if (register_size (regcache->tdesc, 0) == 4)
6fe305f7
UW		 259 {
260 unsigned int newpc = pc;
442ea881 261 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 262 }
263 else
264 {
265 unsigned long newpc = pc;
442ea881 266 supply_register_by_name (regcache, "pc", &newpc);
6fe305f7
UW		 267 }
268}
269
3aee8918
PA		 270#ifndef __powerpc64__
271static int ppc_regmap_adjusted;
272#endif
273
0d62e5e8 274
5b0a002e 275/* Correct in either endianness.
0d62e5e8
DJ		 276 This instruction is "twge r2, r2", which GDB uses as a software
277 breakpoint. */
5b0a002e 278static const unsigned int ppc_breakpoint = 0x7d821008;
0d62e5e8
DJ		 279#define ppc_breakpoint_len 4
280
dd373349
AT		 281/* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */
282
283static const gdb_byte *
284ppc_sw_breakpoint_from_kind (int kind, int *size)
285{
286 *size = ppc_breakpoint_len;
287 return (const gdb_byte *) &ppc_breakpoint;
288}
289
0d62e5e8
DJ		 290static int
291ppc_breakpoint_at (CORE_ADDR where)
292{
5b0a002e 293 unsigned int insn;
0d62e5e8 294
52405d85 295 the_target->read_memory (where, (unsigned char *) &insn, 4);
abf516c6
UW		 296 if (insn == ppc_breakpoint)
297 return 1;
298 /* If necessary, recognize more trap instructions here. GDB only uses
299 the one. */
0b9ff2c0 300
0d62e5e8
DJ		 301 return 0;
302}
303
657f9cde
WW		 304/* Implement supports_z_point_type target-ops.
305 Returns true if type Z_TYPE breakpoint is supported.
306
307 Handling software breakpoint at server side, so tracepoints
308 and breakpoints can be inserted at the same location. */
309
310static int
311ppc_supports_z_point_type (char z_type)
312{
313 switch (z_type)
314 {
315 case Z_PACKET_SW_BP:
316 return 1;
317 case Z_PACKET_HW_BP:
318 case Z_PACKET_WRITE_WP:
319 case Z_PACKET_ACCESS_WP:
320 default:
321 return 0;
322 }
323}
324
325/* Implement insert_point target-ops.
326 Returns 0 on success, -1 on failure and 1 on unsupported. */
327
328static int
329ppc_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
330 int size, struct raw_breakpoint *bp)
331{
332 switch (type)
333 {
334 case raw_bkpt_type_sw:
335 return insert_memory_breakpoint (bp);
336
337 case raw_bkpt_type_hw:
338 case raw_bkpt_type_write_wp:
339 case raw_bkpt_type_access_wp:
340 default:
341 /* Unsupported. */
342 return 1;
343 }
344}
345
346/* Implement remove_point target-ops.
347 Returns 0 on success, -1 on failure and 1 on unsupported. */
348
349static int
350ppc_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
351 int size, struct raw_breakpoint *bp)
352{
353 switch (type)
354 {
355 case raw_bkpt_type_sw:
356 return remove_memory_breakpoint (bp);
357
358 case raw_bkpt_type_hw:
359 case raw_bkpt_type_write_wp:
360 case raw_bkpt_type_access_wp:
361 default:
362 /* Unsupported. */
363 return 1;
364 }
365}
366
e9d25b98
DJ		 367/* Provide only a fill function for the general register set. ps_lgetregs
368 will use this for NPTL support. */
369
442ea881 370static void ppc_fill_gregset (struct regcache *regcache, void *buf)
e9d25b98
DJ		 371{
372 int i;
373
374 for (i = 0; i < 32; i++)
442ea881 375 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 376
377 for (i = 64; i < 70; i++)
442ea881 378 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
7284e1be
UW		 379
380 for (i = 71; i < 73; i++)
442ea881 381 ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
e9d25b98
DJ		 382}
383
7ca18ed6
EBM		 384/* Program Priority Register regset fill function. */
385
386static void
387ppc_fill_pprregset (struct regcache *regcache, void *buf)
388{
389 char *ppr = (char *) buf;
390
391 collect_register_by_name (regcache, "ppr", ppr);
392}
393
394/* Program Priority Register regset store function. */
395
396static void
397ppc_store_pprregset (struct regcache *regcache, const void *buf)
398{
399 const char *ppr = (const char *) buf;
400
401 supply_register_by_name (regcache, "ppr", ppr);
402}
403
404/* Data Stream Control Register regset fill function. */
405
406static void
407ppc_fill_dscrregset (struct regcache *regcache, void *buf)
408{
409 char *dscr = (char *) buf;
410
411 collect_register_by_name (regcache, "dscr", dscr);
412}
413
414/* Data Stream Control Register regset store function. */
415
416static void
417ppc_store_dscrregset (struct regcache *regcache, const void *buf)
418{
419 const char *dscr = (const char *) buf;
420
421 supply_register_by_name (regcache, "dscr", dscr);
422}
423
f2cf6173
EBM		 424/* Target Address Register regset fill function. */
425
426static void
427ppc_fill_tarregset (struct regcache *regcache, void *buf)
428{
429 char *tar = (char *) buf;
430
431 collect_register_by_name (regcache, "tar", tar);
432}
433
434/* Target Address Register regset store function. */
435
436static void
437ppc_store_tarregset (struct regcache *regcache, const void *buf)
438{
439 const char *tar = (const char *) buf;
440
441 supply_register_by_name (regcache, "tar", tar);
442}
443
232bfb86
EBM		 444/* Event-Based Branching regset store function. Unless the inferior
445 has a perf event open, ptrace can return in error when reading and
446 writing to the regset, with ENODATA. For reading, the registers
447 will correctly show as unavailable. For writing, gdbserver
448 currently only caches any register writes from P and G packets and
449 the stub always tries to write all the regsets when resuming the
450 inferior, which would result in frequent warnings. For this
451 reason, we don't define a fill function. This also means that the
452 client-side regcache will be dirty if the user tries to write to
453 the EBB registers. G packets that the client sends to write to
454 unrelated registers will also include data for EBB registers, even
455 if they are unavailable. */
456
457static void
458ppc_store_ebbregset (struct regcache *regcache, const void *buf)
459{
460 const char *regset = (const char *) buf;
461
462 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
463 .dat file is BESCR, EBBHR, EBBRR. */
464 supply_register_by_name (regcache, "ebbrr", &regset[0]);
465 supply_register_by_name (regcache, "ebbhr", &regset[8]);
466 supply_register_by_name (regcache, "bescr", &regset[16]);
467}
468
469/* Performance Monitoring Unit regset fill function. */
470
471static void
472ppc_fill_pmuregset (struct regcache *regcache, void *buf)
473{
474 char *regset = (char *) buf;
475
476 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
477 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
478 collect_register_by_name (regcache, "siar", &regset[0]);
479 collect_register_by_name (regcache, "sdar", &regset[8]);
480 collect_register_by_name (regcache, "sier", &regset[16]);
481 collect_register_by_name (regcache, "mmcr2", &regset[24]);
482 collect_register_by_name (regcache, "mmcr0", &regset[32]);
483}
484
485/* Performance Monitoring Unit regset store function. */
486
487static void
488ppc_store_pmuregset (struct regcache *regcache, const void *buf)
489{
490 const char *regset = (const char *) buf;
491
492 supply_register_by_name (regcache, "siar", &regset[0]);
493 supply_register_by_name (regcache, "sdar", &regset[8]);
494 supply_register_by_name (regcache, "sier", &regset[16]);
495 supply_register_by_name (regcache, "mmcr2", &regset[24]);
496 supply_register_by_name (regcache, "mmcr0", &regset[32]);
497}
498
8d619c01
EBM		 499/* Hardware Transactional Memory special-purpose register regset fill
500 function. */
501
502static void
503ppc_fill_tm_sprregset (struct regcache *regcache, void *buf)
504{
505 int i, base;
506 char *regset = (char *) buf;
507
508 base = find_regno (regcache->tdesc, "tfhar");
509 for (i = 0; i < 3; i++)
510 collect_register (regcache, base + i, &regset[i * 8]);
511}
512
513/* Hardware Transactional Memory special-purpose register regset store
514 function. */
515
516static void
517ppc_store_tm_sprregset (struct regcache *regcache, const void *buf)
518{
519 int i, base;
520 const char *regset = (const char *) buf;
521
522 base = find_regno (regcache->tdesc, "tfhar");
523 for (i = 0; i < 3; i++)
524 supply_register (regcache, base + i, &regset[i * 8]);
525}
526
527/* For the same reasons as the EBB regset, none of the HTM
528 checkpointed regsets have a fill function. These registers are
529 only available if the inferior is in a transaction. */
530
531/* Hardware Transactional Memory checkpointed general-purpose regset
532 store function. */
533
534static void
535ppc_store_tm_cgprregset (struct regcache *regcache, const void *buf)
536{
537 int i, base, size, endian_offset;
538 const char *regset = (const char *) buf;
539
540 base = find_regno (regcache->tdesc, "cr0");
541 size = register_size (regcache->tdesc, base);
542
543 gdb_assert (size == 4 || size == 8);
544
545 for (i = 0; i < 32; i++)
546 supply_register (regcache, base + i, &regset[i * size]);
547
548 endian_offset = 0;
549
550 if ((size == 8) && (__BYTE_ORDER == __BIG_ENDIAN))
551 endian_offset = 4;
552
553 supply_register_by_name (regcache, "ccr",
554 &regset[PT_CCR * size + endian_offset]);
555
556 supply_register_by_name (regcache, "cxer",
557 &regset[PT_XER * size + endian_offset]);
558
559 supply_register_by_name (regcache, "clr", &regset[PT_LNK * size]);
560 supply_register_by_name (regcache, "cctr", &regset[PT_CTR * size]);
561}
562
563/* Hardware Transactional Memory checkpointed floating-point regset
564 store function. */
565
566static void
567ppc_store_tm_cfprregset (struct regcache *regcache, const void *buf)
568{
569 int i, base;
570 const char *regset = (const char *) buf;
571
572 base = find_regno (regcache->tdesc, "cf0");
573
574 for (i = 0; i < 32; i++)
575 supply_register (regcache, base + i, &regset[i * 8]);
576
577 supply_register_by_name (regcache, "cfpscr", &regset[32 * 8]);
578}
579
580/* Hardware Transactional Memory checkpointed vector regset store
581 function. */
582
583static void
584ppc_store_tm_cvrregset (struct regcache *regcache, const void *buf)
585{
586 int i, base;
587 const char *regset = (const char *) buf;
588 int vscr_offset = 0;
589
590 base = find_regno (regcache->tdesc, "cvr0");
591
592 for (i = 0; i < 32; i++)
593 supply_register (regcache, base + i, &regset[i * 16]);
594
595 if (__BYTE_ORDER == __BIG_ENDIAN)
596 vscr_offset = 12;
597
598 supply_register_by_name (regcache, "cvscr",
599 &regset[32 * 16 + vscr_offset]);
600
601 supply_register_by_name (regcache, "cvrsave", &regset[33 * 16]);
602}
603
604/* Hardware Transactional Memory checkpointed vector-scalar regset
605 store function. */
606
607static void
608ppc_store_tm_cvsxregset (struct regcache *regcache, const void *buf)
609{
610 int i, base;
611 const char *regset = (const char *) buf;
612
613 base = find_regno (regcache->tdesc, "cvs0h");
614 for (i = 0; i < 32; i++)
615 supply_register (regcache, base + i, &regset[i * 8]);
616}
617
618/* Hardware Transactional Memory checkpointed Program Priority
619 Register regset store function. */
620
621static void
622ppc_store_tm_cpprregset (struct regcache *regcache, const void *buf)
623{
624 const char *cppr = (const char *) buf;
625
626 supply_register_by_name (regcache, "cppr", cppr);
627}
628
629/* Hardware Transactional Memory checkpointed Data Stream Control
630 Register regset store function. */
631
632static void
633ppc_store_tm_cdscrregset (struct regcache *regcache, const void *buf)
634{
635 const char *cdscr = (const char *) buf;
636
637 supply_register_by_name (regcache, "cdscr", cdscr);
638}
639
640/* Hardware Transactional Memory checkpointed Target Address Register
641 regset store function. */
642
643static void
644ppc_store_tm_ctarregset (struct regcache *regcache, const void *buf)
645{
646 const char *ctar = (const char *) buf;
647
648 supply_register_by_name (regcache, "ctar", ctar);
649}
650
677c5bb1 651static void
442ea881 652ppc_fill_vsxregset (struct regcache *regcache, void *buf)
677c5bb1
LM		 653{
654 int i, base;
2bc84e8a 655 char *regset = (char *) buf;
677c5bb1 656
3aee8918 657 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 658 for (i = 0; i < 32; i++)
442ea881 659 collect_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 660}
661
662static void
442ea881 663ppc_store_vsxregset (struct regcache *regcache, const void *buf)
677c5bb1
LM		 664{
665 int i, base;
2bc84e8a 666 const char *regset = (const char *) buf;
677c5bb1 667
3aee8918 668 base = find_regno (regcache->tdesc, "vs0h");
677c5bb1 669 for (i = 0; i < 32; i++)
442ea881 670 supply_register (regcache, base + i, &regset[i * 8]);
677c5bb1
LM		 671}
672
30ed0a8f 673static void
442ea881 674ppc_fill_vrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 675{
676 int i, base;
2bc84e8a 677 char *regset = (char *) buf;
1d75a658 678 int vscr_offset = 0;
30ed0a8f 679
3aee8918 680 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 681 for (i = 0; i < 32; i++)
442ea881 682 collect_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 683
1d75a658
PFC		 684 if (__BYTE_ORDER == __BIG_ENDIAN)
685 vscr_offset = 12;
686
1d75a658
PFC		 687 collect_register_by_name (regcache, "vscr",
688 &regset[32 * 16 + vscr_offset]);
689
442ea881 690 collect_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 691}
692
693static void
442ea881 694ppc_store_vrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 695{
696 int i, base;
2bc84e8a 697 const char *regset = (const char *) buf;
1d75a658 698 int vscr_offset = 0;
30ed0a8f 699
3aee8918 700 base = find_regno (regcache->tdesc, "vr0");
30ed0a8f 701 for (i = 0; i < 32; i++)
442ea881 702 supply_register (regcache, base + i, &regset[i * 16]);
30ed0a8f 703
1d75a658
PFC		 704 if (__BYTE_ORDER == __BIG_ENDIAN)
705 vscr_offset = 12;
706
707 supply_register_by_name (regcache, "vscr",
708 &regset[32 * 16 + vscr_offset]);
442ea881 709 supply_register_by_name (regcache, "vrsave", &regset[33 * 16]);
30ed0a8f
DJ		 710}
711
30ed0a8f
DJ		 712struct gdb_evrregset_t
713{
714 unsigned long evr[32];
715 unsigned long long acc;
716 unsigned long spefscr;
717};
718
719static void
442ea881 720ppc_fill_evrregset (struct regcache *regcache, void *buf)
30ed0a8f
DJ		 721{
722 int i, ev0;
2bc84e8a 723 struct gdb_evrregset_t *regset = (struct gdb_evrregset_t *) buf;
30ed0a8f 724
3aee8918 725 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 726 for (i = 0; i < 32; i++)
442ea881 727 collect_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 728
442ea881
PA		 729 collect_register_by_name (regcache, "acc", &regset->acc);
730 collect_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f
DJ		 731}
732
733static void
442ea881 734ppc_store_evrregset (struct regcache *regcache, const void *buf)
30ed0a8f
DJ		 735{
736 int i, ev0;
2bc84e8a 737 const struct gdb_evrregset_t *regset = (const struct gdb_evrregset_t *) buf;
30ed0a8f 738
3aee8918 739 ev0 = find_regno (regcache->tdesc, "ev0h");
30ed0a8f 740 for (i = 0; i < 32; i++)
442ea881 741 supply_register (regcache, ev0 + i, &regset->evr[i]);
30ed0a8f 742
442ea881
PA		 743 supply_register_by_name (regcache, "acc", &regset->acc);
744 supply_register_by_name (regcache, "spefscr", &regset->spefscr);
30ed0a8f 745}
30ed0a8f 746
7d00775e
AT		 747/* Support for hardware single step. */
748
749static int
750ppc_supports_hardware_single_step (void)
751{
752 return 1;
753}
754
3aee8918 755static struct regset_info ppc_regsets[] = {
30ed0a8f
DJ		 756 /* List the extra register sets before GENERAL_REGS. That way we will
757 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
758 general registers. Some kernels support these, but not the newer
759 PPC_PTRACE_GETREGS. */
8d619c01
EBM		 760 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CTAR, 0, EXTENDED_REGS,
761 NULL, ppc_store_tm_ctarregset },
762 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CDSCR, 0, EXTENDED_REGS,
763 NULL, ppc_store_tm_cdscrregset },
764 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CPPR, 0, EXTENDED_REGS,
765 NULL, ppc_store_tm_cpprregset },
766 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVSX, 0, EXTENDED_REGS,
767 NULL, ppc_store_tm_cvsxregset },
768 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CVMX, 0, EXTENDED_REGS,
769 NULL, ppc_store_tm_cvrregset },
770 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CFPR, 0, EXTENDED_REGS,
771 NULL, ppc_store_tm_cfprregset },
772 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_CGPR, 0, EXTENDED_REGS,
773 NULL, ppc_store_tm_cgprregset },
774 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TM_SPR, 0, EXTENDED_REGS,
775 ppc_fill_tm_sprregset, ppc_store_tm_sprregset },
232bfb86
EBM		 776 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_EBB, 0, EXTENDED_REGS,
777 NULL, ppc_store_ebbregset },
778 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PMU, 0, EXTENDED_REGS,
779 ppc_fill_pmuregset, ppc_store_pmuregset },
f2cf6173
EBM		 780 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS,
781 ppc_fill_tarregset, ppc_store_tarregset },
7ca18ed6
EBM		 782 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS,
783 ppc_fill_pprregset, ppc_store_pprregset },
784 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS,
785 ppc_fill_dscrregset, ppc_store_dscrregset },
7273b5fc 786 { PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, 0, EXTENDED_REGS,
677c5bb1 787 ppc_fill_vsxregset, ppc_store_vsxregset },
7273b5fc 788 { PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 789 ppc_fill_vrregset, ppc_store_vrregset },
7273b5fc 790 { PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 0, EXTENDED_REGS,
30ed0a8f 791 ppc_fill_evrregset, ppc_store_evrregset },
1570b33e 792 { 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL },
50bc912a 793 NULL_REGSET
e9d25b98
DJ		 794};
795
3aee8918
PA		 796static struct usrregs_info ppc_usrregs_info =
797 {
798 ppc_num_regs,
799 ppc_regmap,
800 };
801
802static struct regsets_info ppc_regsets_info =
803 {
804 ppc_regsets, /* regsets */
805 0, /* num_regsets */
806 NULL, /* disabled_regsets */
807 };
808
809static struct regs_info regs_info =
810 {
811 NULL, /* regset_bitmap */
812 &ppc_usrregs_info,
813 &ppc_regsets_info
814 };
815
816static const struct regs_info *
817ppc_regs_info (void)
818{
819 return &regs_info;
820}
821
797bcff5
TBA		 822void
823ppc_target::low_arch_setup ()
e6c5bb05
SM		 824{
825 const struct target_desc *tdesc;
7273b5fc 826 struct regset_info *regset;
bd64614e 827 struct ppc_linux_features features = ppc_linux_no_features;
7273b5fc 828
2e077f5e 829 int tid = lwpid_of (current_thread);
bd64614e 830
2e077f5e 831 features.wordsize = ppc_linux_target_wordsize (tid);
e6c5bb05 832
bd64614e 833 if (features.wordsize == 4)
bd64614e 834 tdesc = tdesc_powerpc_32l;
2e077f5e
PFC		 835 else
836 tdesc = tdesc_powerpc_64l;
837
838 current_process ()->tdesc = tdesc;
e6c5bb05 839
bd64614e
PFC		 840 /* The value of current_process ()->tdesc needs to be set for this
841 call. */
974c89e0
AH		 842 ppc_hwcap = linux_get_hwcap (features.wordsize);
843 ppc_hwcap2 = linux_get_hwcap2 (features.wordsize);
bd64614e
PFC		 844
845 features.isa205 = ppc_linux_has_isa205 (ppc_hwcap);
846
847 if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
848 features.vsx = true;
849
850 if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
851 features.altivec = true;
852
7ca18ed6
EBM		 853 if ((ppc_hwcap2 & PPC_FEATURE2_DSCR)
854 && ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET)
855 && ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET))
f2cf6173
EBM		 856 {
857 features.ppr_dscr = true;
858 if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07)
859 && (ppc_hwcap2 & PPC_FEATURE2_TAR)
232bfb86 860 && (ppc_hwcap2 & PPC_FEATURE2_EBB)
f2cf6173 861 && ppc_check_regset (tid, NT_PPC_TAR,
232bfb86
EBM		 862 PPC_LINUX_SIZEOF_TARREGSET)
863 && ppc_check_regset (tid, NT_PPC_EBB,
864 PPC_LINUX_SIZEOF_EBBREGSET)
865 && ppc_check_regset (tid, NT_PPC_PMU,
866 PPC_LINUX_SIZEOF_PMUREGSET))
8d619c01
EBM		 867 {
868 features.isa207 = true;
869 if ((ppc_hwcap2 & PPC_FEATURE2_HTM)
870 && ppc_check_regset (tid, NT_PPC_TM_SPR,
871 PPC_LINUX_SIZEOF_TM_SPRREGSET))
872 features.htm = true;
873 }
f2cf6173 874 }
7ca18ed6 875
bd64614e 876 tdesc = ppc_linux_match_description (features);
e6c5bb05
SM		 877
878 /* On 32-bit machines, check for SPE registers.
879 Set the low target's regmap field as appropriately. */
880#ifndef __powerpc64__
881 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
882 tdesc = tdesc_powerpc_e500l;
883
884 if (!ppc_regmap_adjusted)
885 {
886 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
887 ppc_usrregs_info.regmap = ppc_regmap_e500;
888
889 /* If the FPSCR is 64-bit wide, we need to fetch the whole
890 64-bit slot and not just its second word. The PT_FPSCR
891 supplied in a 32-bit GDB compilation doesn't reflect
892 this. */
893 if (register_size (tdesc, 70) == 8)
894 ppc_regmap[70] = (48 + 2*32) * sizeof (long);
895
896 ppc_regmap_adjusted = 1;
897 }
898#endif
bd64614e 899
e6c5bb05 900 current_process ()->tdesc = tdesc;
7273b5fc
PFC		 901
902 for (regset = ppc_regsets; regset->size >= 0; regset++)
903 switch (regset->get_request)
904 {
905 case PTRACE_GETVRREGS:
d078308a 906 regset->size = features.altivec ? PPC_LINUX_SIZEOF_VRREGSET : 0;
7273b5fc
PFC		 907 break;
908 case PTRACE_GETVSXREGS:
d078308a 909 regset->size = features.vsx ? PPC_LINUX_SIZEOF_VSXREGSET : 0;
7273b5fc
PFC		 910 break;
911 case PTRACE_GETEVRREGS:
912 if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
913 regset->size = 32 * 4 + 8 + 4;
914 else
915 regset->size = 0;
916 break;
7ca18ed6
EBM		 917 case PTRACE_GETREGSET:
918 switch (regset->nt_type)
919 {
920 case NT_PPC_PPR:
921 regset->size = (features.ppr_dscr ?
922 PPC_LINUX_SIZEOF_PPRREGSET : 0);
923 break;
924 case NT_PPC_DSCR:
925 regset->size = (features.ppr_dscr ?
926 PPC_LINUX_SIZEOF_DSCRREGSET : 0);
927 break;
f2cf6173
EBM		 928 case NT_PPC_TAR:
929 regset->size = (features.isa207 ?
930 PPC_LINUX_SIZEOF_TARREGSET : 0);
931 break;
232bfb86
EBM		 932 case NT_PPC_EBB:
933 regset->size = (features.isa207 ?
934 PPC_LINUX_SIZEOF_EBBREGSET : 0);
935 break;
936 case NT_PPC_PMU:
937 regset->size = (features.isa207 ?
938 PPC_LINUX_SIZEOF_PMUREGSET : 0);
939 break;
8d619c01
EBM		 940 case NT_PPC_TM_SPR:
941 regset->size = (features.htm ?
942 PPC_LINUX_SIZEOF_TM_SPRREGSET : 0);
943 break;
944 case NT_PPC_TM_CGPR:
945 if (features.wordsize == 4)
946 regset->size = (features.htm ?
947 PPC32_LINUX_SIZEOF_CGPRREGSET : 0);
948 else
949 regset->size = (features.htm ?
950 PPC64_LINUX_SIZEOF_CGPRREGSET : 0);
951 break;
952 case NT_PPC_TM_CFPR:
953 regset->size = (features.htm ?
954 PPC_LINUX_SIZEOF_CFPRREGSET : 0);
955 break;
956 case NT_PPC_TM_CVMX:
957 regset->size = (features.htm ?
958 PPC_LINUX_SIZEOF_CVMXREGSET : 0);
959 break;
960 case NT_PPC_TM_CVSX:
961 regset->size = (features.htm ?
962 PPC_LINUX_SIZEOF_CVSXREGSET : 0);
963 break;
964 case NT_PPC_TM_CPPR:
965 regset->size = (features.htm ?
966 PPC_LINUX_SIZEOF_CPPRREGSET : 0);
967 break;
968 case NT_PPC_TM_CDSCR:
969 regset->size = (features.htm ?
970 PPC_LINUX_SIZEOF_CDSCRREGSET : 0);
971 break;
972 case NT_PPC_TM_CTAR:
973 regset->size = (features.htm ?
974 PPC_LINUX_SIZEOF_CTARREGSET : 0);
975 break;
7ca18ed6
EBM		 976 default:
977 break;
978 }
979 break;
7273b5fc
PFC		 980 default:
981 break;
982 }
e6c5bb05
SM		 983}
984
a2174ba4
MK		 985/* Implementation of linux_target_ops method "supports_tracepoints". */
986
b04fd3be
MK		 987static int
988ppc_supports_tracepoints (void)
989{
990 return 1;
991}
992
a2174ba4
MK		 993/* Get the thread area address. This is used to recognize which
994 thread is which when tracing with the in-process agent library. We
995 don't read anything from the address, and treat it as opaque; it's
996 the address itself that we assume is unique per-thread. */
997
998static int
999ppc_get_thread_area (int lwpid, CORE_ADDR *addr)
1000{
f2907e49 1001 struct lwp_info *lwp = find_lwp_pid (ptid_t (lwpid));
a2174ba4
MK		 1002 struct thread_info *thr = get_lwp_thread (lwp);
1003 struct regcache *regcache = get_thread_regcache (thr, 1);
1004 ULONGEST tp = 0;
1005
1006#ifdef __powerpc64__
1007 if (register_size (regcache->tdesc, 0) == 8)
1008 collect_register_by_name (regcache, "r13", &tp);
1009 else
1010#endif
1011 collect_register_by_name (regcache, "r2", &tp);
1012
1013 *addr = tp;
1014
1015 return 0;
1016}
1017
1018#ifdef __powerpc64__
1019
1020/* Older glibc doesn't provide this. */
1021
1022#ifndef EF_PPC64_ABI
1023#define EF_PPC64_ABI 3
1024#endif
1025
1026/* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1027 inferiors. */
1028
1029static int
1030is_elfv2_inferior (void)
1031{
1032 /* To be used as fallback if we're unable to determine the right result -
1033 assume inferior uses the same ABI as gdbserver. */
1034#if _CALL_ELF == 2
1035 const int def_res = 1;
1036#else
1037 const int def_res = 0;
1038#endif
0570503d 1039 CORE_ADDR phdr;
a2174ba4
MK		 1040 Elf64_Ehdr ehdr;
1041
0570503d
PFC		 1042 const struct target_desc *tdesc = current_process ()->tdesc;
1043 int wordsize = register_size (tdesc, 0);
1044
1045 if (!linux_get_auxv (wordsize, AT_PHDR, &phdr))
a2174ba4
MK		 1046 return def_res;
1047
1048 /* Assume ELF header is at the beginning of the page where program headers
1049 are located. If it doesn't look like one, bail. */
1050
1051 read_inferior_memory (phdr & ~0xfff, (unsigned char *) &ehdr, sizeof ehdr);
1052 if (memcmp(ehdr.e_ident, ELFMAG, SELFMAG))
1053 return def_res;
1054
1055 return (ehdr.e_flags & EF_PPC64_ABI) == 2;
1056}
1057
1058#endif
1059
1060/* Generate a ds-form instruction in BUF and return the number of bytes written
1061
1062 0 6 11 16 30 32
1063 | OPCD | RST | RA | DS |XO| */
1064
1065__attribute__((unused)) /* Maybe unused due to conditional compilation. */
1066static int
1067gen_ds_form (uint32_t *buf, int opcd, int rst, int ra, int ds, int xo)
1068{
1069 uint32_t insn;
1070
1071 gdb_assert ((opcd & ~0x3f) == 0);
1072 gdb_assert ((rst & ~0x1f) == 0);
1073 gdb_assert ((ra & ~0x1f) == 0);
1074 gdb_assert ((xo & ~0x3) == 0);
1075
1076 insn = (rst << 21) | (ra << 16) | (ds & 0xfffc) | (xo & 0x3);
1077 *buf = (opcd << 26) | insn;
1078 return 1;
1079}
1080
1081/* Followings are frequently used ds-form instructions. */
1082
1083#define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1084#define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1085#define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1086#define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1087
1088/* Generate a d-form instruction in BUF.
1089
1090 0 6 11 16 32
1091 | OPCD | RST | RA | D | */
1092
1093static int
1094gen_d_form (uint32_t *buf, int opcd, int rst, int ra, int si)
1095{
1096 uint32_t insn;
1097
1098 gdb_assert ((opcd & ~0x3f) == 0);
1099 gdb_assert ((rst & ~0x1f) == 0);
1100 gdb_assert ((ra & ~0x1f) == 0);
1101
1102 insn = (rst << 21) | (ra << 16) | (si & 0xffff);
1103 *buf = (opcd << 26) | insn;
1104 return 1;
1105}
1106
1107/* Followings are frequently used d-form instructions. */
1108
1109#define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1110#define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1111#define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1112#define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1113#define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1114#define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1115#define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1116#define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1117#define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1118
1119/* Generate a xfx-form instruction in BUF and return the number of bytes
1120 written.
1121
1122 0 6 11 21 31 32
1123 | OPCD | RST | RI | XO |/| */
1124
1125static int
1126gen_xfx_form (uint32_t *buf, int opcd, int rst, int ri, int xo)
1127{
1128 uint32_t insn;
1129 unsigned int n = ((ri & 0x1f) << 5) | ((ri >> 5) & 0x1f);
1130
1131 gdb_assert ((opcd & ~0x3f) == 0);
1132 gdb_assert ((rst & ~0x1f) == 0);
1133 gdb_assert ((xo & ~0x3ff) == 0);
1134
1135 insn = (rst << 21) | (n << 11) | (xo << 1);
1136 *buf = (opcd << 26) | insn;
1137 return 1;
1138}
1139
1140/* Followings are frequently used xfx-form instructions. */
1141
1142#define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1143#define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1144#define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1145#define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1146#define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1147 E & 0xf, 598)
1148#define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1149
1150
1151/* Generate a x-form instruction in BUF and return the number of bytes written.
1152
1153 0 6 11 16 21 31 32
1154 | OPCD | RST | RA | RB | XO |RC| */
1155
1156static int
1157gen_x_form (uint32_t *buf, int opcd, int rst, int ra, int rb, int xo, int rc)
1158{
1159 uint32_t insn;
1160
1161 gdb_assert ((opcd & ~0x3f) == 0);
1162 gdb_assert ((rst & ~0x1f) == 0);
1163 gdb_assert ((ra & ~0x1f) == 0);
1164 gdb_assert ((rb & ~0x1f) == 0);
1165 gdb_assert ((xo & ~0x3ff) == 0);
1166 gdb_assert ((rc & ~1) == 0);
1167
1168 insn = (rst << 21) | (ra << 16) | (rb << 11) | (xo << 1) | rc;
1169 *buf = (opcd << 26) | insn;
1170 return 1;
1171}
1172
1173/* Followings are frequently used x-form instructions. */
1174
1175#define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1176#define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1177#define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1178#define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1179/* Assume bf = cr7. */
1180#define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1181
1182
1183/* Generate a md-form instruction in BUF and return the number of bytes written.
1184
1185 0 6 11 16 21 27 30 31 32
1186 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1187
1188static int
1189gen_md_form (uint32_t *buf, int opcd, int rs, int ra, int sh, int mb,
1190 int xo, int rc)
1191{
1192 uint32_t insn;
1193 unsigned int n = ((mb & 0x1f) << 1) | ((mb >> 5) & 0x1);
1194 unsigned int sh0_4 = sh & 0x1f;
1195 unsigned int sh5 = (sh >> 5) & 1;
1196
1197 gdb_assert ((opcd & ~0x3f) == 0);
1198 gdb_assert ((rs & ~0x1f) == 0);
1199 gdb_assert ((ra & ~0x1f) == 0);
1200 gdb_assert ((sh & ~0x3f) == 0);
1201 gdb_assert ((mb & ~0x3f) == 0);
1202 gdb_assert ((xo & ~0x7) == 0);
1203 gdb_assert ((rc & ~0x1) == 0);
1204
1205 insn = (rs << 21) | (ra << 16) | (sh0_4 << 11) | (n << 5)
1206 | (sh5 << 1) | (xo << 2) | (rc & 1);
1207 *buf = (opcd << 26) | insn;
1208 return 1;
1209}
1210
1211/* The following are frequently used md-form instructions. */
1212
1213#define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1214 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1215#define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1216 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1217
1218/* Generate a i-form instruction in BUF and return the number of bytes written.
1219
1220 0 6 30 31 32
1221 | OPCD | LI |AA|LK| */
1222
1223static int
1224gen_i_form (uint32_t *buf, int opcd, int li, int aa, int lk)
1225{
1226 uint32_t insn;
1227
1228 gdb_assert ((opcd & ~0x3f) == 0);
1229
1230 insn = (li & 0x3fffffc) | (aa & 1) | (lk & 1);
1231 *buf = (opcd << 26) | insn;
1232 return 1;
1233}
1234
1235/* The following are frequently used i-form instructions. */
1236
1237#define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1238#define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1239
1240/* Generate a b-form instruction in BUF and return the number of bytes written.
1241
1242 0 6 11 16 30 31 32
1243 | OPCD | BO | BI | BD |AA|LK| */
1244
1245static int
1246gen_b_form (uint32_t *buf, int opcd, int bo, int bi, int bd,
1247 int aa, int lk)
1248{
1249 uint32_t insn;
1250
1251 gdb_assert ((opcd & ~0x3f) == 0);
1252 gdb_assert ((bo & ~0x1f) == 0);
1253 gdb_assert ((bi & ~0x1f) == 0);
1254
1255 insn = (bo << 21) | (bi << 16) | (bd & 0xfffc) | (aa & 1) | (lk & 1);
1256 *buf = (opcd << 26) | insn;
1257 return 1;
1258}
1259
1260/* The following are frequently used b-form instructions. */
1261/* Assume bi = cr7. */
1262#define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1263
1264/* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1265 respectively. They are primary used for save/restore GPRs in jump-pad,
1266 not used for bytecode compiling. */
1267
1268#ifdef __powerpc64__
1269#define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1270 GEN_LD (buf, rt, ra, si) : \
1271 GEN_LWZ (buf, rt, ra, si))
1272#define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1273 GEN_STD (buf, rt, ra, si) : \
1274 GEN_STW (buf, rt, ra, si))
1275#else
1276#define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1277#define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1278#endif
1279
1280/* Generate a sequence of instructions to load IMM in the register REG.
1281 Write the instructions in BUF and return the number of bytes written. */
1282
1283static int
1284gen_limm (uint32_t *buf, int reg, uint64_t imm, int is_64)
1285{
1286 uint32_t *p = buf;
1287
1288 if ((imm + 32768) < 65536)
1289 {
1290 /* li reg, imm[15:0] */
1291 p += GEN_LI (p, reg, imm);
1292 }
1293 else if ((imm >> 32) == 0)
1294 {
1295 /* lis reg, imm[31:16]
1296 ori reg, reg, imm[15:0]
1297 rldicl reg, reg, 0, 32 */
1298 p += GEN_LIS (p, reg, (imm >> 16) & 0xffff);
1299 if ((imm & 0xffff) != 0)
1300 p += GEN_ORI (p, reg, reg, imm & 0xffff);
1301 /* Clear upper 32-bit if sign-bit is set. */
1302 if (imm & (1u << 31) && is_64)
1303 p += GEN_RLDICL (p, reg, reg, 0, 32);
1304 }
1305 else
1306 {
1307 gdb_assert (is_64);
1308 /* lis reg, <imm[63:48]>
1309 ori reg, reg, <imm[48:32]>
1310 rldicr reg, reg, 32, 31
1311 oris reg, reg, <imm[31:16]>
1312 ori reg, reg, <imm[15:0]> */
1313 p += GEN_LIS (p, reg, ((imm >> 48) & 0xffff));
1314 if (((imm >> 32) & 0xffff) != 0)
1315 p += GEN_ORI (p, reg, reg, ((imm >> 32) & 0xffff));
1316 p += GEN_RLDICR (p, reg, reg, 32, 31);
1317 if (((imm >> 16) & 0xffff) != 0)
1318 p += GEN_ORIS (p, reg, reg, ((imm >> 16) & 0xffff));
1319 if ((imm & 0xffff) != 0)
1320 p += GEN_ORI (p, reg, reg, (imm & 0xffff));
1321 }
1322
1323 return p - buf;
1324}
1325
1326/* Generate a sequence for atomically exchange at location LOCK.
1327 This code sequence clobbers r6, r7, r8. LOCK is the location for
1328 the atomic-xchg, OLD_VALUE is expected old value stored in the
1329 location, and R_NEW is a register for the new value. */
1330
1331static int
1332gen_atomic_xchg (uint32_t *buf, CORE_ADDR lock, int old_value, int r_new,
1333 int is_64)
1334{
1335 const int r_lock = 6;
1336 const int r_old = 7;
1337 const int r_tmp = 8;
1338 uint32_t *p = buf;
1339
1340 /*
1341 1: lwarx TMP, 0, LOCK
1342 cmpwi TMP, OLD
1343 bne 1b
1344 stwcx. NEW, 0, LOCK
1345 bne 1b */
1346
1347 p += gen_limm (p, r_lock, lock, is_64);
1348 p += gen_limm (p, r_old, old_value, is_64);
1349
1350 p += GEN_LWARX (p, r_tmp, 0, r_lock);
1351 p += GEN_CMPW (p, r_tmp, r_old);
1352 p += GEN_BNE (p, -8);
1353 p += GEN_STWCX (p, r_new, 0, r_lock);
1354 p += GEN_BNE (p, -16);
1355
1356 return p - buf;
1357}
1358
1359/* Generate a sequence of instructions for calling a function
1360 at address of FN. Return the number of bytes are written in BUF. */
1361
1362static int
1363gen_call (uint32_t *buf, CORE_ADDR fn, int is_64, int is_opd)
1364{
1365 uint32_t *p = buf;
1366
1367 /* Must be called by r12 for caller to calculate TOC address. */
1368 p += gen_limm (p, 12, fn, is_64);
1369 if (is_opd)
1370 {
1371 p += GEN_LOAD (p, 11, 12, 16, is_64);
1372 p += GEN_LOAD (p, 2, 12, 8, is_64);
1373 p += GEN_LOAD (p, 12, 12, 0, is_64);
1374 }
1375 p += GEN_MTSPR (p, 12, 9); /* mtctr r12 */
1376 *p++ = 0x4e800421; /* bctrl */
1377
1378 return p - buf;
1379}
1380
1381/* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1382 of instruction. This function is used to adjust pc-relative instructions
1383 when copying. */
1384
1385static void
1386ppc_relocate_instruction (CORE_ADDR *to, CORE_ADDR oldloc)
1387{
1388 uint32_t insn, op6;
1389 long rel, newrel;
1390
1391 read_inferior_memory (oldloc, (unsigned char *) &insn, 4);
1392 op6 = PPC_OP6 (insn);
1393
1394 if (op6 == 18 && (insn & 2) == 0)
1395 {
1396 /* branch && AA = 0 */
1397 rel = PPC_LI (insn);
1398 newrel = (oldloc - *to) + rel;
1399
1400 /* Out of range. Cannot relocate instruction. */
1401 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1402 return;
1403
1404 insn = (insn & ~0x3fffffc) | (newrel & 0x3fffffc);
1405 }
1406 else if (op6 == 16 && (insn & 2) == 0)
1407 {
1408 /* conditional branch && AA = 0 */
1409
1410 /* If the new relocation is too big for even a 26-bit unconditional
1411 branch, there is nothing we can do. Just abort.
1412
1413 Otherwise, if it can be fit in 16-bit conditional branch, just
1414 copy the instruction and relocate the address.
1415
1416 If the it's big for conditional-branch (16-bit), try to invert the
1417 condition and jump with 26-bit branch. For example,
1418
1419 beq .Lgoto
1420 INSN1
1421
1422 =>
1423
1424 bne 1f (+8)
1425 b .Lgoto
1426 1:INSN1
1427
1428 After this transform, we are actually jump from *TO+4 instead of *TO,
1429 so check the relocation again because it will be 1-insn farther then
1430 before if *TO is after OLDLOC.
1431
1432
1433 For BDNZT (or so) is transformed from
1434
1435 bdnzt eq, .Lgoto
1436 INSN1
1437
1438 =>
1439
1440 bdz 1f (+12)
1441 bf eq, 1f (+8)
1442 b .Lgoto
1443 1:INSN1
1444
1445 See also "BO field encodings". */
1446
1447 rel = PPC_BD (insn);
1448 newrel = (oldloc - *to) + rel;
1449
1450 if (newrel < (1 << 15) && newrel >= -(1 << 15))
1451 insn = (insn & ~0xfffc) | (newrel & 0xfffc);
1452 else if ((PPC_BO (insn) & 0x14) == 0x4 || (PPC_BO (insn) & 0x14) == 0x10)
1453 {
1454 newrel -= 4;
1455
1456 /* Out of range. Cannot relocate instruction. */
1457 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1458 return;
1459
1460 if ((PPC_BO (insn) & 0x14) == 0x4)
1461 insn ^= (1 << 24);
1462 else if ((PPC_BO (insn) & 0x14) == 0x10)
1463 insn ^= (1 << 22);
1464
1465 /* Jump over the unconditional branch. */
1466 insn = (insn & ~0xfffc) | 0x8;
4196ab2a 1467 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1468 *to += 4;
1469
1470 /* Build a unconditional branch and copy LK bit. */
1471 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1472 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1473 *to += 4;
1474
1475 return;
1476 }
1477 else if ((PPC_BO (insn) & 0x14) == 0)
1478 {
1479 uint32_t bdnz_insn = (16 << 26) | (0x10 << 21) | 12;
1480 uint32_t bf_insn = (16 << 26) | (0x4 << 21) | 8;
1481
1482 newrel -= 8;
1483
1484 /* Out of range. Cannot relocate instruction. */
1485 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1486 return;
1487
1488 /* Copy BI field. */
1489 bf_insn |= (insn & 0x1f0000);
1490
1491 /* Invert condition. */
1492 bdnz_insn |= (insn ^ (1 << 22)) & (1 << 22);
1493 bf_insn |= (insn ^ (1 << 24)) & (1 << 24);
1494
4196ab2a 1495 target_write_memory (*to, (unsigned char *) &bdnz_insn, 4);
a2174ba4 1496 *to += 4;
4196ab2a 1497 target_write_memory (*to, (unsigned char *) &bf_insn, 4);
a2174ba4
MK		 1498 *to += 4;
1499
1500 /* Build a unconditional branch and copy LK bit. */
1501 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1502 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1503 *to += 4;
1504
1505 return;
1506 }
1507 else /* (BO & 0x14) == 0x14, branch always. */
1508 {
1509 /* Out of range. Cannot relocate instruction. */
1510 if (newrel >= (1 << 25) || newrel < -(1 << 25))
1511 return;
1512
1513 /* Build a unconditional branch and copy LK bit. */
1514 insn = (18 << 26) | (0x3fffffc & newrel) | (insn & 0x3);
4196ab2a 1515 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1516 *to += 4;
1517
1518 return;
1519 }
1520 }
1521
4196ab2a 1522 target_write_memory (*to, (unsigned char *) &insn, 4);
a2174ba4
MK		 1523 *to += 4;
1524}
1525
1526/* Implement install_fast_tracepoint_jump_pad of target_ops.
1527 See target.h for details. */
1528
1529static int
1530ppc_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr,
1531 CORE_ADDR collector,
1532 CORE_ADDR lockaddr,
1533 ULONGEST orig_size,
1534 CORE_ADDR *jump_entry,
1535 CORE_ADDR *trampoline,
1536 ULONGEST *trampoline_size,
1537 unsigned char *jjump_pad_insn,
1538 ULONGEST *jjump_pad_insn_size,
1539 CORE_ADDR *adjusted_insn_addr,
1540 CORE_ADDR *adjusted_insn_addr_end,
1541 char *err)
1542{
1543 uint32_t buf[256];
1544 uint32_t *p = buf;
1545 int j, offset;
1546 CORE_ADDR buildaddr = *jump_entry;
1547 const CORE_ADDR entryaddr = *jump_entry;
1548 int rsz, min_frame, frame_size, tp_reg;
1549#ifdef __powerpc64__
1550 struct regcache *regcache = get_thread_regcache (current_thread, 0);
1551 int is_64 = register_size (regcache->tdesc, 0) == 8;
1552 int is_opd = is_64 && !is_elfv2_inferior ();
1553#else
1554 int is_64 = 0, is_opd = 0;
1555#endif
1556
1557#ifdef __powerpc64__
1558 if (is_64)
1559 {
1560 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1561 rsz = 8;
1562 min_frame = 112;
1563 frame_size = (40 * rsz) + min_frame;
1564 tp_reg = 13;
1565 }
1566 else
1567 {
1568#endif
1569 rsz = 4;
1570 min_frame = 16;
1571 frame_size = (40 * rsz) + min_frame;
1572 tp_reg = 2;
1573#ifdef __powerpc64__
1574 }
1575#endif
1576
1577 /* Stack frame layout for this jump pad,
1578
1579 High thread_area (r13/r2) |
1580 tpoint - collecting_t obj
1581 PC/<tpaddr> | +36
1582 CTR | +35
1583 LR | +34
1584 XER | +33
1585 CR | +32
1586 R31 |
1587 R29 |
1588 ... |
1589 R1 | +1
1590 R0 - collected registers
1591 ... |
1592 ... |
1593 Low Back-chain -
1594
1595
1596 The code flow of this jump pad,
1597
1598 1. Adjust SP
1599 2. Save GPR and SPR
1600 3. Prepare argument
1601 4. Call gdb_collector
1602 5. Restore GPR and SPR
1603 6. Restore SP
1604 7. Build a jump for back to the program
1605 8. Copy/relocate original instruction
30baf67b 1606 9. Build a jump for replacing original instruction. */
a2174ba4
MK		 1607
1608 /* Adjust stack pointer. */
1609 if (is_64)
1610 p += GEN_STDU (p, 1, 1, -frame_size); /* stdu r1,-frame_size(r1) */
1611 else
1612 p += GEN_STWU (p, 1, 1, -frame_size); /* stwu r1,-frame_size(r1) */
1613
1614 /* Store GPRs. Save R1 later, because it had just been modified, but
1615 we want the original value. */
1616 for (j = 2; j < 32; j++)
1617 p += GEN_STORE (p, j, 1, min_frame + j * rsz, is_64);
1618 p += GEN_STORE (p, 0, 1, min_frame + 0 * rsz, is_64);
1619 /* Set r0 to the original value of r1 before adjusting stack frame,
1620 and then save it. */
1621 p += GEN_ADDI (p, 0, 1, frame_size);
1622 p += GEN_STORE (p, 0, 1, min_frame + 1 * rsz, is_64);
1623
1624 /* Save CR, XER, LR, and CTR. */
1625 p += GEN_MFCR (p, 3); /* mfcr r3 */
1626 p += GEN_MFSPR (p, 4, 1); /* mfxer r4 */
1627 p += GEN_MFSPR (p, 5, 8); /* mflr r5 */
1628 p += GEN_MFSPR (p, 6, 9); /* mfctr r6 */
1629 p += GEN_STORE (p, 3, 1, min_frame + 32 * rsz, is_64);/* std r3, 32(r1) */
1630 p += GEN_STORE (p, 4, 1, min_frame + 33 * rsz, is_64);/* std r4, 33(r1) */
1631 p += GEN_STORE (p, 5, 1, min_frame + 34 * rsz, is_64);/* std r5, 34(r1) */
1632 p += GEN_STORE (p, 6, 1, min_frame + 35 * rsz, is_64);/* std r6, 35(r1) */
1633
1634 /* Save PC<tpaddr> */
1635 p += gen_limm (p, 3, tpaddr, is_64);
1636 p += GEN_STORE (p, 3, 1, min_frame + 36 * rsz, is_64);
1637
1638
1639 /* Setup arguments to collector. */
1640 /* Set r4 to collected registers. */
1641 p += GEN_ADDI (p, 4, 1, min_frame);
1642 /* Set r3 to TPOINT. */
1643 p += gen_limm (p, 3, tpoint, is_64);
1644
1645 /* Prepare collecting_t object for lock. */
1646 p += GEN_STORE (p, 3, 1, min_frame + 37 * rsz, is_64);
1647 p += GEN_STORE (p, tp_reg, 1, min_frame + 38 * rsz, is_64);
1648 /* Set R5 to collecting object. */
1649 p += GEN_ADDI (p, 5, 1, 37 * rsz);
1650
1651 p += GEN_LWSYNC (p);
1652 p += gen_atomic_xchg (p, lockaddr, 0, 5, is_64);
1653 p += GEN_LWSYNC (p);
1654
1655 /* Call to collector. */
1656 p += gen_call (p, collector, is_64, is_opd);
1657
1658 /* Simply write 0 to release the lock. */
1659 p += gen_limm (p, 3, lockaddr, is_64);
1660 p += gen_limm (p, 4, 0, is_64);
1661 p += GEN_LWSYNC (p);
1662 p += GEN_STORE (p, 4, 3, 0, is_64);
1663
1664 /* Restore stack and registers. */
1665 p += GEN_LOAD (p, 3, 1, min_frame + 32 * rsz, is_64); /* ld r3, 32(r1) */
1666 p += GEN_LOAD (p, 4, 1, min_frame + 33 * rsz, is_64); /* ld r4, 33(r1) */
1667 p += GEN_LOAD (p, 5, 1, min_frame + 34 * rsz, is_64); /* ld r5, 34(r1) */
1668 p += GEN_LOAD (p, 6, 1, min_frame + 35 * rsz, is_64); /* ld r6, 35(r1) */
1669 p += GEN_MTCR (p, 3); /* mtcr r3 */
1670 p += GEN_MTSPR (p, 4, 1); /* mtxer r4 */
1671 p += GEN_MTSPR (p, 5, 8); /* mtlr r5 */
1672 p += GEN_MTSPR (p, 6, 9); /* mtctr r6 */
1673
1674 /* Restore GPRs. */
1675 for (j = 2; j < 32; j++)
1676 p += GEN_LOAD (p, j, 1, min_frame + j * rsz, is_64);
1677 p += GEN_LOAD (p, 0, 1, min_frame + 0 * rsz, is_64);
1678 /* Restore SP. */
1679 p += GEN_ADDI (p, 1, 1, frame_size);
1680
1681 /* Flush instructions to inferior memory. */
4196ab2a 1682 target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
a2174ba4
MK		 1683
1684 /* Now, insert the original instruction to execute in the jump pad. */
1685 *adjusted_insn_addr = buildaddr + (p - buf) * 4;
1686 *adjusted_insn_addr_end = *adjusted_insn_addr;
1687 ppc_relocate_instruction (adjusted_insn_addr_end, tpaddr);
1688
1689 /* Verify the relocation size. If should be 4 for normal copy,
1690 8 or 12 for some conditional branch. */
1691 if ((*adjusted_insn_addr_end - *adjusted_insn_addr == 0)
1692 || (*adjusted_insn_addr_end - *adjusted_insn_addr > 12))
1693 {
1694 sprintf (err, "E.Unexpected instruction length = %d"
1695 "when relocate instruction.",
1696 (int) (*adjusted_insn_addr_end - *adjusted_insn_addr));
1697 return 1;
1698 }
1699
1700 buildaddr = *adjusted_insn_addr_end;
1701 p = buf;
1702 /* Finally, write a jump back to the program. */
1703 offset = (tpaddr + 4) - buildaddr;
1704 if (offset >= (1 << 25) || offset < -(1 << 25))
1705 {
1706 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1707 "(offset 0x%x > 26-bit).", offset);
1708 return 1;
1709 }
1710 /* b <tpaddr+4> */
1711 p += GEN_B (p, offset);
4196ab2a 1712 target_write_memory (buildaddr, (unsigned char *) buf, (p - buf) * 4);
a2174ba4
MK		 1713 *jump_entry = buildaddr + (p - buf) * 4;
1714
1715 /* The jump pad is now built. Wire in a jump to our jump pad. This
1716 is always done last (by our caller actually), so that we can
1717 install fast tracepoints with threads running. This relies on
1718 the agent's atomic write support. */
1719 offset = entryaddr - tpaddr;
1720 if (offset >= (1 << 25) || offset < -(1 << 25))
1721 {
1722 sprintf (err, "E.Jump back from jump pad too far from tracepoint "
1723 "(offset 0x%x > 26-bit).", offset);
1724 return 1;
1725 }
1726 /* b <jentry> */
1727 GEN_B ((uint32_t *) jjump_pad_insn, offset);
1728 *jjump_pad_insn_size = 4;
1729
1730 return 0;
1731}
1732
1733/* Returns the minimum instruction length for installing a tracepoint. */
1734
1735static int
1736ppc_get_min_fast_tracepoint_insn_len (void)
1737{
1738 return 4;
1739}
1740
14e2b6d9
MK		 1741/* Emits a given buffer into the target at current_insn_ptr. Length
1742 is in units of 32-bit words. */
1743
1744static void
1745emit_insns (uint32_t *buf, int n)
1746{
1747 n = n * sizeof (uint32_t);
4196ab2a 1748 target_write_memory (current_insn_ptr, (unsigned char *) buf, n);
14e2b6d9
MK		 1749 current_insn_ptr += n;
1750}
1751
1752#define __EMIT_ASM(NAME, INSNS) \
1753 do \
1754 { \
1755 extern uint32_t start_bcax_ ## NAME []; \
1756 extern uint32_t end_bcax_ ## NAME []; \
1757 emit_insns (start_bcax_ ## NAME, \
1758 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1759 __asm__ (".section .text.__ppcbcax\n\t" \
1760 "start_bcax_" #NAME ":\n\t" \
1761 INSNS "\n\t" \
1762 "end_bcax_" #NAME ":\n\t" \
1763 ".previous\n\t"); \
1764 } while (0)
1765
1766#define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1767#define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1768
1769/*
1770
1771 Bytecode execution stack frame - 32-bit
1772
1773 | LR save area (SP + 4)
1774 SP' -> +- Back chain (SP + 0)
1775 | Save r31 for access saved arguments
1776 | Save r30 for bytecode stack pointer
1777 | Save r4 for incoming argument *value
1778 | Save r3 for incoming argument regs
1779 r30 -> +- Bytecode execution stack
1780 |
1781 | 64-byte (8 doublewords) at initial.
1782 | Expand stack as needed.
1783 |
1784 +-
1785 | Some padding for minimum stack frame and 16-byte alignment.
1786 | 16 bytes.
1787 SP +- Back-chain (SP')
1788
1789 initial frame size
1790 = 16 + (4 * 4) + 64
1791 = 96
1792
1793 r30 is the stack-pointer for bytecode machine.
1794 It should point to next-empty, so we can use LDU for pop.
1795 r3 is used for cache of the high part of TOP value.
1796 It was the first argument, pointer to regs.
1797 r4 is used for cache of the low part of TOP value.
1798 It was the second argument, pointer to the result.
1799 We should set *result = TOP after leaving this function.
1800
1801 Note:
1802 * To restore stack at epilogue
1803 => sp = r31
1804 * To check stack is big enough for bytecode execution.
1805 => r30 - 8 > SP + 8
1806 * To return execution result.
1807 => 0(r4) = TOP
1808
1809 */
1810
1811/* Regardless of endian, register 3 is always high part, 4 is low part.
1812 These defines are used when the register pair is stored/loaded.
1813 Likewise, to simplify code, have a similiar define for 5:6. */
1814
1815#if __BYTE_ORDER == __LITTLE_ENDIAN
1816#define TOP_FIRST "4"
1817#define TOP_SECOND "3"
1818#define TMP_FIRST "6"
1819#define TMP_SECOND "5"
1820#else
1821#define TOP_FIRST "3"
1822#define TOP_SECOND "4"
1823#define TMP_FIRST "5"
1824#define TMP_SECOND "6"
1825#endif
1826
1827/* Emit prologue in inferior memory. See above comments. */
1828
1829static void
1830ppc_emit_prologue (void)
1831{
1832 EMIT_ASM (/* Save return address. */
1833 "mflr 0 \n"
1834 "stw 0, 4(1) \n"
1835 /* Adjust SP. 96 is the initial frame size. */
1836 "stwu 1, -96(1) \n"
1837 /* Save r30 and incoming arguments. */
1838 "stw 31, 96-4(1) \n"
1839 "stw 30, 96-8(1) \n"
1840 "stw 4, 96-12(1) \n"
1841 "stw 3, 96-16(1) \n"
1842 /* Point r31 to original r1 for access arguments. */
1843 "addi 31, 1, 96 \n"
1844 /* Set r30 to pointing stack-top. */
1845 "addi 30, 1, 64 \n"
1846 /* Initial r3/TOP to 0. */
1847 "li 3, 0 \n"
1848 "li 4, 0 \n");
1849}
1850
1851/* Emit epilogue in inferior memory. See above comments. */
1852
1853static void
1854ppc_emit_epilogue (void)
1855{
1856 EMIT_ASM (/* *result = TOP */
1857 "lwz 5, -12(31) \n"
1858 "stw " TOP_FIRST ", 0(5) \n"
1859 "stw " TOP_SECOND ", 4(5) \n"
1860 /* Restore registers. */
1861 "lwz 31, -4(31) \n"
1862 "lwz 30, -8(31) \n"
1863 /* Restore SP. */
1864 "lwz 1, 0(1) \n"
1865 /* Restore LR. */
1866 "lwz 0, 4(1) \n"
1867 /* Return 0 for no-error. */
1868 "li 3, 0 \n"
1869 "mtlr 0 \n"
1870 "blr \n");
1871}
1872
1873/* TOP = stack[--sp] + TOP */
1874
1875static void
1876ppc_emit_add (void)
1877{
1878 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1879 "lwz " TMP_SECOND ", 4(30)\n"
1880 "addc 4, 6, 4 \n"
1881 "adde 3, 5, 3 \n");
1882}
1883
1884/* TOP = stack[--sp] - TOP */
1885
1886static void
1887ppc_emit_sub (void)
1888{
1889 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1890 "lwz " TMP_SECOND ", 4(30) \n"
1891 "subfc 4, 4, 6 \n"
1892 "subfe 3, 3, 5 \n");
1893}
1894
1895/* TOP = stack[--sp] * TOP */
1896
1897static void
1898ppc_emit_mul (void)
1899{
1900 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1901 "lwz " TMP_SECOND ", 4(30) \n"
1902 "mulhwu 7, 6, 4 \n"
1903 "mullw 3, 6, 3 \n"
1904 "mullw 5, 4, 5 \n"
1905 "mullw 4, 6, 4 \n"
1906 "add 3, 5, 3 \n"
1907 "add 3, 7, 3 \n");
1908}
1909
1910/* TOP = stack[--sp] << TOP */
1911
1912static void
1913ppc_emit_lsh (void)
1914{
1915 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1916 "lwz " TMP_SECOND ", 4(30) \n"
1917 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1918 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1919 "slw 5, 5, 4\n" /* Shift high part left */
1920 "slw 4, 6, 4\n" /* Shift low part left */
1921 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1922 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1923 "or 3, 5, 3\n"
1924 "or 3, 7, 3\n"); /* Assemble high part */
1925}
1926
1927/* Top = stack[--sp] >> TOP
1928 (Arithmetic shift right) */
1929
1930static void
1931ppc_emit_rsh_signed (void)
1932{
1933 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1934 "lwz " TMP_SECOND ", 4(30) \n"
1935 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1936 "sraw 3, 5, 4\n" /* Shift high part right */
1937 "cmpwi 7, 1\n"
1938 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1939 "sraw 4, 5, 7\n" /* Shift high to low */
1940 "b 2f\n"
1941 "1:\n"
1942 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
1943 "srw 4, 6, 4\n" /* Shift low part right */
1944 "slw 5, 5, 7\n" /* Shift high to low */
1945 "or 4, 4, 5\n" /* Assemble low part */
1946 "2:\n");
1947}
1948
1949/* Top = stack[--sp] >> TOP
1950 (Logical shift right) */
1951
1952static void
1953ppc_emit_rsh_unsigned (void)
1954{
1955 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
1956 "lwz " TMP_SECOND ", 4(30) \n"
1957 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1958 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1959 "srw 6, 6, 4\n" /* Shift low part right */
1960 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
1961 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
1962 "or 6, 6, 3\n"
1963 "srw 3, 5, 4\n" /* Shift high part right */
1964 "or 4, 6, 7\n"); /* Assemble low part */
1965}
1966
1967/* Emit code for signed-extension specified by ARG. */
1968
1969static void
1970ppc_emit_ext (int arg)
1971{
1972 switch (arg)
1973 {
1974 case 8:
1975 EMIT_ASM ("extsb 4, 4\n"
1976 "srawi 3, 4, 31");
1977 break;
1978 case 16:
1979 EMIT_ASM ("extsh 4, 4\n"
1980 "srawi 3, 4, 31");
1981 break;
1982 case 32:
1983 EMIT_ASM ("srawi 3, 4, 31");
1984 break;
1985 default:
1986 emit_error = 1;
1987 }
1988}
1989
1990/* Emit code for zero-extension specified by ARG. */
1991
1992static void
1993ppc_emit_zero_ext (int arg)
1994{
1995 switch (arg)
1996 {
1997 case 8:
1998 EMIT_ASM ("clrlwi 4,4,24\n"
1999 "li 3, 0\n");
2000 break;
2001 case 16:
2002 EMIT_ASM ("clrlwi 4,4,16\n"
2003 "li 3, 0\n");
2004 break;
2005 case 32:
2006 EMIT_ASM ("li 3, 0");
2007 break;
2008 default:
2009 emit_error = 1;
2010 }
2011}
2012
2013/* TOP = !TOP
2014 i.e., TOP = (TOP == 0) ? 1 : 0; */
2015
2016static void
2017ppc_emit_log_not (void)
2018{
2019 EMIT_ASM ("or 4, 3, 4 \n"
2020 "cntlzw 4, 4 \n"
2021 "srwi 4, 4, 5 \n"
2022 "li 3, 0 \n");
2023}
2024
2025/* TOP = stack[--sp] & TOP */
2026
2027static void
2028ppc_emit_bit_and (void)
2029{
2030 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2031 "lwz " TMP_SECOND ", 4(30) \n"
2032 "and 4, 6, 4 \n"
2033 "and 3, 5, 3 \n");
2034}
2035
2036/* TOP = stack[--sp] | TOP */
2037
2038static void
2039ppc_emit_bit_or (void)
2040{
2041 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2042 "lwz " TMP_SECOND ", 4(30) \n"
2043 "or 4, 6, 4 \n"
2044 "or 3, 5, 3 \n");
2045}
2046
2047/* TOP = stack[--sp] ^ TOP */
2048
2049static void
2050ppc_emit_bit_xor (void)
2051{
2052 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2053 "lwz " TMP_SECOND ", 4(30) \n"
2054 "xor 4, 6, 4 \n"
2055 "xor 3, 5, 3 \n");
2056}
2057
2058/* TOP = ~TOP
2059 i.e., TOP = ~(TOP | TOP) */
2060
2061static void
2062ppc_emit_bit_not (void)
2063{
2064 EMIT_ASM ("nor 3, 3, 3 \n"
2065 "nor 4, 4, 4 \n");
2066}
2067
2068/* TOP = stack[--sp] == TOP */
2069
2070static void
2071ppc_emit_equal (void)
2072{
2073 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2074 "lwz " TMP_SECOND ", 4(30) \n"
2075 "xor 4, 6, 4 \n"
2076 "xor 3, 5, 3 \n"
2077 "or 4, 3, 4 \n"
2078 "cntlzw 4, 4 \n"
2079 "srwi 4, 4, 5 \n"
2080 "li 3, 0 \n");
2081}
2082
2083/* TOP = stack[--sp] < TOP
2084 (Signed comparison) */
2085
2086static void
2087ppc_emit_less_signed (void)
2088{
2089 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2090 "lwz " TMP_SECOND ", 4(30) \n"
2091 "cmplw 6, 6, 4 \n"
2092 "cmpw 7, 5, 3 \n"
2093 /* CR6 bit 0 = low less and high equal */
2094 "crand 6*4+0, 6*4+0, 7*4+2\n"
2095 /* CR7 bit 0 = (low less and high equal) or high less */
2096 "cror 7*4+0, 7*4+0, 6*4+0\n"
2097 "mfcr 4 \n"
2098 "rlwinm 4, 4, 29, 31, 31 \n"
2099 "li 3, 0 \n");
2100}
2101
2102/* TOP = stack[--sp] < TOP
2103 (Unsigned comparison) */
2104
2105static void
2106ppc_emit_less_unsigned (void)
2107{
2108 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2109 "lwz " TMP_SECOND ", 4(30) \n"
2110 "cmplw 6, 6, 4 \n"
2111 "cmplw 7, 5, 3 \n"
2112 /* CR6 bit 0 = low less and high equal */
2113 "crand 6*4+0, 6*4+0, 7*4+2\n"
2114 /* CR7 bit 0 = (low less and high equal) or high less */
2115 "cror 7*4+0, 7*4+0, 6*4+0\n"
2116 "mfcr 4 \n"
2117 "rlwinm 4, 4, 29, 31, 31 \n"
2118 "li 3, 0 \n");
2119}
2120
2121/* Access the memory address in TOP in size of SIZE.
2122 Zero-extend the read value. */
2123
2124static void
2125ppc_emit_ref (int size)
2126{
2127 switch (size)
2128 {
2129 case 1:
2130 EMIT_ASM ("lbz 4, 0(4)\n"
2131 "li 3, 0");
2132 break;
2133 case 2:
2134 EMIT_ASM ("lhz 4, 0(4)\n"
2135 "li 3, 0");
2136 break;
2137 case 4:
2138 EMIT_ASM ("lwz 4, 0(4)\n"
2139 "li 3, 0");
2140 break;
2141 case 8:
2142 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2143 EMIT_ASM ("lwz 3, 4(4)\n"
2144 "lwz 4, 0(4)");
2145 else
2146 EMIT_ASM ("lwz 3, 0(4)\n"
2147 "lwz 4, 4(4)");
2148 break;
2149 }
2150}
2151
2152/* TOP = NUM */
2153
2154static void
2155ppc_emit_const (LONGEST num)
2156{
2157 uint32_t buf[10];
2158 uint32_t *p = buf;
2159
2160 p += gen_limm (p, 3, num >> 32 & 0xffffffff, 0);
2161 p += gen_limm (p, 4, num & 0xffffffff, 0);
2162
2163 emit_insns (buf, p - buf);
2164 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2165}
2166
2167/* Set TOP to the value of register REG by calling get_raw_reg function
2168 with two argument, collected buffer and register number. */
2169
2170static void
2171ppc_emit_reg (int reg)
2172{
2173 uint32_t buf[13];
2174 uint32_t *p = buf;
2175
2176 /* fctx->regs is passed in r3 and then saved in -16(31). */
2177 p += GEN_LWZ (p, 3, 31, -16);
2178 p += GEN_LI (p, 4, reg); /* li r4, reg */
2179 p += gen_call (p, get_raw_reg_func_addr (), 0, 0);
2180
2181 emit_insns (buf, p - buf);
2182 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2183
2184 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2185 {
2186 EMIT_ASM ("mr 5, 4\n"
2187 "mr 4, 3\n"
2188 "mr 3, 5\n");
2189 }
2190}
2191
2192/* TOP = stack[--sp] */
2193
2194static void
2195ppc_emit_pop (void)
2196{
2197 EMIT_ASM ("lwzu " TOP_FIRST ", 8(30) \n"
2198 "lwz " TOP_SECOND ", 4(30) \n");
2199}
2200
2201/* stack[sp++] = TOP
2202
2203 Because we may use up bytecode stack, expand 8 doublewords more
2204 if needed. */
2205
2206static void
2207ppc_emit_stack_flush (void)
2208{
2209 /* Make sure bytecode stack is big enough before push.
2210 Otherwise, expand 64-byte more. */
2211
2212 EMIT_ASM (" stw " TOP_FIRST ", 0(30) \n"
2213 " stw " TOP_SECOND ", 4(30)\n"
2214 " addi 5, 30, -(8 + 8) \n"
2215 " cmpw 7, 5, 1 \n"
2216 " bgt 7, 1f \n"
2217 " stwu 31, -64(1) \n"
2218 "1:addi 30, 30, -8 \n");
2219}
2220
2221/* Swap TOP and stack[sp-1] */
2222
2223static void
2224ppc_emit_swap (void)
2225{
2226 EMIT_ASM ("lwz " TMP_FIRST ", 8(30) \n"
2227 "lwz " TMP_SECOND ", 12(30) \n"
2228 "stw " TOP_FIRST ", 8(30) \n"
2229 "stw " TOP_SECOND ", 12(30) \n"
2230 "mr 3, 5 \n"
2231 "mr 4, 6 \n");
2232}
2233
2234/* Discard N elements in the stack. Also used for ppc64. */
2235
2236static void
2237ppc_emit_stack_adjust (int n)
2238{
2239 uint32_t buf[6];
2240 uint32_t *p = buf;
2241
2242 n = n << 3;
2243 if ((n >> 15) != 0)
2244 {
2245 emit_error = 1;
2246 return;
2247 }
2248
2249 p += GEN_ADDI (p, 30, 30, n);
2250
2251 emit_insns (buf, p - buf);
2252 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2253}
2254
2255/* Call function FN. */
2256
2257static void
2258ppc_emit_call (CORE_ADDR fn)
2259{
2260 uint32_t buf[11];
2261 uint32_t *p = buf;
2262
2263 p += gen_call (p, fn, 0, 0);
2264
2265 emit_insns (buf, p - buf);
2266 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2267}
2268
2269/* FN's prototype is `LONGEST(*fn)(int)'.
2270 TOP = fn (arg1)
2271 */
2272
2273static void
2274ppc_emit_int_call_1 (CORE_ADDR fn, int arg1)
2275{
2276 uint32_t buf[15];
2277 uint32_t *p = buf;
2278
2279 /* Setup argument. arg1 is a 16-bit value. */
2280 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2281 p += gen_call (p, fn, 0, 0);
2282
2283 emit_insns (buf, p - buf);
2284 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2285
2286 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2287 {
2288 EMIT_ASM ("mr 5, 4\n"
2289 "mr 4, 3\n"
2290 "mr 3, 5\n");
2291 }
2292}
2293
2294/* FN's prototype is `void(*fn)(int,LONGEST)'.
2295 fn (arg1, TOP)
2296
2297 TOP should be preserved/restored before/after the call. */
2298
2299static void
2300ppc_emit_void_call_2 (CORE_ADDR fn, int arg1)
2301{
2302 uint32_t buf[21];
2303 uint32_t *p = buf;
2304
2305 /* Save TOP. 0(30) is next-empty. */
2306 p += GEN_STW (p, 3, 30, 0);
2307 p += GEN_STW (p, 4, 30, 4);
2308
2309 /* Setup argument. arg1 is a 16-bit value. */
2310 if (__BYTE_ORDER == __LITTLE_ENDIAN)
2311 {
2312 p += GEN_MR (p, 5, 4);
2313 p += GEN_MR (p, 6, 3);
2314 }
2315 else
2316 {
2317 p += GEN_MR (p, 5, 3);
2318 p += GEN_MR (p, 6, 4);
2319 }
2320 p += gen_limm (p, 3, (uint32_t) arg1, 0);
2321 p += gen_call (p, fn, 0, 0);
2322
2323 /* Restore TOP */
2324 p += GEN_LWZ (p, 3, 30, 0);
2325 p += GEN_LWZ (p, 4, 30, 4);
2326
2327 emit_insns (buf, p - buf);
2328 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2329}
2330
2331/* Note in the following goto ops:
2332
2333 When emitting goto, the target address is later relocated by
2334 write_goto_address. OFFSET_P is the offset of the branch instruction
2335 in the code sequence, and SIZE_P is how to relocate the instruction,
2336 recognized by ppc_write_goto_address. In current implementation,
2337 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2338 */
2339
2340/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2341
2342static void
2343ppc_emit_if_goto (int *offset_p, int *size_p)
2344{
2345 EMIT_ASM ("or. 3, 3, 4 \n"
2346 "lwzu " TOP_FIRST ", 8(30) \n"
2347 "lwz " TOP_SECOND ", 4(30) \n"
2348 "1:bne 0, 1b \n");
2349
2350 if (offset_p)
2351 *offset_p = 12;
2352 if (size_p)
2353 *size_p = 14;
2354}
2355
2356/* Unconditional goto. Also used for ppc64. */
2357
2358static void
2359ppc_emit_goto (int *offset_p, int *size_p)
2360{
2361 EMIT_ASM ("1:b 1b");
2362
2363 if (offset_p)
2364 *offset_p = 0;
2365 if (size_p)
2366 *size_p = 24;
2367}
2368
2369/* Goto if stack[--sp] == TOP */
2370
2371static void
2372ppc_emit_eq_goto (int *offset_p, int *size_p)
2373{
2374 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2375 "lwz " TMP_SECOND ", 4(30) \n"
2376 "xor 4, 6, 4 \n"
2377 "xor 3, 5, 3 \n"
2378 "or. 3, 3, 4 \n"
2379 "lwzu " TOP_FIRST ", 8(30) \n"
2380 "lwz " TOP_SECOND ", 4(30) \n"
2381 "1:beq 0, 1b \n");
2382
2383 if (offset_p)
2384 *offset_p = 28;
2385 if (size_p)
2386 *size_p = 14;
2387}
2388
2389/* Goto if stack[--sp] != TOP */
2390
2391static void
2392ppc_emit_ne_goto (int *offset_p, int *size_p)
2393{
2394 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2395 "lwz " TMP_SECOND ", 4(30) \n"
2396 "xor 4, 6, 4 \n"
2397 "xor 3, 5, 3 \n"
2398 "or. 3, 3, 4 \n"
2399 "lwzu " TOP_FIRST ", 8(30) \n"
2400 "lwz " TOP_SECOND ", 4(30) \n"
2401 "1:bne 0, 1b \n");
2402
2403 if (offset_p)
2404 *offset_p = 28;
2405 if (size_p)
2406 *size_p = 14;
2407}
2408
2409/* Goto if stack[--sp] < TOP */
2410
2411static void
2412ppc_emit_lt_goto (int *offset_p, int *size_p)
2413{
2414 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2415 "lwz " TMP_SECOND ", 4(30) \n"
2416 "cmplw 6, 6, 4 \n"
2417 "cmpw 7, 5, 3 \n"
2418 /* CR6 bit 0 = low less and high equal */
2419 "crand 6*4+0, 6*4+0, 7*4+2\n"
2420 /* CR7 bit 0 = (low less and high equal) or high less */
2421 "cror 7*4+0, 7*4+0, 6*4+0\n"
2422 "lwzu " TOP_FIRST ", 8(30) \n"
2423 "lwz " TOP_SECOND ", 4(30)\n"
2424 "1:blt 7, 1b \n");
2425
2426 if (offset_p)
2427 *offset_p = 32;
2428 if (size_p)
2429 *size_p = 14;
2430}
2431
2432/* Goto if stack[--sp] <= TOP */
2433
2434static void
2435ppc_emit_le_goto (int *offset_p, int *size_p)
2436{
2437 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2438 "lwz " TMP_SECOND ", 4(30) \n"
2439 "cmplw 6, 6, 4 \n"
2440 "cmpw 7, 5, 3 \n"
2441 /* CR6 bit 0 = low less/equal and high equal */
2442 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2443 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2444 "cror 7*4+0, 7*4+0, 6*4+0\n"
2445 "lwzu " TOP_FIRST ", 8(30) \n"
2446 "lwz " TOP_SECOND ", 4(30)\n"
2447 "1:blt 7, 1b \n");
2448
2449 if (offset_p)
2450 *offset_p = 32;
2451 if (size_p)
2452 *size_p = 14;
2453}
2454
2455/* Goto if stack[--sp] > TOP */
2456
2457static void
2458ppc_emit_gt_goto (int *offset_p, int *size_p)
2459{
2460 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2461 "lwz " TMP_SECOND ", 4(30) \n"
2462 "cmplw 6, 6, 4 \n"
2463 "cmpw 7, 5, 3 \n"
2464 /* CR6 bit 0 = low greater and high equal */
2465 "crand 6*4+0, 6*4+1, 7*4+2\n"
2466 /* CR7 bit 0 = (low greater and high equal) or high greater */
2467 "cror 7*4+0, 7*4+1, 6*4+0\n"
2468 "lwzu " TOP_FIRST ", 8(30) \n"
2469 "lwz " TOP_SECOND ", 4(30)\n"
2470 "1:blt 7, 1b \n");
2471
2472 if (offset_p)
2473 *offset_p = 32;
2474 if (size_p)
2475 *size_p = 14;
2476}
2477
2478/* Goto if stack[--sp] >= TOP */
2479
2480static void
2481ppc_emit_ge_goto (int *offset_p, int *size_p)
2482{
2483 EMIT_ASM ("lwzu " TMP_FIRST ", 8(30) \n"
2484 "lwz " TMP_SECOND ", 4(30) \n"
2485 "cmplw 6, 6, 4 \n"
2486 "cmpw 7, 5, 3 \n"
2487 /* CR6 bit 0 = low ge and high equal */
2488 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2489 /* CR7 bit 0 = (low ge and high equal) or high greater */
2490 "cror 7*4+0, 7*4+1, 6*4+0\n"
2491 "lwzu " TOP_FIRST ", 8(30)\n"
2492 "lwz " TOP_SECOND ", 4(30)\n"
2493 "1:blt 7, 1b \n");
2494
2495 if (offset_p)
2496 *offset_p = 32;
2497 if (size_p)
2498 *size_p = 14;
2499}
2500
2501/* Relocate previous emitted branch instruction. FROM is the address
2502 of the branch instruction, TO is the goto target address, and SIZE
2503 if the value we set by *SIZE_P before. Currently, it is either
2504 24 or 14 of branch and conditional-branch instruction.
2505 Also used for ppc64. */
2506
2507static void
2508ppc_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size)
2509{
2510 long rel = to - from;
2511 uint32_t insn;
2512 int opcd;
2513
2514 read_inferior_memory (from, (unsigned char *) &insn, 4);
2515 opcd = (insn >> 26) & 0x3f;
2516
2517 switch (size)
2518 {
2519 case 14:
2520 if (opcd != 16
2521 || (rel >= (1 << 15) || rel < -(1 << 15)))
2522 emit_error = 1;
2523 insn = (insn & ~0xfffc) | (rel & 0xfffc);
2524 break;
2525 case 24:
2526 if (opcd != 18
2527 || (rel >= (1 << 25) || rel < -(1 << 25)))
2528 emit_error = 1;
2529 insn = (insn & ~0x3fffffc) | (rel & 0x3fffffc);
2530 break;
2531 default:
2532 emit_error = 1;
2533 }
2534
2535 if (!emit_error)
4196ab2a 2536 target_write_memory (from, (unsigned char *) &insn, 4);
14e2b6d9
MK		 2537}
2538
2539/* Table of emit ops for 32-bit. */
2540
2541static struct emit_ops ppc_emit_ops_impl =
2542{
2543 ppc_emit_prologue,
2544 ppc_emit_epilogue,
2545 ppc_emit_add,
2546 ppc_emit_sub,
2547 ppc_emit_mul,
2548 ppc_emit_lsh,
2549 ppc_emit_rsh_signed,
2550 ppc_emit_rsh_unsigned,
2551 ppc_emit_ext,
2552 ppc_emit_log_not,
2553 ppc_emit_bit_and,
2554 ppc_emit_bit_or,
2555 ppc_emit_bit_xor,
2556 ppc_emit_bit_not,
2557 ppc_emit_equal,
2558 ppc_emit_less_signed,
2559 ppc_emit_less_unsigned,
2560 ppc_emit_ref,
2561 ppc_emit_if_goto,
2562 ppc_emit_goto,
2563 ppc_write_goto_address,
2564 ppc_emit_const,
2565 ppc_emit_call,
2566 ppc_emit_reg,
2567 ppc_emit_pop,
2568 ppc_emit_stack_flush,
2569 ppc_emit_zero_ext,
2570 ppc_emit_swap,
2571 ppc_emit_stack_adjust,
2572 ppc_emit_int_call_1,
2573 ppc_emit_void_call_2,
2574 ppc_emit_eq_goto,
2575 ppc_emit_ne_goto,
2576 ppc_emit_lt_goto,
2577 ppc_emit_le_goto,
2578 ppc_emit_gt_goto,
2579 ppc_emit_ge_goto
2580};
2581
2582#ifdef __powerpc64__
2583
2584/*
2585
2586 Bytecode execution stack frame - 64-bit
2587
2588 | LR save area (SP + 16)
2589 | CR save area (SP + 8)
2590 SP' -> +- Back chain (SP + 0)
2591 | Save r31 for access saved arguments
2592 | Save r30 for bytecode stack pointer
2593 | Save r4 for incoming argument *value
2594 | Save r3 for incoming argument regs
2595 r30 -> +- Bytecode execution stack
2596 |
2597 | 64-byte (8 doublewords) at initial.
2598 | Expand stack as needed.
2599 |
2600 +-
2601 | Some padding for minimum stack frame.
2602 | 112 for ELFv1.
2603 SP +- Back-chain (SP')
2604
2605 initial frame size
2606 = 112 + (4 * 8) + 64
2607 = 208
2608
2609 r30 is the stack-pointer for bytecode machine.
2610 It should point to next-empty, so we can use LDU for pop.
2611 r3 is used for cache of TOP value.
2612 It was the first argument, pointer to regs.
2613 r4 is the second argument, pointer to the result.
2614 We should set *result = TOP after leaving this function.
2615
2616 Note:
2617 * To restore stack at epilogue
2618 => sp = r31
2619 * To check stack is big enough for bytecode execution.
2620 => r30 - 8 > SP + 112
2621 * To return execution result.
2622 => 0(r4) = TOP
2623
2624 */
2625
2626/* Emit prologue in inferior memory. See above comments. */
2627
2628static void
2629ppc64v1_emit_prologue (void)
2630{
2631 /* On ELFv1, function pointers really point to function descriptor,
2632 so emit one here. We don't care about contents of words 1 and 2,
2633 so let them just overlap out code. */
2634 uint64_t opd = current_insn_ptr + 8;
2635 uint32_t buf[2];
2636
2637 /* Mind the strict aliasing rules. */
2638 memcpy (buf, &opd, sizeof buf);
2639 emit_insns(buf, 2);
2640 EMIT_ASM (/* Save return address. */
2641 "mflr 0 \n"
2642 "std 0, 16(1) \n"
2643 /* Save r30 and incoming arguments. */
2644 "std 31, -8(1) \n"
2645 "std 30, -16(1) \n"
2646 "std 4, -24(1) \n"
2647 "std 3, -32(1) \n"
2648 /* Point r31 to current r1 for access arguments. */
2649 "mr 31, 1 \n"
2650 /* Adjust SP. 208 is the initial frame size. */
2651 "stdu 1, -208(1) \n"
2652 /* Set r30 to pointing stack-top. */
2653 "addi 30, 1, 168 \n"
2654 /* Initial r3/TOP to 0. */
2655 "li 3, 0 \n");
2656}
2657
2658/* Emit prologue in inferior memory. See above comments. */
2659
2660static void
2661ppc64v2_emit_prologue (void)
2662{
2663 EMIT_ASM (/* Save return address. */
2664 "mflr 0 \n"
2665 "std 0, 16(1) \n"
2666 /* Save r30 and incoming arguments. */
2667 "std 31, -8(1) \n"
2668 "std 30, -16(1) \n"
2669 "std 4, -24(1) \n"
2670 "std 3, -32(1) \n"
2671 /* Point r31 to current r1 for access arguments. */
2672 "mr 31, 1 \n"
2673 /* Adjust SP. 208 is the initial frame size. */
2674 "stdu 1, -208(1) \n"
2675 /* Set r30 to pointing stack-top. */
2676 "addi 30, 1, 168 \n"
2677 /* Initial r3/TOP to 0. */
2678 "li 3, 0 \n");
2679}
2680
2681/* Emit epilogue in inferior memory. See above comments. */
2682
2683static void
2684ppc64_emit_epilogue (void)
2685{
2686 EMIT_ASM (/* Restore SP. */
2687 "ld 1, 0(1) \n"
2688 /* *result = TOP */
2689 "ld 4, -24(1) \n"
2690 "std 3, 0(4) \n"
2691 /* Restore registers. */
2692 "ld 31, -8(1) \n"
2693 "ld 30, -16(1) \n"
2694 /* Restore LR. */
2695 "ld 0, 16(1) \n"
2696 /* Return 0 for no-error. */
2697 "li 3, 0 \n"
2698 "mtlr 0 \n"
2699 "blr \n");
2700}
2701
2702/* TOP = stack[--sp] + TOP */
2703
2704static void
2705ppc64_emit_add (void)
2706{
2707 EMIT_ASM ("ldu 4, 8(30) \n"
2708 "add 3, 4, 3 \n");
2709}
2710
2711/* TOP = stack[--sp] - TOP */
2712
2713static void
2714ppc64_emit_sub (void)
2715{
2716 EMIT_ASM ("ldu 4, 8(30) \n"
2717 "sub 3, 4, 3 \n");
2718}
2719
2720/* TOP = stack[--sp] * TOP */
2721
2722static void
2723ppc64_emit_mul (void)
2724{
2725 EMIT_ASM ("ldu 4, 8(30) \n"
2726 "mulld 3, 4, 3 \n");
2727}
2728
2729/* TOP = stack[--sp] << TOP */
2730
2731static void
2732ppc64_emit_lsh (void)
2733{
2734 EMIT_ASM ("ldu 4, 8(30) \n"
2735 "sld 3, 4, 3 \n");
2736}
2737
2738/* Top = stack[--sp] >> TOP
2739 (Arithmetic shift right) */
2740
2741static void
2742ppc64_emit_rsh_signed (void)
2743{
2744 EMIT_ASM ("ldu 4, 8(30) \n"
2745 "srad 3, 4, 3 \n");
2746}
2747
2748/* Top = stack[--sp] >> TOP
2749 (Logical shift right) */
2750
2751static void
2752ppc64_emit_rsh_unsigned (void)
2753{
2754 EMIT_ASM ("ldu 4, 8(30) \n"
2755 "srd 3, 4, 3 \n");
2756}
2757
2758/* Emit code for signed-extension specified by ARG. */
2759
2760static void
2761ppc64_emit_ext (int arg)
2762{
2763 switch (arg)
2764 {
2765 case 8:
2766 EMIT_ASM ("extsb 3, 3");
2767 break;
2768 case 16:
2769 EMIT_ASM ("extsh 3, 3");
2770 break;
2771 case 32:
2772 EMIT_ASM ("extsw 3, 3");
2773 break;
2774 default:
2775 emit_error = 1;
2776 }
2777}
2778
2779/* Emit code for zero-extension specified by ARG. */
2780
2781static void
2782ppc64_emit_zero_ext (int arg)
2783{
2784 switch (arg)
2785 {
2786 case 8:
2787 EMIT_ASM ("rldicl 3,3,0,56");
2788 break;
2789 case 16:
2790 EMIT_ASM ("rldicl 3,3,0,48");
2791 break;
2792 case 32:
2793 EMIT_ASM ("rldicl 3,3,0,32");
2794 break;
2795 default:
2796 emit_error = 1;
2797 }
2798}
2799
2800/* TOP = !TOP
2801 i.e., TOP = (TOP == 0) ? 1 : 0; */
2802
2803static void
2804ppc64_emit_log_not (void)
2805{
2806 EMIT_ASM ("cntlzd 3, 3 \n"
2807 "srdi 3, 3, 6 \n");
2808}
2809
2810/* TOP = stack[--sp] & TOP */
2811
2812static void
2813ppc64_emit_bit_and (void)
2814{
2815 EMIT_ASM ("ldu 4, 8(30) \n"
2816 "and 3, 4, 3 \n");
2817}
2818
2819/* TOP = stack[--sp] | TOP */
2820
2821static void
2822ppc64_emit_bit_or (void)
2823{
2824 EMIT_ASM ("ldu 4, 8(30) \n"
2825 "or 3, 4, 3 \n");
2826}
2827
2828/* TOP = stack[--sp] ^ TOP */
2829
2830static void
2831ppc64_emit_bit_xor (void)
2832{
2833 EMIT_ASM ("ldu 4, 8(30) \n"
2834 "xor 3, 4, 3 \n");
2835}
2836
2837/* TOP = ~TOP
2838 i.e., TOP = ~(TOP | TOP) */
2839
2840static void
2841ppc64_emit_bit_not (void)
2842{
2843 EMIT_ASM ("nor 3, 3, 3 \n");
2844}
2845
2846/* TOP = stack[--sp] == TOP */
2847
2848static void
2849ppc64_emit_equal (void)
2850{
2851 EMIT_ASM ("ldu 4, 8(30) \n"
2852 "xor 3, 3, 4 \n"
2853 "cntlzd 3, 3 \n"
2854 "srdi 3, 3, 6 \n");
2855}
2856
2857/* TOP = stack[--sp] < TOP
2858 (Signed comparison) */
2859
2860static void
2861ppc64_emit_less_signed (void)
2862{
2863 EMIT_ASM ("ldu 4, 8(30) \n"
2864 "cmpd 7, 4, 3 \n"
2865 "mfcr 3 \n"
2866 "rlwinm 3, 3, 29, 31, 31 \n");
2867}
2868
2869/* TOP = stack[--sp] < TOP
2870 (Unsigned comparison) */
2871
2872static void
2873ppc64_emit_less_unsigned (void)
2874{
2875 EMIT_ASM ("ldu 4, 8(30) \n"
2876 "cmpld 7, 4, 3 \n"
2877 "mfcr 3 \n"
2878 "rlwinm 3, 3, 29, 31, 31 \n");
2879}
2880
2881/* Access the memory address in TOP in size of SIZE.
2882 Zero-extend the read value. */
2883
2884static void
2885ppc64_emit_ref (int size)
2886{
2887 switch (size)
2888 {
2889 case 1:
2890 EMIT_ASM ("lbz 3, 0(3)");
2891 break;
2892 case 2:
2893 EMIT_ASM ("lhz 3, 0(3)");
2894 break;
2895 case 4:
2896 EMIT_ASM ("lwz 3, 0(3)");
2897 break;
2898 case 8:
2899 EMIT_ASM ("ld 3, 0(3)");
2900 break;
2901 }
2902}
2903
2904/* TOP = NUM */
2905
2906static void
2907ppc64_emit_const (LONGEST num)
2908{
2909 uint32_t buf[5];
2910 uint32_t *p = buf;
2911
2912 p += gen_limm (p, 3, num, 1);
2913
2914 emit_insns (buf, p - buf);
2915 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2916}
2917
2918/* Set TOP to the value of register REG by calling get_raw_reg function
2919 with two argument, collected buffer and register number. */
2920
2921static void
2922ppc64v1_emit_reg (int reg)
2923{
2924 uint32_t buf[15];
2925 uint32_t *p = buf;
2926
2927 /* fctx->regs is passed in r3 and then saved in 176(1). */
2928 p += GEN_LD (p, 3, 31, -32);
2929 p += GEN_LI (p, 4, reg);
2930 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
2931 p += gen_call (p, get_raw_reg_func_addr (), 1, 1);
2932 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
2933
2934 emit_insns (buf, p - buf);
2935 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2936}
2937
2938/* Likewise, for ELFv2. */
2939
2940static void
2941ppc64v2_emit_reg (int reg)
2942{
2943 uint32_t buf[12];
2944 uint32_t *p = buf;
2945
2946 /* fctx->regs is passed in r3 and then saved in 176(1). */
2947 p += GEN_LD (p, 3, 31, -32);
2948 p += GEN_LI (p, 4, reg);
2949 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
2950 p += gen_call (p, get_raw_reg_func_addr (), 1, 0);
2951 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
2952
2953 emit_insns (buf, p - buf);
2954 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
2955}
2956
2957/* TOP = stack[--sp] */
2958
2959static void
2960ppc64_emit_pop (void)
2961{
2962 EMIT_ASM ("ldu 3, 8(30)");
2963}
2964
2965/* stack[sp++] = TOP
2966
2967 Because we may use up bytecode stack, expand 8 doublewords more
2968 if needed. */
2969
2970static void
2971ppc64_emit_stack_flush (void)
2972{
2973 /* Make sure bytecode stack is big enough before push.
2974 Otherwise, expand 64-byte more. */
2975
2976 EMIT_ASM (" std 3, 0(30) \n"
2977 " addi 4, 30, -(112 + 8) \n"
2978 " cmpd 7, 4, 1 \n"
2979 " bgt 7, 1f \n"
2980 " stdu 31, -64(1) \n"
2981 "1:addi 30, 30, -8 \n");
2982}
2983
2984/* Swap TOP and stack[sp-1] */
2985
2986static void
2987ppc64_emit_swap (void)
2988{
2989 EMIT_ASM ("ld 4, 8(30) \n"
2990 "std 3, 8(30) \n"
2991 "mr 3, 4 \n");
2992}
2993
2994/* Call function FN - ELFv1. */
2995
2996static void
2997ppc64v1_emit_call (CORE_ADDR fn)
2998{
2999 uint32_t buf[13];
3000 uint32_t *p = buf;
3001
3002 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3003 p += gen_call (p, fn, 1, 1);
3004 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3005
3006 emit_insns (buf, p - buf);
3007 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3008}
3009
3010/* Call function FN - ELFv2. */
3011
3012static void
3013ppc64v2_emit_call (CORE_ADDR fn)
3014{
3015 uint32_t buf[10];
3016 uint32_t *p = buf;
3017
3018 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3019 p += gen_call (p, fn, 1, 0);
3020 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3021
3022 emit_insns (buf, p - buf);
3023 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3024}
3025
3026/* FN's prototype is `LONGEST(*fn)(int)'.
3027 TOP = fn (arg1)
3028 */
3029
3030static void
3031ppc64v1_emit_int_call_1 (CORE_ADDR fn, int arg1)
3032{
3033 uint32_t buf[13];
3034 uint32_t *p = buf;
3035
3036 /* Setup argument. arg1 is a 16-bit value. */
3037 p += gen_limm (p, 3, arg1, 1);
3038 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3039 p += gen_call (p, fn, 1, 1);
3040 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3041
3042 emit_insns (buf, p - buf);
3043 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3044}
3045
3046/* Likewise for ELFv2. */
3047
3048static void
3049ppc64v2_emit_int_call_1 (CORE_ADDR fn, int arg1)
3050{
3051 uint32_t buf[10];
3052 uint32_t *p = buf;
3053
3054 /* Setup argument. arg1 is a 16-bit value. */
3055 p += gen_limm (p, 3, arg1, 1);
3056 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3057 p += gen_call (p, fn, 1, 0);
3058 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3059
3060 emit_insns (buf, p - buf);
3061 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3062}
3063
3064/* FN's prototype is `void(*fn)(int,LONGEST)'.
3065 fn (arg1, TOP)
3066
3067 TOP should be preserved/restored before/after the call. */
3068
3069static void
3070ppc64v1_emit_void_call_2 (CORE_ADDR fn, int arg1)
3071{
3072 uint32_t buf[17];
3073 uint32_t *p = buf;
3074
3075 /* Save TOP. 0(30) is next-empty. */
3076 p += GEN_STD (p, 3, 30, 0);
3077
3078 /* Setup argument. arg1 is a 16-bit value. */
3079 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
3080 p += gen_limm (p, 3, arg1, 1);
3081 p += GEN_STD (p, 2, 1, 40); /* Save TOC. */
3082 p += gen_call (p, fn, 1, 1);
3083 p += GEN_LD (p, 2, 1, 40); /* Restore TOC. */
3084
3085 /* Restore TOP */
3086 p += GEN_LD (p, 3, 30, 0);
3087
3088 emit_insns (buf, p - buf);
3089 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3090}
3091
3092/* Likewise for ELFv2. */
3093
3094static void
3095ppc64v2_emit_void_call_2 (CORE_ADDR fn, int arg1)
3096{
3097 uint32_t buf[14];
3098 uint32_t *p = buf;
3099
3100 /* Save TOP. 0(30) is next-empty. */
3101 p += GEN_STD (p, 3, 30, 0);
3102
3103 /* Setup argument. arg1 is a 16-bit value. */
3104 p += GEN_MR (p, 4, 3); /* mr r4, r3 */
3105 p += gen_limm (p, 3, arg1, 1);
3106 p += GEN_STD (p, 2, 1, 24); /* Save TOC. */
3107 p += gen_call (p, fn, 1, 0);
3108 p += GEN_LD (p, 2, 1, 24); /* Restore TOC. */
3109
3110 /* Restore TOP */
3111 p += GEN_LD (p, 3, 30, 0);
3112
3113 emit_insns (buf, p - buf);
3114 gdb_assert ((p - buf) <= (sizeof (buf) / sizeof (*buf)));
3115}
3116
3117/* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3118
3119static void
3120ppc64_emit_if_goto (int *offset_p, int *size_p)
3121{
3122 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3123 "ldu 3, 8(30) \n"
3124 "1:bne 7, 1b \n");
3125
3126 if (offset_p)
3127 *offset_p = 8;
3128 if (size_p)
3129 *size_p = 14;
3130}
3131
3132/* Goto if stack[--sp] == TOP */
3133
3134static void
3135ppc64_emit_eq_goto (int *offset_p, int *size_p)
3136{
3137 EMIT_ASM ("ldu 4, 8(30) \n"
3138 "cmpd 7, 4, 3 \n"
3139 "ldu 3, 8(30) \n"
3140 "1:beq 7, 1b \n");
3141
3142 if (offset_p)
3143 *offset_p = 12;
3144 if (size_p)
3145 *size_p = 14;
3146}
3147
3148/* Goto if stack[--sp] != TOP */
3149
3150static void
3151ppc64_emit_ne_goto (int *offset_p, int *size_p)
3152{
3153 EMIT_ASM ("ldu 4, 8(30) \n"
3154 "cmpd 7, 4, 3 \n"
3155 "ldu 3, 8(30) \n"
3156 "1:bne 7, 1b \n");
3157
3158 if (offset_p)
3159 *offset_p = 12;
3160 if (size_p)
3161 *size_p = 14;
3162}
3163
3164/* Goto if stack[--sp] < TOP */
3165
3166static void
3167ppc64_emit_lt_goto (int *offset_p, int *size_p)
3168{
3169 EMIT_ASM ("ldu 4, 8(30) \n"
3170 "cmpd 7, 4, 3 \n"
3171 "ldu 3, 8(30) \n"
3172 "1:blt 7, 1b \n");
3173
3174 if (offset_p)
3175 *offset_p = 12;
3176 if (size_p)
3177 *size_p = 14;
3178}
3179
3180/* Goto if stack[--sp] <= TOP */
3181
3182static void
3183ppc64_emit_le_goto (int *offset_p, int *size_p)
3184{
3185 EMIT_ASM ("ldu 4, 8(30) \n"
3186 "cmpd 7, 4, 3 \n"
3187 "ldu 3, 8(30) \n"
3188 "1:ble 7, 1b \n");
3189
3190 if (offset_p)
3191 *offset_p = 12;
3192 if (size_p)
3193 *size_p = 14;
3194}
3195
3196/* Goto if stack[--sp] > TOP */
3197
3198static void
3199ppc64_emit_gt_goto (int *offset_p, int *size_p)
3200{
3201 EMIT_ASM ("ldu 4, 8(30) \n"
3202 "cmpd 7, 4, 3 \n"
3203 "ldu 3, 8(30) \n"
3204 "1:bgt 7, 1b \n");
3205
3206 if (offset_p)
3207 *offset_p = 12;
3208 if (size_p)
3209 *size_p = 14;
3210}
3211
3212/* Goto if stack[--sp] >= TOP */
3213
3214static void
3215ppc64_emit_ge_goto (int *offset_p, int *size_p)
3216{
3217 EMIT_ASM ("ldu 4, 8(30) \n"
3218 "cmpd 7, 4, 3 \n"
3219 "ldu 3, 8(30) \n"
3220 "1:bge 7, 1b \n");
3221
3222 if (offset_p)
3223 *offset_p = 12;
3224 if (size_p)
3225 *size_p = 14;
3226}
3227
3228/* Table of emit ops for 64-bit ELFv1. */
3229
3230static struct emit_ops ppc64v1_emit_ops_impl =
3231{
3232 ppc64v1_emit_prologue,
3233 ppc64_emit_epilogue,
3234 ppc64_emit_add,
3235 ppc64_emit_sub,
3236 ppc64_emit_mul,
3237 ppc64_emit_lsh,
3238 ppc64_emit_rsh_signed,
3239 ppc64_emit_rsh_unsigned,
3240 ppc64_emit_ext,
3241 ppc64_emit_log_not,
3242 ppc64_emit_bit_and,
3243 ppc64_emit_bit_or,
3244 ppc64_emit_bit_xor,
3245 ppc64_emit_bit_not,
3246 ppc64_emit_equal,
3247 ppc64_emit_less_signed,
3248 ppc64_emit_less_unsigned,
3249 ppc64_emit_ref,
3250 ppc64_emit_if_goto,
3251 ppc_emit_goto,
3252 ppc_write_goto_address,
3253 ppc64_emit_const,
3254 ppc64v1_emit_call,
3255 ppc64v1_emit_reg,
3256 ppc64_emit_pop,
3257 ppc64_emit_stack_flush,
3258 ppc64_emit_zero_ext,
3259 ppc64_emit_swap,
3260 ppc_emit_stack_adjust,
3261 ppc64v1_emit_int_call_1,
3262 ppc64v1_emit_void_call_2,
3263 ppc64_emit_eq_goto,
3264 ppc64_emit_ne_goto,
3265 ppc64_emit_lt_goto,
3266 ppc64_emit_le_goto,
3267 ppc64_emit_gt_goto,
3268 ppc64_emit_ge_goto
3269};
3270
3271/* Table of emit ops for 64-bit ELFv2. */
3272
3273static struct emit_ops ppc64v2_emit_ops_impl =
3274{
3275 ppc64v2_emit_prologue,
3276 ppc64_emit_epilogue,
3277 ppc64_emit_add,
3278 ppc64_emit_sub,
3279 ppc64_emit_mul,
3280 ppc64_emit_lsh,
3281 ppc64_emit_rsh_signed,
3282 ppc64_emit_rsh_unsigned,
3283 ppc64_emit_ext,
3284 ppc64_emit_log_not,
3285 ppc64_emit_bit_and,
3286 ppc64_emit_bit_or,
3287 ppc64_emit_bit_xor,
3288 ppc64_emit_bit_not,
3289 ppc64_emit_equal,
3290 ppc64_emit_less_signed,
3291 ppc64_emit_less_unsigned,
3292 ppc64_emit_ref,
3293 ppc64_emit_if_goto,
3294 ppc_emit_goto,
3295 ppc_write_goto_address,
3296 ppc64_emit_const,
3297 ppc64v2_emit_call,
3298 ppc64v2_emit_reg,
3299 ppc64_emit_pop,
3300 ppc64_emit_stack_flush,
3301 ppc64_emit_zero_ext,
3302 ppc64_emit_swap,
3303 ppc_emit_stack_adjust,
3304 ppc64v2_emit_int_call_1,
3305 ppc64v2_emit_void_call_2,
3306 ppc64_emit_eq_goto,
3307 ppc64_emit_ne_goto,
3308 ppc64_emit_lt_goto,
3309 ppc64_emit_le_goto,
3310 ppc64_emit_gt_goto,
3311 ppc64_emit_ge_goto
3312};
3313
3314#endif
3315
3316/* Implementation of linux_target_ops method "emit_ops". */
3317
3318static struct emit_ops *
3319ppc_emit_ops (void)
3320{
3321#ifdef __powerpc64__
3322 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3323
3324 if (register_size (regcache->tdesc, 0) == 8)
3325 {
3326 if (is_elfv2_inferior ())
3327 return &ppc64v2_emit_ops_impl;
3328 else
3329 return &ppc64v1_emit_ops_impl;
3330 }
3331#endif
3332 return &ppc_emit_ops_impl;
3333}
3334
a2174ba4
MK		 3335/* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3336
3337static int
3338ppc_get_ipa_tdesc_idx (void)
3339{
3340 struct regcache *regcache = get_thread_regcache (current_thread, 0);
3341 const struct target_desc *tdesc = regcache->tdesc;
3342
3343#ifdef __powerpc64__
3344 if (tdesc == tdesc_powerpc_64l)
3345 return PPC_TDESC_BASE;
3346 if (tdesc == tdesc_powerpc_altivec64l)
3347 return PPC_TDESC_ALTIVEC;
a2174ba4
MK		 3348 if (tdesc == tdesc_powerpc_vsx64l)
3349 return PPC_TDESC_VSX;
3350 if (tdesc == tdesc_powerpc_isa205_64l)
3351 return PPC_TDESC_ISA205;
3352 if (tdesc == tdesc_powerpc_isa205_altivec64l)
3353 return PPC_TDESC_ISA205_ALTIVEC;
3354 if (tdesc == tdesc_powerpc_isa205_vsx64l)
3355 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3356 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l)
3357 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3358 if (tdesc == tdesc_powerpc_isa207_vsx64l)
3359 return PPC_TDESC_ISA207_VSX;
8d619c01
EBM		 3360 if (tdesc == tdesc_powerpc_isa207_htm_vsx64l)
3361 return PPC_TDESC_ISA207_HTM_VSX;
a2174ba4
MK		 3362#endif
3363
3364 if (tdesc == tdesc_powerpc_32l)
3365 return PPC_TDESC_BASE;
3366 if (tdesc == tdesc_powerpc_altivec32l)
3367 return PPC_TDESC_ALTIVEC;
a2174ba4
MK		 3368 if (tdesc == tdesc_powerpc_vsx32l)
3369 return PPC_TDESC_VSX;
3370 if (tdesc == tdesc_powerpc_isa205_32l)
3371 return PPC_TDESC_ISA205;
3372 if (tdesc == tdesc_powerpc_isa205_altivec32l)
3373 return PPC_TDESC_ISA205_ALTIVEC;
3374 if (tdesc == tdesc_powerpc_isa205_vsx32l)
3375 return PPC_TDESC_ISA205_VSX;
7ca18ed6
EBM		 3376 if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l)
3377 return PPC_TDESC_ISA205_PPR_DSCR_VSX;
f2cf6173
EBM		 3378 if (tdesc == tdesc_powerpc_isa207_vsx32l)
3379 return PPC_TDESC_ISA207_VSX;
8d619c01
EBM		 3380 if (tdesc == tdesc_powerpc_isa207_htm_vsx32l)
3381 return PPC_TDESC_ISA207_HTM_VSX;
a2174ba4
MK		 3382 if (tdesc == tdesc_powerpc_e500l)
3383 return PPC_TDESC_E500;
3384
3385 return 0;
3386}
3387
2ec06d2e 3388struct linux_target_ops the_low_target = {
3aee8918 3389 ppc_regs_info,
2ec06d2e
DJ		 3390 ppc_cannot_fetch_register,
3391 ppc_cannot_store_register,
c14dfd32 3392 NULL, /* fetch_register */
0d62e5e8
DJ		 3393 ppc_get_pc,
3394 ppc_set_pc,
dd373349
AT		 3395 NULL, /* breakpoint_kind_from_pc */
3396 ppc_sw_breakpoint_from_kind,
0d62e5e8
DJ		 3397 NULL,
3398 0,
3399 ppc_breakpoint_at,
657f9cde
WW		 3400 ppc_supports_z_point_type,
3401 ppc_insert_point,
3402 ppc_remove_point,
5b0a002e
UW		 3403 NULL,
3404 NULL,
3405 ppc_collect_ptrace_register,
3406 ppc_supply_ptrace_register,
7d00775e
AT		 3407 NULL, /* siginfo_fixup */
3408 NULL, /* new_process */
04ec7890 3409 NULL, /* delete_process */
7d00775e 3410 NULL, /* new_thread */
466eecee 3411 NULL, /* delete_thread */
7d00775e
AT		 3412 NULL, /* new_fork */
3413 NULL, /* prepare_to_resume */
3414 NULL, /* process_qsupported */
b04fd3be 3415 ppc_supports_tracepoints,
a2174ba4
MK		 3416 ppc_get_thread_area,
3417 ppc_install_fast_tracepoint_jump_pad,
14e2b6d9 3418 ppc_emit_ops,
a2174ba4 3419 ppc_get_min_fast_tracepoint_insn_len,
7d00775e
AT		 3420 NULL, /* supports_range_stepping */
3421 NULL, /* breakpoint_kind_from_current_state */
3422 ppc_supports_hardware_single_step,
a2174ba4
MK		 3423 NULL, /* get_syscall_trapinfo */
3424 ppc_get_ipa_tdesc_idx,
2ec06d2e 3425};
3aee8918 3426
ef0478f6
TBA		 3427/* The linux target ops object. */
3428
3429linux_process_target *the_linux_target = &the_ppc_target;
3430
3aee8918
PA		 3431void
3432initialize_low_arch (void)
3433{
3434 /* Initialize the Linux target descriptions. */
3435
3436 init_registers_powerpc_32l ();
3437 init_registers_powerpc_altivec32l ();
3aee8918
PA		 3438 init_registers_powerpc_vsx32l ();
3439 init_registers_powerpc_isa205_32l ();
3440 init_registers_powerpc_isa205_altivec32l ();
3441 init_registers_powerpc_isa205_vsx32l ();
7ca18ed6 3442 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
f2cf6173 3443 init_registers_powerpc_isa207_vsx32l ();
8d619c01 3444 init_registers_powerpc_isa207_htm_vsx32l ();
3aee8918 3445 init_registers_powerpc_e500l ();
a2174ba4 3446#if __powerpc64__
3aee8918
PA		 3447 init_registers_powerpc_64l ();
3448 init_registers_powerpc_altivec64l ();
3aee8918
PA		 3449 init_registers_powerpc_vsx64l ();
3450 init_registers_powerpc_isa205_64l ();
3451 init_registers_powerpc_isa205_altivec64l ();
3452 init_registers_powerpc_isa205_vsx64l ();
7ca18ed6 3453 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
f2cf6173 3454 init_registers_powerpc_isa207_vsx64l ();
8d619c01 3455 init_registers_powerpc_isa207_htm_vsx64l ();
a2174ba4 3456#endif
3aee8918
PA		 3457
3458 initialize_regsets_info (&ppc_regsets_info);
3459}
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