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c609719b 1/*
a20b27a3 2 * (C) Copyright 2001-2004
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3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
3765b3e7 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c609719b 21#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
c837dcb1 22#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
6f35c531 23#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
c609719b 24
2ae18241
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25#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
26
c837dcb1 27#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
3a8f28d0 28#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
c609719b 29
a20b27a3 30#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
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31
32#define CONFIG_BAUDRATE 9600
c609719b 33
c609719b 34#undef CONFIG_BOOTARGS
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35#undef CONFIG_BOOTCOMMAND
36
37#define CONFIG_PREBOOT /* enable preboot variable */
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38
39#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf 40#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
c609719b 41
96e21f86 42#define CONFIG_PPC4xx_EMAC
c609719b 43#define CONFIG_MII 1 /* MII PHY management */
c837dcb1 44#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3 45#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
6f35c531
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46#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
47
6f35c531 48#undef CONFIG_HAS_ETH1
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49
50#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
51
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52/*
53 * BOOTP options
54 */
55#define CONFIG_BOOTP_SUBNETMASK
56#define CONFIG_BOOTP_GATEWAY
57#define CONFIG_BOOTP_HOSTNAME
58#define CONFIG_BOOTP_BOOTPATH
59#define CONFIG_BOOTP_DNS
60#define CONFIG_BOOTP_DNS2
61#define CONFIG_BOOTP_SEND_HOSTNAME
62
49cf7e8e
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63/*
64 * Command line configuration.
65 */
49cf7e8e
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66#define CONFIG_CMD_PCI
67#define CONFIG_CMD_IRQ
68#define CONFIG_CMD_IDE
49cf7e8e 69#define CONFIG_CMD_DATE
49cf7e8e
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70#define CONFIG_CMD_BSP
71#define CONFIG_CMD_EEPROM
72
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73#define CONFIG_MAC_PARTITION
74#define CONFIG_DOS_PARTITION
75
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76#define CONFIG_SUPPORT_VFAT
77
c837dcb1 78#undef CONFIG_WATCHDOG /* watchdog disabled */
c609719b 79
c837dcb1 80#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
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81
82/*
83 * Miscellaneous configurable options
84 */
c6265f7f 85#undef CONFIG_SYS_LONGHELP /* undef to save memory */
c609719b 86
49cf7e8e 87#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 88#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b 89#else
6d0f6bcf 90#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c609719b 91#endif
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92#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
93#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
94#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c609719b 95
6d0f6bcf 96#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
c609719b 97
6d0f6bcf 98#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
c609719b 99
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100#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
101#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
c609719b 102
550650dd 103#define CONFIG_CONS_INDEX 1 /* Use UART0 */
550650dd
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104#define CONFIG_SYS_NS16550_SERIAL
105#define CONFIG_SYS_NS16550_REG_SIZE 1
106#define CONFIG_SYS_NS16550_CLK get_serial_clock()
107
6d0f6bcf 108#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
6d0f6bcf 109#define CONFIG_SYS_BASE_BAUD 691200
c609719b 110
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111#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
112#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
c609719b 113
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114#define CONFIG_CMDLINE_EDITING /* add command line history */
115
6d0f6bcf 116#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
53cf9435 117
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118/*-----------------------------------------------------------------------
119 * PCI stuff
120 *-----------------------------------------------------------------------
121 */
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122#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
123#define PCI_HOST_FORCE 1 /* configure as pci host */
124#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
125
126#define CONFIG_PCI /* include pci support */
842033e6 127#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
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128#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
129#define CONFIG_PCI_PNP /* do pci plug-and-play */
130 /* resource configuration */
131
132#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
133
134#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
135
136#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
137
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138#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
139#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
140#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
141#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
142#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
143#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
144#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
145#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
146#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
468ebf19 147#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
c609719b 148
82379b55
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149#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
150
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151/*-----------------------------------------------------------------------
152 * IDE/ATA stuff
153 *-----------------------------------------------------------------------
154 */
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155#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
156#undef CONFIG_IDE_LED /* no led for ide supported */
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157#define CONFIG_IDE_RESET 1 /* reset for ide supported */
158
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159#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
160#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
c609719b 161
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162#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
163#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
c609719b 164
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165#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
166#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
167#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
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168
169/*-----------------------------------------------------------------------
170 * Start addresses for the final memory configuration
171 * (Set up by the startup code)
6d0f6bcf 172 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b 173 */
6d0f6bcf
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174#define CONFIG_SYS_SDRAM_BASE 0x00000000
175#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
176#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
177#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
178#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
c609719b 179
3ba605d4
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180#define CONFIG_PRAM 0 /* use pram variable to overwrite */
181
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182/*
183 * For booting Linux, the board info and command line data
184 * have to be in the first 8 MB of memory, since this is
185 * the maximum mapped by the Linux kernel during initialization.
186 */
6d0f6bcf 187#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
ac53ee83 188
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189/*-----------------------------------------------------------------------
190 * FLASH organization
191 */
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192#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
193#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
c609719b 194
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195#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
196#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b 197
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198#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
199#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
200#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
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201/*
202 * The following defines are added for buggy IOP480 byte interface.
203 * All other boards should use the standard values (CPCI405 etc.)
204 */
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205#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
206#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
207#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
c609719b 208
6d0f6bcf 209#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
c609719b 210
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211#if 0 /* Use NVRAM for environment variables */
212/*-----------------------------------------------------------------------
213 * NVRAM organization
214 */
9314cee6 215#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
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216#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
217#define CONFIG_ENV_ADDR \
6d0f6bcf 218 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
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219
220#else /* Use EEPROM for environment variables */
221
bb1f8b4f 222#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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223#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
224#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
8bde7f77 225 /* total size of a CAT24WC16 is 2048 bytes */
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226#endif
227
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228#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
229#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
230#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
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231
232/*-----------------------------------------------------------------------
233 * I2C EEPROM (CAT24WC16) for environment
234 */
880540de
DE
235#define CONFIG_SYS_I2C
236#define CONFIG_SYS_I2C_PPC4XX
237#define CONFIG_SYS_I2C_PPC4XX_CH0
238#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
239#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
c609719b 240
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241#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
242#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1 243/* mask of address bits that overflow into the "EEPROM chip address" */
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244#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
245#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
c609719b 246 /* 16 byte page write mode using*/
c837dcb1 247 /* last 4 bits of the address */
6d0f6bcf 248#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
c609719b 249
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250/*
251 * Init Memory Controller:
252 *
253 * BR0/1 and OR0/1 (FLASH)
254 */
255
256#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
257#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
258
259/*-----------------------------------------------------------------------
260 * External Bus Controller (EBC) Setup
261 */
262
c837dcb1 263/* Memory Bank 0 (Flash Bank 0) initialization */
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264#define CONFIG_SYS_EBC_PB0AP 0x92015480
265#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
c609719b 266
c837dcb1 267/* Memory Bank 1 (Flash Bank 1) initialization */
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268#define CONFIG_SYS_EBC_PB1AP 0x92015480
269#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
c609719b 270
c837dcb1 271/* Memory Bank 2 (CAN0, 1) initialization */
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272#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
273#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
274#define CONFIG_SYS_LED_ADDR 0xF0000380
c609719b 275
c837dcb1 276/* Memory Bank 3 (CompactFlash IDE) initialization */
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277#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
278#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
c609719b 279
c837dcb1 280/* Memory Bank 4 (NVRAM/RTC) initialization */
6d0f6bcf
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281/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
282#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
283#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
c609719b 284
c837dcb1 285/* Memory Bank 5 (optional Quart) initialization */
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286#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
287#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
c609719b 288
c837dcb1 289/* Memory Bank 6 (FPGA internal) initialization */
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290#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
291#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
292#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
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293
294/*-----------------------------------------------------------------------
295 * FPGA stuff
296 */
297/* FPGA internal regs */
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298#define CONFIG_SYS_FPGA_MODE 0x00
299#define CONFIG_SYS_FPGA_STATUS 0x02
300#define CONFIG_SYS_FPGA_TS 0x04
301#define CONFIG_SYS_FPGA_TS_LOW 0x06
302#define CONFIG_SYS_FPGA_TS_CAP0 0x10
303#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
304#define CONFIG_SYS_FPGA_TS_CAP1 0x14
305#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
306#define CONFIG_SYS_FPGA_TS_CAP2 0x18
307#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
308#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
309#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
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310
311/* FPGA Mode Reg */
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312#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
313#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
314#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
315#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
316#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
317#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
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318
319/* FPGA Status Reg */
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320#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
321#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
322#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
323#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
324#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
c609719b 325
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326#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
327#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
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328
329/* FPGA program pin configuration */
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330#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
331#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
332#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
333#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
334#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
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335
336/*-----------------------------------------------------------------------
337 * Definitions for initial stack pointer and data area (in data cache)
338 */
6d0f6bcf 339#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
c609719b 340
6d0f6bcf 341#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
553f0982 342#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
25ddd1fb 343#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 344#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c609719b 345
c609719b 346#endif /* __CONFIG_H */