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96b8a054 SW |
1 | /* |
2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
96b8a054 SW |
21 | */ |
22 | /* | |
23 | * mpc8313epb board configuration file | |
24 | */ | |
25 | ||
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | /* | |
30 | * High Level Configuration Options | |
31 | */ | |
32 | #define CONFIG_E300 1 | |
33 | #define CONFIG_MPC83XX 1 | |
34 | #define CONFIG_MPC831X 1 | |
35 | #define CONFIG_MPC8313 1 | |
36 | #define CONFIG_MPC8313ERDB 1 | |
37 | ||
38 | #define CONFIG_PCI | |
39 | #define CONFIG_83XX_GENERIC_PCI | |
40 | ||
89c7784e TT |
41 | #define CONFIG_MISC_INIT_R |
42 | ||
43 | /* | |
44 | * On-board devices | |
4ce1e23b YS |
45 | * |
46 | * TSEC1 is VSC switch | |
47 | * TSEC2 is SoC TSEC | |
89c7784e TT |
48 | */ |
49 | #define CONFIG_VSC7385_ENET | |
4ce1e23b | 50 | #define CONFIG_TSEC2 |
89c7784e | 51 | |
96b8a054 | 52 | #ifdef CFG_66MHZ |
5c5d3242 | 53 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ |
96b8a054 | 54 | #elif defined(CFG_33MHZ) |
5c5d3242 | 55 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ |
96b8a054 SW |
56 | #else |
57 | #error Unknown oscillator frequency. | |
58 | #endif | |
59 | ||
60 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
61 | ||
62 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
63 | ||
64 | #define CFG_IMMR 0xE0000000 | |
65 | ||
66 | #define CFG_MEMTEST_START 0x00001000 | |
67 | #define CFG_MEMTEST_END 0x07f00000 | |
68 | ||
69 | /* Early revs of this board will lock up hard when attempting | |
70 | * to access the PMC registers, unless a JTAG debugger is | |
71 | * connected, or some resistor modifications are made. | |
72 | */ | |
73 | #define CFG_8313ERDB_BROKEN_PMC 1 | |
74 | ||
75 | #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ | |
76 | #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
77 | ||
89c7784e TT |
78 | /* |
79 | * Device configurations | |
80 | */ | |
81 | ||
82 | /* Vitesse 7385 */ | |
83 | ||
84 | #ifdef CONFIG_VSC7385_ENET | |
85 | ||
4ce1e23b | 86 | #define CONFIG_TSEC1 |
89c7784e TT |
87 | |
88 | /* The flash address and size of the VSC7385 firmware image */ | |
89 | #define CONFIG_VSC7385_IMAGE 0xFE7FE000 | |
90 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
91 | ||
92 | #endif | |
93 | ||
96b8a054 SW |
94 | /* |
95 | * DDR Setup | |
96 | */ | |
97 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ | |
98 | #define CFG_SDRAM_BASE CFG_DDR_BASE | |
99 | #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE | |
100 | ||
101 | /* | |
102 | * Manually set up DDR parameters, as this board does not | |
103 | * seem to have the SPD connected to I2C. | |
104 | */ | |
105 | #define CFG_DDR_SIZE 128 /* MB */ | |
e1d8ed2c PA |
106 | #define CFG_DDR_CONFIG ( CSCONFIG_EN \ |
107 | | 0x00010000 /* TODO */ \ | |
96b8a054 | 108 | | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) |
e1d8ed2c | 109 | /* 0x80010102 */ |
96b8a054 SW |
110 | |
111 | #define CFG_DDR_TIMING_3 0x00000000 | |
112 | #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ | |
113 | | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ | |
114 | | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ | |
115 | | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ | |
116 | | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ | |
117 | | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ | |
118 | | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | |
119 | | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) | |
120 | /* 0x00220802 */ | |
121 | #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ | |
e1d8ed2c | 122 | | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ |
96b8a054 SW |
123 | | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ |
124 | | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ | |
e1d8ed2c | 125 | | (10 << TIMING_CFG1_REFREC_SHIFT ) \ |
96b8a054 SW |
126 | | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ |
127 | | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | |
128 | | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) | |
e1d8ed2c PA |
129 | /* 0x3835a322 */ |
130 | #define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ | |
131 | | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ | |
96b8a054 SW |
132 | | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ |
133 | | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | |
134 | | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | |
135 | | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ | |
e1d8ed2c PA |
136 | | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) ) |
137 | /* 0x129048c6 */ /* P9-45,may need tuning */ | |
138 | #define CFG_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \ | |
139 | | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) | |
140 | /* 0x05100500 */ | |
96b8a054 SW |
141 | #if defined(CONFIG_DDR_2T_TIMING) |
142 | #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ | |
bbea46f7 | 143 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
96b8a054 SW |
144 | | SDRAM_CFG_2T_EN \ |
145 | | SDRAM_CFG_DBW_32 ) | |
146 | #else | |
147 | #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ | |
bbea46f7 | 148 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
96b8a054 SW |
149 | | SDRAM_CFG_32_BE ) |
150 | /* 0x43080000 */ | |
151 | #endif | |
152 | #define CFG_SDRAM_CFG2 0x00401000; | |
153 | /* set burst length to 8 for 32-bit data path */ | |
e1d8ed2c PA |
154 | #define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ |
155 | | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) | |
156 | /* 0x44480632 */ | |
96b8a054 SW |
157 | #define CFG_DDR_MODE_2 0x8000C000; |
158 | ||
159 | #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
160 | /*0x02000000*/ | |
161 | #define CFG_DDRCDR_VALUE ( DDRCDR_EN \ | |
162 | | DDRCDR_PZ_NOMZ \ | |
163 | | DDRCDR_NZ_NOMZ \ | |
164 | | DDRCDR_M_ODR ) | |
165 | ||
166 | /* | |
167 | * FLASH on the Local Bus | |
168 | */ | |
169 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ | |
170 | #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
171 | #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ | |
172 | #define CFG_FLASH_SIZE 8 /* flash size in MB */ | |
173 | #define CFG_FLASH_EMPTY_INFO /* display empty sectors */ | |
174 | #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ | |
175 | ||
a7676ea7 WD |
176 | #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ |
177 | (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ | |
178 | BR_V) /* valid */ | |
179 | #define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ | |
96b8a054 SW |
180 | | OR_GPCM_XACS \ |
181 | | OR_GPCM_SCY_9 \ | |
182 | | OR_GPCM_EHTR \ | |
183 | | OR_GPCM_EAD ) | |
184 | /* 0xFF006FF7 TODO SLOW 16 MB flash size */ | |
185 | #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ | |
186 | #define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ | |
187 | ||
188 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
189 | #define CFG_MAX_FLASH_SECT 135 /* sectors per device */ | |
190 | ||
191 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
192 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
193 | ||
194 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
195 | ||
196 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
197 | #define CFG_RAMBOOT | |
198 | #endif | |
199 | ||
200 | #define CFG_INIT_RAM_LOCK 1 | |
201 | #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ | |
202 | #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ | |
203 | ||
204 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
205 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
206 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
207 | ||
b2893e1f | 208 | /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ |
96b8a054 SW |
209 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
210 | #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
211 | ||
212 | /* | |
213 | * Local Bus LCRR and LBCR regs | |
214 | */ | |
4ce1e23b | 215 | #define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4 |
96b8a054 SW |
216 | #define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ |
217 | | (0xFF << LBCR_BMT_SHIFT) \ | |
218 | | 0xF ) /* 0x0004ff0f */ | |
219 | ||
a7676ea7 | 220 | #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ |
96b8a054 | 221 | |
7817cb20 | 222 | /* drivers/mtd/nand/nand.c */ |
a7676ea7 | 223 | #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ |
96b8a054 SW |
224 | #define CFG_MAX_NAND_DEVICE 1 |
225 | #define NAND_MAX_CHIPS 1 | |
226 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
227 | ||
228 | #define CFG_BR1_PRELIM ( CFG_NAND_BASE \ | |
a7676ea7 WD |
229 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
230 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
231 | | BR_MS_FCM /* MSEL = FCM */ \ | |
232 | | BR_V ) /* valid */ | |
233 | #define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ | |
96b8a054 SW |
234 | | OR_FCM_CSCT \ |
235 | | OR_FCM_CST \ | |
236 | | OR_FCM_CHT \ | |
237 | | OR_FCM_SCY_1 \ | |
238 | | OR_FCM_TRLX \ | |
239 | | OR_FCM_EHTR ) | |
240 | /* 0xFFFF8396 */ | |
241 | #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE | |
242 | #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ | |
243 | ||
89c7784e TT |
244 | /* local bus read write buffer mapping */ |
245 | #define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ | |
246 | #define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ | |
247 | #define CFG_LBLAWBAR3_PRELIM 0xFA000000 | |
248 | #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ | |
249 | ||
250 | /* Vitesse 7385 */ | |
251 | ||
96b8a054 SW |
252 | #define CFG_VSC7385_BASE 0xF0000000 |
253 | ||
89c7784e TT |
254 | #ifdef CONFIG_VSC7385_ENET |
255 | ||
96b8a054 SW |
256 | #define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ |
257 | #define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ | |
258 | #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */ | |
259 | #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ | |
260 | ||
89c7784e | 261 | #endif |
96b8a054 SW |
262 | |
263 | /* pass open firmware flat tree */ | |
35cc4e48 | 264 | #define CONFIG_OF_LIBFDT 1 |
96b8a054 | 265 | #define CONFIG_OF_BOARD_SETUP 1 |
5b8bc606 | 266 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
96b8a054 SW |
267 | |
268 | /* | |
269 | * Serial Port | |
270 | */ | |
271 | #define CONFIG_CONS_INDEX 1 | |
272 | #define CFG_NS16550 | |
273 | #define CFG_NS16550_SERIAL | |
274 | #define CFG_NS16550_REG_SIZE 1 | |
275 | #define CFG_NS16550_CLK get_bus_freq(0) | |
276 | ||
277 | #define CFG_BAUDRATE_TABLE \ | |
278 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
279 | ||
280 | #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) | |
281 | #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) | |
282 | ||
283 | /* Use the HUSH parser */ | |
284 | #define CFG_HUSH_PARSER | |
285 | #define CFG_PROMPT_HUSH_PS2 "> " | |
286 | ||
287 | /* I2C */ | |
288 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
289 | #define CONFIG_FSL_I2C | |
290 | #define CONFIG_I2C_MULTI_BUS | |
291 | #define CONFIG_I2C_CMD_TREE | |
292 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
293 | #define CFG_I2C_SLAVE 0x7F | |
cdd917a4 | 294 | #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
96b8a054 SW |
295 | #define CFG_I2C_OFFSET 0x3000 |
296 | #define CFG_I2C2_OFFSET 0x3100 | |
297 | ||
96b8a054 SW |
298 | /* |
299 | * General PCI | |
300 | * Addresses are mapped 1-1. | |
301 | */ | |
302 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
303 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
304 | #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
305 | #define CFG_PCI1_MMIO_BASE 0x90000000 | |
306 | #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE | |
307 | #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
308 | #define CFG_PCI1_IO_BASE 0x00000000 | |
309 | #define CFG_PCI1_IO_PHYS 0xE2000000 | |
310 | #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
311 | ||
312 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
313 | #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
314 | ||
315 | /* | |
89c7784e | 316 | * TSEC |
96b8a054 SW |
317 | */ |
318 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
319 | ||
89c7784e TT |
320 | #define CONFIG_NET_MULTI |
321 | #define CONFIG_GMII /* MII PHY management */ | |
96b8a054 | 322 | |
89c7784e TT |
323 | #ifdef CONFIG_TSEC1 |
324 | #define CONFIG_HAS_ETH0 | |
255a3577 | 325 | #define CONFIG_TSEC1_NAME "TSEC0" |
89c7784e TT |
326 | #define CFG_TSEC1_OFFSET 0x24000 |
327 | #define TSEC1_PHY_ADDR 0x1c | |
328 | #define TSEC1_FLAGS TSEC_GIGABIT | |
329 | #define TSEC1_PHYIDX 0 | |
330 | #endif | |
331 | ||
332 | #ifdef CONFIG_TSEC2 | |
333 | #define CONFIG_HAS_ETH1 | |
255a3577 | 334 | #define CONFIG_TSEC2_NAME "TSEC1" |
89c7784e TT |
335 | #define CFG_TSEC2_OFFSET 0x25000 |
336 | #define TSEC2_PHY_ADDR 4 | |
337 | #define TSEC2_FLAGS TSEC_GIGABIT | |
338 | #define TSEC2_PHYIDX 0 | |
339 | #endif | |
340 | ||
96b8a054 SW |
341 | |
342 | /* Options are: TSEC[0-1] */ | |
343 | #define CONFIG_ETHPRIME "TSEC1" | |
344 | ||
345 | /* | |
346 | * Configure on-board RTC | |
347 | */ | |
348 | #define CONFIG_RTC_DS1337 | |
349 | #define CFG_I2C_RTC_ADDR 0x68 | |
350 | ||
351 | /* | |
352 | * Environment | |
353 | */ | |
354 | #ifndef CFG_RAMBOOT | |
355 | #define CFG_ENV_IS_IN_FLASH 1 | |
b2893e1f | 356 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
96b8a054 SW |
357 | #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
358 | #define CFG_ENV_SIZE 0x2000 | |
359 | ||
360 | /* Address and size of Redundant Environment Sector */ | |
361 | #else | |
362 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
363 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
364 | #define CFG_ENV_SIZE 0x2000 | |
365 | #endif | |
366 | ||
367 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
368 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
369 | ||
079a136c JL |
370 | /* |
371 | * BOOTP options | |
372 | */ | |
373 | #define CONFIG_BOOTP_BOOTFILESIZE | |
374 | #define CONFIG_BOOTP_BOOTPATH | |
375 | #define CONFIG_BOOTP_GATEWAY | |
376 | #define CONFIG_BOOTP_HOSTNAME | |
377 | ||
378 | ||
8ea5499a JL |
379 | /* |
380 | * Command line configuration. | |
381 | */ | |
382 | #include <config_cmd_default.h> | |
96b8a054 | 383 | |
8ea5499a JL |
384 | #define CONFIG_CMD_PING |
385 | #define CONFIG_CMD_DHCP | |
386 | #define CONFIG_CMD_I2C | |
387 | #define CONFIG_CMD_MII | |
388 | #define CONFIG_CMD_DATE | |
389 | #define CONFIG_CMD_PCI | |
96b8a054 SW |
390 | |
391 | #if defined(CFG_RAMBOOT) | |
8ea5499a JL |
392 | #undef CONFIG_CMD_ENV |
393 | #undef CONFIG_CMD_LOADS | |
96b8a054 SW |
394 | #endif |
395 | ||
8ea5499a JL |
396 | #define CONFIG_CMDLINE_EDITING 1 |
397 | ||
96b8a054 SW |
398 | |
399 | /* | |
400 | * Miscellaneous configurable options | |
401 | */ | |
402 | #define CFG_LONGHELP /* undef to save memory */ | |
403 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
404 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
405 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
406 | ||
a7676ea7 | 407 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
96b8a054 SW |
408 | #define CFG_MAXARGS 16 /* max number of command args */ |
409 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
410 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
411 | ||
412 | /* | |
413 | * For booting Linux, the board info and command line data | |
414 | * have to be in the first 8 MB of memory, since this is | |
415 | * the maximum mapped by the Linux kernel during initialization. | |
416 | */ | |
417 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
418 | ||
a7676ea7 | 419 | #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
96b8a054 SW |
420 | |
421 | #ifdef CFG_66MHZ | |
422 | ||
423 | /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ | |
424 | /* 0x62040000 */ | |
425 | #define CFG_HRCW_LOW (\ | |
426 | 0x20000000 /* reserved, must be set */ |\ | |
427 | HRCWL_DDRCM |\ | |
428 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
429 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
430 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
431 | HRCWL_CORE_TO_CSB_2X1) | |
432 | ||
433 | #elif defined(CFG_33MHZ) | |
434 | ||
435 | /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ | |
436 | /* 0x65040000 */ | |
437 | #define CFG_HRCW_LOW (\ | |
438 | 0x20000000 /* reserved, must be set */ |\ | |
439 | HRCWL_DDRCM |\ | |
440 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
441 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
442 | HRCWL_CSB_TO_CLKIN_5X1 |\ | |
443 | HRCWL_CORE_TO_CSB_2X1) | |
444 | ||
445 | #endif | |
446 | ||
447 | /* 0xa0606c00 */ | |
448 | #define CFG_HRCW_HIGH (\ | |
449 | HRCWH_PCI_HOST |\ | |
450 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
451 | HRCWH_CORE_ENABLE |\ | |
452 | HRCWH_FROM_0X00000100 |\ | |
453 | HRCWH_BOOTSEQ_DISABLE |\ | |
454 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
455 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
456 | HRCWH_RL_EXT_LEGACY |\ | |
457 | HRCWH_TSEC1M_IN_RGMII |\ | |
458 | HRCWH_TSEC2M_IN_RGMII |\ | |
459 | HRCWH_BIG_ENDIAN |\ | |
460 | HRCWH_LALE_NORMAL) | |
461 | ||
462 | /* System IO Config */ | |
a7676ea7 WD |
463 | #define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ |
464 | #define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ | |
96b8a054 SW |
465 | |
466 | #define CFG_HID0_INIT 0x000000000 | |
467 | #define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
a7676ea7 | 468 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) |
96b8a054 SW |
469 | |
470 | #define CFG_HID2 HID2_HBE | |
471 | ||
472 | /* DDR @ 0x00000000 */ | |
473 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) | |
474 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
475 | ||
476 | /* PCI @ 0x80000000 */ | |
477 | #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10) | |
478 | #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
479 | #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
480 | #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
481 | ||
482 | /* PCI2 not supported on 8313 */ | |
483 | #define CFG_IBAT3L (0) | |
484 | #define CFG_IBAT3U (0) | |
485 | #define CFG_IBAT4L (0) | |
486 | #define CFG_IBAT4U (0) | |
487 | ||
488 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
489 | #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
490 | #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | |
491 | ||
492 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
493 | #define CFG_IBAT6L (0xF0000000 | BATL_PP_10) | |
494 | #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
495 | ||
496 | #define CFG_IBAT7L (0) | |
497 | #define CFG_IBAT7U (0) | |
498 | ||
499 | #define CFG_DBAT0L CFG_IBAT0L | |
500 | #define CFG_DBAT0U CFG_IBAT0U | |
501 | #define CFG_DBAT1L CFG_IBAT1L | |
502 | #define CFG_DBAT1U CFG_IBAT1U | |
503 | #define CFG_DBAT2L CFG_IBAT2L | |
504 | #define CFG_DBAT2U CFG_IBAT2U | |
505 | #define CFG_DBAT3L CFG_IBAT3L | |
506 | #define CFG_DBAT3U CFG_IBAT3U | |
507 | #define CFG_DBAT4L CFG_IBAT4L | |
508 | #define CFG_DBAT4U CFG_IBAT4U | |
509 | #define CFG_DBAT5L CFG_IBAT5L | |
510 | #define CFG_DBAT5U CFG_IBAT5U | |
511 | #define CFG_DBAT6L CFG_IBAT6L | |
512 | #define CFG_DBAT6U CFG_IBAT6U | |
513 | #define CFG_DBAT7L CFG_IBAT7L | |
514 | #define CFG_DBAT7U CFG_IBAT7U | |
515 | ||
516 | /* | |
517 | * Internal Definitions | |
518 | * | |
519 | * Boot Flags | |
520 | */ | |
521 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
522 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
523 | ||
524 | /* | |
525 | * Environment Configuration | |
526 | */ | |
527 | #define CONFIG_ENV_OVERWRITE | |
528 | ||
529 | #define CONFIG_ETHADDR 00:E0:0C:00:95:01 | |
96b8a054 SW |
530 | #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 |
531 | ||
532 | #define CONFIG_IPADDR 10.0.0.2 | |
533 | #define CONFIG_SERVERIP 10.0.0.1 | |
534 | #define CONFIG_GATEWAYIP 10.0.0.1 | |
535 | #define CONFIG_NETMASK 255.0.0.0 | |
536 | #define CONFIG_NETDEV eth1 | |
537 | ||
538 | #define CONFIG_HOSTNAME mpc8313erdb | |
539 | #define CONFIG_ROOTPATH /nfs/root/path | |
540 | #define CONFIG_BOOTFILE uImage | |
541 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
542 | #define CONFIG_FDTFILE mpc8313erdb.dtb | |
543 | ||
b2115757 | 544 | #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ |
96b8a054 SW |
545 | #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ |
546 | #define CONFIG_BAUDRATE 115200 | |
547 | ||
548 | #define XMK_STR(x) #x | |
549 | #define MK_STR(x) XMK_STR(x) | |
550 | ||
551 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
552 | "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ | |
553 | "ethprime=TSEC1\0" \ | |
554 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
555 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
556 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
557 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
558 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
559 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
560 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
561 | "fdtaddr=400000\0" \ | |
562 | "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ | |
563 | "console=ttyS0\0" \ | |
564 | "setbootargs=setenv bootargs " \ | |
565 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
566 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ | |
567 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
568 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" | |
569 | ||
570 | #define CONFIG_NFSBOOTCOMMAND \ | |
571 | "setenv rootdev /dev/nfs;" \ | |
572 | "run setbootargs;" \ | |
573 | "run setipargs;" \ | |
574 | "tftp $loadaddr $bootfile;" \ | |
575 | "tftp $fdtaddr $fdtfile;" \ | |
576 | "bootm $loadaddr - $fdtaddr" | |
577 | ||
578 | #define CONFIG_RAMBOOTCOMMAND \ | |
579 | "setenv rootdev /dev/ram;" \ | |
580 | "run setbootargs;" \ | |
581 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
582 | "tftp $loadaddr $bootfile;" \ | |
583 | "tftp $fdtaddr $fdtfile;" \ | |
584 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
585 | ||
586 | #undef MK_STR | |
587 | #undef XMK_STR | |
588 | ||
589 | #endif /* __CONFIG_H */ |