[people/ms/u-boot.git] / include / configs / MPC837XEMDS.h

/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc.
 * Dave Liu <daveliu@freescale.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */
#define CONFIG_MPC83XX		1 /* MPC83XX family */
#define CONFIG_MPC837X		1 /* MPC837X CPU specific */
#define CONFIG_MPC837XEMDS	1 /* MPC837XEMDS board specific */

/*
 * System Clock Setup
 */
#ifdef CONFIG_PCISLAVE
#define CONFIG_83XX_PCICLK	66000000 /* in HZ */
#else
#define CONFIG_83XX_CLKIN	66000000 /* in Hz */
#endif

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	66000000
#endif

/*
 * Hardware Reset Configuration Word
 * if CLKIN is 66MHz, then
 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
 */
#define CFG_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_SVCOD_DIV_2 |\
	HRCWL_CSB_TO_CLKIN_6X1 |\
	HRCWL_CORE_TO_CSB_1_5X1)

#ifdef CONFIG_PCISLAVE
#define CFG_HRCW_HIGH (\
	HRCWH_PCI_AGENT |\
	HRCWH_PCI1_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0XFFF00100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_RL_EXT_LEGACY |\
	HRCWH_TSEC1M_IN_RGMII |\
	HRCWH_TSEC2M_IN_RGMII |\
	HRCWH_BIG_ENDIAN |\
	HRCWH_LDP_CLEAR)
#else
#define CFG_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_RL_EXT_LEGACY |\
	HRCWH_TSEC1M_IN_RGMII |\
	HRCWH_TSEC2M_IN_RGMII |\
	HRCWH_BIG_ENDIAN |\
	HRCWH_LDP_CLEAR)
#endif

/* Arbiter Configuration Register */
#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth is 4 */
#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count is 4 */

/* System Priority Control Register */
#define CFG_SPCR_TSECEP		3	/* eTSEC1/2 emergency has highest priority */

/*
 * IP blocks clock configuration
 */
#define CFG_SCCR_TSEC1CM	1	/* CSB:eTSEC1 = 1:1 */
#define CFG_SCCR_TSEC2CM	1	/* CSB:eTSEC2 = 1:1 */
#define CFG_SCCR_SATACM		SCCR_SATACM_2	/* CSB:SATA[0:3] = 2:1 */

/*
 * System IO Config
 */
#define CFG_SICRH		0x00000000
#define CFG_SICRL		0x00000000

/*
 * Output Buffer Impedance
 */
#define CFG_OBIR		0x31100000

#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R

/*
 * IMMR new address
 */
#define CFG_IMMR		0xE0000000

/*
 * DDR Setup
 */
#define CFG_DDR_BASE		0x00000000 /* DDR is system memory */
#define CFG_SDRAM_BASE		CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
#define CFG_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CFG_83XX_DDR_USES_CS0
#define CFG_DDRCDR_VALUE	0x80080001 /* ODT 150ohm on SoC */

#undef CONFIG_DDR_ECC		/* support DDR ECC function */
#undef CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */

#define CONFIG_SPD_EEPROM	/* Use SPD EEPROM for DDR setup */
#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */

#if defined(CONFIG_SPD_EEPROM)
#define SPD_EEPROM_ADDRESS	0x51 /* I2C address of DDR SODIMM SPD */
#else
/*
 * Manually set up DDR parameters
 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
 */
#define CFG_DDR_SIZE		512 /* MB */
#define CFG_DDR_CS0_BNDS	0x0000001f
#define CFG_DDR_CS0_CONFIG	( CSCONFIG_EN \
				| 0x00010000  /* ODT_WR to CSn */ \
				| CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
				/* 0x80010202 */
#define CFG_DDR_TIMING_3	0x00000000
#define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
				| ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
				/* 0x00620802 */
#define CFG_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
				| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
				| (13 << TIMING_CFG1_REFREC_SHIFT ) \
				| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
				/* 0x3935d322 */
#define CFG_DDR_TIMING_2	( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
				| ( 6 << TIMING_CFG2_CPO_SHIFT ) \
				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
				| ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
				| ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
				/* 0x131088c8 */
#define CFG_DDR_INTERVAL	( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
				| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
				/* 0x03E00100 */
#define CFG_DDR_SDRAM_CFG	0x43000000
#define CFG_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
#define CFG_DDR_MODE		( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
				| ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
				/* ODT 150ohm CL=3, AL=1 on SDRAM */
#define CFG_DDR_MODE2		0x00000000
#endif

/*
 * Memory test
 */
#undef CFG_DRAM_TEST		/* memory test, takes time */
#define CFG_MEMTEST_START	0x00040000 /* memtest region */
#define CFG_MEMTEST_END		0x00140000

/*
 * The reserved memory
 */
#define CFG_MONITOR_BASE	TEXT_BASE /* start of monitor */

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef CFG_RAMBOOT
#endif

/* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN		(512 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CFG_INIT_RAM_LOCK	1
#define CFG_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CFG_INIT_RAM_END	0x1000 /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE	0x100 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CFG_LCRR		(LCRR_DBYP | LCRR_CLKDIV_8)
#define CFG_LBC_LBCR		0x00000000

/*
 * FLASH on the Local Bus
 */
#define CFG_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
#define CFG_FLASH_BASE		0xFE000000 /* FLASH base address */
#define CFG_FLASH_SIZE		32 /* max FLASH size is 32M */
#define CFG_FLASH_PROTECTION	1		/* Use h/w Flash protection. */

#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */

#define CFG_BR0_PRELIM		( CFG_FLASH_BASE	/* Flash Base address */ \
				| (2 << BR_PS_SHIFT)	/* 16 bit port size */ \
				| BR_V )		/* valid */
#define CFG_OR0_PRELIM		( (~(CFG_FLASH_SIZE - 1) << 20) \
				| OR_UPM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_ACS_DIV2 \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_15 \
				| OR_GPCM_TRLX \
				| OR_GPCM_EHTR \
				| OR_GPCM_EAD )
				/* 0xFE000FF7 */

#define CFG_MAX_FLASH_BANKS	1 /* number of banks */
#define CFG_MAX_FLASH_SECT	256 /* max sectors per device */

#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */

/*
 * BCSR on the Local Bus
 */
#define CFG_BCSR		0xF8000000
#define CFG_LBLAWBAR1_PRELIM	CFG_BCSR /* Access window base at BCSR base */
#define CFG_LBLAWAR1_PRELIM	0x8000000E /* Access window size 32K */

#define CFG_BR1_PRELIM		(CFG_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
#define CFG_OR1_PRELIM		0xFFFFE9f7 /* length 32K */

/*
 * NAND Flash on the Local Bus
 */
#define CFG_NAND_BASE		0xE0600000	/* 0xE0600000 */
#define CFG_BR3_PRELIM		( CFG_NAND_BASE \
				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
				| BR_PS_8		/* Port Size = 8 bit */ \
				| BR_MS_FCM		/* MSEL = FCM */ \
				| BR_V )		/* valid */
#define CFG_OR3_PRELIM		( 0xFFFF8000		/* length 32K */ \
				| OR_FCM_CSCT \
				| OR_FCM_CST \
				| OR_FCM_CHT \
				| OR_FCM_SCY_1 \
				| OR_FCM_TRLX \
				| OR_FCM_EHTR )
				/* 0xFFFF8396 */

#define CFG_LBLAWBAR3_PRELIM	CFG_NAND_BASE
#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/* I2C */
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#undef CONFIG_SOFT_I2C		/* I2C bit-banged */
#define CONFIG_FSL_I2C
#define CFG_I2C_SPEED		400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES	{0x51} /* Don't probe these addrs */
#define CFG_I2C_OFFSET		0x3000
#define CFG_I2C2_OFFSET		0x3100

/*
 * Config on-board RTC
 */
#define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
#define CFG_I2C_RTC_ADDR	0x68 /* at address 0x68 */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CFG_PCI_MEM_BASE	0x80000000
#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
#define CFG_PCI_MEM_SIZE	0x10000000 /* 256M */
#define CFG_PCI_MMIO_BASE	0x90000000
#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
#define CFG_PCI_MMIO_SIZE	0x10000000 /* 256M */
#define CFG_PCI_IO_BASE		0x00000000
#define CFG_PCI_IO_PHYS		0xE0300000
#define CFG_PCI_IO_SIZE		0x100000 /* 1M */

#define CFG_PCI_SLV_MEM_LOCAL	CFG_SDRAM_BASE
#define CFG_PCI_SLV_MEM_BUS	0x00000000
#define CFG_PCI_SLV_MEM_SIZE	0x80000000

#ifdef CONFIG_PCI
#define CONFIG_83XX_GENERIC_PCI	1 /* Use generic PCI setup */
#define CONFIG_PQ_MDS_PIB	1 /* PQ MDS Platform IO Board */

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP		/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
#endif /* CONFIG_PCI */

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

/*
 * TSEC
 */
#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
#define CFG_TSEC1_OFFSET	0x24000
#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
#define CFG_TSEC2_OFFSET	0x25000
#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)

/*
 * TSEC ethernet configuration
 */
#define CONFIG_MII		1 /* MII PHY management */
#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC1"
#define TSEC1_PHY_ADDR		2
#define TSEC2_PHY_ADDR		3
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"eTSEC1"

/* SERDES */
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1	0xe3000
#define CONFIG_FSL_SERDES2	0xe3100

/*
 * SATA
 */
#define CONFIG_LIBATA
#define CONFIG_FSL_SATA

#define CFG_SATA_MAX_DEVICE	2
#define CONFIG_SATA1
#define CFG_SATA1_OFFSET	0x18000
#define CFG_SATA1		(CFG_IMMR + CFG_SATA1_OFFSET)
#define CFG_SATA1_FLAGS		FLAGS_DMA
#define CONFIG_SATA2
#define CFG_SATA2_OFFSET	0x19000
#define CFG_SATA2		(CFG_IMMR + CFG_SATA2_OFFSET)
#define CFG_SATA2_FLAGS		FLAGS_DMA

#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#endif

/*
 * Environment
 */
#ifndef CFG_RAMBOOT
	#define CONFIG_ENV_IS_IN_FLASH	1
	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env */
	#define CONFIG_ENV_SIZE		0x2000
#else
	#define CFG_NO_FLASH		1	/* Flash is not usable now */
	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
	#define CONFIG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_DATE

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CFG_RAMBOOT)
    #undef CONFIG_CMD_ENV
    #undef CONFIG_CMD_LOADS
#endif

#define CONFIG_CMDLINE_EDITING	1	/* add command line history */

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP		/* undef to save memory */
#define CFG_LOAD_ADDR		0x2000000 /* default load address */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt */

#if defined(CONFIG_CMD_KGDB)
	#define CFG_CBSIZE	1024 /* Console I/O Buffer Size */
#else
	#define CFG_CBSIZE	256 /* Console I/O Buffer Size */
#endif

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*
 * Core HID Setup
 */
#define CFG_HID0_INIT		0x000000000
#define CFG_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
#define CFG_HID2		HID2_HBE

/*
 * MMU Setup
 */
#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR: cache cacheable */
#define CFG_SDRAM_LOWER		CFG_SDRAM_BASE
#define CFG_SDRAM_UPPER		(CFG_SDRAM_BASE + 0x10000000)

#define CFG_IBAT0L	(CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT0U	(CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT0L	CFG_IBAT0L
#define CFG_DBAT0U	CFG_IBAT0U

#define CFG_IBAT1L	(CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT1U	(CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT1L	CFG_IBAT1L
#define CFG_DBAT1U	CFG_IBAT1U

/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
#define CFG_IBAT2L	(CFG_IMMR | BATL_PP_10 | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT2U	(CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
#define CFG_DBAT2L	CFG_IBAT2L
#define CFG_DBAT2U	CFG_IBAT2U

/* BCSR: cache-inhibit and guarded */
#define CFG_IBAT3L	(CFG_BCSR | BATL_PP_10 | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT3U	(CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CFG_DBAT3L	CFG_IBAT3L
#define CFG_DBAT3U	CFG_IBAT3U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CFG_IBAT4L	(CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT4U	(CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
#define CFG_DBAT4L	(CFG_FLASH_BASE | BATL_PP_10 | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_DBAT4U	CFG_IBAT4U

/* Stack in dcache: cacheable, no memory coherence */
#define CFG_IBAT5L	(CFG_INIT_RAM_ADDR | BATL_PP_10)
#define CFG_IBAT5U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CFG_DBAT5L	CFG_IBAT5L
#define CFG_DBAT5U	CFG_IBAT5U

#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CFG_IBAT6L	(CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT6U	(CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT6L	CFG_IBAT6L
#define CFG_DBAT6U	CFG_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
#define CFG_IBAT7L	(CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT7U	(CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_DBAT7L	CFG_IBAT7L
#define CFG_DBAT7U	CFG_IBAT7U
#else
#define CFG_IBAT6L	(0)
#define CFG_IBAT6U	(0)
#define CFG_IBAT7L	(0)
#define CFG_IBAT7U	(0)
#define CFG_DBAT6L	CFG_IBAT6L
#define CFG_DBAT6U	CFG_IBAT6U
#define CFG_DBAT7L	CFG_IBAT7L
#define CFG_DBAT7U	CFG_IBAT7U
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02 /* Software reboot */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */

#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR		00:E0:0C:00:83:79
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR		00:E0:0C:00:83:78
#endif

#define CONFIG_BAUDRATE 115200

#define CONFIG_LOADADDR 500000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
#undef CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_EXTRA_ENV_SETTINGS					\
   "netdev=eth0\0"							\
   "consoledev=ttyS0\0"							\
   "ramdiskaddr=1000000\0"						\
   "ramdiskfile=ramfs.83xx\0"						\
   "fdtaddr=400000\0"							\
   "fdtfile=mpc8379_mds.dtb\0"						\
   ""

#define CONFIG_NFSBOOTCOMMAND						\
   "setenv bootargs root=/dev/nfs rw "					\
      "nfsroot=$serverip:$rootpath "					\
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"			\
   "tftp $loadaddr $bootfile;"						\
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
   "setenv bootargs root=/dev/ram rw "					\
      "console=$consoledev,$baudrate $othbootargs;"			\
   "tftp $ramdiskaddr $ramdiskfile;"					\
   "tftp $loadaddr $bootfile;"						\
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr $ramdiskaddr $fdtaddr"


#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
19580e66 DL	1	/*
	2	* Copyright (C) 2007 Freescale Semiconductor, Inc.
	3	* Dave Liu <daveliu@freescale.com>
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	* MA 02111-1307 USA
	19	*/
	20
	21	#ifndef __CONFIG_H
	22	#define __CONFIG_H
	23
19580e66 DL	24	/*
	25	* High Level Configuration Options
	26	*/
	27	#define CONFIG_E300 1 /* E300 family */
	28	#define CONFIG_MPC83XX 1 /* MPC83XX family */
	29	#define CONFIG_MPC837X 1 /* MPC837X CPU specific */
	30	#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
	31
	32	/*
	33	* System Clock Setup
	34	*/
	35	#ifdef CONFIG_PCISLAVE
	36	#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
	37	#else
	38	#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
	39	#endif
	40
	41	#ifndef CONFIG_SYS_CLK_FREQ
	42	#define CONFIG_SYS_CLK_FREQ 66000000
	43	#endif
	44
	45	/*
	46	* Hardware Reset Configuration Word
	47	* if CLKIN is 66MHz, then
	48	* CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
	49	*/
	50	#define CFG_HRCW_LOW (\
	51	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	52	HRCWL_DDR_TO_SCB_CLK_1X1 \|\
	53	HRCWL_SVCOD_DIV_2 \|\
	54	HRCWL_CSB_TO_CLKIN_6X1 \|\
	55	HRCWL_CORE_TO_CSB_1_5X1)
	56
	57	#ifdef CONFIG_PCISLAVE
	58	#define CFG_HRCW_HIGH (\
	59	HRCWH_PCI_AGENT \|\
	60	HRCWH_PCI1_ARBITER_DISABLE \|\
	61	HRCWH_CORE_ENABLE \|\
	62	HRCWH_FROM_0XFFF00100 \|\
	63	HRCWH_BOOTSEQ_DISABLE \|\
	64	HRCWH_SW_WATCHDOG_DISABLE \|\
	65	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	66	HRCWH_RL_EXT_LEGACY \|\
	67	HRCWH_TSEC1M_IN_RGMII \|\
	68	HRCWH_TSEC2M_IN_RGMII \|\
	69	HRCWH_BIG_ENDIAN \|\
	70	HRCWH_LDP_CLEAR)
	71	#else
	72	#define CFG_HRCW_HIGH (\
	73	HRCWH_PCI_HOST \|\
	74	HRCWH_PCI1_ARBITER_ENABLE \|\
	75	HRCWH_CORE_ENABLE \|\
	76	HRCWH_FROM_0X00000100 \|\
	77	HRCWH_BOOTSEQ_DISABLE \|\
	78	HRCWH_SW_WATCHDOG_DISABLE \|\
	79	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	80	HRCWH_RL_EXT_LEGACY \|\
	81	HRCWH_TSEC1M_IN_RGMII \|\
	82	HRCWH_TSEC2M_IN_RGMII \|\
	83	HRCWH_BIG_ENDIAN \|\
	84	HRCWH_LDP_CLEAR)
	85	#endif
	86
bd4458cb DL	87	/* Arbiter Configuration Register */
	88	#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
	89	#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
	90
	91	/* System Priority Control Register */
	92	#define CFG_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
	93
19580e66	94	/*
bd4458cb	95	* IP blocks clock configuration
19580e66 DL	96	*/
	97	#define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
	98	#define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
20007848	99	#define CFG_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
19580e66 DL	100
	101	/*
	102	* System IO Config
	103	*/
	104	#define CFG_SICRH 0x00000000
	105	#define CFG_SICRL 0x00000000
	106
	107	/*
	108	* Output Buffer Impedance
	109	*/
	110	#define CFG_OBIR 0x31100000
	111
	112	#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
	113	#define CONFIG_BOARD_EARLY_INIT_R
	114
	115	/*
	116	* IMMR new address
	117	*/
	118	#define CFG_IMMR 0xE0000000
	119
	120	/*
	121	* DDR Setup
	122	*/
	123	#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
	124	#define CFG_SDRAM_BASE CFG_DDR_BASE
	125	#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
	126	#define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
	127	#define CFG_83XX_DDR_USES_CS0
	128	#define CFG_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */
	129
	130	#undef CONFIG_DDR_ECC /* support DDR ECC function */
	131	#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
	132
	133	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	134	#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
	135
	136	#if defined(CONFIG_SPD_EEPROM)
	137	#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
	138	#else
	139	/*
	140	* Manually set up DDR parameters
7e74d63d	141	* WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
19580e66 DL	142	* consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
	143	*/
	144	#define CFG_DDR_SIZE 512 /* MB */
	145	#define CFG_DDR_CS0_BNDS 0x0000001f
	146	#define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \
	147	\| 0x00010000 /* ODT_WR to CSn */ \
	148	\| CSCONFIG_ROW_BIT_14 \| CSCONFIG_COL_BIT_10 )
	149	/* 0x80010202 */
	150	#define CFG_DDR_TIMING_3 0x00000000
	151	#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
	152	\| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
	153	\| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
	154	\| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
	155	\| ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
	156	\| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
	157	\| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
	158	\| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
	159	/* 0x00620802 */
	160	#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
	161	\| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
	162	\| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
	163	\| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
	164	\| (13 << TIMING_CFG1_REFREC_SHIFT ) \
	165	\| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
	166	\| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
	167	\| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
	168	/* 0x3935d322 */
7e74d63d	169	#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
19580e66 DL	170	\| ( 6 << TIMING_CFG2_CPO_SHIFT ) \
	171	\| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
	172	\| ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
	173	\| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
	174	\| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
	175	\| ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
7e74d63d	176	/* 0x131088c8 */
19580e66 DL	177	#define CFG_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
	178	\| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
	179	/* 0x03E00100 */
	180	#define CFG_DDR_SDRAM_CFG 0x43000000
	181	#define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
7e74d63d	182	#define CFG_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
19580e66	183	\| ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
7e74d63d	184	/* ODT 150ohm CL=3, AL=1 on SDRAM */
19580e66 DL	185	#define CFG_DDR_MODE2 0x00000000
	186	#endif
	187
	188	/*
	189	* Memory test
	190	*/
	191	#undef CFG_DRAM_TEST /* memory test, takes time */
	192	#define CFG_MEMTEST_START 0x00040000 /* memtest region */
	193	#define CFG_MEMTEST_END 0x00140000
	194
	195	/*
	196	* The reserved memory
	197	*/
	198	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
	199
	200	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	201	#define CFG_RAMBOOT
	202	#else
	203	#undef CFG_RAMBOOT
	204	#endif
	205
0e8d1586	206	/* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
19580e66 DL	207	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
	208	#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
	209
	210	/*
	211	* Initial RAM Base Address Setup
	212	*/
	213	#define CFG_INIT_RAM_LOCK 1
	214	#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
	215	#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
	216	#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
	217	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	218
	219	/*
	220	* Local Bus Configuration & Clock Setup
	221	*/
	222	#define CFG_LCRR (LCRR_DBYP \| LCRR_CLKDIV_8)
	223	#define CFG_LBC_LBCR 0x00000000
	224
	225	/*
	226	* FLASH on the Local Bus
	227	*/
	228	#define CFG_FLASH_CFI /* use the Common Flash Interface */
00b1883a	229	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
19580e66 DL	230	#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
19580e66 DL	231	#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */
162c41c0	232	#define CFG_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
19580e66 DL	233
	234	#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
	235	#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
	236
ded08317 DL	237	#define CFG_BR0_PRELIM ( CFG_FLASH_BASE /* Flash Base address */ \
	238	\| (2 << BR_PS_SHIFT) /* 16 bit port size */ \
	239	\| BR_V ) /* valid */
	240	#define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \
	241	\| OR_UPM_XAM \
	242	\| OR_GPCM_CSNT \
f9023afb	243	\| OR_GPCM_ACS_DIV2 \
ded08317 DL	244	\| OR_GPCM_XACS \
	245	\| OR_GPCM_SCY_15 \
	246	\| OR_GPCM_TRLX \
	247	\| OR_GPCM_EHTR \
	248	\| OR_GPCM_EAD )
	249	/* 0xFE000FF7 */
19580e66 DL	250
	251	#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
	252	#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
	253
	254	#undef CFG_FLASH_CHECKSUM
	255	#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	256	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	257
	258	/*
	259	* BCSR on the Local Bus
	260	*/
	261	#define CFG_BCSR 0xF8000000
	262	#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
	263	#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
	264
	265	#define CFG_BR1_PRELIM (CFG_BCSR \| 0x00000801) /* Port size=8bit, MSEL=GPCM */
	266	#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
	267
	268	/*
	269	* NAND Flash on the Local Bus
	270	*/
	271	#define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */
	272	#define CFG_BR3_PRELIM ( CFG_NAND_BASE \
	273	\| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
	274	\| BR_PS_8 /* Port Size = 8 bit */ \
	275	\| BR_MS_FCM /* MSEL = FCM */ \
	276	\| BR_V ) /* valid */
	277	#define CFG_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \
	278	\| OR_FCM_CSCT \
	279	\| OR_FCM_CST \
	280	\| OR_FCM_CHT \
	281	\| OR_FCM_SCY_1 \
	282	\| OR_FCM_TRLX \
	283	\| OR_FCM_EHTR )
	284	/* 0xFFFF8396 */
	285
	286	#define CFG_LBLAWBAR3_PRELIM CFG_NAND_BASE
	287	#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
	288
	289	/*
	290	* Serial Port
	291	*/
	292	#define CONFIG_CONS_INDEX 1
	293	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	294	#define CFG_NS16550
	295	#define CFG_NS16550_SERIAL
	296	#define CFG_NS16550_REG_SIZE 1
	297	#define CFG_NS16550_CLK get_bus_freq(0)
	298
	299	#define CFG_BAUDRATE_TABLE \
	300	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	301
	302	#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
	303	#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
	304
	305	/* Use the HUSH parser */
	306	#define CFG_HUSH_PARSER
	307	#ifdef CFG_HUSH_PARSER
	308	#define CFG_PROMPT_HUSH_PS2 "> "
	309	#endif
	310
	311	/* Pass open firmware flat tree */
	312	#define CONFIG_OF_LIBFDT 1
	313	#define CONFIG_OF_BOARD_SETUP 1
5b8bc606	314	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
19580e66 DL	315
	316	/* I2C */
	317	#define CONFIG_HARD_I2C /* I2C with hardware support */
	318	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	319	#define CONFIG_FSL_I2C
	320	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	321	#define CFG_I2C_SLAVE 0x7F
	322	#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
	323	#define CFG_I2C_OFFSET 0x3000
	324	#define CFG_I2C2_OFFSET 0x3100
	325
	326	/*
	327	* Config on-board RTC
	328	*/
	329	#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
	330	#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
	331
	332	/*
	333	* General PCI
	334	* Addresses are mapped 1-1.
	335	*/
	336	#define CFG_PCI_MEM_BASE 0x80000000
	337	#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
	338	#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
	339	#define CFG_PCI_MMIO_BASE 0x90000000
	340	#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
	341	#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
a7ba32d4	342	#define CFG_PCI_IO_BASE 0x00000000
19580e66 DL	343	#define CFG_PCI_IO_PHYS 0xE0300000
	344	#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
	345
	346	#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
	347	#define CFG_PCI_SLV_MEM_BUS 0x00000000
	348	#define CFG_PCI_SLV_MEM_SIZE 0x80000000
	349
	350	#ifdef CONFIG_PCI
	351	#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
	352	#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
	353
	354	#define CONFIG_NET_MULTI
	355	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	356
	357	#undef CONFIG_EEPRO100
	358	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	359	#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
	360	#endif /* CONFIG_PCI */
	361
	362	#ifndef CONFIG_NET_MULTI
	363	#define CONFIG_NET_MULTI 1
	364	#endif
	365
	366	/*
	367	* TSEC
	368	*/
	369	#define CONFIG_TSEC_ENET /* TSEC ethernet support */
	370	#define CFG_TSEC1_OFFSET 0x24000
	371	#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
	372	#define CFG_TSEC2_OFFSET 0x25000
	373	#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
	374
	375	/*
	376	* TSEC ethernet configuration
	377	*/
	378	#define CONFIG_MII 1 /* MII PHY management */
	379	#define CONFIG_TSEC1 1
	380	#define CONFIG_TSEC1_NAME "eTSEC0"
	381	#define CONFIG_TSEC2 1
	382	#define CONFIG_TSEC2_NAME "eTSEC1"
	383	#define TSEC1_PHY_ADDR 2
	384	#define TSEC2_PHY_ADDR 3
	385	#define TSEC1_PHYIDX 0
	386	#define TSEC2_PHYIDX 0
	387	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	388	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	389
	390	/* Options are: TSEC[0-1] */
	391	#define CONFIG_ETHPRIME "eTSEC1"
	392
6f8c85e8 DL	393	/* SERDES */
	394	#define CONFIG_FSL_SERDES
	395	#define CONFIG_FSL_SERDES1 0xe3000
	396	#define CONFIG_FSL_SERDES2 0xe3100
	397
2eeb3e4f DL	398	/*
	399	* SATA
	400	*/
	401	#define CONFIG_LIBATA
	402	#define CONFIG_FSL_SATA
	403
	404	#define CFG_SATA_MAX_DEVICE 2
	405	#define CONFIG_SATA1
	406	#define CFG_SATA1_OFFSET 0x18000
	407	#define CFG_SATA1 (CFG_IMMR + CFG_SATA1_OFFSET)
	408	#define CFG_SATA1_FLAGS FLAGS_DMA
	409	#define CONFIG_SATA2
	410	#define CFG_SATA2_OFFSET 0x19000
	411	#define CFG_SATA2 (CFG_IMMR + CFG_SATA2_OFFSET)
	412	#define CFG_SATA2_FLAGS FLAGS_DMA
	413
	414	#ifdef CONFIG_FSL_SATA
	415	#define CONFIG_LBA48
	416	#define CONFIG_CMD_SATA
	417	#define CONFIG_DOS_PARTITION
	418	#define CONFIG_CMD_EXT2
	419	#endif
	420
19580e66 DL	421	/*
	422	* Environment
	423	*/
	424	#ifndef CFG_RAMBOOT
5a1aceb0	425	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	426	#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
	427	#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
	428	#define CONFIG_ENV_SIZE 0x2000
19580e66 DL	429	#else
19580e66 DL	430	#define CFG_NO_FLASH 1 /* Flash is not usable now */
93f6d725	431	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
0e8d1586 JCPV	432	#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
0e8d1586 JCPV	433	#define CONFIG_ENV_SIZE 0x2000
19580e66 DL	434	#endif
	435
	436	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	437	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	438
	439	/*
	440	* BOOTP options
	441	*/
	442	#define CONFIG_BOOTP_BOOTFILESIZE
	443	#define CONFIG_BOOTP_BOOTPATH
	444	#define CONFIG_BOOTP_GATEWAY
	445	#define CONFIG_BOOTP_HOSTNAME
	446
	447
	448	/*
	449	* Command line configuration.
	450	*/
	451	#include <config_cmd_default.h>
	452
	453	#define CONFIG_CMD_PING
	454	#define CONFIG_CMD_I2C
	455	#define CONFIG_CMD_MII
	456	#define CONFIG_CMD_DATE
	457
	458	#if defined(CONFIG_PCI)
	459	#define CONFIG_CMD_PCI
	460	#endif
	461
	462	#if defined(CFG_RAMBOOT)
	463	#undef CONFIG_CMD_ENV
	464	#undef CONFIG_CMD_LOADS
	465	#endif
	466
	467	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	468
	469	#undef CONFIG_WATCHDOG /* watchdog disabled */
	470
	471	/*
	472	* Miscellaneous configurable options
	473	*/
	474	#define CFG_LONGHELP /* undef to save memory */
	475	#define CFG_LOAD_ADDR 0x2000000 /* default load address */
	476	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	477
	478	#if defined(CONFIG_CMD_KGDB)
	479	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	480	#else
	481	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	482	#endif
	483
	484	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	485	#define CFG_MAXARGS 16 /* max number of command args */
	486	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	487	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
	488
	489	/*
	490	* For booting Linux, the board info and command line data
	491	* have to be in the first 8 MB of memory, since this is
	492	* the maximum mapped by the Linux kernel during initialization.
	493	*/
	494	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	495
	496	/*
	497	* Core HID Setup
498	*/
499	#define CFG_HID0_INIT 0x000000000
500	#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
501	#define CFG_HID2 HID2_HBE
502
19580e66 DL	503	/*
	504	* MMU Setup
	505	*/
31d82672	506	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
19580e66 DL	507
	508	/* DDR: cache cacheable */
	509	#define CFG_SDRAM_LOWER CFG_SDRAM_BASE
	510	#define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000)
	511
	512	#define CFG_IBAT0L (CFG_SDRAM_LOWER \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	513	#define CFG_IBAT0U (CFG_SDRAM_LOWER \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	514	#define CFG_DBAT0L CFG_IBAT0L
	515	#define CFG_DBAT0U CFG_IBAT0U
	516
	517	#define CFG_IBAT1L (CFG_SDRAM_UPPER \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	518	#define CFG_IBAT1U (CFG_SDRAM_UPPER \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	519	#define CFG_DBAT1L CFG_IBAT1L
	520	#define CFG_DBAT1U CFG_IBAT1U
	521
	522	/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
	523	#define CFG_IBAT2L (CFG_IMMR \| BATL_PP_10 \| \
	524	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	525	#define CFG_IBAT2U (CFG_IMMR \| BATU_BL_8M \| BATU_VS \| BATU_VP)
	526	#define CFG_DBAT2L CFG_IBAT2L
	527	#define CFG_DBAT2U CFG_IBAT2U
	528
	529	/* BCSR: cache-inhibit and guarded */
	530	#define CFG_IBAT3L (CFG_BCSR \| BATL_PP_10 \| \
	531	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	532	#define CFG_IBAT3U (CFG_BCSR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	533	#define CFG_DBAT3L CFG_IBAT3L
	534	#define CFG_DBAT3U CFG_IBAT3U
	535
	536	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
	537	#define CFG_IBAT4L (CFG_FLASH_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	538	#define CFG_IBAT4U (CFG_FLASH_BASE \| BATU_BL_32M \| BATU_VS \| BATU_VP)
	539	#define CFG_DBAT4L (CFG_FLASH_BASE \| BATL_PP_10 \| \
	540	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	541	#define CFG_DBAT4U CFG_IBAT4U
	542
	543	/* Stack in dcache: cacheable, no memory coherence */
	544	#define CFG_IBAT5L (CFG_INIT_RAM_ADDR \| BATL_PP_10)
	545	#define CFG_IBAT5U (CFG_INIT_RAM_ADDR \| BATU_BL_128K \| BATU_VS \| BATU_VP)
	546	#define CFG_DBAT5L CFG_IBAT5L
	547	#define CFG_DBAT5U CFG_IBAT5U
	548
	549	#ifdef CONFIG_PCI
	550	/* PCI MEM space: cacheable */
	551	#define CFG_IBAT6L (CFG_PCI_MEM_PHYS \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	552	#define CFG_IBAT6U (CFG_PCI_MEM_PHYS \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	553	#define CFG_DBAT6L CFG_IBAT6L
	554	#define CFG_DBAT6U CFG_IBAT6U
	555	/* PCI MMIO space: cache-inhibit and guarded */
	556	#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS \| BATL_PP_10 \| \
	557	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	558	#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	559	#define CFG_DBAT7L CFG_IBAT7L
	560	#define CFG_DBAT7U CFG_IBAT7U
	561	#else
	562	#define CFG_IBAT6L (0)
	563	#define CFG_IBAT6U (0)
	564	#define CFG_IBAT7L (0)
	565	#define CFG_IBAT7U (0)
	566	#define CFG_DBAT6L CFG_IBAT6L
	567	#define CFG_DBAT6U CFG_IBAT6U
	568	#define CFG_DBAT7L CFG_IBAT7L
	569	#define CFG_DBAT7U CFG_IBAT7U
	570	#endif
571
572	/*
573	* Internal Definitions
574	*
575	* Boot Flags
576	*/
577	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
578	#define BOOTFLAG_WARM 0x02 /* Software reboot */
579
580	#if defined(CONFIG_CMD_KGDB)
581	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
582	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
583	#endif
584
585	/*
586	* Environment Configuration
587	*/
588
589	#define CONFIG_ENV_OVERWRITE
590
591	#if defined(CONFIG_TSEC_ENET)
592	#define CONFIG_HAS_ETH0
593	#define CONFIG_ETHADDR 00:E0:0C:00:83:79
594	#define CONFIG_HAS_ETH1
595	#define CONFIG_ETH1ADDR 00:E0:0C:00:83:78
596	#endif
597
598	#define CONFIG_BAUDRATE 115200
599
b2115757	600	#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
19580e66 DL	601
	602	#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
	603	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	604
	605	#define CONFIG_EXTRA_ENV_SETTINGS \
	606	"netdev=eth0\0" \
	607	"consoledev=ttyS0\0" \
	608	"ramdiskaddr=1000000\0" \
	609	"ramdiskfile=ramfs.83xx\0" \
	610	"fdtaddr=400000\0" \
270fe261	611	"fdtfile=mpc8379_mds.dtb\0" \
19580e66 DL	612	""
	613
	614	#define CONFIG_NFSBOOTCOMMAND \
	615	"setenv bootargs root=/dev/nfs rw " \
	616	"nfsroot=$serverip:$rootpath " \
	617	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	618	"console=$consoledev,$baudrate $othbootargs;" \
	619	"tftp $loadaddr $bootfile;" \
	620	"tftp $fdtaddr $fdtfile;" \
	621	"bootm $loadaddr - $fdtaddr"
	622
	623	#define CONFIG_RAMBOOTCOMMAND \
	624	"setenv bootargs root=/dev/ram rw " \
	625	"console=$consoledev,$baudrate $othbootargs;" \
	626	"tftp $ramdiskaddr $ramdiskfile;" \
	627	"tftp $loadaddr $bootfile;" \
	628	"tftp $fdtaddr $fdtfile;" \
	629	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	630
	631
	632	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	633
	634	#endif /* __CONFIG_H */