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Commit | Line | Data |
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19580e66 DL |
1 | /* |
2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
3 | * Dave Liu <daveliu@freescale.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
19580e66 DL |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
19580e66 DL |
11 | /* |
12 | * High Level Configuration Options | |
13 | */ | |
14 | #define CONFIG_E300 1 /* E300 family */ | |
2c7920af | 15 | #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ |
19580e66 DL |
16 | #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ |
17 | ||
2ae18241 WD |
18 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
19 | ||
19580e66 DL |
20 | /* |
21 | * System Clock Setup | |
22 | */ | |
23 | #ifdef CONFIG_PCISLAVE | |
24 | #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ | |
25 | #else | |
26 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
27 | #endif | |
28 | ||
29 | #ifndef CONFIG_SYS_CLK_FREQ | |
30 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
31 | #endif | |
32 | ||
33 | /* | |
34 | * Hardware Reset Configuration Word | |
35 | * if CLKIN is 66MHz, then | |
36 | * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz | |
37 | */ | |
6d0f6bcf | 38 | #define CONFIG_SYS_HRCW_LOW (\ |
19580e66 DL |
39 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
40 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
41 | HRCWL_SVCOD_DIV_2 |\ | |
42 | HRCWL_CSB_TO_CLKIN_6X1 |\ | |
43 | HRCWL_CORE_TO_CSB_1_5X1) | |
44 | ||
45 | #ifdef CONFIG_PCISLAVE | |
6d0f6bcf | 46 | #define CONFIG_SYS_HRCW_HIGH (\ |
19580e66 DL |
47 | HRCWH_PCI_AGENT |\ |
48 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
49 | HRCWH_CORE_ENABLE |\ | |
50 | HRCWH_FROM_0XFFF00100 |\ | |
51 | HRCWH_BOOTSEQ_DISABLE |\ | |
52 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
53 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
54 | HRCWH_RL_EXT_LEGACY |\ | |
55 | HRCWH_TSEC1M_IN_RGMII |\ | |
56 | HRCWH_TSEC2M_IN_RGMII |\ | |
57 | HRCWH_BIG_ENDIAN |\ | |
58 | HRCWH_LDP_CLEAR) | |
59 | #else | |
6d0f6bcf | 60 | #define CONFIG_SYS_HRCW_HIGH (\ |
19580e66 DL |
61 | HRCWH_PCI_HOST |\ |
62 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
63 | HRCWH_CORE_ENABLE |\ | |
64 | HRCWH_FROM_0X00000100 |\ | |
65 | HRCWH_BOOTSEQ_DISABLE |\ | |
66 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
67 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
68 | HRCWH_RL_EXT_LEGACY |\ | |
69 | HRCWH_TSEC1M_IN_RGMII |\ | |
70 | HRCWH_TSEC2M_IN_RGMII |\ | |
71 | HRCWH_BIG_ENDIAN |\ | |
72 | HRCWH_LDP_CLEAR) | |
73 | #endif | |
74 | ||
bd4458cb | 75 | /* Arbiter Configuration Register */ |
6d0f6bcf | 76 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ |
8d85808f | 77 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ |
bd4458cb DL |
78 | |
79 | /* System Priority Control Register */ | |
8d85808f | 80 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ |
bd4458cb | 81 | |
19580e66 | 82 | /* |
bd4458cb | 83 | * IP blocks clock configuration |
19580e66 | 84 | */ |
6d0f6bcf JCPV |
85 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ |
86 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ | |
8d85808f | 87 | #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ |
19580e66 DL |
88 | |
89 | /* | |
90 | * System IO Config | |
91 | */ | |
6d0f6bcf JCPV |
92 | #define CONFIG_SYS_SICRH 0x00000000 |
93 | #define CONFIG_SYS_SICRL 0x00000000 | |
19580e66 DL |
94 | |
95 | /* | |
96 | * Output Buffer Impedance | |
97 | */ | |
6d0f6bcf | 98 | #define CONFIG_SYS_OBIR 0x31100000 |
19580e66 | 99 | |
19580e66 | 100 | #define CONFIG_BOARD_EARLY_INIT_R |
c78c6783 | 101 | #define CONFIG_HWCONFIG |
19580e66 DL |
102 | |
103 | /* | |
104 | * IMMR new address | |
105 | */ | |
6d0f6bcf | 106 | #define CONFIG_SYS_IMMR 0xE0000000 |
19580e66 DL |
107 | |
108 | /* | |
109 | * DDR Setup | |
110 | */ | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
112 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
113 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
114 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
115 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
2fef4020 JH |
116 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ |
117 | | DDRCDR_ODT \ | |
118 | | DDRCDR_Q_DRN) | |
119 | /* 0x80080001 */ /* ODT 150ohm on SoC */ | |
19580e66 DL |
120 | |
121 | #undef CONFIG_DDR_ECC /* support DDR ECC function */ | |
122 | #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ | |
123 | ||
124 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
125 | #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ | |
126 | ||
127 | #if defined(CONFIG_SPD_EEPROM) | |
128 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ | |
129 | #else | |
130 | /* | |
131 | * Manually set up DDR parameters | |
7e74d63d | 132 | * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM |
19580e66 DL |
133 | * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 |
134 | */ | |
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_DDR_SIZE 512 /* MB */ |
136 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f | |
8d85808f | 137 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
2fef4020 JH |
138 | | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ |
139 | | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ | |
140 | | CSCONFIG_ROW_BIT_14 \ | |
141 | | CSCONFIG_COL_BIT_10) | |
142 | /* 0x80010202 */ | |
6d0f6bcf | 143 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
8d85808f JH |
144 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
145 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
146 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
147 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
148 | | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
149 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
150 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
151 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
19580e66 | 152 | /* 0x00620802 */ |
8d85808f JH |
153 | #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ |
154 | | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
155 | | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
156 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
157 | | (13 << TIMING_CFG1_REFREC_SHIFT) \ | |
158 | | (3 << TIMING_CFG1_WRREC_SHIFT) \ | |
159 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
160 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
19580e66 | 161 | /* 0x3935d322 */ |
8d85808f JH |
162 | #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
163 | | (6 << TIMING_CFG2_CPO_SHIFT) \ | |
164 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
165 | | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
166 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
167 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
168 | | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
7e74d63d | 169 | /* 0x131088c8 */ |
8d85808f JH |
170 | #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
171 | | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
19580e66 | 172 | /* 0x03E00100 */ |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 |
174 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ | |
8d85808f JH |
175 | #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ |
176 | | (0x1432 << SDRAM_MODE_SD_SHIFT)) | |
7e74d63d | 177 | /* ODT 150ohm CL=3, AL=1 on SDRAM */ |
8d85808f | 178 | #define CONFIG_SYS_DDR_MODE2 0x00000000 |
19580e66 DL |
179 | #endif |
180 | ||
181 | /* | |
182 | * Memory test | |
183 | */ | |
6d0f6bcf JCPV |
184 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
185 | #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ | |
186 | #define CONFIG_SYS_MEMTEST_END 0x00140000 | |
19580e66 DL |
187 | |
188 | /* | |
189 | * The reserved memory | |
190 | */ | |
14d0a02a | 191 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
19580e66 | 192 | |
6d0f6bcf JCPV |
193 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
194 | #define CONFIG_SYS_RAMBOOT | |
19580e66 | 195 | #else |
6d0f6bcf | 196 | #undef CONFIG_SYS_RAMBOOT |
19580e66 DL |
197 | #endif |
198 | ||
6d0f6bcf | 199 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
16c8c170 | 200 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
8d85808f | 201 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
19580e66 DL |
202 | |
203 | /* | |
204 | * Initial RAM Base Address Setup | |
205 | */ | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
207 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 208 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
8d85808f JH |
209 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
210 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
19580e66 DL |
211 | |
212 | /* | |
213 | * Local Bus Configuration & Clock Setup | |
214 | */ | |
c7190f02 KP |
215 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
216 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 | |
6d0f6bcf | 217 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
0914f483 | 218 | #define CONFIG_FSL_ELBC 1 |
19580e66 DL |
219 | |
220 | /* | |
221 | * FLASH on the Local Bus | |
222 | */ | |
8d85808f | 223 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 224 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
8d85808f JH |
225 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
226 | #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ | |
227 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
19580e66 | 228 | |
8d85808f JH |
229 | /* Window base at flash base */ |
230 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 231 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
19580e66 | 232 | |
8d85808f | 233 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
234 | | BR_PS_16 /* 16 bit port */ \ |
235 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
236 | | BR_V) /* valid */ | |
237 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
ded08317 DL |
238 | | OR_UPM_XAM \ |
239 | | OR_GPCM_CSNT \ | |
f9023afb | 240 | | OR_GPCM_ACS_DIV2 \ |
ded08317 DL |
241 | | OR_GPCM_XACS \ |
242 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
243 | | OR_GPCM_TRLX_SET \ |
244 | | OR_GPCM_EHTR_SET \ | |
8d85808f | 245 | | OR_GPCM_EAD) |
ded08317 | 246 | /* 0xFE000FF7 */ |
19580e66 | 247 | |
6d0f6bcf JCPV |
248 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
249 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
19580e66 | 250 | |
6d0f6bcf JCPV |
251 | #undef CONFIG_SYS_FLASH_CHECKSUM |
252 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
253 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
19580e66 DL |
254 | |
255 | /* | |
256 | * BCSR on the Local Bus | |
257 | */ | |
6d0f6bcf | 258 | #define CONFIG_SYS_BCSR 0xF8000000 |
8d85808f JH |
259 | /* Access window base at BCSR base */ |
260 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR | |
7d6a0982 JH |
261 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
262 | ||
263 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | |
264 | | BR_PS_8 \ | |
265 | | BR_MS_GPCM \ | |
266 | | BR_V) | |
267 | /* 0xF8000801 */ | |
268 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | |
269 | | OR_GPCM_XAM \ | |
270 | | OR_GPCM_CSNT \ | |
271 | | OR_GPCM_XACS \ | |
272 | | OR_GPCM_SCY_15 \ | |
273 | | OR_GPCM_TRLX_SET \ | |
274 | | OR_GPCM_EHTR_SET \ | |
275 | | OR_GPCM_EAD) | |
276 | /* 0xFFFFE9F7 */ | |
19580e66 DL |
277 | |
278 | /* | |
279 | * NAND Flash on the Local Bus | |
280 | */ | |
b3379f3f | 281 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
8d85808f | 282 | #define CONFIG_NAND_FSL_ELBC 1 |
b3379f3f | 283 | |
7d6a0982 | 284 | #define CONFIG_SYS_NAND_BASE 0xE0600000 |
8d85808f | 285 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ |
7d6a0982 | 286 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
8d85808f | 287 | | BR_PS_8 /* 8 bit port */ \ |
19580e66 | 288 | | BR_MS_FCM /* MSEL = FCM */ \ |
7d6a0982 JH |
289 | | BR_V) /* valid */ |
290 | #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ | |
b3379f3f | 291 | | OR_FCM_BCTLD \ |
19580e66 DL |
292 | | OR_FCM_CST \ |
293 | | OR_FCM_CHT \ | |
294 | | OR_FCM_SCY_1 \ | |
b3379f3f | 295 | | OR_FCM_RST \ |
19580e66 | 296 | | OR_FCM_TRLX \ |
8d85808f | 297 | | OR_FCM_EHTR) |
b3379f3f | 298 | /* 0xFFFF919E */ |
19580e66 | 299 | |
6d0f6bcf | 300 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 | 301 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
19580e66 DL |
302 | |
303 | /* | |
304 | * Serial Port | |
305 | */ | |
306 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_NS16550_SERIAL |
308 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
309 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
19580e66 | 310 | |
6d0f6bcf | 311 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8d85808f | 312 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
19580e66 | 313 | |
6d0f6bcf JCPV |
314 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
315 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
19580e66 | 316 | |
19580e66 | 317 | /* I2C */ |
00f792e0 HS |
318 | #define CONFIG_SYS_I2C |
319 | #define CONFIG_SYS_I2C_FSL | |
320 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
321 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
322 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
323 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
19580e66 DL |
324 | |
325 | /* | |
326 | * Config on-board RTC | |
327 | */ | |
328 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
6d0f6bcf | 329 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
19580e66 DL |
330 | |
331 | /* | |
332 | * General PCI | |
333 | * Addresses are mapped 1-1. | |
334 | */ | |
8d85808f JH |
335 | #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 |
336 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
337 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
6d0f6bcf JCPV |
338 | #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 |
339 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
340 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
341 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
342 | #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 | |
343 | #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ | |
19580e66 | 344 | |
6d0f6bcf JCPV |
345 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE |
346 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
347 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
19580e66 | 348 | |
8b34557c AV |
349 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
350 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 | |
351 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 | |
352 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 | |
353 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 | |
354 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
355 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
356 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 | |
357 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
358 | ||
359 | #define CONFIG_SYS_PCIE2_BASE 0xC0000000 | |
360 | #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 | |
361 | #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 | |
362 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 | |
363 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 | |
364 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 | |
365 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
366 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 | |
367 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 | |
368 | ||
19580e66 | 369 | #ifdef CONFIG_PCI |
842033e6 | 370 | #define CONFIG_PCI_INDIRECT_BRIDGE |
00f7bbae AV |
371 | #ifndef __ASSEMBLY__ |
372 | extern int board_pci_host_broken(void); | |
373 | #endif | |
be9b56df | 374 | #define CONFIG_PCIE |
19580e66 DL |
375 | #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ |
376 | ||
3bf1be3c | 377 | #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ |
6c3c5750 NB |
378 | #define CONFIG_USB_EHCI_FSL |
379 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
3bf1be3c | 380 | |
19580e66 DL |
381 | #undef CONFIG_EEPRO100 |
382 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 383 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
19580e66 DL |
384 | #endif /* CONFIG_PCI */ |
385 | ||
19580e66 DL |
386 | /* |
387 | * TSEC | |
388 | */ | |
389 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
6d0f6bcf | 390 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
8d85808f | 391 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 392 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
8d85808f | 393 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
19580e66 DL |
394 | |
395 | /* | |
396 | * TSEC ethernet configuration | |
397 | */ | |
398 | #define CONFIG_MII 1 /* MII PHY management */ | |
399 | #define CONFIG_TSEC1 1 | |
400 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
401 | #define CONFIG_TSEC2 1 | |
402 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
403 | #define TSEC1_PHY_ADDR 2 | |
404 | #define TSEC2_PHY_ADDR 3 | |
1da83a63 AV |
405 | #define TSEC1_PHY_ADDR_SGMII 8 |
406 | #define TSEC2_PHY_ADDR_SGMII 4 | |
19580e66 DL |
407 | #define TSEC1_PHYIDX 0 |
408 | #define TSEC2_PHYIDX 0 | |
409 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
410 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
411 | ||
412 | /* Options are: TSEC[0-1] */ | |
413 | #define CONFIG_ETHPRIME "eTSEC1" | |
414 | ||
6f8c85e8 DL |
415 | /* SERDES */ |
416 | #define CONFIG_FSL_SERDES | |
417 | #define CONFIG_FSL_SERDES1 0xe3000 | |
418 | #define CONFIG_FSL_SERDES2 0xe3100 | |
419 | ||
2eeb3e4f DL |
420 | /* |
421 | * SATA | |
422 | */ | |
423 | #define CONFIG_LIBATA | |
424 | #define CONFIG_FSL_SATA | |
425 | ||
6d0f6bcf | 426 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
2eeb3e4f | 427 | #define CONFIG_SATA1 |
6d0f6bcf | 428 | #define CONFIG_SYS_SATA1_OFFSET 0x18000 |
8d85808f JH |
429 | #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) |
430 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
2eeb3e4f | 431 | #define CONFIG_SATA2 |
6d0f6bcf | 432 | #define CONFIG_SYS_SATA2_OFFSET 0x19000 |
8d85808f JH |
433 | #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) |
434 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
2eeb3e4f DL |
435 | |
436 | #ifdef CONFIG_FSL_SATA | |
437 | #define CONFIG_LBA48 | |
2eeb3e4f DL |
438 | #endif |
439 | ||
19580e66 DL |
440 | /* |
441 | * Environment | |
442 | */ | |
6d0f6bcf | 443 | #ifndef CONFIG_SYS_RAMBOOT |
8d85808f JH |
444 | #define CONFIG_ENV_ADDR \ |
445 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
446 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
447 | #define CONFIG_ENV_SIZE 0x2000 | |
19580e66 | 448 | #else |
6d0f6bcf | 449 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 450 | #define CONFIG_ENV_SIZE 0x2000 |
19580e66 DL |
451 | #endif |
452 | ||
453 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 454 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
19580e66 DL |
455 | |
456 | /* | |
457 | * BOOTP options | |
458 | */ | |
459 | #define CONFIG_BOOTP_BOOTFILESIZE | |
460 | #define CONFIG_BOOTP_BOOTPATH | |
461 | #define CONFIG_BOOTP_GATEWAY | |
462 | #define CONFIG_BOOTP_HOSTNAME | |
463 | ||
19580e66 DL |
464 | /* |
465 | * Command line configuration. | |
466 | */ | |
19580e66 | 467 | |
19580e66 | 468 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
a059e90e | 469 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
19580e66 DL |
470 | |
471 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
472 | ||
e1ac387f AF |
473 | #ifdef CONFIG_MMC |
474 | #define CONFIG_FSL_ESDHC | |
a6da8b81 | 475 | #define CONFIG_FSL_ESDHC_PIN_MUX |
e1ac387f | 476 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR |
e1ac387f AF |
477 | #endif |
478 | ||
19580e66 DL |
479 | /* |
480 | * Miscellaneous configurable options | |
481 | */ | |
6d0f6bcf JCPV |
482 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
483 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
19580e66 | 484 | |
19580e66 DL |
485 | /* |
486 | * For booting Linux, the board info and command line data | |
9f530d59 | 487 | * have to be in the first 256 MB of memory, since this is |
19580e66 DL |
488 | * the maximum mapped by the Linux kernel during initialization. |
489 | */ | |
8d85808f | 490 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
63865278 | 491 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
19580e66 DL |
492 | |
493 | /* | |
494 | * Core HID Setup | |
495 | */ | |
1a2e203b KP |
496 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
497 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
498 | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 499 | #define CONFIG_SYS_HID2 HID2_HBE |
19580e66 | 500 | |
19580e66 DL |
501 | /* |
502 | * MMU Setup | |
503 | */ | |
31d82672 | 504 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
19580e66 DL |
505 | |
506 | /* DDR: cache cacheable */ | |
6d0f6bcf JCPV |
507 | #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE |
508 | #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) | |
19580e66 | 509 | |
8d85808f | 510 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ |
72cd4087 | 511 | | BATL_PP_RW \ |
8d85808f JH |
512 | | BATL_MEMCOHERENCE) |
513 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ | |
514 | | BATU_BL_256M \ | |
515 | | BATU_VS \ | |
516 | | BATU_VP) | |
6d0f6bcf JCPV |
517 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
518 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
19580e66 | 519 | |
8d85808f | 520 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ |
72cd4087 | 521 | | BATL_PP_RW \ |
8d85808f JH |
522 | | BATL_MEMCOHERENCE) |
523 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ | |
524 | | BATU_BL_256M \ | |
525 | | BATU_VS \ | |
526 | | BATU_VP) | |
6d0f6bcf JCPV |
527 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
528 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
19580e66 DL |
529 | |
530 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
8d85808f | 531 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ |
72cd4087 | 532 | | BATL_PP_RW \ |
8d85808f JH |
533 | | BATL_CACHEINHIBIT \ |
534 | | BATL_GUARDEDSTORAGE) | |
535 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ | |
536 | | BATU_BL_8M \ | |
537 | | BATU_VS \ | |
538 | | BATU_VP) | |
6d0f6bcf JCPV |
539 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
540 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
19580e66 DL |
541 | |
542 | /* BCSR: cache-inhibit and guarded */ | |
8d85808f | 543 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ |
72cd4087 | 544 | | BATL_PP_RW \ |
8d85808f JH |
545 | | BATL_CACHEINHIBIT \ |
546 | | BATL_GUARDEDSTORAGE) | |
547 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ | |
548 | | BATU_BL_128K \ | |
549 | | BATU_VS \ | |
550 | | BATU_VP) | |
6d0f6bcf JCPV |
551 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
552 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
19580e66 DL |
553 | |
554 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
8d85808f | 555 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 556 | | BATL_PP_RW \ |
8d85808f JH |
557 | | BATL_MEMCOHERENCE) |
558 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ | |
559 | | BATU_BL_32M \ | |
560 | | BATU_VS \ | |
561 | | BATU_VP) | |
562 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 563 | | BATL_PP_RW \ |
8d85808f JH |
564 | | BATL_CACHEINHIBIT \ |
565 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 566 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
19580e66 DL |
567 | |
568 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 569 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
8d85808f JH |
570 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ |
571 | | BATU_BL_128K \ | |
572 | | BATU_VS \ | |
573 | | BATU_VP) | |
6d0f6bcf JCPV |
574 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
575 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
19580e66 DL |
576 | |
577 | #ifdef CONFIG_PCI | |
578 | /* PCI MEM space: cacheable */ | |
8d85808f | 579 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ |
72cd4087 | 580 | | BATL_PP_RW \ |
8d85808f JH |
581 | | BATL_MEMCOHERENCE) |
582 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ | |
583 | | BATU_BL_256M \ | |
584 | | BATU_VS \ | |
585 | | BATU_VP) | |
6d0f6bcf JCPV |
586 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
587 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
19580e66 | 588 | /* PCI MMIO space: cache-inhibit and guarded */ |
8d85808f | 589 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ |
72cd4087 | 590 | | BATL_PP_RW \ |
8d85808f JH |
591 | | BATL_CACHEINHIBIT \ |
592 | | BATL_GUARDEDSTORAGE) | |
593 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ | |
594 | | BATU_BL_256M \ | |
595 | | BATU_VS \ | |
596 | | BATU_VP) | |
6d0f6bcf JCPV |
597 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
598 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
19580e66 | 599 | #else |
6d0f6bcf JCPV |
600 | #define CONFIG_SYS_IBAT6L (0) |
601 | #define CONFIG_SYS_IBAT6U (0) | |
602 | #define CONFIG_SYS_IBAT7L (0) | |
603 | #define CONFIG_SYS_IBAT7U (0) | |
604 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
605 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
606 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
607 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
19580e66 DL |
608 | #endif |
609 | ||
19580e66 DL |
610 | #if defined(CONFIG_CMD_KGDB) |
611 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
19580e66 DL |
612 | #endif |
613 | ||
614 | /* | |
615 | * Environment Configuration | |
616 | */ | |
617 | ||
618 | #define CONFIG_ENV_OVERWRITE | |
619 | ||
620 | #if defined(CONFIG_TSEC_ENET) | |
621 | #define CONFIG_HAS_ETH0 | |
19580e66 | 622 | #define CONFIG_HAS_ETH1 |
19580e66 DL |
623 | #endif |
624 | ||
79f516bc | 625 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
19580e66 | 626 | |
19580e66 | 627 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
8d85808f JH |
628 | "netdev=eth0\0" \ |
629 | "consoledev=ttyS0\0" \ | |
630 | "ramdiskaddr=1000000\0" \ | |
631 | "ramdiskfile=ramfs.83xx\0" \ | |
632 | "fdtaddr=780000\0" \ | |
633 | "fdtfile=mpc8379_mds.dtb\0" \ | |
634 | "" | |
19580e66 DL |
635 | |
636 | #define CONFIG_NFSBOOTCOMMAND \ | |
8d85808f JH |
637 | "setenv bootargs root=/dev/nfs rw " \ |
638 | "nfsroot=$serverip:$rootpath " \ | |
639 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
640 | "$netdev:off " \ | |
641 | "console=$consoledev,$baudrate $othbootargs;" \ | |
642 | "tftp $loadaddr $bootfile;" \ | |
643 | "tftp $fdtaddr $fdtfile;" \ | |
644 | "bootm $loadaddr - $fdtaddr" | |
19580e66 DL |
645 | |
646 | #define CONFIG_RAMBOOTCOMMAND \ | |
8d85808f JH |
647 | "setenv bootargs root=/dev/ram rw " \ |
648 | "console=$consoledev,$baudrate $othbootargs;" \ | |
649 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
650 | "tftp $loadaddr $bootfile;" \ | |
651 | "tftp $fdtaddr $fdtfile;" \ | |
652 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
19580e66 | 653 | |
19580e66 DL |
654 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
655 | ||
656 | #endif /* __CONFIG_H */ |