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19580e66 DL |
1 | /* |
2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
3 | * Dave Liu <daveliu@freescale.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #ifndef __CONFIG_H | |
22 | #define __CONFIG_H | |
23 | ||
19580e66 DL |
24 | /* |
25 | * High Level Configuration Options | |
26 | */ | |
27 | #define CONFIG_E300 1 /* E300 family */ | |
0f898604 | 28 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ |
2c7920af | 29 | #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ |
19580e66 DL |
30 | #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ |
31 | ||
32 | /* | |
33 | * System Clock Setup | |
34 | */ | |
35 | #ifdef CONFIG_PCISLAVE | |
36 | #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ | |
37 | #else | |
38 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
39 | #endif | |
40 | ||
41 | #ifndef CONFIG_SYS_CLK_FREQ | |
42 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
43 | #endif | |
44 | ||
45 | /* | |
46 | * Hardware Reset Configuration Word | |
47 | * if CLKIN is 66MHz, then | |
48 | * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz | |
49 | */ | |
6d0f6bcf | 50 | #define CONFIG_SYS_HRCW_LOW (\ |
19580e66 DL |
51 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
52 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
53 | HRCWL_SVCOD_DIV_2 |\ | |
54 | HRCWL_CSB_TO_CLKIN_6X1 |\ | |
55 | HRCWL_CORE_TO_CSB_1_5X1) | |
56 | ||
57 | #ifdef CONFIG_PCISLAVE | |
6d0f6bcf | 58 | #define CONFIG_SYS_HRCW_HIGH (\ |
19580e66 DL |
59 | HRCWH_PCI_AGENT |\ |
60 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
61 | HRCWH_CORE_ENABLE |\ | |
62 | HRCWH_FROM_0XFFF00100 |\ | |
63 | HRCWH_BOOTSEQ_DISABLE |\ | |
64 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
65 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
66 | HRCWH_RL_EXT_LEGACY |\ | |
67 | HRCWH_TSEC1M_IN_RGMII |\ | |
68 | HRCWH_TSEC2M_IN_RGMII |\ | |
69 | HRCWH_BIG_ENDIAN |\ | |
70 | HRCWH_LDP_CLEAR) | |
71 | #else | |
6d0f6bcf | 72 | #define CONFIG_SYS_HRCW_HIGH (\ |
19580e66 DL |
73 | HRCWH_PCI_HOST |\ |
74 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
75 | HRCWH_CORE_ENABLE |\ | |
76 | HRCWH_FROM_0X00000100 |\ | |
77 | HRCWH_BOOTSEQ_DISABLE |\ | |
78 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
79 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
80 | HRCWH_RL_EXT_LEGACY |\ | |
81 | HRCWH_TSEC1M_IN_RGMII |\ | |
82 | HRCWH_TSEC2M_IN_RGMII |\ | |
83 | HRCWH_BIG_ENDIAN |\ | |
84 | HRCWH_LDP_CLEAR) | |
85 | #endif | |
86 | ||
bd4458cb | 87 | /* Arbiter Configuration Register */ |
6d0f6bcf JCPV |
88 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ |
89 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ | |
bd4458cb DL |
90 | |
91 | /* System Priority Control Register */ | |
6d0f6bcf | 92 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ |
bd4458cb | 93 | |
19580e66 | 94 | /* |
bd4458cb | 95 | * IP blocks clock configuration |
19580e66 | 96 | */ |
6d0f6bcf JCPV |
97 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ |
98 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ | |
99 | #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ | |
19580e66 DL |
100 | |
101 | /* | |
102 | * System IO Config | |
103 | */ | |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_SICRH 0x00000000 |
105 | #define CONFIG_SYS_SICRL 0x00000000 | |
19580e66 DL |
106 | |
107 | /* | |
108 | * Output Buffer Impedance | |
109 | */ | |
6d0f6bcf | 110 | #define CONFIG_SYS_OBIR 0x31100000 |
19580e66 DL |
111 | |
112 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
113 | #define CONFIG_BOARD_EARLY_INIT_R | |
c78c6783 | 114 | #define CONFIG_HWCONFIG |
19580e66 DL |
115 | |
116 | /* | |
117 | * IMMR new address | |
118 | */ | |
6d0f6bcf | 119 | #define CONFIG_SYS_IMMR 0xE0000000 |
19580e66 DL |
120 | |
121 | /* | |
122 | * DDR Setup | |
123 | */ | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
125 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
126 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
127 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
128 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
129 | #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */ | |
19580e66 DL |
130 | |
131 | #undef CONFIG_DDR_ECC /* support DDR ECC function */ | |
132 | #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ | |
133 | ||
134 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
135 | #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ | |
136 | ||
137 | #if defined(CONFIG_SPD_EEPROM) | |
138 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ | |
139 | #else | |
140 | /* | |
141 | * Manually set up DDR parameters | |
7e74d63d | 142 | * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM |
19580e66 DL |
143 | * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 |
144 | */ | |
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_DDR_SIZE 512 /* MB */ |
146 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f | |
147 | #define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ | |
19580e66 DL |
148 | | 0x00010000 /* ODT_WR to CSn */ \ |
149 | | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 ) | |
150 | /* 0x80010202 */ | |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
152 | #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ | |
19580e66 DL |
153 | | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ |
154 | | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ | |
155 | | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ | |
156 | | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ | |
157 | | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ | |
158 | | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | |
159 | | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) | |
160 | /* 0x00620802 */ | |
6d0f6bcf | 161 | #define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ |
19580e66 DL |
162 | | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ |
163 | | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ | |
164 | | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ | |
165 | | (13 << TIMING_CFG1_REFREC_SHIFT ) \ | |
166 | | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ | |
167 | | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | |
168 | | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) | |
169 | /* 0x3935d322 */ | |
6d0f6bcf | 170 | #define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ |
19580e66 DL |
171 | | ( 6 << TIMING_CFG2_CPO_SHIFT ) \ |
172 | | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ | |
173 | | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | |
174 | | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | |
175 | | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ | |
176 | | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) ) | |
7e74d63d | 177 | /* 0x131088c8 */ |
6d0f6bcf | 178 | #define CONFIG_SYS_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \ |
19580e66 DL |
179 | | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) |
180 | /* 0x03E00100 */ | |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 |
182 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ | |
183 | #define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ | |
19580e66 | 184 | | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) ) |
7e74d63d | 185 | /* ODT 150ohm CL=3, AL=1 on SDRAM */ |
6d0f6bcf | 186 | #define CONFIG_SYS_DDR_MODE2 0x00000000 |
19580e66 DL |
187 | #endif |
188 | ||
189 | /* | |
190 | * Memory test | |
191 | */ | |
6d0f6bcf JCPV |
192 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
193 | #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ | |
194 | #define CONFIG_SYS_MEMTEST_END 0x00140000 | |
19580e66 DL |
195 | |
196 | /* | |
197 | * The reserved memory | |
198 | */ | |
6d0f6bcf | 199 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
19580e66 | 200 | |
6d0f6bcf JCPV |
201 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
202 | #define CONFIG_SYS_RAMBOOT | |
19580e66 | 203 | #else |
6d0f6bcf | 204 | #undef CONFIG_SYS_RAMBOOT |
19580e66 DL |
205 | #endif |
206 | ||
6d0f6bcf | 207 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
b3379f3f | 208 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
6d0f6bcf | 209 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
19580e66 DL |
210 | |
211 | /* | |
212 | * Initial RAM Base Address Setup | |
213 | */ | |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
215 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
216 | #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ | |
217 | #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
218 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
19580e66 DL |
219 | |
220 | /* | |
221 | * Local Bus Configuration & Clock Setup | |
222 | */ | |
c7190f02 KP |
223 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
224 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 | |
6d0f6bcf | 225 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
19580e66 DL |
226 | |
227 | /* | |
228 | * FLASH on the Local Bus | |
229 | */ | |
6d0f6bcf | 230 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 231 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf JCPV |
232 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
233 | #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ | |
234 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
19580e66 | 235 | |
6d0f6bcf JCPV |
236 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ |
237 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ | |
19580e66 | 238 | |
6d0f6bcf | 239 | #define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ |
ded08317 DL |
240 | | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ |
241 | | BR_V ) /* valid */ | |
6d0f6bcf | 242 | #define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ |
ded08317 DL |
243 | | OR_UPM_XAM \ |
244 | | OR_GPCM_CSNT \ | |
f9023afb | 245 | | OR_GPCM_ACS_DIV2 \ |
ded08317 DL |
246 | | OR_GPCM_XACS \ |
247 | | OR_GPCM_SCY_15 \ | |
248 | | OR_GPCM_TRLX \ | |
249 | | OR_GPCM_EHTR \ | |
250 | | OR_GPCM_EAD ) | |
251 | /* 0xFE000FF7 */ | |
19580e66 | 252 | |
6d0f6bcf JCPV |
253 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
254 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
19580e66 | 255 | |
6d0f6bcf JCPV |
256 | #undef CONFIG_SYS_FLASH_CHECKSUM |
257 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
258 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
19580e66 DL |
259 | |
260 | /* | |
261 | * BCSR on the Local Bus | |
262 | */ | |
6d0f6bcf JCPV |
263 | #define CONFIG_SYS_BCSR 0xF8000000 |
264 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ | |
265 | #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ | |
19580e66 | 266 | |
6d0f6bcf JCPV |
267 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */ |
268 | #define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ | |
19580e66 DL |
269 | |
270 | /* | |
271 | * NAND Flash on the Local Bus | |
272 | */ | |
b3379f3f AV |
273 | #define CONFIG_CMD_NAND 1 |
274 | #define CONFIG_MTD_NAND_VERIFY_WRITE 1 | |
275 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
b3379f3f AV |
276 | #define CONFIG_NAND_FSL_ELBC 1 |
277 | ||
6d0f6bcf JCPV |
278 | #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ |
279 | #define CONFIG_SYS_BR3_PRELIM ( CONFIG_SYS_NAND_BASE \ | |
19580e66 DL |
280 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
281 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
282 | | BR_MS_FCM /* MSEL = FCM */ \ | |
283 | | BR_V ) /* valid */ | |
6d0f6bcf | 284 | #define CONFIG_SYS_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \ |
b3379f3f | 285 | | OR_FCM_BCTLD \ |
19580e66 DL |
286 | | OR_FCM_CST \ |
287 | | OR_FCM_CHT \ | |
288 | | OR_FCM_SCY_1 \ | |
b3379f3f | 289 | | OR_FCM_RST \ |
19580e66 DL |
290 | | OR_FCM_TRLX \ |
291 | | OR_FCM_EHTR ) | |
b3379f3f | 292 | /* 0xFFFF919E */ |
19580e66 | 293 | |
6d0f6bcf JCPV |
294 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE |
295 | #define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ | |
19580e66 DL |
296 | |
297 | /* | |
298 | * Serial Port | |
299 | */ | |
300 | #define CONFIG_CONS_INDEX 1 | |
301 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_NS16550 |
303 | #define CONFIG_SYS_NS16550_SERIAL | |
304 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
305 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
19580e66 | 306 | |
6d0f6bcf | 307 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
19580e66 DL |
308 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
309 | ||
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
311 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
19580e66 DL |
312 | |
313 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
314 | #define CONFIG_SYS_HUSH_PARSER |
315 | #ifdef CONFIG_SYS_HUSH_PARSER | |
316 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
19580e66 DL |
317 | #endif |
318 | ||
319 | /* Pass open firmware flat tree */ | |
320 | #define CONFIG_OF_LIBFDT 1 | |
321 | #define CONFIG_OF_BOARD_SETUP 1 | |
5b8bc606 | 322 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
19580e66 DL |
323 | |
324 | /* I2C */ | |
325 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
326 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
327 | #define CONFIG_FSL_I2C | |
6d0f6bcf JCPV |
328 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
329 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
330 | #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ | |
331 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
332 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
19580e66 DL |
333 | |
334 | /* | |
335 | * Config on-board RTC | |
336 | */ | |
337 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
6d0f6bcf | 338 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
19580e66 DL |
339 | |
340 | /* | |
341 | * General PCI | |
342 | * Addresses are mapped 1-1. | |
343 | */ | |
6d0f6bcf JCPV |
344 | #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 |
345 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
346 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
347 | #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 | |
348 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
349 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
350 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
351 | #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 | |
352 | #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ | |
19580e66 | 353 | |
6d0f6bcf JCPV |
354 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE |
355 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
356 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
19580e66 | 357 | |
8b34557c AV |
358 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
359 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 | |
360 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 | |
361 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 | |
362 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 | |
363 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
364 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
365 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 | |
366 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
367 | ||
368 | #define CONFIG_SYS_PCIE2_BASE 0xC0000000 | |
369 | #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 | |
370 | #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 | |
371 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 | |
372 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 | |
373 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 | |
374 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
375 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 | |
376 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 | |
377 | ||
19580e66 | 378 | #ifdef CONFIG_PCI |
00f7bbae AV |
379 | #ifndef __ASSEMBLY__ |
380 | extern int board_pci_host_broken(void); | |
381 | #endif | |
be9b56df | 382 | #define CONFIG_PCIE |
19580e66 DL |
383 | #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ |
384 | ||
3bf1be3c AV |
385 | #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ |
386 | ||
19580e66 DL |
387 | #define CONFIG_NET_MULTI |
388 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
389 | ||
390 | #undef CONFIG_EEPRO100 | |
391 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 392 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
19580e66 DL |
393 | #endif /* CONFIG_PCI */ |
394 | ||
395 | #ifndef CONFIG_NET_MULTI | |
396 | #define CONFIG_NET_MULTI 1 | |
397 | #endif | |
398 | ||
399 | /* | |
400 | * TSEC | |
401 | */ | |
402 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
6d0f6bcf JCPV |
403 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
404 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) | |
405 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 | |
406 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) | |
19580e66 DL |
407 | |
408 | /* | |
409 | * TSEC ethernet configuration | |
410 | */ | |
411 | #define CONFIG_MII 1 /* MII PHY management */ | |
412 | #define CONFIG_TSEC1 1 | |
413 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
414 | #define CONFIG_TSEC2 1 | |
415 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
416 | #define TSEC1_PHY_ADDR 2 | |
417 | #define TSEC2_PHY_ADDR 3 | |
1da83a63 AV |
418 | #define TSEC1_PHY_ADDR_SGMII 8 |
419 | #define TSEC2_PHY_ADDR_SGMII 4 | |
19580e66 DL |
420 | #define TSEC1_PHYIDX 0 |
421 | #define TSEC2_PHYIDX 0 | |
422 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
423 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
424 | ||
425 | /* Options are: TSEC[0-1] */ | |
426 | #define CONFIG_ETHPRIME "eTSEC1" | |
427 | ||
6f8c85e8 DL |
428 | /* SERDES */ |
429 | #define CONFIG_FSL_SERDES | |
430 | #define CONFIG_FSL_SERDES1 0xe3000 | |
431 | #define CONFIG_FSL_SERDES2 0xe3100 | |
432 | ||
2eeb3e4f DL |
433 | /* |
434 | * SATA | |
435 | */ | |
436 | #define CONFIG_LIBATA | |
437 | #define CONFIG_FSL_SATA | |
438 | ||
6d0f6bcf | 439 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
2eeb3e4f | 440 | #define CONFIG_SATA1 |
6d0f6bcf JCPV |
441 | #define CONFIG_SYS_SATA1_OFFSET 0x18000 |
442 | #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) | |
443 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
2eeb3e4f | 444 | #define CONFIG_SATA2 |
6d0f6bcf JCPV |
445 | #define CONFIG_SYS_SATA2_OFFSET 0x19000 |
446 | #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) | |
447 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
2eeb3e4f DL |
448 | |
449 | #ifdef CONFIG_FSL_SATA | |
450 | #define CONFIG_LBA48 | |
451 | #define CONFIG_CMD_SATA | |
452 | #define CONFIG_DOS_PARTITION | |
453 | #define CONFIG_CMD_EXT2 | |
454 | #endif | |
455 | ||
19580e66 DL |
456 | /* |
457 | * Environment | |
458 | */ | |
6d0f6bcf | 459 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 460 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 461 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 JCPV |
462 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
463 | #define CONFIG_ENV_SIZE 0x2000 | |
19580e66 | 464 | #else |
6d0f6bcf | 465 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 466 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 467 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 468 | #define CONFIG_ENV_SIZE 0x2000 |
19580e66 DL |
469 | #endif |
470 | ||
471 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 472 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
19580e66 DL |
473 | |
474 | /* | |
475 | * BOOTP options | |
476 | */ | |
477 | #define CONFIG_BOOTP_BOOTFILESIZE | |
478 | #define CONFIG_BOOTP_BOOTPATH | |
479 | #define CONFIG_BOOTP_GATEWAY | |
480 | #define CONFIG_BOOTP_HOSTNAME | |
481 | ||
482 | ||
483 | /* | |
484 | * Command line configuration. | |
485 | */ | |
486 | #include <config_cmd_default.h> | |
487 | ||
488 | #define CONFIG_CMD_PING | |
489 | #define CONFIG_CMD_I2C | |
490 | #define CONFIG_CMD_MII | |
491 | #define CONFIG_CMD_DATE | |
492 | ||
493 | #if defined(CONFIG_PCI) | |
494 | #define CONFIG_CMD_PCI | |
495 | #endif | |
496 | ||
6d0f6bcf | 497 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 498 | #undef CONFIG_CMD_SAVEENV |
19580e66 DL |
499 | #undef CONFIG_CMD_LOADS |
500 | #endif | |
501 | ||
502 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
503 | ||
504 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
505 | ||
e1ac387f AF |
506 | #define CONFIG_MMC 1 |
507 | ||
508 | #ifdef CONFIG_MMC | |
509 | #define CONFIG_FSL_ESDHC | |
510 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR | |
511 | #define CONFIG_CMD_MMC | |
512 | #define CONFIG_GENERIC_MMC | |
513 | #define CONFIG_CMD_EXT2 | |
514 | #define CONFIG_CMD_FAT | |
515 | #define CONFIG_DOS_PARTITION | |
516 | #endif | |
517 | ||
19580e66 DL |
518 | /* |
519 | * Miscellaneous configurable options | |
520 | */ | |
6d0f6bcf JCPV |
521 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
522 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
523 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
19580e66 DL |
524 | |
525 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 526 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
19580e66 | 527 | #else |
6d0f6bcf | 528 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
19580e66 DL |
529 | #endif |
530 | ||
6d0f6bcf JCPV |
531 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
532 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
533 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
534 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
19580e66 DL |
535 | |
536 | /* | |
537 | * For booting Linux, the board info and command line data | |
538 | * have to be in the first 8 MB of memory, since this is | |
539 | * the maximum mapped by the Linux kernel during initialization. | |
540 | */ | |
6d0f6bcf | 541 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
19580e66 DL |
542 | |
543 | /* | |
544 | * Core HID Setup | |
545 | */ | |
6d0f6bcf JCPV |
546 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
547 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | |
548 | #define CONFIG_SYS_HID2 HID2_HBE | |
19580e66 | 549 | |
19580e66 DL |
550 | /* |
551 | * MMU Setup | |
552 | */ | |
31d82672 | 553 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
19580e66 DL |
554 | |
555 | /* DDR: cache cacheable */ | |
6d0f6bcf JCPV |
556 | #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE |
557 | #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) | |
19580e66 | 558 | |
6d0f6bcf JCPV |
559 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) |
560 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) | |
561 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
562 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
19580e66 | 563 | |
6d0f6bcf JCPV |
564 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) |
565 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) | |
566 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
567 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
19580e66 DL |
568 | |
569 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
6d0f6bcf | 570 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \ |
19580e66 | 571 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
6d0f6bcf JCPV |
572 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) |
573 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
574 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
19580e66 DL |
575 | |
576 | /* BCSR: cache-inhibit and guarded */ | |
6d0f6bcf | 577 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR | BATL_PP_10 | \ |
19580e66 | 578 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
6d0f6bcf JCPV |
579 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) |
580 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
581 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
19580e66 DL |
582 | |
583 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
6d0f6bcf JCPV |
584 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
585 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) | |
586 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ | |
19580e66 | 587 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
6d0f6bcf | 588 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
19580e66 DL |
589 | |
590 | /* Stack in dcache: cacheable, no memory coherence */ | |
6d0f6bcf JCPV |
591 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) |
592 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
593 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
594 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
19580e66 DL |
595 | |
596 | #ifdef CONFIG_PCI | |
597 | /* PCI MEM space: cacheable */ | |
6d0f6bcf JCPV |
598 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) |
599 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
600 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
601 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
19580e66 | 602 | /* PCI MMIO space: cache-inhibit and guarded */ |
6d0f6bcf | 603 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ |
19580e66 | 604 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
6d0f6bcf JCPV |
605 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) |
606 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
607 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
19580e66 | 608 | #else |
6d0f6bcf JCPV |
609 | #define CONFIG_SYS_IBAT6L (0) |
610 | #define CONFIG_SYS_IBAT6U (0) | |
611 | #define CONFIG_SYS_IBAT7L (0) | |
612 | #define CONFIG_SYS_IBAT7U (0) | |
613 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
614 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
615 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
616 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
19580e66 DL |
617 | #endif |
618 | ||
619 | /* | |
620 | * Internal Definitions | |
621 | * | |
622 | * Boot Flags | |
623 | */ | |
624 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
625 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
626 | ||
627 | #if defined(CONFIG_CMD_KGDB) | |
628 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
629 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
630 | #endif | |
631 | ||
632 | /* | |
633 | * Environment Configuration | |
634 | */ | |
635 | ||
636 | #define CONFIG_ENV_OVERWRITE | |
637 | ||
638 | #if defined(CONFIG_TSEC_ENET) | |
639 | #define CONFIG_HAS_ETH0 | |
19580e66 | 640 | #define CONFIG_HAS_ETH1 |
19580e66 DL |
641 | #endif |
642 | ||
643 | #define CONFIG_BAUDRATE 115200 | |
644 | ||
79f516bc | 645 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
19580e66 DL |
646 | |
647 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
648 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
649 | ||
650 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
651 | "netdev=eth0\0" \ | |
652 | "consoledev=ttyS0\0" \ | |
653 | "ramdiskaddr=1000000\0" \ | |
654 | "ramdiskfile=ramfs.83xx\0" \ | |
79f516bc | 655 | "fdtaddr=780000\0" \ |
270fe261 | 656 | "fdtfile=mpc8379_mds.dtb\0" \ |
19580e66 DL |
657 | "" |
658 | ||
659 | #define CONFIG_NFSBOOTCOMMAND \ | |
660 | "setenv bootargs root=/dev/nfs rw " \ | |
661 | "nfsroot=$serverip:$rootpath " \ | |
662 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
663 | "console=$consoledev,$baudrate $othbootargs;" \ | |
664 | "tftp $loadaddr $bootfile;" \ | |
665 | "tftp $fdtaddr $fdtfile;" \ | |
666 | "bootm $loadaddr - $fdtaddr" | |
667 | ||
668 | #define CONFIG_RAMBOOTCOMMAND \ | |
669 | "setenv bootargs root=/dev/ram rw " \ | |
670 | "console=$consoledev,$baudrate $othbootargs;" \ | |
671 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
672 | "tftp $loadaddr $bootfile;" \ | |
673 | "tftp $fdtaddr $fdtfile;" \ | |
674 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
675 | ||
676 | ||
677 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
678 | ||
679 | #endif /* __CONFIG_H */ |