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5e918a98 KP |
1 | /* |
2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
3 | * Kevin Lam <kevin.lam@freescale.com> | |
4 | * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
5e918a98 KP |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | /* | |
13 | * High Level Configuration Options | |
14 | */ | |
15 | #define CONFIG_E300 1 /* E300 family */ | |
2c7920af PT |
16 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ |
17 | #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ | |
5e918a98 KP |
18 | #define CONFIG_MPC837XERDB 1 |
19 | ||
2ae18241 WD |
20 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
21 | ||
5e918a98 KP |
22 | #define CONFIG_PCI 1 |
23 | ||
2bd7460e | 24 | #define CONFIG_BOARD_EARLY_INIT_F |
89c7784e | 25 | #define CONFIG_MISC_INIT_R |
c9646ed7 | 26 | #define CONFIG_HWCONFIG |
89c7784e TT |
27 | |
28 | /* | |
29 | * On-board devices | |
30 | */ | |
31 | #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ | |
32 | #define CONFIG_VSC7385_ENET | |
33 | ||
5e918a98 KP |
34 | /* |
35 | * System Clock Setup | |
36 | */ | |
37 | #ifdef CONFIG_PCISLAVE | |
38 | #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ | |
39 | #else | |
40 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ | |
be9b56df | 41 | #define CONFIG_PCIE |
5e918a98 KP |
42 | #endif |
43 | ||
44 | #ifndef CONFIG_SYS_CLK_FREQ | |
45 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
46 | #endif | |
47 | ||
48 | /* | |
49 | * Hardware Reset Configuration Word | |
50 | */ | |
6d0f6bcf | 51 | #define CONFIG_SYS_HRCW_LOW (\ |
5e918a98 KP |
52 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
53 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
54 | HRCWL_SVCOD_DIV_2 |\ | |
55 | HRCWL_CSB_TO_CLKIN_5X1 |\ | |
56 | HRCWL_CORE_TO_CSB_2X1) | |
57 | ||
58 | #ifdef CONFIG_PCISLAVE | |
6d0f6bcf | 59 | #define CONFIG_SYS_HRCW_HIGH (\ |
5e918a98 KP |
60 | HRCWH_PCI_AGENT |\ |
61 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
62 | HRCWH_CORE_ENABLE |\ | |
63 | HRCWH_FROM_0XFFF00100 |\ | |
64 | HRCWH_BOOTSEQ_DISABLE |\ | |
65 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
66 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
67 | HRCWH_RL_EXT_LEGACY |\ | |
68 | HRCWH_TSEC1M_IN_RGMII |\ | |
69 | HRCWH_TSEC2M_IN_RGMII |\ | |
70 | HRCWH_BIG_ENDIAN |\ | |
71 | HRCWH_LDP_CLEAR) | |
72 | #else | |
6d0f6bcf | 73 | #define CONFIG_SYS_HRCW_HIGH (\ |
5e918a98 KP |
74 | HRCWH_PCI_HOST |\ |
75 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
76 | HRCWH_CORE_ENABLE |\ | |
77 | HRCWH_FROM_0X00000100 |\ | |
78 | HRCWH_BOOTSEQ_DISABLE |\ | |
79 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
80 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
81 | HRCWH_RL_EXT_LEGACY |\ | |
82 | HRCWH_TSEC1M_IN_RGMII |\ | |
83 | HRCWH_TSEC2M_IN_RGMII |\ | |
84 | HRCWH_BIG_ENDIAN |\ | |
85 | HRCWH_LDP_CLEAR) | |
86 | #endif | |
87 | ||
6d0f6bcf | 88 | /* System performance - define the value i.e. CONFIG_SYS_XXX |
5e918a98 KP |
89 | */ |
90 | ||
91 | /* Arbiter Configuration Register */ | |
6d0f6bcf | 92 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
5afe9722 | 93 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
5e918a98 KP |
94 | |
95 | /* System Priority Control Regsiter */ | |
5afe9722 | 96 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ |
5e918a98 KP |
97 | |
98 | /* System Clock Configuration Register */ | |
6d0f6bcf JCPV |
99 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ |
100 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ | |
5afe9722 | 101 | #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ |
5e918a98 KP |
102 | |
103 | /* | |
104 | * System IO Config | |
105 | */ | |
6d0f6bcf JCPV |
106 | #define CONFIG_SYS_SICRH 0x08200000 |
107 | #define CONFIG_SYS_SICRL 0x00000000 | |
5e918a98 KP |
108 | |
109 | /* | |
110 | * Output Buffer Impedance | |
111 | */ | |
6d0f6bcf | 112 | #define CONFIG_SYS_OBIR 0x30100000 |
5e918a98 KP |
113 | |
114 | /* | |
115 | * IMMR new address | |
116 | */ | |
6d0f6bcf | 117 | #define CONFIG_SYS_IMMR 0xE0000000 |
5e918a98 | 118 | |
89c7784e TT |
119 | /* |
120 | * Device configurations | |
121 | */ | |
122 | ||
123 | /* Vitesse 7385 */ | |
124 | ||
125 | #ifdef CONFIG_VSC7385_ENET | |
126 | ||
127 | #define CONFIG_TSEC2 | |
128 | ||
129 | /* The flash address and size of the VSC7385 firmware image */ | |
130 | #define CONFIG_VSC7385_IMAGE 0xFE7FE000 | |
131 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
132 | ||
133 | #endif | |
134 | ||
5e918a98 KP |
135 | /* |
136 | * DDR Setup | |
137 | */ | |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
139 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
140 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
141 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 | |
142 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
5e918a98 | 143 | |
6d0f6bcf | 144 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) |
5e918a98 KP |
145 | |
146 | #undef CONFIG_DDR_ECC /* support DDR ECC function */ | |
147 | #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ | |
148 | ||
149 | #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ | |
150 | ||
151 | /* | |
152 | * Manually set up DDR parameters | |
153 | */ | |
6d0f6bcf | 154 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
2fef4020 JH |
155 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f |
156 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | |
157 | | CSCONFIG_ODT_WR_ONLY_CURRENT \ | |
158 | | CSCONFIG_ROW_BIT_13 \ | |
159 | | CSCONFIG_COL_BIT_10) | |
5e918a98 | 160 | |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
162 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | |
5e918a98 KP |
163 | | (0 << TIMING_CFG0_WRT_SHIFT) \ |
164 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
165 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
166 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
167 | | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
168 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
169 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
5e918a98 | 170 | /* 0x00260802 */ /* DDR400 */ |
6d0f6bcf | 171 | #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ |
5e918a98 KP |
172 | | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ |
173 | | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
174 | | (7 << TIMING_CFG1_CASLAT_SHIFT) \ | |
175 | | (13 << TIMING_CFG1_REFREC_SHIFT) \ | |
176 | | (3 << TIMING_CFG1_WRREC_SHIFT) \ | |
177 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
178 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
5e918a98 | 179 | /* 0x3937d322 */ |
2fef4020 JH |
180 | #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
181 | | (5 << TIMING_CFG2_CPO_SHIFT) \ | |
182 | | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
183 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
184 | | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
185 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
186 | | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
187 | /* 0x02984cc8 */ | |
5e918a98 | 188 | |
8eceeb7f KP |
189 | #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
190 | | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
5e918a98 KP |
191 | /* 0x06090100 */ |
192 | ||
193 | #if defined(CONFIG_DDR_2T_TIMING) | |
5afe9722 | 194 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
2fef4020 JH |
195 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
196 | | SDRAM_CFG_32_BE \ | |
197 | | SDRAM_CFG_2T_EN) | |
198 | /* 0x43088000 */ | |
5e918a98 | 199 | #else |
5afe9722 | 200 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
2fef4020 | 201 | | SDRAM_CFG_SDRAM_TYPE_DDR2) |
5afe9722 | 202 | /* 0x43000000 */ |
5e918a98 | 203 | #endif |
6d0f6bcf | 204 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ |
8eceeb7f | 205 | #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ |
5afe9722 JH |
206 | | (0x0442 << SDRAM_MODE_SD_SHIFT)) |
207 | /* 0x04400442 */ /* DDR400 */ | |
6d0f6bcf | 208 | #define CONFIG_SYS_DDR_MODE2 0x00000000 |
5e918a98 KP |
209 | |
210 | /* | |
211 | * Memory test | |
212 | */ | |
6d0f6bcf JCPV |
213 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
214 | #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ | |
215 | #define CONFIG_SYS_MEMTEST_END 0x0ef70010 | |
5e918a98 KP |
216 | |
217 | /* | |
218 | * The reserved memory | |
219 | */ | |
14d0a02a | 220 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
5e918a98 | 221 | |
6d0f6bcf JCPV |
222 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
223 | #define CONFIG_SYS_RAMBOOT | |
5e918a98 | 224 | #else |
6d0f6bcf | 225 | #undef CONFIG_SYS_RAMBOOT |
5e918a98 KP |
226 | #endif |
227 | ||
5afe9722 JH |
228 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
229 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
5e918a98 KP |
230 | |
231 | /* | |
232 | * Initial RAM Base Address Setup | |
233 | */ | |
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
235 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 236 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
5afe9722 JH |
237 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
238 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
5e918a98 KP |
239 | |
240 | /* | |
241 | * Local Bus Configuration & Clock Setup | |
242 | */ | |
c7190f02 KP |
243 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
244 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 | |
6d0f6bcf | 245 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
0914f483 | 246 | #define CONFIG_FSL_ELBC 1 |
5e918a98 KP |
247 | |
248 | /* | |
249 | * FLASH on the Local Bus | |
250 | */ | |
6d0f6bcf | 251 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 252 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf JCPV |
253 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
254 | #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ | |
5e918a98 | 255 | |
5afe9722 JH |
256 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
257 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ | |
258 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ | |
5e918a98 | 259 | |
5afe9722 JH |
260 | /* Window base at flash base */ |
261 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
6d0f6bcf | 262 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ |
5e918a98 | 263 | |
5afe9722 | 264 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
265 | | BR_PS_16 /* 16 bit port */ \ |
266 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
267 | | BR_V) /* valid */ | |
268 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
5e918a98 KP |
269 | | OR_GPCM_XACS \ |
270 | | OR_GPCM_SCY_9 \ | |
7d6a0982 | 271 | | OR_GPCM_EHTR_SET \ |
5e918a98 | 272 | | OR_GPCM_EAD) |
7d6a0982 | 273 | /* 0xFF800191 */ |
5e918a98 | 274 | |
6d0f6bcf JCPV |
275 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
276 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
5e918a98 | 277 | |
6d0f6bcf JCPV |
278 | #undef CONFIG_SYS_FLASH_CHECKSUM |
279 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
280 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
5e918a98 | 281 | |
46a3aeea AV |
282 | /* |
283 | * NAND Flash on the Local Bus | |
284 | */ | |
7d6a0982 | 285 | #define CONFIG_SYS_NAND_BASE 0xE0600000 |
5afe9722 | 286 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ |
7d6a0982 JH |
287 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
288 | | BR_PS_8 /* 8 bit port */ \ | |
289 | | BR_MS_FCM /* MSEL = FCM */ \ | |
5afe9722 | 290 | | BR_V) /* valid */ |
7d6a0982 | 291 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ |
5afe9722 JH |
292 | | OR_FCM_CSCT \ |
293 | | OR_FCM_CST \ | |
294 | | OR_FCM_CHT \ | |
295 | | OR_FCM_SCY_1 \ | |
296 | | OR_FCM_TRLX \ | |
297 | | OR_FCM_EHTR) | |
6d0f6bcf | 298 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 | 299 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
46a3aeea | 300 | |
89c7784e TT |
301 | /* Vitesse 7385 */ |
302 | ||
6d0f6bcf | 303 | #define CONFIG_SYS_VSC7385_BASE 0xF0000000 |
5e918a98 | 304 | |
89c7784e TT |
305 | #ifdef CONFIG_VSC7385_ENET |
306 | ||
7d6a0982 JH |
307 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ |
308 | | BR_PS_8 \ | |
309 | | BR_MS_GPCM \ | |
310 | | BR_V) | |
311 | /* 0xF0000801 */ | |
312 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ | |
313 | | OR_GPCM_CSNT \ | |
314 | | OR_GPCM_XACS \ | |
315 | | OR_GPCM_SCY_15 \ | |
316 | | OR_GPCM_SETA \ | |
317 | | OR_GPCM_TRLX_SET \ | |
318 | | OR_GPCM_EHTR_SET \ | |
319 | | OR_GPCM_EAD) | |
320 | /* 0xfffe09ff */ | |
321 | ||
5afe9722 JH |
322 | /* Access Base */ |
323 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE | |
7d6a0982 | 324 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) |
5e918a98 | 325 | |
89c7784e TT |
326 | #endif |
327 | ||
5e918a98 KP |
328 | /* |
329 | * Serial Port | |
330 | */ | |
331 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
332 | #define CONFIG_SYS_NS16550 |
333 | #define CONFIG_SYS_NS16550_SERIAL | |
334 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
335 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
5e918a98 | 336 | |
6d0f6bcf | 337 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
5afe9722 | 338 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
5e918a98 | 339 | |
6d0f6bcf JCPV |
340 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
341 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
5e918a98 | 342 | |
2bd7460e AV |
343 | /* SERDES */ |
344 | #define CONFIG_FSL_SERDES | |
345 | #define CONFIG_FSL_SERDES1 0xe3000 | |
346 | #define CONFIG_FSL_SERDES2 0xe3100 | |
347 | ||
5e918a98 | 348 | /* Use the HUSH parser */ |
6d0f6bcf | 349 | #define CONFIG_SYS_HUSH_PARSER |
5e918a98 KP |
350 | |
351 | /* Pass open firmware flat tree */ | |
352 | #define CONFIG_OF_LIBFDT 1 | |
353 | #define CONFIG_OF_BOARD_SETUP 1 | |
aabce7fb | 354 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
5e918a98 KP |
355 | |
356 | /* I2C */ | |
357 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
358 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
359 | #define CONFIG_FSL_I2C | |
5afe9722 JH |
360 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
361 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
6d0f6bcf | 362 | #define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */ |
5afe9722 JH |
363 | #define CONFIG_SYS_I2C_OFFSET 0x3000 |
364 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
5e918a98 KP |
365 | |
366 | /* | |
367 | * Config on-board RTC | |
368 | */ | |
369 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
6d0f6bcf | 370 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
5e918a98 KP |
371 | |
372 | /* | |
373 | * General PCI | |
374 | * Addresses are mapped 1-1. | |
375 | */ | |
5afe9722 JH |
376 | #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 |
377 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
378 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
6d0f6bcf JCPV |
379 | #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 |
380 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
381 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
382 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
383 | #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 | |
384 | #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ | |
385 | ||
386 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE | |
387 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
388 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
5e918a98 | 389 | |
7e915580 AV |
390 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
391 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 | |
392 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 | |
393 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 | |
394 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 | |
395 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
396 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
397 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 | |
398 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
399 | ||
400 | #define CONFIG_SYS_PCIE2_BASE 0xC0000000 | |
401 | #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 | |
402 | #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 | |
403 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 | |
404 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 | |
405 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 | |
406 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
407 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 | |
408 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 | |
409 | ||
5e918a98 | 410 | #ifdef CONFIG_PCI |
842033e6 | 411 | #define CONFIG_PCI_INDIRECT_BRIDGE |
5e918a98 KP |
412 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
413 | ||
5e918a98 | 414 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 415 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
5e918a98 KP |
416 | #endif /* CONFIG_PCI */ |
417 | ||
5e918a98 KP |
418 | /* |
419 | * TSEC | |
420 | */ | |
89c7784e | 421 | #ifdef CONFIG_TSEC_ENET |
5e918a98 | 422 | |
89c7784e TT |
423 | #define CONFIG_GMII /* MII PHY management */ |
424 | ||
425 | #define CONFIG_TSEC1 | |
426 | ||
427 | #ifdef CONFIG_TSEC1 | |
428 | #define CONFIG_HAS_ETH0 | |
5e918a98 | 429 | #define CONFIG_TSEC1_NAME "TSEC0" |
6d0f6bcf | 430 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
5e918a98 | 431 | #define TSEC1_PHY_ADDR 2 |
5e918a98 | 432 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
5e918a98 | 433 | #define TSEC1_PHYIDX 0 |
89c7784e | 434 | #endif |
5e918a98 | 435 | |
89c7784e TT |
436 | #ifdef CONFIG_TSEC2 |
437 | #define CONFIG_HAS_ETH1 | |
438 | #define CONFIG_TSEC2_NAME "TSEC1" | |
6d0f6bcf | 439 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
89c7784e TT |
440 | #define TSEC2_PHY_ADDR 0x1c |
441 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
442 | #define TSEC2_PHYIDX 0 | |
443 | #endif | |
5e918a98 KP |
444 | |
445 | /* Options are: TSEC[0-1] */ | |
446 | #define CONFIG_ETHPRIME "TSEC0" | |
447 | ||
89c7784e TT |
448 | #endif |
449 | ||
730e7929 KP |
450 | /* |
451 | * SATA | |
452 | */ | |
453 | #define CONFIG_LIBATA | |
454 | #define CONFIG_FSL_SATA | |
455 | ||
6d0f6bcf | 456 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
730e7929 | 457 | #define CONFIG_SATA1 |
6d0f6bcf | 458 | #define CONFIG_SYS_SATA1_OFFSET 0x18000 |
5afe9722 JH |
459 | #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) |
460 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
730e7929 | 461 | #define CONFIG_SATA2 |
6d0f6bcf | 462 | #define CONFIG_SYS_SATA2_OFFSET 0x19000 |
5afe9722 JH |
463 | #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) |
464 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
730e7929 KP |
465 | |
466 | #ifdef CONFIG_FSL_SATA | |
467 | #define CONFIG_LBA48 | |
468 | #define CONFIG_CMD_SATA | |
469 | #define CONFIG_DOS_PARTITION | |
470 | #define CONFIG_CMD_EXT2 | |
471 | #endif | |
472 | ||
5e918a98 KP |
473 | /* |
474 | * Environment | |
475 | */ | |
6d0f6bcf | 476 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 477 | #define CONFIG_ENV_IS_IN_FLASH 1 |
5afe9722 JH |
478 | #define CONFIG_ENV_ADDR \ |
479 | (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
480 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ |
481 | #define CONFIG_ENV_SIZE 0x4000 | |
5e918a98 | 482 | #else |
5afe9722 | 483 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 484 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 485 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) |
0e8d1586 | 486 | #define CONFIG_ENV_SIZE 0x2000 |
5e918a98 KP |
487 | #endif |
488 | ||
489 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 490 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
5e918a98 KP |
491 | |
492 | /* | |
493 | * BOOTP options | |
494 | */ | |
495 | #define CONFIG_BOOTP_BOOTFILESIZE | |
496 | #define CONFIG_BOOTP_BOOTPATH | |
497 | #define CONFIG_BOOTP_GATEWAY | |
498 | #define CONFIG_BOOTP_HOSTNAME | |
499 | ||
500 | ||
501 | /* | |
502 | * Command line configuration. | |
503 | */ | |
504 | #include <config_cmd_default.h> | |
505 | ||
506 | #define CONFIG_CMD_PING | |
507 | #define CONFIG_CMD_I2C | |
508 | #define CONFIG_CMD_MII | |
509 | #define CONFIG_CMD_DATE | |
510 | ||
511 | #if defined(CONFIG_PCI) | |
512 | #define CONFIG_CMD_PCI | |
513 | #endif | |
514 | ||
6d0f6bcf | 515 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 516 | #undef CONFIG_CMD_SAVEENV |
5e918a98 KP |
517 | #undef CONFIG_CMD_LOADS |
518 | #endif | |
519 | ||
520 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
5afe9722 | 521 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
5e918a98 KP |
522 | |
523 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
524 | ||
c9646ed7 AV |
525 | #define CONFIG_MMC 1 |
526 | ||
527 | #ifdef CONFIG_MMC | |
528 | #define CONFIG_FSL_ESDHC | |
a6da8b81 | 529 | #define CONFIG_FSL_ESDHC_PIN_MUX |
c9646ed7 AV |
530 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR |
531 | #define CONFIG_CMD_MMC | |
532 | #define CONFIG_GENERIC_MMC | |
533 | #define CONFIG_CMD_EXT2 | |
534 | #define CONFIG_CMD_FAT | |
535 | #define CONFIG_DOS_PARTITION | |
536 | #endif | |
537 | ||
5e918a98 KP |
538 | /* |
539 | * Miscellaneous configurable options | |
540 | */ | |
5afe9722 JH |
541 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
542 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
543 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
5e918a98 KP |
544 | |
545 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 546 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
5e918a98 | 547 | #else |
6d0f6bcf | 548 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
5e918a98 KP |
549 | #endif |
550 | ||
5afe9722 JH |
551 | /* Print Buffer Size */ |
552 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
553 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
554 | /* Boot Argument Buffer Size */ | |
555 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
556 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
5e918a98 KP |
557 | |
558 | /* | |
559 | * For booting Linux, the board info and command line data | |
9f530d59 | 560 | * have to be in the first 256 MB of memory, since this is |
5e918a98 KP |
561 | * the maximum mapped by the Linux kernel during initialization. |
562 | */ | |
5afe9722 | 563 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
5e918a98 KP |
564 | |
565 | /* | |
566 | * Core HID Setup | |
567 | */ | |
1a2e203b | 568 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
5afe9722 JH |
569 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
570 | | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 571 | #define CONFIG_SYS_HID2 HID2_HBE |
5e918a98 KP |
572 | |
573 | /* | |
574 | * MMU Setup | |
575 | */ | |
576 | ||
31d82672 BB |
577 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
578 | ||
5e918a98 | 579 | /* DDR: cache cacheable */ |
6d0f6bcf JCPV |
580 | #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE |
581 | #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) | |
5e918a98 | 582 | |
5afe9722 | 583 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ |
72cd4087 | 584 | | BATL_PP_RW \ |
5afe9722 JH |
585 | | BATL_MEMCOHERENCE) |
586 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ | |
587 | | BATU_BL_256M \ | |
588 | | BATU_VS \ | |
589 | | BATU_VP) | |
6d0f6bcf JCPV |
590 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
591 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
5e918a98 | 592 | |
5afe9722 | 593 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ |
72cd4087 | 594 | | BATL_PP_RW \ |
5afe9722 JH |
595 | | BATL_MEMCOHERENCE) |
596 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ | |
597 | | BATU_BL_256M \ | |
598 | | BATU_VS \ | |
599 | | BATU_VP) | |
6d0f6bcf JCPV |
600 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
601 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
5e918a98 KP |
602 | |
603 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
5afe9722 | 604 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ |
72cd4087 | 605 | | BATL_PP_RW \ |
5afe9722 JH |
606 | | BATL_CACHEINHIBIT \ |
607 | | BATL_GUARDEDSTORAGE) | |
608 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ | |
609 | | BATU_BL_8M \ | |
610 | | BATU_VS \ | |
611 | | BATU_VP) | |
6d0f6bcf JCPV |
612 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
613 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
5e918a98 KP |
614 | |
615 | /* L2 Switch: cache-inhibit and guarded */ | |
5afe9722 | 616 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ |
72cd4087 | 617 | | BATL_PP_RW \ |
5afe9722 JH |
618 | | BATL_CACHEINHIBIT \ |
619 | | BATL_GUARDEDSTORAGE) | |
620 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ | |
621 | | BATU_BL_128K \ | |
622 | | BATU_VS \ | |
623 | | BATU_VP) | |
6d0f6bcf JCPV |
624 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
625 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
5e918a98 KP |
626 | |
627 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
5afe9722 | 628 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 629 | | BATL_PP_RW \ |
5afe9722 JH |
630 | | BATL_MEMCOHERENCE) |
631 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ | |
632 | | BATU_BL_32M \ | |
633 | | BATU_VS \ | |
634 | | BATU_VP) | |
635 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 636 | | BATL_PP_RW \ |
5afe9722 JH |
637 | | BATL_CACHEINHIBIT \ |
638 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 639 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
5e918a98 KP |
640 | |
641 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 642 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
5afe9722 JH |
643 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ |
644 | | BATU_BL_128K \ | |
645 | | BATU_VS \ | |
646 | | BATU_VP) | |
6d0f6bcf JCPV |
647 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
648 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
5e918a98 KP |
649 | |
650 | #ifdef CONFIG_PCI | |
651 | /* PCI MEM space: cacheable */ | |
5afe9722 | 652 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ |
72cd4087 | 653 | | BATL_PP_RW \ |
5afe9722 JH |
654 | | BATL_MEMCOHERENCE) |
655 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ | |
656 | | BATU_BL_256M \ | |
657 | | BATU_VS \ | |
658 | | BATU_VP) | |
6d0f6bcf JCPV |
659 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
660 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
5e918a98 | 661 | /* PCI MMIO space: cache-inhibit and guarded */ |
5afe9722 | 662 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ |
72cd4087 | 663 | | BATL_PP_RW \ |
5afe9722 JH |
664 | | BATL_CACHEINHIBIT \ |
665 | | BATL_GUARDEDSTORAGE) | |
666 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ | |
667 | | BATU_BL_256M \ | |
668 | | BATU_VS \ | |
669 | | BATU_VP) | |
6d0f6bcf JCPV |
670 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
671 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
5e918a98 | 672 | #else |
6d0f6bcf JCPV |
673 | #define CONFIG_SYS_IBAT6L (0) |
674 | #define CONFIG_SYS_IBAT6U (0) | |
675 | #define CONFIG_SYS_IBAT7L (0) | |
676 | #define CONFIG_SYS_IBAT7U (0) | |
677 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
678 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
679 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
680 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
5e918a98 KP |
681 | #endif |
682 | ||
5e918a98 KP |
683 | #if defined(CONFIG_CMD_KGDB) |
684 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
685 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
686 | #endif | |
687 | ||
688 | /* | |
689 | * Environment Configuration | |
690 | */ | |
691 | #define CONFIG_ENV_OVERWRITE | |
692 | ||
18e69a35 AV |
693 | #define CONFIG_HAS_FSL_DR_USB |
694 | ||
5afe9722 | 695 | #define CONFIG_NETDEV "eth1" |
5e918a98 KP |
696 | |
697 | #define CONFIG_HOSTNAME mpc837x_rdb | |
8b3637c6 | 698 | #define CONFIG_ROOTPATH "/nfsroot" |
5afe9722 | 699 | #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" |
b3f44c21 | 700 | #define CONFIG_BOOTFILE "uImage" |
5afe9722 JH |
701 | /* U-Boot image on TFTP server */ |
702 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
703 | #define CONFIG_FDTFILE "mpc8379_rdb.dtb" | |
5e918a98 | 704 | |
5afe9722 JH |
705 | /* default location for tftp and bootm */ |
706 | #define CONFIG_LOADADDR 800000 | |
7fd0bea2 | 707 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
5e918a98 KP |
708 | #define CONFIG_BAUDRATE 115200 |
709 | ||
5e918a98 | 710 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5afe9722 JH |
711 | "netdev=" CONFIG_NETDEV "\0" \ |
712 | "uboot=" CONFIG_UBOOTPATH "\0" \ | |
5e918a98 | 713 | "tftpflash=tftp $loadaddr $uboot;" \ |
5368c55d MV |
714 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
715 | " +$filesize; " \ | |
716 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
717 | " +$filesize; " \ | |
718 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
719 | " $filesize; " \ | |
720 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
721 | " +$filesize; " \ | |
722 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
723 | " $filesize\0" \ | |
79f516bc | 724 | "fdtaddr=780000\0" \ |
5afe9722 | 725 | "fdtfile=" CONFIG_FDTFILE "\0" \ |
5e918a98 | 726 | "ramdiskaddr=1000000\0" \ |
5afe9722 | 727 | "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ |
5e918a98 KP |
728 | "console=ttyS0\0" \ |
729 | "setbootargs=setenv bootargs " \ | |
730 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
731 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ | |
5afe9722 JH |
732 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ |
733 | "$netdev:off " \ | |
5e918a98 KP |
734 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" |
735 | ||
736 | #define CONFIG_NFSBOOTCOMMAND \ | |
737 | "setenv rootdev /dev/nfs;" \ | |
738 | "run setbootargs;" \ | |
739 | "run setipargs;" \ | |
740 | "tftp $loadaddr $bootfile;" \ | |
741 | "tftp $fdtaddr $fdtfile;" \ | |
742 | "bootm $loadaddr - $fdtaddr" | |
743 | ||
744 | #define CONFIG_RAMBOOTCOMMAND \ | |
745 | "setenv rootdev /dev/ram;" \ | |
746 | "run setbootargs;" \ | |
747 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
748 | "tftp $loadaddr $bootfile;" \ | |
749 | "tftp $fdtaddr $fdtfile;" \ | |
750 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
751 | ||
5e918a98 | 752 | #endif /* __CONFIG_H */ |