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5e918a98 KP |
1 | /* |
2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
3 | * Kevin Lam <kevin.lam@freescale.com> | |
4 | * Joe D'Abbraccio <joe.d'abbraccio@freescale.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
5e918a98 KP |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | /* | |
13 | * High Level Configuration Options | |
14 | */ | |
15 | #define CONFIG_E300 1 /* E300 family */ | |
2c7920af | 16 | #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ |
5e918a98 KP |
17 | #define CONFIG_MPC837XERDB 1 |
18 | ||
2ae18241 WD |
19 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
20 | ||
89c7784e | 21 | #define CONFIG_MISC_INIT_R |
c9646ed7 | 22 | #define CONFIG_HWCONFIG |
89c7784e TT |
23 | |
24 | /* | |
25 | * On-board devices | |
26 | */ | |
27 | #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ | |
28 | #define CONFIG_VSC7385_ENET | |
29 | ||
5e918a98 KP |
30 | /* |
31 | * System Clock Setup | |
32 | */ | |
33 | #ifdef CONFIG_PCISLAVE | |
34 | #define CONFIG_83XX_PCICLK 66666667 /* in HZ */ | |
35 | #else | |
36 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ | |
be9b56df | 37 | #define CONFIG_PCIE |
5e918a98 KP |
38 | #endif |
39 | ||
40 | #ifndef CONFIG_SYS_CLK_FREQ | |
41 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
42 | #endif | |
43 | ||
44 | /* | |
45 | * Hardware Reset Configuration Word | |
46 | */ | |
6d0f6bcf | 47 | #define CONFIG_SYS_HRCW_LOW (\ |
5e918a98 KP |
48 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
49 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
50 | HRCWL_SVCOD_DIV_2 |\ | |
51 | HRCWL_CSB_TO_CLKIN_5X1 |\ | |
52 | HRCWL_CORE_TO_CSB_2X1) | |
53 | ||
54 | #ifdef CONFIG_PCISLAVE | |
6d0f6bcf | 55 | #define CONFIG_SYS_HRCW_HIGH (\ |
5e918a98 KP |
56 | HRCWH_PCI_AGENT |\ |
57 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
58 | HRCWH_CORE_ENABLE |\ | |
59 | HRCWH_FROM_0XFFF00100 |\ | |
60 | HRCWH_BOOTSEQ_DISABLE |\ | |
61 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
62 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
63 | HRCWH_RL_EXT_LEGACY |\ | |
64 | HRCWH_TSEC1M_IN_RGMII |\ | |
65 | HRCWH_TSEC2M_IN_RGMII |\ | |
66 | HRCWH_BIG_ENDIAN |\ | |
67 | HRCWH_LDP_CLEAR) | |
68 | #else | |
6d0f6bcf | 69 | #define CONFIG_SYS_HRCW_HIGH (\ |
5e918a98 KP |
70 | HRCWH_PCI_HOST |\ |
71 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
72 | HRCWH_CORE_ENABLE |\ | |
73 | HRCWH_FROM_0X00000100 |\ | |
74 | HRCWH_BOOTSEQ_DISABLE |\ | |
75 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
76 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
77 | HRCWH_RL_EXT_LEGACY |\ | |
78 | HRCWH_TSEC1M_IN_RGMII |\ | |
79 | HRCWH_TSEC2M_IN_RGMII |\ | |
80 | HRCWH_BIG_ENDIAN |\ | |
81 | HRCWH_LDP_CLEAR) | |
82 | #endif | |
83 | ||
6d0f6bcf | 84 | /* System performance - define the value i.e. CONFIG_SYS_XXX |
5e918a98 KP |
85 | */ |
86 | ||
87 | /* Arbiter Configuration Register */ | |
6d0f6bcf | 88 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
5afe9722 | 89 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
5e918a98 KP |
90 | |
91 | /* System Priority Control Regsiter */ | |
5afe9722 | 92 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ |
5e918a98 KP |
93 | |
94 | /* System Clock Configuration Register */ | |
6d0f6bcf JCPV |
95 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ |
96 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ | |
5afe9722 | 97 | #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ |
5e918a98 KP |
98 | |
99 | /* | |
100 | * System IO Config | |
101 | */ | |
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_SICRH 0x08200000 |
103 | #define CONFIG_SYS_SICRL 0x00000000 | |
5e918a98 KP |
104 | |
105 | /* | |
106 | * Output Buffer Impedance | |
107 | */ | |
6d0f6bcf | 108 | #define CONFIG_SYS_OBIR 0x30100000 |
5e918a98 KP |
109 | |
110 | /* | |
111 | * IMMR new address | |
112 | */ | |
6d0f6bcf | 113 | #define CONFIG_SYS_IMMR 0xE0000000 |
5e918a98 | 114 | |
89c7784e TT |
115 | /* |
116 | * Device configurations | |
117 | */ | |
118 | ||
119 | /* Vitesse 7385 */ | |
120 | ||
121 | #ifdef CONFIG_VSC7385_ENET | |
122 | ||
123 | #define CONFIG_TSEC2 | |
124 | ||
125 | /* The flash address and size of the VSC7385 firmware image */ | |
126 | #define CONFIG_VSC7385_IMAGE 0xFE7FE000 | |
127 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
128 | ||
129 | #endif | |
130 | ||
5e918a98 KP |
131 | /* |
132 | * DDR Setup | |
133 | */ | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
135 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
136 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
137 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 | |
138 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
5e918a98 | 139 | |
6d0f6bcf | 140 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) |
5e918a98 KP |
141 | |
142 | #undef CONFIG_DDR_ECC /* support DDR ECC function */ | |
143 | #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ | |
144 | ||
145 | #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ | |
146 | ||
147 | /* | |
148 | * Manually set up DDR parameters | |
149 | */ | |
6d0f6bcf | 150 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
2fef4020 JH |
151 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f |
152 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | |
153 | | CSCONFIG_ODT_WR_ONLY_CURRENT \ | |
154 | | CSCONFIG_ROW_BIT_13 \ | |
155 | | CSCONFIG_COL_BIT_10) | |
5e918a98 | 156 | |
6d0f6bcf JCPV |
157 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
158 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | |
5e918a98 KP |
159 | | (0 << TIMING_CFG0_WRT_SHIFT) \ |
160 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
161 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
162 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
163 | | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
164 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
165 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
5e918a98 | 166 | /* 0x00260802 */ /* DDR400 */ |
6d0f6bcf | 167 | #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ |
5e918a98 KP |
168 | | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ |
169 | | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
170 | | (7 << TIMING_CFG1_CASLAT_SHIFT) \ | |
171 | | (13 << TIMING_CFG1_REFREC_SHIFT) \ | |
172 | | (3 << TIMING_CFG1_WRREC_SHIFT) \ | |
173 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
174 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
5e918a98 | 175 | /* 0x3937d322 */ |
2fef4020 JH |
176 | #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
177 | | (5 << TIMING_CFG2_CPO_SHIFT) \ | |
178 | | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
179 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
180 | | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
181 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
182 | | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
183 | /* 0x02984cc8 */ | |
5e918a98 | 184 | |
8eceeb7f KP |
185 | #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
186 | | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
5e918a98 KP |
187 | /* 0x06090100 */ |
188 | ||
189 | #if defined(CONFIG_DDR_2T_TIMING) | |
5afe9722 | 190 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
2fef4020 JH |
191 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
192 | | SDRAM_CFG_32_BE \ | |
193 | | SDRAM_CFG_2T_EN) | |
194 | /* 0x43088000 */ | |
5e918a98 | 195 | #else |
5afe9722 | 196 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
2fef4020 | 197 | | SDRAM_CFG_SDRAM_TYPE_DDR2) |
5afe9722 | 198 | /* 0x43000000 */ |
5e918a98 | 199 | #endif |
6d0f6bcf | 200 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ |
8eceeb7f | 201 | #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ |
5afe9722 JH |
202 | | (0x0442 << SDRAM_MODE_SD_SHIFT)) |
203 | /* 0x04400442 */ /* DDR400 */ | |
6d0f6bcf | 204 | #define CONFIG_SYS_DDR_MODE2 0x00000000 |
5e918a98 KP |
205 | |
206 | /* | |
207 | * Memory test | |
208 | */ | |
6d0f6bcf JCPV |
209 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
210 | #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ | |
211 | #define CONFIG_SYS_MEMTEST_END 0x0ef70010 | |
5e918a98 KP |
212 | |
213 | /* | |
214 | * The reserved memory | |
215 | */ | |
14d0a02a | 216 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
5e918a98 | 217 | |
6d0f6bcf JCPV |
218 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
219 | #define CONFIG_SYS_RAMBOOT | |
5e918a98 | 220 | #else |
6d0f6bcf | 221 | #undef CONFIG_SYS_RAMBOOT |
5e918a98 KP |
222 | #endif |
223 | ||
16c8c170 | 224 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
5afe9722 | 225 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
5e918a98 KP |
226 | |
227 | /* | |
228 | * Initial RAM Base Address Setup | |
229 | */ | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
231 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 232 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
5afe9722 JH |
233 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
234 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
5e918a98 KP |
235 | |
236 | /* | |
237 | * Local Bus Configuration & Clock Setup | |
238 | */ | |
c7190f02 KP |
239 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
240 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 | |
6d0f6bcf | 241 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
0914f483 | 242 | #define CONFIG_FSL_ELBC 1 |
5e918a98 KP |
243 | |
244 | /* | |
245 | * FLASH on the Local Bus | |
246 | */ | |
6d0f6bcf | 247 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 248 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
250 | #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ | |
5e918a98 | 251 | |
5afe9722 JH |
252 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
253 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ | |
254 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ | |
5e918a98 | 255 | |
5afe9722 JH |
256 | /* Window base at flash base */ |
257 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
6d0f6bcf | 258 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ |
5e918a98 | 259 | |
5afe9722 | 260 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
261 | | BR_PS_16 /* 16 bit port */ \ |
262 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
263 | | BR_V) /* valid */ | |
264 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
5e918a98 KP |
265 | | OR_GPCM_XACS \ |
266 | | OR_GPCM_SCY_9 \ | |
7d6a0982 | 267 | | OR_GPCM_EHTR_SET \ |
5e918a98 | 268 | | OR_GPCM_EAD) |
7d6a0982 | 269 | /* 0xFF800191 */ |
5e918a98 | 270 | |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
272 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
5e918a98 | 273 | |
6d0f6bcf JCPV |
274 | #undef CONFIG_SYS_FLASH_CHECKSUM |
275 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
276 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
5e918a98 | 277 | |
46a3aeea AV |
278 | /* |
279 | * NAND Flash on the Local Bus | |
280 | */ | |
7d6a0982 | 281 | #define CONFIG_SYS_NAND_BASE 0xE0600000 |
5afe9722 | 282 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ |
7d6a0982 JH |
283 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
284 | | BR_PS_8 /* 8 bit port */ \ | |
285 | | BR_MS_FCM /* MSEL = FCM */ \ | |
5afe9722 | 286 | | BR_V) /* valid */ |
7d6a0982 | 287 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ |
5afe9722 JH |
288 | | OR_FCM_CSCT \ |
289 | | OR_FCM_CST \ | |
290 | | OR_FCM_CHT \ | |
291 | | OR_FCM_SCY_1 \ | |
292 | | OR_FCM_TRLX \ | |
293 | | OR_FCM_EHTR) | |
6d0f6bcf | 294 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 | 295 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
46a3aeea | 296 | |
89c7784e TT |
297 | /* Vitesse 7385 */ |
298 | ||
6d0f6bcf | 299 | #define CONFIG_SYS_VSC7385_BASE 0xF0000000 |
5e918a98 | 300 | |
89c7784e TT |
301 | #ifdef CONFIG_VSC7385_ENET |
302 | ||
7d6a0982 JH |
303 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ |
304 | | BR_PS_8 \ | |
305 | | BR_MS_GPCM \ | |
306 | | BR_V) | |
307 | /* 0xF0000801 */ | |
308 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ | |
309 | | OR_GPCM_CSNT \ | |
310 | | OR_GPCM_XACS \ | |
311 | | OR_GPCM_SCY_15 \ | |
312 | | OR_GPCM_SETA \ | |
313 | | OR_GPCM_TRLX_SET \ | |
314 | | OR_GPCM_EHTR_SET \ | |
315 | | OR_GPCM_EAD) | |
316 | /* 0xfffe09ff */ | |
317 | ||
5afe9722 JH |
318 | /* Access Base */ |
319 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE | |
7d6a0982 | 320 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) |
5e918a98 | 321 | |
89c7784e TT |
322 | #endif |
323 | ||
5e918a98 KP |
324 | /* |
325 | * Serial Port | |
326 | */ | |
327 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
328 | #define CONFIG_SYS_NS16550_SERIAL |
329 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
330 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
5e918a98 | 331 | |
6d0f6bcf | 332 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
5afe9722 | 333 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
5e918a98 | 334 | |
6d0f6bcf JCPV |
335 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
336 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
5e918a98 | 337 | |
2bd7460e AV |
338 | /* SERDES */ |
339 | #define CONFIG_FSL_SERDES | |
340 | #define CONFIG_FSL_SERDES1 0xe3000 | |
341 | #define CONFIG_FSL_SERDES2 0xe3100 | |
342 | ||
5e918a98 | 343 | /* I2C */ |
00f792e0 HS |
344 | #define CONFIG_SYS_I2C |
345 | #define CONFIG_SYS_I2C_FSL | |
346 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
347 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
348 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
349 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
5e918a98 KP |
350 | |
351 | /* | |
352 | * Config on-board RTC | |
353 | */ | |
354 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
6d0f6bcf | 355 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
5e918a98 KP |
356 | |
357 | /* | |
358 | * General PCI | |
359 | * Addresses are mapped 1-1. | |
360 | */ | |
5afe9722 JH |
361 | #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 |
362 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
363 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
6d0f6bcf JCPV |
364 | #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 |
365 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
366 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
367 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
368 | #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 | |
369 | #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ | |
370 | ||
371 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE | |
372 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
373 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
5e918a98 | 374 | |
7e915580 AV |
375 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
376 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 | |
377 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 | |
378 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 | |
379 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 | |
380 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
381 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
382 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 | |
383 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
384 | ||
385 | #define CONFIG_SYS_PCIE2_BASE 0xC0000000 | |
386 | #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 | |
387 | #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 | |
388 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 | |
389 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 | |
390 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 | |
391 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
392 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 | |
393 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 | |
394 | ||
5e918a98 | 395 | #ifdef CONFIG_PCI |
842033e6 | 396 | #define CONFIG_PCI_INDIRECT_BRIDGE |
5e918a98 | 397 | |
5e918a98 | 398 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 399 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
5e918a98 KP |
400 | #endif /* CONFIG_PCI */ |
401 | ||
5e918a98 KP |
402 | /* |
403 | * TSEC | |
404 | */ | |
89c7784e | 405 | #ifdef CONFIG_TSEC_ENET |
5e918a98 | 406 | |
89c7784e TT |
407 | #define CONFIG_GMII /* MII PHY management */ |
408 | ||
409 | #define CONFIG_TSEC1 | |
410 | ||
411 | #ifdef CONFIG_TSEC1 | |
412 | #define CONFIG_HAS_ETH0 | |
5e918a98 | 413 | #define CONFIG_TSEC1_NAME "TSEC0" |
6d0f6bcf | 414 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
5e918a98 | 415 | #define TSEC1_PHY_ADDR 2 |
5e918a98 | 416 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
5e918a98 | 417 | #define TSEC1_PHYIDX 0 |
89c7784e | 418 | #endif |
5e918a98 | 419 | |
89c7784e TT |
420 | #ifdef CONFIG_TSEC2 |
421 | #define CONFIG_HAS_ETH1 | |
422 | #define CONFIG_TSEC2_NAME "TSEC1" | |
6d0f6bcf | 423 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
89c7784e TT |
424 | #define TSEC2_PHY_ADDR 0x1c |
425 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
426 | #define TSEC2_PHYIDX 0 | |
427 | #endif | |
5e918a98 KP |
428 | |
429 | /* Options are: TSEC[0-1] */ | |
430 | #define CONFIG_ETHPRIME "TSEC0" | |
431 | ||
89c7784e TT |
432 | #endif |
433 | ||
730e7929 KP |
434 | /* |
435 | * SATA | |
436 | */ | |
437 | #define CONFIG_LIBATA | |
438 | #define CONFIG_FSL_SATA | |
439 | ||
6d0f6bcf | 440 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
730e7929 | 441 | #define CONFIG_SATA1 |
6d0f6bcf | 442 | #define CONFIG_SYS_SATA1_OFFSET 0x18000 |
5afe9722 JH |
443 | #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) |
444 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
730e7929 | 445 | #define CONFIG_SATA2 |
6d0f6bcf | 446 | #define CONFIG_SYS_SATA2_OFFSET 0x19000 |
5afe9722 JH |
447 | #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) |
448 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
730e7929 KP |
449 | |
450 | #ifdef CONFIG_FSL_SATA | |
451 | #define CONFIG_LBA48 | |
730e7929 KP |
452 | #endif |
453 | ||
5e918a98 KP |
454 | /* |
455 | * Environment | |
456 | */ | |
6d0f6bcf | 457 | #ifndef CONFIG_SYS_RAMBOOT |
5afe9722 JH |
458 | #define CONFIG_ENV_ADDR \ |
459 | (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
460 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ |
461 | #define CONFIG_ENV_SIZE 0x4000 | |
5e918a98 | 462 | #else |
6d0f6bcf | 463 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) |
0e8d1586 | 464 | #define CONFIG_ENV_SIZE 0x2000 |
5e918a98 KP |
465 | #endif |
466 | ||
467 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 468 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
5e918a98 KP |
469 | |
470 | /* | |
471 | * BOOTP options | |
472 | */ | |
473 | #define CONFIG_BOOTP_BOOTFILESIZE | |
474 | #define CONFIG_BOOTP_BOOTPATH | |
475 | #define CONFIG_BOOTP_GATEWAY | |
476 | #define CONFIG_BOOTP_HOSTNAME | |
477 | ||
5e918a98 KP |
478 | /* |
479 | * Command line configuration. | |
480 | */ | |
5e918a98 | 481 | |
5e918a98 | 482 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
5afe9722 | 483 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
5e918a98 KP |
484 | |
485 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
486 | ||
c9646ed7 AV |
487 | #ifdef CONFIG_MMC |
488 | #define CONFIG_FSL_ESDHC | |
a6da8b81 | 489 | #define CONFIG_FSL_ESDHC_PIN_MUX |
c9646ed7 | 490 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR |
c9646ed7 AV |
491 | #endif |
492 | ||
5e918a98 KP |
493 | /* |
494 | * Miscellaneous configurable options | |
495 | */ | |
5afe9722 JH |
496 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
497 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
5e918a98 | 498 | |
5afe9722 JH |
499 | /* Boot Argument Buffer Size */ |
500 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
5e918a98 KP |
501 | |
502 | /* | |
503 | * For booting Linux, the board info and command line data | |
9f530d59 | 504 | * have to be in the first 256 MB of memory, since this is |
5e918a98 KP |
505 | * the maximum mapped by the Linux kernel during initialization. |
506 | */ | |
5afe9722 | 507 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
63865278 | 508 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
5e918a98 KP |
509 | |
510 | /* | |
511 | * Core HID Setup | |
512 | */ | |
1a2e203b | 513 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
5afe9722 JH |
514 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
515 | | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 516 | #define CONFIG_SYS_HID2 HID2_HBE |
5e918a98 KP |
517 | |
518 | /* | |
519 | * MMU Setup | |
520 | */ | |
521 | ||
31d82672 BB |
522 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
523 | ||
5e918a98 | 524 | /* DDR: cache cacheable */ |
6d0f6bcf JCPV |
525 | #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE |
526 | #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) | |
5e918a98 | 527 | |
5afe9722 | 528 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ |
72cd4087 | 529 | | BATL_PP_RW \ |
5afe9722 JH |
530 | | BATL_MEMCOHERENCE) |
531 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ | |
532 | | BATU_BL_256M \ | |
533 | | BATU_VS \ | |
534 | | BATU_VP) | |
6d0f6bcf JCPV |
535 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
536 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
5e918a98 | 537 | |
5afe9722 | 538 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ |
72cd4087 | 539 | | BATL_PP_RW \ |
5afe9722 JH |
540 | | BATL_MEMCOHERENCE) |
541 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ | |
542 | | BATU_BL_256M \ | |
543 | | BATU_VS \ | |
544 | | BATU_VP) | |
6d0f6bcf JCPV |
545 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
546 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
5e918a98 KP |
547 | |
548 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
5afe9722 | 549 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ |
72cd4087 | 550 | | BATL_PP_RW \ |
5afe9722 JH |
551 | | BATL_CACHEINHIBIT \ |
552 | | BATL_GUARDEDSTORAGE) | |
553 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ | |
554 | | BATU_BL_8M \ | |
555 | | BATU_VS \ | |
556 | | BATU_VP) | |
6d0f6bcf JCPV |
557 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
558 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
5e918a98 KP |
559 | |
560 | /* L2 Switch: cache-inhibit and guarded */ | |
5afe9722 | 561 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ |
72cd4087 | 562 | | BATL_PP_RW \ |
5afe9722 JH |
563 | | BATL_CACHEINHIBIT \ |
564 | | BATL_GUARDEDSTORAGE) | |
565 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ | |
566 | | BATU_BL_128K \ | |
567 | | BATU_VS \ | |
568 | | BATU_VP) | |
6d0f6bcf JCPV |
569 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
570 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
5e918a98 KP |
571 | |
572 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
5afe9722 | 573 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 574 | | BATL_PP_RW \ |
5afe9722 JH |
575 | | BATL_MEMCOHERENCE) |
576 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ | |
577 | | BATU_BL_32M \ | |
578 | | BATU_VS \ | |
579 | | BATU_VP) | |
580 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 581 | | BATL_PP_RW \ |
5afe9722 JH |
582 | | BATL_CACHEINHIBIT \ |
583 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 584 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
5e918a98 KP |
585 | |
586 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 587 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
5afe9722 JH |
588 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ |
589 | | BATU_BL_128K \ | |
590 | | BATU_VS \ | |
591 | | BATU_VP) | |
6d0f6bcf JCPV |
592 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
593 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
5e918a98 KP |
594 | |
595 | #ifdef CONFIG_PCI | |
596 | /* PCI MEM space: cacheable */ | |
5afe9722 | 597 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ |
72cd4087 | 598 | | BATL_PP_RW \ |
5afe9722 JH |
599 | | BATL_MEMCOHERENCE) |
600 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ | |
601 | | BATU_BL_256M \ | |
602 | | BATU_VS \ | |
603 | | BATU_VP) | |
6d0f6bcf JCPV |
604 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
605 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
5e918a98 | 606 | /* PCI MMIO space: cache-inhibit and guarded */ |
5afe9722 | 607 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ |
72cd4087 | 608 | | BATL_PP_RW \ |
5afe9722 JH |
609 | | BATL_CACHEINHIBIT \ |
610 | | BATL_GUARDEDSTORAGE) | |
611 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ | |
612 | | BATU_BL_256M \ | |
613 | | BATU_VS \ | |
614 | | BATU_VP) | |
6d0f6bcf JCPV |
615 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
616 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
5e918a98 | 617 | #else |
6d0f6bcf JCPV |
618 | #define CONFIG_SYS_IBAT6L (0) |
619 | #define CONFIG_SYS_IBAT6U (0) | |
620 | #define CONFIG_SYS_IBAT7L (0) | |
621 | #define CONFIG_SYS_IBAT7U (0) | |
622 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
623 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
624 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
625 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
5e918a98 KP |
626 | #endif |
627 | ||
5e918a98 KP |
628 | #if defined(CONFIG_CMD_KGDB) |
629 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
5e918a98 KP |
630 | #endif |
631 | ||
632 | /* | |
633 | * Environment Configuration | |
634 | */ | |
635 | #define CONFIG_ENV_OVERWRITE | |
636 | ||
18e69a35 | 637 | #define CONFIG_HAS_FSL_DR_USB |
6c3c5750 NB |
638 | #define CONFIG_USB_EHCI_FSL |
639 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
18e69a35 | 640 | |
5afe9722 | 641 | #define CONFIG_NETDEV "eth1" |
5e918a98 KP |
642 | |
643 | #define CONFIG_HOSTNAME mpc837x_rdb | |
8b3637c6 | 644 | #define CONFIG_ROOTPATH "/nfsroot" |
5afe9722 | 645 | #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" |
b3f44c21 | 646 | #define CONFIG_BOOTFILE "uImage" |
5afe9722 JH |
647 | /* U-Boot image on TFTP server */ |
648 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
649 | #define CONFIG_FDTFILE "mpc8379_rdb.dtb" | |
5e918a98 | 650 | |
5afe9722 JH |
651 | /* default location for tftp and bootm */ |
652 | #define CONFIG_LOADADDR 800000 | |
5e918a98 | 653 | |
5e918a98 | 654 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5afe9722 JH |
655 | "netdev=" CONFIG_NETDEV "\0" \ |
656 | "uboot=" CONFIG_UBOOTPATH "\0" \ | |
5e918a98 | 657 | "tftpflash=tftp $loadaddr $uboot;" \ |
5368c55d MV |
658 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
659 | " +$filesize; " \ | |
660 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
661 | " +$filesize; " \ | |
662 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
663 | " $filesize; " \ | |
664 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
665 | " +$filesize; " \ | |
666 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
667 | " $filesize\0" \ | |
79f516bc | 668 | "fdtaddr=780000\0" \ |
5afe9722 | 669 | "fdtfile=" CONFIG_FDTFILE "\0" \ |
5e918a98 | 670 | "ramdiskaddr=1000000\0" \ |
5afe9722 | 671 | "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ |
5e918a98 KP |
672 | "console=ttyS0\0" \ |
673 | "setbootargs=setenv bootargs " \ | |
674 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
675 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ | |
5afe9722 JH |
676 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ |
677 | "$netdev:off " \ | |
5e918a98 KP |
678 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" |
679 | ||
680 | #define CONFIG_NFSBOOTCOMMAND \ | |
681 | "setenv rootdev /dev/nfs;" \ | |
682 | "run setbootargs;" \ | |
683 | "run setipargs;" \ | |
684 | "tftp $loadaddr $bootfile;" \ | |
685 | "tftp $fdtaddr $fdtfile;" \ | |
686 | "bootm $loadaddr - $fdtaddr" | |
687 | ||
688 | #define CONFIG_RAMBOOTCOMMAND \ | |
689 | "setenv rootdev /dev/ram;" \ | |
690 | "run setbootargs;" \ | |
691 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
692 | "tftp $loadaddr $bootfile;" \ | |
693 | "tftp $fdtaddr $fdtfile;" \ | |
694 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
695 | ||
5e918a98 | 696 | #endif /* __CONFIG_H */ |