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9490a7f1 | 1 | /* |
3d7506fa | 2 | * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. |
9490a7f1 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
9490a7f1 KG |
5 | */ |
6 | ||
7 | /* | |
8 | * mpc8536ds board configuration file | |
9 | * | |
10 | */ | |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
c7e1a43d KG |
14 | #include "../board/freescale/common/ics307_clk.h" |
15 | ||
d24f2d32 | 16 | #ifdef CONFIG_SDCARD |
e40ac487 | 17 | #define CONFIG_RAMBOOT_SDCARD 1 |
e2c9bc5e | 18 | #define CONFIG_SYS_TEXT_BASE 0xf8f40000 |
7a577fda | 19 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc |
e40ac487 MH |
20 | #endif |
21 | ||
d24f2d32 | 22 | #ifdef CONFIG_SPIFLASH |
e40ac487 | 23 | #define CONFIG_RAMBOOT_SPIFLASH 1 |
e2c9bc5e | 24 | #define CONFIG_SYS_TEXT_BASE 0xf8f40000 |
7a577fda | 25 | #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc |
2ae18241 WD |
26 | #endif |
27 | ||
28 | #ifndef CONFIG_SYS_TEXT_BASE | |
c6e8f49a | 29 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
e40ac487 MH |
30 | #endif |
31 | ||
7a577fda KG |
32 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
33 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
34 | #endif | |
35 | ||
96196a1f HW |
36 | #ifndef CONFIG_SYS_MONITOR_BASE |
37 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
38 | #endif | |
39 | ||
9490a7f1 | 40 | #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ |
b38eaec5 RD |
41 | #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ |
42 | #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ | |
43 | #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ | |
9490a7f1 | 44 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
842033e6 | 45 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
9490a7f1 | 46 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
0151cbac | 47 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
9490a7f1 | 48 | |
9490a7f1 KG |
49 | |
50 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
51 | #define CONFIG_ENV_OVERWRITE | |
52 | ||
c7e1a43d KG |
53 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
54 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
9490a7f1 | 55 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
9490a7f1 KG |
56 | |
57 | /* | |
58 | * These can be toggled for performance analysis, otherwise use default. | |
59 | */ | |
60 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
61 | #define CONFIG_BTB /* toggle branch predition */ | |
9490a7f1 KG |
62 | |
63 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
64 | ||
337f9fde KG |
65 | #ifdef CONFIG_PHYS_64BIT |
66 | #define CONFIG_ADDR_MAP 1 | |
67 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
68 | #endif | |
69 | ||
07355700 MH |
70 | #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ |
71 | #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ | |
9490a7f1 KG |
72 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
73 | ||
9a1a0aed MH |
74 | /* |
75 | * Config the L2 Cache as L2 SRAM | |
76 | */ | |
77 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
78 | #ifdef CONFIG_PHYS_64BIT | |
79 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull | |
80 | #else | |
81 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
82 | #endif | |
83 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
84 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
85 | ||
e46fedfe TT |
86 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
87 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
9490a7f1 | 88 | |
8d22ddca | 89 | #if defined(CONFIG_NAND_SPL) |
e46fedfe | 90 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
9a1a0aed MH |
91 | #endif |
92 | ||
9490a7f1 | 93 | /* DDR Setup */ |
337f9fde | 94 | #define CONFIG_VERY_BIG_RAM |
9490a7f1 KG |
95 | #undef CONFIG_FSL_DDR_INTERACTIVE |
96 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
97 | #define CONFIG_DDR_SPD | |
9490a7f1 | 98 | |
9b0ad1b1 | 99 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
9490a7f1 KG |
100 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
101 | ||
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
103 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
9490a7f1 | 104 | |
9490a7f1 KG |
105 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
106 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
107 | ||
108 | /* I2C addresses of SPD EEPROMs */ | |
109 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
6d0f6bcf | 110 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
9490a7f1 KG |
111 | |
112 | /* These are used when DDR doesn't use SPD. */ | |
07355700 | 113 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
6d0f6bcf | 114 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F |
07355700 | 115 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ |
6d0f6bcf JCPV |
116 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
117 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
118 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 | |
119 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
120 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
121 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
122 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 | |
123 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
124 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
125 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
126 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
07355700 | 127 | #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 |
129 | ||
130 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
131 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
132 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
9490a7f1 | 133 | |
9490a7f1 KG |
134 | /* Make sure required options are set */ |
135 | #ifndef CONFIG_SPD_EEPROM | |
136 | #error ("CONFIG_SPD_EEPROM is required") | |
137 | #endif | |
138 | ||
139 | #undef CONFIG_CLOCKS_IN_MHZ | |
140 | ||
9490a7f1 KG |
141 | /* |
142 | * Memory map -- xxx -this is wrong, needs updating | |
143 | * | |
144 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
145 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
146 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
147 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
148 | * | |
149 | * Localbus cacheable (TBD) | |
150 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
151 | * | |
152 | * Localbus non-cacheable | |
c57fc289 | 153 | * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable |
9490a7f1 | 154 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable |
c57fc289 | 155 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
9490a7f1 KG |
156 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
157 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
158 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
159 | */ | |
160 | ||
161 | /* | |
162 | * Local Bus Definitions | |
163 | */ | |
6d0f6bcf | 164 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
337f9fde KG |
165 | #ifdef CONFIG_PHYS_64BIT |
166 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
167 | #else | |
c953ddfd | 168 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
337f9fde | 169 | #endif |
9490a7f1 | 170 | |
9a1a0aed | 171 | #define CONFIG_FLASH_BR_PRELIM \ |
7ee41107 | 172 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) |
9a1a0aed | 173 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
9490a7f1 | 174 | |
07355700 MH |
175 | #define CONFIG_SYS_BR1_PRELIM \ |
176 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ | |
177 | | BR_PS_16 | BR_V) | |
c953ddfd | 178 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 |
9490a7f1 | 179 | |
07355700 MH |
180 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ |
181 | CONFIG_SYS_FLASH_BASE_PHYS } | |
6d0f6bcf | 182 | #define CONFIG_SYS_FLASH_QUIET_TEST |
9490a7f1 KG |
183 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
184 | ||
07355700 MH |
185 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
186 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
6d0f6bcf | 187 | #undef CONFIG_SYS_FLASH_CHECKSUM |
07355700 MH |
188 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
189 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
9490a7f1 | 190 | |
0234446f | 191 | #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) |
9a1a0aed | 192 | #define CONFIG_SYS_RAMBOOT |
a55bb834 | 193 | #define CONFIG_SYS_EXTRA_ENV_RELOC |
9a1a0aed MH |
194 | #else |
195 | #undef CONFIG_SYS_RAMBOOT | |
196 | #endif | |
197 | ||
9490a7f1 | 198 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
199 | #define CONFIG_SYS_FLASH_CFI |
200 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
201 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
9490a7f1 KG |
202 | |
203 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
204 | ||
68d4230c | 205 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
9490a7f1 KG |
206 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
207 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
337f9fde KG |
208 | #ifdef CONFIG_PHYS_64BIT |
209 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
210 | #else | |
52b565f5 | 211 | #define PIXIS_BASE_PHYS PIXIS_BASE |
337f9fde | 212 | #endif |
9490a7f1 | 213 | |
52b565f5 | 214 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
07355700 | 215 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
9490a7f1 KG |
216 | |
217 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
218 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
219 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
220 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ | |
221 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
222 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ | |
223 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ | |
224 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
225 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ | |
226 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
227 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ | |
228 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
229 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
230 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ | |
231 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
6bb5b412 KG |
232 | #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ |
233 | #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ | |
234 | #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ | |
235 | #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ | |
236 | #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ | |
237 | #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ | |
238 | #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ | |
9490a7f1 KG |
239 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
240 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
241 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ | |
242 | #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ | |
243 | #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ | |
244 | #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ | |
245 | #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ | |
246 | #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ | |
247 | #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ | |
248 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ | |
249 | #define PIXIS_LED 0x25 /* LED Register */ | |
250 | ||
9a1a0aed MH |
251 | #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ |
252 | ||
9490a7f1 KG |
253 | /* old pixis referenced names */ |
254 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
255 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
509e19ca | 256 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e |
9490a7f1 | 257 | |
6d0f6bcf JCPV |
258 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
259 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
553f0982 | 260 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
9490a7f1 | 261 | |
07355700 | 262 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
25ddd1fb | 263 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 264 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
9490a7f1 | 265 | |
07355700 MH |
266 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
267 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
9490a7f1 | 268 | |
9a1a0aed | 269 | #ifndef CONFIG_NAND_SPL |
337f9fde KG |
270 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
271 | #ifdef CONFIG_PHYS_64BIT | |
272 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
273 | #else | |
274 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
275 | #endif | |
9a1a0aed MH |
276 | #else |
277 | #define CONFIG_SYS_NAND_BASE 0xfff00000 | |
278 | #ifdef CONFIG_PHYS_64BIT | |
279 | #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull | |
280 | #else | |
281 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
282 | #endif | |
283 | #endif | |
c57fc289 JJ |
284 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
285 | CONFIG_SYS_NAND_BASE + 0x40000, \ | |
286 | CONFIG_SYS_NAND_BASE + 0x80000, \ | |
287 | CONFIG_SYS_NAND_BASE + 0xC0000} | |
288 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 | |
c57fc289 JJ |
289 | #define CONFIG_NAND_FSL_ELBC 1 |
290 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
291 | ||
9a1a0aed MH |
292 | /* NAND boot: 4K NAND loader config */ |
293 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
c6e8f49a | 294 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) |
9a1a0aed MH |
295 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) |
296 | #define CONFIG_SYS_NAND_U_BOOT_START \ | |
297 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) | |
298 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
299 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) | |
300 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
301 | ||
c57fc289 | 302 | /* NAND flash config */ |
a3055c58 | 303 | #define CONFIG_SYS_NAND_BR_PRELIM \ |
07355700 MH |
304 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
305 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
306 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
307 | | BR_MS_FCM /* MSEL = FCM */ \ | |
308 | | BR_V) /* valid */ | |
a3055c58 | 309 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
07355700 MH |
310 | | OR_FCM_PGS /* Large Page*/ \ |
311 | | OR_FCM_CSCT \ | |
312 | | OR_FCM_CST \ | |
313 | | OR_FCM_CHT \ | |
314 | | OR_FCM_SCY_1 \ | |
315 | | OR_FCM_TRLX \ | |
316 | | OR_FCM_EHTR) | |
317 | ||
9a1a0aed MH |
318 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
319 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
a3055c58 MM |
320 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
321 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
07355700 MH |
322 | |
323 | #define CONFIG_SYS_BR4_PRELIM \ | |
7ee41107 | 324 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ |
07355700 MH |
325 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
326 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
327 | | BR_MS_FCM /* MSEL = FCM */ \ | |
328 | | BR_V) /* valid */ | |
a3055c58 | 329 | #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
07355700 | 330 | #define CONFIG_SYS_BR5_PRELIM \ |
7ee41107 | 331 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \ |
07355700 MH |
332 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
333 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
334 | | BR_MS_FCM /* MSEL = FCM */ \ | |
335 | | BR_V) /* valid */ | |
a3055c58 | 336 | #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
07355700 MH |
337 | |
338 | #define CONFIG_SYS_BR6_PRELIM \ | |
7ee41107 | 339 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \ |
07355700 MH |
340 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
341 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
342 | | BR_MS_FCM /* MSEL = FCM */ \ | |
343 | | BR_V) /* valid */ | |
a3055c58 | 344 | #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ |
c57fc289 | 345 | |
9490a7f1 KG |
346 | /* Serial Port - controlled on board with jumper J8 |
347 | * open - index 2 | |
348 | * shorted - index 1 | |
349 | */ | |
350 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
351 | #define CONFIG_SYS_NS16550_SERIAL |
352 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
353 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
93341909 KG |
354 | #ifdef CONFIG_NAND_SPL |
355 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
356 | #endif | |
9490a7f1 | 357 | |
6d0f6bcf | 358 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
9490a7f1 KG |
359 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
360 | ||
07355700 MH |
361 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) |
362 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) | |
9490a7f1 | 363 | |
9490a7f1 KG |
364 | /* |
365 | * I2C | |
366 | */ | |
00f792e0 HS |
367 | #define CONFIG_SYS_I2C |
368 | #define CONFIG_SYS_I2C_FSL | |
369 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
370 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
371 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
372 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
373 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
374 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
375 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } | |
9490a7f1 KG |
376 | |
377 | /* | |
378 | * I2C2 EEPROM | |
379 | */ | |
32628c50 JCPV |
380 | #define CONFIG_ID_EEPROM |
381 | #ifdef CONFIG_ID_EEPROM | |
6d0f6bcf | 382 | #define CONFIG_SYS_I2C_EEPROM_NXID |
9490a7f1 | 383 | #endif |
6d0f6bcf JCPV |
384 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
385 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
386 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
9490a7f1 | 387 | |
ae2044d8 XX |
388 | /* |
389 | * eSPI - Enhanced SPI | |
390 | */ | |
391 | #define CONFIG_HARD_SPI | |
ae2044d8 XX |
392 | |
393 | #if defined(CONFIG_SPI_FLASH) | |
ae2044d8 XX |
394 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
395 | #define CONFIG_SF_DEFAULT_MODE 0 | |
396 | #endif | |
397 | ||
9490a7f1 KG |
398 | /* |
399 | * General PCI | |
400 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
401 | */ | |
402 | ||
5af0fdd8 | 403 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
337f9fde KG |
404 | #ifdef CONFIG_PHYS_64BIT |
405 | #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 | |
406 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull | |
407 | #else | |
5af0fdd8 KG |
408 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
409 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 | |
337f9fde | 410 | #endif |
6d0f6bcf | 411 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
337f9fde KG |
412 | #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 |
413 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 | |
414 | #ifdef CONFIG_PHYS_64BIT | |
415 | #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull | |
416 | #else | |
417 | #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 | |
418 | #endif | |
419 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ | |
9490a7f1 KG |
420 | |
421 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
5f7b31b0 | 422 | #define CONFIG_SYS_PCIE1_NAME "Slot 1" |
5af0fdd8 | 423 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 |
337f9fde KG |
424 | #ifdef CONFIG_PHYS_64BIT |
425 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 | |
426 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull | |
427 | #else | |
10795f42 | 428 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 |
5af0fdd8 | 429 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 |
337f9fde | 430 | #endif |
6d0f6bcf | 431 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ |
aca5f018 | 432 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 |
337f9fde KG |
433 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
434 | #ifdef CONFIG_PHYS_64BIT | |
435 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull | |
436 | #else | |
6d0f6bcf | 437 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 |
337f9fde | 438 | #endif |
6d0f6bcf | 439 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
9490a7f1 KG |
440 | |
441 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
5f7b31b0 | 442 | #define CONFIG_SYS_PCIE2_NAME "Slot 2" |
5af0fdd8 | 443 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 |
337f9fde KG |
444 | #ifdef CONFIG_PHYS_64BIT |
445 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 | |
446 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull | |
447 | #else | |
10795f42 | 448 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 |
5af0fdd8 | 449 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 |
337f9fde | 450 | #endif |
6d0f6bcf | 451 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ |
aca5f018 | 452 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 |
337f9fde KG |
453 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
454 | #ifdef CONFIG_PHYS_64BIT | |
455 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull | |
456 | #else | |
6d0f6bcf | 457 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 |
337f9fde | 458 | #endif |
6d0f6bcf | 459 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
9490a7f1 KG |
460 | |
461 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ | |
5f7b31b0 | 462 | #define CONFIG_SYS_PCIE3_NAME "Slot 3" |
5af0fdd8 | 463 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 |
337f9fde KG |
464 | #ifdef CONFIG_PHYS_64BIT |
465 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
466 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull | |
467 | #else | |
10795f42 | 468 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 |
5af0fdd8 | 469 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 |
337f9fde | 470 | #endif |
6d0f6bcf | 471 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 472 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 |
337f9fde KG |
473 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
474 | #ifdef CONFIG_PHYS_64BIT | |
475 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull | |
476 | #else | |
6d0f6bcf | 477 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 |
337f9fde | 478 | #endif |
6d0f6bcf | 479 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
9490a7f1 KG |
480 | |
481 | #if defined(CONFIG_PCI) | |
9490a7f1 | 482 | /*PCIE video card used*/ |
aca5f018 | 483 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT |
9490a7f1 KG |
484 | |
485 | /*PCI video card used*/ | |
aca5f018 | 486 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ |
9490a7f1 KG |
487 | |
488 | /* video */ | |
9490a7f1 KG |
489 | |
490 | #if defined(CONFIG_VIDEO) | |
491 | #define CONFIG_BIOSEMU | |
9490a7f1 KG |
492 | #define CONFIG_ATI_RADEON_FB |
493 | #define CONFIG_VIDEO_LOGO | |
aca5f018 | 494 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT |
9490a7f1 KG |
495 | #endif |
496 | ||
497 | #undef CONFIG_EEPRO100 | |
498 | #undef CONFIG_TULIP | |
9490a7f1 | 499 | |
9490a7f1 | 500 | #ifndef CONFIG_PCI_PNP |
5f91ef6a KG |
501 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS |
502 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS | |
9490a7f1 KG |
503 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
504 | #endif | |
505 | ||
506 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
507 | ||
508 | #endif /* CONFIG_PCI */ | |
509 | ||
510 | /* SATA */ | |
6d0f6bcf | 511 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
9490a7f1 | 512 | #define CONFIG_SATA1 |
6d0f6bcf JCPV |
513 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
514 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
9490a7f1 | 515 | #define CONFIG_SATA2 |
6d0f6bcf JCPV |
516 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
517 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
9490a7f1 KG |
518 | |
519 | #ifdef CONFIG_FSL_SATA | |
520 | #define CONFIG_LBA48 | |
9490a7f1 KG |
521 | #endif |
522 | ||
523 | #if defined(CONFIG_TSEC_ENET) | |
524 | ||
9490a7f1 KG |
525 | #define CONFIG_MII 1 /* MII PHY management */ |
526 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
527 | #define CONFIG_TSEC1 1 | |
528 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
529 | #define CONFIG_TSEC3 1 | |
530 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
531 | ||
2e26d837 JJ |
532 | #define CONFIG_FSL_SGMII_RISER 1 |
533 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
534 | ||
9490a7f1 KG |
535 | #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ |
536 | #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ | |
537 | ||
538 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
539 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
540 | ||
541 | #define TSEC1_PHYIDX 0 | |
542 | #define TSEC3_PHYIDX 0 | |
543 | ||
544 | #define CONFIG_ETHPRIME "eTSEC1" | |
545 | ||
9490a7f1 KG |
546 | #endif /* CONFIG_TSEC_ENET */ |
547 | ||
548 | /* | |
549 | * Environment | |
550 | */ | |
9a1a0aed MH |
551 | |
552 | #if defined(CONFIG_SYS_RAMBOOT) | |
0234446f | 553 | #if defined(CONFIG_RAMBOOT_SPIFLASH) |
2d4afd49 XX |
554 | #define CONFIG_ENV_SPI_BUS 0 |
555 | #define CONFIG_ENV_SPI_CS 0 | |
556 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
557 | #define CONFIG_ENV_SPI_MODE 0 | |
558 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
559 | #define CONFIG_ENV_OFFSET 0xF0000 | |
560 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
561 | #elif defined(CONFIG_RAMBOOT_SDCARD) | |
4394d0c2 | 562 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
2d4afd49 XX |
563 | #define CONFIG_ENV_SIZE 0x2000 |
564 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
565 | #else | |
e40ac487 MH |
566 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
567 | #define CONFIG_ENV_SIZE 0x2000 | |
9a1a0aed | 568 | #endif |
9490a7f1 | 569 | #else |
9a1a0aed | 570 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
9a1a0aed MH |
571 | #define CONFIG_ENV_SIZE 0x2000 |
572 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
9490a7f1 | 573 | #endif |
9490a7f1 KG |
574 | |
575 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 576 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
9490a7f1 | 577 | |
9490a7f1 KG |
578 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
579 | ||
80522dc8 AF |
580 | #ifdef CONFIG_MMC |
581 | #define CONFIG_FSL_ESDHC | |
582 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
1116ebb9 F |
583 | #endif |
584 | ||
585 | /* | |
586 | * USB | |
587 | */ | |
3d7506fa | 588 | #define CONFIG_HAS_FSL_MPH_USB |
589 | #ifdef CONFIG_HAS_FSL_MPH_USB | |
8850c5d5 | 590 | #ifdef CONFIG_USB_EHCI_HCD |
1116ebb9 F |
591 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
592 | #define CONFIG_USB_EHCI_FSL | |
1116ebb9 | 593 | #endif |
3d7506fa | 594 | #endif |
1116ebb9 | 595 | |
9490a7f1 KG |
596 | /* |
597 | * Miscellaneous configurable options | |
598 | */ | |
6d0f6bcf | 599 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
07355700 | 600 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
5be58f5f | 601 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
6d0f6bcf | 602 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
9490a7f1 KG |
603 | |
604 | /* | |
605 | * For booting Linux, the board info and command line data | |
a832ac41 | 606 | * have to be in the first 64 MB of memory, since this is |
9490a7f1 KG |
607 | * the maximum mapped by the Linux kernel during initialization. |
608 | */ | |
a832ac41 KG |
609 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ |
610 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
9490a7f1 | 611 | |
9490a7f1 KG |
612 | #if defined(CONFIG_CMD_KGDB) |
613 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
9490a7f1 KG |
614 | #endif |
615 | ||
616 | /* | |
617 | * Environment Configuration | |
618 | */ | |
619 | ||
620 | /* The mac addresses for all ethernet interface */ | |
621 | #if defined(CONFIG_TSEC_ENET) | |
622 | #define CONFIG_HAS_ETH0 | |
9490a7f1 | 623 | #define CONFIG_HAS_ETH1 |
9490a7f1 | 624 | #define CONFIG_HAS_ETH2 |
9490a7f1 | 625 | #define CONFIG_HAS_ETH3 |
9490a7f1 KG |
626 | #endif |
627 | ||
628 | #define CONFIG_IPADDR 192.168.1.254 | |
629 | ||
630 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 631 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 632 | #define CONFIG_BOOTFILE "uImage" |
07355700 | 633 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
9490a7f1 KG |
634 | |
635 | #define CONFIG_SERVERIP 192.168.1.1 | |
636 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
637 | #define CONFIG_NETMASK 255.255.255.0 | |
638 | ||
639 | /* default location for tftp and bootm */ | |
640 | #define CONFIG_LOADADDR 1000000 | |
641 | ||
9490a7f1 | 642 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d MV |
643 | "netdev=eth0\0" \ |
644 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
645 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
646 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
647 | " +$filesize; " \ | |
648 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
649 | " +$filesize; " \ | |
650 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
651 | " $filesize; " \ | |
652 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
653 | " +$filesize; " \ | |
654 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
655 | " $filesize\0" \ | |
656 | "consoledev=ttyS0\0" \ | |
657 | "ramdiskaddr=2000000\0" \ | |
658 | "ramdiskfile=8536ds/ramdisk.uboot\0" \ | |
b24a4f62 | 659 | "fdtaddr=1e00000\0" \ |
5368c55d MV |
660 | "fdtfile=8536ds/mpc8536ds.dtb\0" \ |
661 | "bdev=sda3\0" \ | |
662 | "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" | |
9490a7f1 KG |
663 | |
664 | #define CONFIG_HDBOOT \ | |
665 | "setenv bootargs root=/dev/$bdev rw " \ | |
666 | "console=$consoledev,$baudrate $othbootargs;" \ | |
667 | "tftp $loadaddr $bootfile;" \ | |
668 | "tftp $fdtaddr $fdtfile;" \ | |
669 | "bootm $loadaddr - $fdtaddr" | |
670 | ||
671 | #define CONFIG_NFSBOOTCOMMAND \ | |
672 | "setenv bootargs root=/dev/nfs rw " \ | |
673 | "nfsroot=$serverip:$rootpath " \ | |
674 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
675 | "console=$consoledev,$baudrate $othbootargs;" \ | |
676 | "tftp $loadaddr $bootfile;" \ | |
677 | "tftp $fdtaddr $fdtfile;" \ | |
678 | "bootm $loadaddr - $fdtaddr" | |
679 | ||
680 | #define CONFIG_RAMBOOTCOMMAND \ | |
681 | "setenv bootargs root=/dev/ram rw " \ | |
682 | "console=$consoledev,$baudrate $othbootargs;" \ | |
683 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
684 | "tftp $loadaddr $bootfile;" \ | |
685 | "tftp $fdtaddr $fdtfile;" \ | |
686 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
687 | ||
688 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
689 | ||
690 | #endif /* __CONFIG_H */ |