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d9b94f28 | 1 | /* |
8b47d7ec | 2 | * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. |
d9b94f28 JL |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
f2cff6b1 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
d9b94f28 JL |
15 | * GNU General Public License for more details. |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * mpc8548cds board configuration file | |
25 | * | |
26 | * Please refer to doc/README.mpc85xxcds for more info. | |
27 | * | |
28 | */ | |
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
b76aef60 | 32 | #ifdef CONFIG_36BIT |
33 | #define CONFIG_PHYS_64BIT | |
34 | #endif | |
35 | ||
d9b94f28 JL |
36 | /* High Level Configuration Options */ |
37 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
38 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
39 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
40 | #define CONFIG_MPC8548 1 /* MPC8548 specific */ | |
41 | #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ | |
42 | ||
2ae18241 WD |
43 | #ifndef CONFIG_SYS_TEXT_BASE |
44 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
45 | #endif | |
46 | ||
8b47d7ec KG |
47 | #define CONFIG_SYS_SRIO |
48 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
49 | ||
f2cff6b1 ES |
50 | #define CONFIG_PCI /* enable any pci type devices */ |
51 | #define CONFIG_PCI1 /* PCI controller 1 */ | |
52 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ | |
f2cff6b1 ES |
53 | #undef CONFIG_PCI2 |
54 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
8ff3de61 | 55 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
0151cbac | 56 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
f2cff6b1 ES |
57 | |
58 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
d9b94f28 | 59 | #define CONFIG_ENV_OVERWRITE |
f2cff6b1 | 60 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
2cfaa1aa | 61 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
d9b94f28 | 62 | |
25eedb2c | 63 | #define CONFIG_FSL_VIA |
25eedb2c | 64 | |
d9b94f28 JL |
65 | #ifndef __ASSEMBLY__ |
66 | extern unsigned long get_clock_freq(void); | |
67 | #endif | |
68 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ | |
69 | ||
70 | /* | |
71 | * These can be toggled for performance analysis, otherwise use default. | |
72 | */ | |
f2cff6b1 ES |
73 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
74 | #define CONFIG_BTB /* toggle branch predition */ | |
d9b94f28 JL |
75 | |
76 | /* | |
77 | * Only possible on E500 Version 2 or newer cores. | |
78 | */ | |
79 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
80 | ||
b76aef60 | 81 | #ifdef CONFIG_PHYS_64BIT |
82 | #define CONFIG_ADDR_MAP | |
83 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
84 | #endif | |
85 | ||
6d0f6bcf JCPV |
86 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
87 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
d9b94f28 | 88 | |
e46fedfe TT |
89 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
90 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
d9b94f28 | 91 | |
e31d2c1e JL |
92 | /* DDR Setup */ |
93 | #define CONFIG_FSL_DDR2 | |
94 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
95 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
96 | #define CONFIG_DDR_SPD | |
e31d2c1e | 97 | |
867b06f4 | 98 | #define CONFIG_DDR_ECC |
9b0ad1b1 | 99 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
e31d2c1e JL |
100 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
101 | ||
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
103 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
d9b94f28 | 104 | |
e31d2c1e JL |
105 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
106 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
107 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
d9b94f28 | 108 | |
e31d2c1e JL |
109 | /* I2C addresses of SPD EEPROMs */ |
110 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
111 | ||
112 | /* Make sure required options are set */ | |
d9b94f28 JL |
113 | #ifndef CONFIG_SPD_EEPROM |
114 | #error ("CONFIG_SPD_EEPROM is required") | |
115 | #endif | |
116 | ||
117 | #undef CONFIG_CLOCKS_IN_MHZ | |
fff80975 | 118 | /* |
119 | * Physical Address Map | |
120 | * | |
121 | * 32bit: | |
122 | * 0x0000_0000 0x7fff_ffff DDR 2G cacheable | |
123 | * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable | |
124 | * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable | |
125 | * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable | |
126 | * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable | |
127 | * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable | |
128 | * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable | |
129 | * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable | |
130 | * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable | |
131 | * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable | |
132 | * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable | |
133 | * | |
b76aef60 | 134 | * 36bit: |
135 | * 0x00000_0000 0x07fff_ffff DDR 2G cacheable | |
136 | * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable | |
137 | * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable | |
138 | * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable | |
139 | * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable | |
140 | * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable | |
141 | * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable | |
142 | * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable | |
143 | * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable | |
144 | * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable | |
145 | * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable | |
146 | * | |
fff80975 | 147 | */ |
148 | ||
d9b94f28 | 149 | |
d9b94f28 JL |
150 | /* |
151 | * Local Bus Definitions | |
152 | */ | |
153 | ||
154 | /* | |
155 | * FLASH on the Local Bus | |
156 | * Two banks, 8M each, using the CFI driver. | |
157 | * Boot from BR0/OR0 bank at 0xff00_0000 | |
158 | * Alternate BR1/OR1 bank at 0xff80_0000 | |
159 | * | |
160 | * BR0, BR1: | |
161 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 | |
162 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 | |
163 | * Port Size = 16 bits = BRx[19:20] = 10 | |
164 | * Use GPCM = BRx[24:26] = 000 | |
165 | * Valid = BRx[31] = 1 | |
166 | * | |
f2cff6b1 ES |
167 | * 0 4 8 12 16 20 24 28 |
168 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
169 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
d9b94f28 JL |
170 | * |
171 | * OR0, OR1: | |
172 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 | |
173 | * Reserved ORx[17:18] = 11, confusion here? | |
174 | * CSNT = ORx[20] = 1 | |
175 | * ACS = half cycle delay = ORx[21:22] = 11 | |
176 | * SCY = 6 = ORx[24:27] = 0110 | |
177 | * TRLX = use relaxed timing = ORx[29] = 1 | |
178 | * EAD = use external address latch delay = OR[31] = 1 | |
179 | * | |
f2cff6b1 ES |
180 | * 0 4 8 12 16 20 24 28 |
181 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
d9b94f28 JL |
182 | */ |
183 | ||
fff80975 | 184 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
b76aef60 | 185 | #ifdef CONFIG_PHYS_64BIT |
186 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull | |
187 | #else | |
fff80975 | 188 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
b76aef60 | 189 | #endif |
d9b94f28 | 190 | |
fff80975 | 191 | #define CONFIG_SYS_BR0_PRELIM \ |
192 | (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800000)) \ | |
193 | | BR_PS_16 | BR_V) | |
194 | #define CONFIG_SYS_BR1_PRELIM \ | |
195 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) | |
d9b94f28 | 196 | |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
198 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 | |
d9b94f28 | 199 | |
fff80975 | 200 | #define CONFIG_SYS_FLASH_BANKS_LIST \ |
201 | {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} | |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
203 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
204 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
205 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
206 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
d9b94f28 | 207 | |
14d0a02a | 208 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
d9b94f28 | 209 | |
00b1883a | 210 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_FLASH_CFI |
212 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
d9b94f28 | 213 | |
867b06f4 | 214 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
d9b94f28 JL |
215 | |
216 | /* | |
217 | * SDRAM on the Local Bus | |
218 | */ | |
fff80975 | 219 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
b76aef60 | 220 | #ifdef CONFIG_PHYS_64BIT |
221 | #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull | |
222 | #else | |
fff80975 | 223 | #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE |
b76aef60 | 224 | #endif |
6d0f6bcf | 225 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
d9b94f28 JL |
226 | |
227 | /* | |
228 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 229 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
d9b94f28 JL |
230 | * |
231 | * For BR2, need: | |
232 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
233 | * port-size = 32-bits = BR2[19:20] = 11 | |
234 | * no parity checking = BR2[21:22] = 00 | |
235 | * SDRAM for MSEL = BR2[24:26] = 011 | |
236 | * Valid = BR[31] = 1 | |
237 | * | |
f2cff6b1 | 238 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
239 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
240 | * | |
6d0f6bcf | 241 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
d9b94f28 JL |
242 | * FIXME: the top 17 bits of BR2. |
243 | */ | |
244 | ||
fff80975 | 245 | #define CONFIG_SYS_BR2_PRELIM \ |
246 | (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ | |
247 | | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) | |
d9b94f28 JL |
248 | |
249 | /* | |
6d0f6bcf | 250 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
d9b94f28 JL |
251 | * |
252 | * For OR2, need: | |
253 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
254 | * XAM, OR2[17:18] = 11 | |
255 | * 9 columns OR2[19-21] = 010 | |
f2cff6b1 | 256 | * 13 rows OR2[23-25] = 100 |
d9b94f28 JL |
257 | * EAD set for extra time OR[31] = 1 |
258 | * | |
f2cff6b1 | 259 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
260 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
261 | */ | |
262 | ||
6d0f6bcf | 263 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
d9b94f28 | 264 | |
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
266 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
267 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
268 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
d9b94f28 | 269 | |
d9b94f28 JL |
270 | /* |
271 | * Common settings for all Local Bus SDRAM commands. | |
272 | * At run time, either BSMA1516 (for CPU 1.1) | |
f2cff6b1 | 273 | * or BSMA1617 (for CPU 1.0) (old) |
d9b94f28 JL |
274 | * is OR'ed in too. |
275 | */ | |
b0fe93ed KG |
276 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
277 | | LSDMR_PRETOACT7 \ | |
278 | | LSDMR_ACTTORW7 \ | |
279 | | LSDMR_BL8 \ | |
280 | | LSDMR_WRC4 \ | |
281 | | LSDMR_CL3 \ | |
282 | | LSDMR_RFEN \ | |
d9b94f28 JL |
283 | ) |
284 | ||
285 | /* | |
286 | * The CADMUS registers are connected to CS3 on CDS. | |
287 | * The new memory map places CADMUS at 0xf8000000. | |
288 | * | |
289 | * For BR3, need: | |
290 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 | |
291 | * port-size = 8-bits = BR[19:20] = 01 | |
292 | * no parity checking = BR[21:22] = 00 | |
f2cff6b1 ES |
293 | * GPMC for MSEL = BR[24:26] = 000 |
294 | * Valid = BR[31] = 1 | |
d9b94f28 | 295 | * |
f2cff6b1 | 296 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
297 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 |
298 | * | |
299 | * For OR3, need: | |
f2cff6b1 | 300 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 |
d9b94f28 | 301 | * disable buffer ctrl OR[19] = 0 |
f2cff6b1 ES |
302 | * CSNT OR[20] = 1 |
303 | * ACS OR[21:22] = 11 | |
304 | * XACS OR[23] = 1 | |
d9b94f28 | 305 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe |
f2cff6b1 ES |
306 | * SETA OR[28] = 0 |
307 | * TRLX OR[29] = 1 | |
308 | * EHTR OR[30] = 1 | |
309 | * EAD extra time OR[31] = 1 | |
d9b94f28 | 310 | * |
f2cff6b1 | 311 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
312 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 |
313 | */ | |
314 | ||
25eedb2c JL |
315 | #define CONFIG_FSL_CADMUS |
316 | ||
d9b94f28 | 317 | #define CADMUS_BASE_ADDR 0xf8000000 |
b76aef60 | 318 | #ifdef CONFIG_PHYS_64BIT |
319 | #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull | |
320 | #else | |
fff80975 | 321 | #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR |
b76aef60 | 322 | #endif |
fff80975 | 323 | #define CONFIG_SYS_BR3_PRELIM \ |
324 | (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) | |
6d0f6bcf | 325 | #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 |
d9b94f28 | 326 | |
6d0f6bcf JCPV |
327 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
328 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 329 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
f2cff6b1 | 330 | |
25ddd1fb | 331 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 332 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
d9b94f28 | 333 | |
6d0f6bcf | 334 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
867b06f4 | 335 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
d9b94f28 JL |
336 | |
337 | /* Serial Port */ | |
f2cff6b1 | 338 | #define CONFIG_CONS_INDEX 2 |
6d0f6bcf JCPV |
339 | #define CONFIG_SYS_NS16550 |
340 | #define CONFIG_SYS_NS16550_SERIAL | |
341 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
342 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
d9b94f28 | 343 | |
6d0f6bcf | 344 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
d9b94f28 JL |
345 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
346 | ||
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
348 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
d9b94f28 JL |
349 | |
350 | /* Use the HUSH parser */ | |
6d0f6bcf | 351 | #define CONFIG_SYS_HUSH_PARSER |
d9b94f28 | 352 | |
40d5fa35 | 353 | /* pass open firmware flat tree */ |
b90d2549 KG |
354 | #define CONFIG_OF_LIBFDT 1 |
355 | #define CONFIG_OF_BOARD_SETUP 1 | |
356 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
40d5fa35 | 357 | |
20476726 JL |
358 | /* |
359 | * I2C | |
360 | */ | |
361 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
362 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
f2cff6b1 | 363 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
6d0f6bcf JCPV |
364 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
365 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
366 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
367 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
d9b94f28 | 368 | |
e8d18541 TT |
369 | /* EEPROM */ |
370 | #define CONFIG_ID_EEPROM | |
6d0f6bcf JCPV |
371 | #define CONFIG_SYS_I2C_EEPROM_CCID |
372 | #define CONFIG_SYS_ID_EEPROM | |
373 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
374 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
e8d18541 | 375 | |
d9b94f28 JL |
376 | /* |
377 | * General PCI | |
362dd830 | 378 | * Memory space is mapped 1-1, but I/O space must start from 0. |
d9b94f28 | 379 | */ |
5af0fdd8 | 380 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
b76aef60 | 381 | #ifdef CONFIG_PHYS_64BIT |
382 | #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 | |
383 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull | |
384 | #else | |
10795f42 | 385 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 386 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
b76aef60 | 387 | #endif |
6d0f6bcf | 388 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 389 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 390 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
b76aef60 | 391 | #ifdef CONFIG_PHYS_64BIT |
392 | #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull | |
393 | #else | |
6d0f6bcf | 394 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
b76aef60 | 395 | #endif |
6d0f6bcf | 396 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ |
d9b94f28 | 397 | |
f2cff6b1 | 398 | #ifdef CONFIG_PCIE1 |
f5fa8f36 | 399 | #define CONFIG_SYS_PCIE1_NAME "Slot" |
5af0fdd8 | 400 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
b76aef60 | 401 | #ifdef CONFIG_PHYS_64BIT |
402 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
403 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull | |
404 | #else | |
10795f42 | 405 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
5af0fdd8 | 406 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
b76aef60 | 407 | #endif |
6d0f6bcf | 408 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 409 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 |
5f91ef6a | 410 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
b76aef60 | 411 | #ifdef CONFIG_PHYS_64BIT |
412 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull | |
413 | #else | |
6d0f6bcf | 414 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 |
b76aef60 | 415 | #endif |
6d0f6bcf | 416 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ |
f2cff6b1 | 417 | #endif |
d9b94f28 | 418 | |
41fb7e0f ZR |
419 | /* |
420 | * RapidIO MMU | |
421 | */ | |
fff80975 | 422 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 |
b76aef60 | 423 | #ifdef CONFIG_PHYS_64BIT |
424 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull | |
425 | #else | |
fff80975 | 426 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 |
b76aef60 | 427 | #endif |
8b47d7ec | 428 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ |
d9b94f28 | 429 | |
7f3f2bd2 RV |
430 | #ifdef CONFIG_LEGACY |
431 | #define BRIDGE_ID 17 | |
432 | #define VIA_ID 2 | |
433 | #else | |
434 | #define BRIDGE_ID 28 | |
435 | #define VIA_ID 4 | |
436 | #endif | |
437 | ||
d9b94f28 JL |
438 | #if defined(CONFIG_PCI) |
439 | ||
f2cff6b1 | 440 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
d9b94f28 JL |
441 | |
442 | #undef CONFIG_EEPRO100 | |
443 | #undef CONFIG_TULIP | |
867b06f4 | 444 | #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ |
d9b94f28 | 445 | |
867b06f4 | 446 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
f2cff6b1 | 447 | |
d9b94f28 JL |
448 | #endif /* CONFIG_PCI */ |
449 | ||
450 | ||
451 | #if defined(CONFIG_TSEC_ENET) | |
452 | ||
d9b94f28 | 453 | #define CONFIG_MII 1 /* MII PHY management */ |
255a3577 KP |
454 | #define CONFIG_TSEC1 1 |
455 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
456 | #define CONFIG_TSEC2 1 | |
457 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
458 | #define CONFIG_TSEC3 1 | |
459 | #define CONFIG_TSEC3_NAME "eTSEC2" | |
f2cff6b1 | 460 | #define CONFIG_TSEC4 |
255a3577 | 461 | #define CONFIG_TSEC4_NAME "eTSEC3" |
d9b94f28 JL |
462 | #undef CONFIG_MPC85XX_FEC |
463 | ||
d3701228 | 464 | #define CONFIG_PHY_MARVELL |
465 | ||
d9b94f28 JL |
466 | #define TSEC1_PHY_ADDR 0 |
467 | #define TSEC2_PHY_ADDR 1 | |
468 | #define TSEC3_PHY_ADDR 2 | |
469 | #define TSEC4_PHY_ADDR 3 | |
d9b94f28 JL |
470 | |
471 | #define TSEC1_PHYIDX 0 | |
472 | #define TSEC2_PHYIDX 0 | |
473 | #define TSEC3_PHYIDX 0 | |
474 | #define TSEC4_PHYIDX 0 | |
3a79013e AF |
475 | #define TSEC1_FLAGS TSEC_GIGABIT |
476 | #define TSEC2_FLAGS TSEC_GIGABIT | |
477 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
478 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
d9b94f28 JL |
479 | |
480 | /* Options are: eTSEC[0-3] */ | |
481 | #define CONFIG_ETHPRIME "eTSEC0" | |
f2cff6b1 | 482 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
d9b94f28 JL |
483 | #endif /* CONFIG_TSEC_ENET */ |
484 | ||
485 | /* | |
486 | * Environment | |
487 | */ | |
5a1aceb0 | 488 | #define CONFIG_ENV_IS_IN_FLASH 1 |
867b06f4 | 489 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
490 | #define CONFIG_ENV_ADDR 0xfff80000 | |
491 | #else | |
492 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
493 | #endif | |
494 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ | |
0e8d1586 | 495 | #define CONFIG_ENV_SIZE 0x2000 |
d9b94f28 JL |
496 | |
497 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 498 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
d9b94f28 | 499 | |
659e2f67 JL |
500 | /* |
501 | * BOOTP options | |
502 | */ | |
503 | #define CONFIG_BOOTP_BOOTFILESIZE | |
504 | #define CONFIG_BOOTP_BOOTPATH | |
505 | #define CONFIG_BOOTP_GATEWAY | |
506 | #define CONFIG_BOOTP_HOSTNAME | |
507 | ||
508 | ||
2835e518 JL |
509 | /* |
510 | * Command line configuration. | |
511 | */ | |
512 | #include <config_cmd_default.h> | |
513 | ||
514 | #define CONFIG_CMD_PING | |
515 | #define CONFIG_CMD_I2C | |
516 | #define CONFIG_CMD_MII | |
82ac8c97 | 517 | #define CONFIG_CMD_ELF |
1c9aa76b KG |
518 | #define CONFIG_CMD_IRQ |
519 | #define CONFIG_CMD_SETEXPR | |
199e262e | 520 | #define CONFIG_CMD_REGINFO |
2835e518 | 521 | |
d9b94f28 | 522 | #if defined(CONFIG_PCI) |
2835e518 | 523 | #define CONFIG_CMD_PCI |
d9b94f28 | 524 | #endif |
2835e518 | 525 | |
d9b94f28 JL |
526 | |
527 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
528 | ||
529 | /* | |
530 | * Miscellaneous configurable options | |
531 | */ | |
6d0f6bcf | 532 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
533 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
534 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf JCPV |
535 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
536 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
2835e518 | 537 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 538 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
d9b94f28 | 539 | #else |
6d0f6bcf | 540 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
d9b94f28 | 541 | #endif |
6d0f6bcf JCPV |
542 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
543 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
544 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
545 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
d9b94f28 JL |
546 | |
547 | /* | |
548 | * For booting Linux, the board info and command line data | |
a832ac41 | 549 | * have to be in the first 64 MB of memory, since this is |
d9b94f28 JL |
550 | * the maximum mapped by the Linux kernel during initialization. |
551 | */ | |
a832ac41 KG |
552 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
553 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
d9b94f28 | 554 | |
2835e518 | 555 | #if defined(CONFIG_CMD_KGDB) |
d9b94f28 JL |
556 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
557 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
558 | #endif | |
559 | ||
560 | /* | |
561 | * Environment Configuration | |
562 | */ | |
563 | ||
564 | /* The mac addresses for all ethernet interface */ | |
565 | #if defined(CONFIG_TSEC_ENET) | |
10327dc5 | 566 | #define CONFIG_HAS_ETH0 |
f2cff6b1 | 567 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
d9b94f28 | 568 | #define CONFIG_HAS_ETH1 |
f2cff6b1 | 569 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
d9b94f28 | 570 | #define CONFIG_HAS_ETH2 |
f2cff6b1 | 571 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
09f3e09e | 572 | #define CONFIG_HAS_ETH3 |
f2cff6b1 | 573 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD |
d9b94f28 JL |
574 | #endif |
575 | ||
f2cff6b1 | 576 | #define CONFIG_IPADDR 192.168.1.253 |
d9b94f28 | 577 | |
f2cff6b1 | 578 | #define CONFIG_HOSTNAME unknown |
8b3637c6 | 579 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 580 | #define CONFIG_BOOTFILE "8548cds/uImage.uboot" |
f2cff6b1 | 581 | #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ |
d9b94f28 | 582 | |
f2cff6b1 | 583 | #define CONFIG_SERVERIP 192.168.1.1 |
d9b94f28 | 584 | #define CONFIG_GATEWAYIP 192.168.1.1 |
f2cff6b1 | 585 | #define CONFIG_NETMASK 255.255.255.0 |
d9b94f28 | 586 | |
f2cff6b1 | 587 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
d9b94f28 | 588 | |
f2cff6b1 ES |
589 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
590 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
d9b94f28 JL |
591 | |
592 | #define CONFIG_BAUDRATE 115200 | |
593 | ||
867b06f4 | 594 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
595 | "hwconfig=fsl_ddr:ecc=off\0" \ | |
596 | "netdev=eth0\0" \ | |
597 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
598 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
599 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
600 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
601 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
602 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
603 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\ | |
604 | "consoledev=ttyS1\0" \ | |
605 | "ramdiskaddr=2000000\0" \ | |
606 | "ramdiskfile=ramdisk.uboot\0" \ | |
607 | "fdtaddr=c00000\0" \ | |
608 | "fdtfile=mpc8548cds.dtb\0" | |
f2cff6b1 ES |
609 | |
610 | #define CONFIG_NFSBOOTCOMMAND \ | |
611 | "setenv bootargs root=/dev/nfs rw " \ | |
612 | "nfsroot=$serverip:$rootpath " \ | |
d9b94f28 | 613 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
f2cff6b1 ES |
614 | "console=$consoledev,$baudrate $othbootargs;" \ |
615 | "tftp $loadaddr $bootfile;" \ | |
4bf4abb8 ES |
616 | "tftp $fdtaddr $fdtfile;" \ |
617 | "bootm $loadaddr - $fdtaddr" | |
8272dc2f | 618 | |
d9b94f28 JL |
619 | |
620 | #define CONFIG_RAMBOOTCOMMAND \ | |
f2cff6b1 ES |
621 | "setenv bootargs root=/dev/ram rw " \ |
622 | "console=$consoledev,$baudrate $othbootargs;" \ | |
623 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
624 | "tftp $loadaddr $bootfile;" \ | |
4bf4abb8 ES |
625 | "tftp $fdtaddr $fdtfile;" \ |
626 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
f2cff6b1 ES |
627 | |
628 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
d9b94f28 JL |
629 | |
630 | #endif /* __CONFIG_H */ |