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d9b94f28 | 1 | /* |
8b47d7ec | 2 | * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. |
d9b94f28 JL |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
f2cff6b1 | 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
d9b94f28 JL |
15 | * GNU General Public License for more details. |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * mpc8548cds board configuration file | |
25 | * | |
26 | * Please refer to doc/README.mpc85xxcds for more info. | |
27 | * | |
28 | */ | |
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
32 | /* High Level Configuration Options */ | |
33 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
34 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
35 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
36 | #define CONFIG_MPC8548 1 /* MPC8548 specific */ | |
37 | #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ | |
38 | ||
2ae18241 WD |
39 | #ifndef CONFIG_SYS_TEXT_BASE |
40 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
41 | #endif | |
42 | ||
8b47d7ec KG |
43 | #define CONFIG_SYS_SRIO |
44 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
45 | ||
f2cff6b1 ES |
46 | #define CONFIG_PCI /* enable any pci type devices */ |
47 | #define CONFIG_PCI1 /* PCI controller 1 */ | |
48 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ | |
f2cff6b1 ES |
49 | #undef CONFIG_PCI2 |
50 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
8ff3de61 | 51 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
0151cbac | 52 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
f2cff6b1 ES |
53 | |
54 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
d9b94f28 | 55 | #define CONFIG_ENV_OVERWRITE |
f2cff6b1 | 56 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
2cfaa1aa | 57 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
d9b94f28 | 58 | |
25eedb2c | 59 | #define CONFIG_FSL_VIA |
25eedb2c | 60 | |
d9b94f28 JL |
61 | #ifndef __ASSEMBLY__ |
62 | extern unsigned long get_clock_freq(void); | |
63 | #endif | |
64 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ | |
65 | ||
66 | /* | |
67 | * These can be toggled for performance analysis, otherwise use default. | |
68 | */ | |
f2cff6b1 ES |
69 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
70 | #define CONFIG_BTB /* toggle branch predition */ | |
d9b94f28 JL |
71 | |
72 | /* | |
73 | * Only possible on E500 Version 2 or newer cores. | |
74 | */ | |
75 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
76 | ||
6d0f6bcf JCPV |
77 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
78 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
d9b94f28 JL |
79 | |
80 | /* | |
81 | * Base addresses -- Note these are effective addresses where the | |
82 | * actual resources get mapped (not physical addresses) | |
83 | */ | |
6d0f6bcf JCPV |
84 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
85 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ | |
86 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
87 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
d9b94f28 | 88 | |
e31d2c1e JL |
89 | /* DDR Setup */ |
90 | #define CONFIG_FSL_DDR2 | |
91 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
92 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
93 | #define CONFIG_DDR_SPD | |
810c4427 | 94 | #define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ |
e31d2c1e | 95 | |
9b0ad1b1 | 96 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
e31d2c1e JL |
97 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
98 | ||
6d0f6bcf JCPV |
99 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
100 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
d9b94f28 | 101 | |
e31d2c1e JL |
102 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
103 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
104 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
d9b94f28 | 105 | |
e31d2c1e JL |
106 | /* I2C addresses of SPD EEPROMs */ |
107 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
108 | ||
109 | /* Make sure required options are set */ | |
d9b94f28 JL |
110 | #ifndef CONFIG_SPD_EEPROM |
111 | #error ("CONFIG_SPD_EEPROM is required") | |
112 | #endif | |
113 | ||
114 | #undef CONFIG_CLOCKS_IN_MHZ | |
115 | ||
d9b94f28 JL |
116 | /* |
117 | * Local Bus Definitions | |
118 | */ | |
119 | ||
120 | /* | |
121 | * FLASH on the Local Bus | |
122 | * Two banks, 8M each, using the CFI driver. | |
123 | * Boot from BR0/OR0 bank at 0xff00_0000 | |
124 | * Alternate BR1/OR1 bank at 0xff80_0000 | |
125 | * | |
126 | * BR0, BR1: | |
127 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 | |
128 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 | |
129 | * Port Size = 16 bits = BRx[19:20] = 10 | |
130 | * Use GPCM = BRx[24:26] = 000 | |
131 | * Valid = BRx[31] = 1 | |
132 | * | |
f2cff6b1 ES |
133 | * 0 4 8 12 16 20 24 28 |
134 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
135 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
d9b94f28 JL |
136 | * |
137 | * OR0, OR1: | |
138 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 | |
139 | * Reserved ORx[17:18] = 11, confusion here? | |
140 | * CSNT = ORx[20] = 1 | |
141 | * ACS = half cycle delay = ORx[21:22] = 11 | |
142 | * SCY = 6 = ORx[24:27] = 0110 | |
143 | * TRLX = use relaxed timing = ORx[29] = 1 | |
144 | * EAD = use external address latch delay = OR[31] = 1 | |
145 | * | |
f2cff6b1 ES |
146 | * 0 4 8 12 16 20 24 28 |
147 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
d9b94f28 JL |
148 | */ |
149 | ||
6d0f6bcf JCPV |
150 | #define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */ |
151 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ | |
d9b94f28 | 152 | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_BR0_PRELIM 0xff801001 |
154 | #define CONFIG_SYS_BR1_PRELIM 0xff001001 | |
d9b94f28 | 155 | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
157 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 | |
d9b94f28 | 158 | |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} |
160 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
161 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
162 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
163 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
164 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
d9b94f28 | 165 | |
14d0a02a | 166 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
d9b94f28 | 167 | |
00b1883a | 168 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_FLASH_CFI |
170 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
d9b94f28 JL |
171 | |
172 | ||
173 | /* | |
174 | * SDRAM on the Local Bus | |
175 | */ | |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ |
177 | #define CONFIG_SYS_LBC_CACHE_SIZE 64 | |
178 | #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */ | |
179 | #define CONFIG_SYS_LBC_NONCACHE_SIZE 64 | |
f2cff6b1 | 180 | |
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */ |
182 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
d9b94f28 JL |
183 | |
184 | /* | |
185 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 186 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
d9b94f28 JL |
187 | * |
188 | * For BR2, need: | |
189 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
190 | * port-size = 32-bits = BR2[19:20] = 11 | |
191 | * no parity checking = BR2[21:22] = 00 | |
192 | * SDRAM for MSEL = BR2[24:26] = 011 | |
193 | * Valid = BR[31] = 1 | |
194 | * | |
f2cff6b1 | 195 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
196 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
197 | * | |
6d0f6bcf | 198 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
d9b94f28 JL |
199 | * FIXME: the top 17 bits of BR2. |
200 | */ | |
201 | ||
6d0f6bcf | 202 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
d9b94f28 JL |
203 | |
204 | /* | |
6d0f6bcf | 205 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
d9b94f28 JL |
206 | * |
207 | * For OR2, need: | |
208 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
209 | * XAM, OR2[17:18] = 11 | |
210 | * 9 columns OR2[19-21] = 010 | |
f2cff6b1 | 211 | * 13 rows OR2[23-25] = 100 |
d9b94f28 JL |
212 | * EAD set for extra time OR[31] = 1 |
213 | * | |
f2cff6b1 | 214 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
215 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
216 | */ | |
217 | ||
6d0f6bcf | 218 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
d9b94f28 | 219 | |
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
221 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
222 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
223 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
d9b94f28 | 224 | |
d9b94f28 JL |
225 | /* |
226 | * Common settings for all Local Bus SDRAM commands. | |
227 | * At run time, either BSMA1516 (for CPU 1.1) | |
f2cff6b1 | 228 | * or BSMA1617 (for CPU 1.0) (old) |
d9b94f28 JL |
229 | * is OR'ed in too. |
230 | */ | |
b0fe93ed KG |
231 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
232 | | LSDMR_PRETOACT7 \ | |
233 | | LSDMR_ACTTORW7 \ | |
234 | | LSDMR_BL8 \ | |
235 | | LSDMR_WRC4 \ | |
236 | | LSDMR_CL3 \ | |
237 | | LSDMR_RFEN \ | |
d9b94f28 JL |
238 | ) |
239 | ||
240 | /* | |
241 | * The CADMUS registers are connected to CS3 on CDS. | |
242 | * The new memory map places CADMUS at 0xf8000000. | |
243 | * | |
244 | * For BR3, need: | |
245 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 | |
246 | * port-size = 8-bits = BR[19:20] = 01 | |
247 | * no parity checking = BR[21:22] = 00 | |
f2cff6b1 ES |
248 | * GPMC for MSEL = BR[24:26] = 000 |
249 | * Valid = BR[31] = 1 | |
d9b94f28 | 250 | * |
f2cff6b1 | 251 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
252 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 |
253 | * | |
254 | * For OR3, need: | |
f2cff6b1 | 255 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 |
d9b94f28 | 256 | * disable buffer ctrl OR[19] = 0 |
f2cff6b1 ES |
257 | * CSNT OR[20] = 1 |
258 | * ACS OR[21:22] = 11 | |
259 | * XACS OR[23] = 1 | |
d9b94f28 | 260 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe |
f2cff6b1 ES |
261 | * SETA OR[28] = 0 |
262 | * TRLX OR[29] = 1 | |
263 | * EHTR OR[30] = 1 | |
264 | * EAD extra time OR[31] = 1 | |
d9b94f28 | 265 | * |
f2cff6b1 | 266 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
267 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 |
268 | */ | |
269 | ||
25eedb2c JL |
270 | #define CONFIG_FSL_CADMUS |
271 | ||
d9b94f28 | 272 | #define CADMUS_BASE_ADDR 0xf8000000 |
6d0f6bcf JCPV |
273 | #define CONFIG_SYS_BR3_PRELIM 0xf8000801 |
274 | #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 | |
d9b94f28 | 275 | |
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
277 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 278 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
f2cff6b1 | 279 | |
6d0f6bcf | 280 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ |
d9b94f28 | 281 | |
25ddd1fb | 282 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 283 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
d9b94f28 | 284 | |
6d0f6bcf JCPV |
285 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
286 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
d9b94f28 JL |
287 | |
288 | /* Serial Port */ | |
f2cff6b1 | 289 | #define CONFIG_CONS_INDEX 2 |
6d0f6bcf JCPV |
290 | #define CONFIG_SYS_NS16550 |
291 | #define CONFIG_SYS_NS16550_SERIAL | |
292 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
293 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
d9b94f28 | 294 | |
6d0f6bcf | 295 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
d9b94f28 JL |
296 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
297 | ||
6d0f6bcf JCPV |
298 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
299 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
d9b94f28 JL |
300 | |
301 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_HUSH_PARSER |
303 | #ifdef CONFIG_SYS_HUSH_PARSER | |
304 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
d9b94f28 JL |
305 | #endif |
306 | ||
40d5fa35 | 307 | /* pass open firmware flat tree */ |
b90d2549 KG |
308 | #define CONFIG_OF_LIBFDT 1 |
309 | #define CONFIG_OF_BOARD_SETUP 1 | |
310 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
40d5fa35 | 311 | |
20476726 JL |
312 | /* |
313 | * I2C | |
314 | */ | |
315 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
316 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
f2cff6b1 | 317 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
6d0f6bcf JCPV |
318 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
319 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
320 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
321 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
d9b94f28 | 322 | |
e8d18541 TT |
323 | /* EEPROM */ |
324 | #define CONFIG_ID_EEPROM | |
6d0f6bcf JCPV |
325 | #define CONFIG_SYS_I2C_EEPROM_CCID |
326 | #define CONFIG_SYS_ID_EEPROM | |
327 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
328 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
e8d18541 | 329 | |
d9b94f28 JL |
330 | /* |
331 | * General PCI | |
362dd830 | 332 | * Memory space is mapped 1-1, but I/O space must start from 0. |
d9b94f28 | 333 | */ |
5af0fdd8 | 334 | #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ |
6d0f6bcf | 335 | #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ |
f2cff6b1 | 336 | |
5af0fdd8 | 337 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
10795f42 | 338 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 339 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
6d0f6bcf | 340 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 341 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 342 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
343 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
344 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
d9b94f28 | 345 | |
f2cff6b1 | 346 | #ifdef CONFIG_PCI2 |
5af0fdd8 | 347 | #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 |
10795f42 | 348 | #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 |
5af0fdd8 | 349 | #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 |
6d0f6bcf | 350 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 351 | #define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 |
5f91ef6a | 352 | #define CONFIG_SYS_PCI2_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
353 | #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 |
354 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
f2cff6b1 | 355 | #endif |
41fb7e0f | 356 | |
f2cff6b1 | 357 | #ifdef CONFIG_PCIE1 |
f5fa8f36 | 358 | #define CONFIG_SYS_PCIE1_NAME "Slot" |
5af0fdd8 | 359 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
10795f42 | 360 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
5af0fdd8 | 361 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
6d0f6bcf | 362 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 363 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 |
5f91ef6a | 364 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
365 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 |
366 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ | |
f2cff6b1 | 367 | #endif |
d9b94f28 | 368 | |
41fb7e0f ZR |
369 | /* |
370 | * RapidIO MMU | |
371 | */ | |
8b47d7ec KG |
372 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 |
373 | #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 | |
374 | #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS | |
375 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ | |
d9b94f28 | 376 | |
7f3f2bd2 RV |
377 | #ifdef CONFIG_LEGACY |
378 | #define BRIDGE_ID 17 | |
379 | #define VIA_ID 2 | |
380 | #else | |
381 | #define BRIDGE_ID 28 | |
382 | #define VIA_ID 4 | |
383 | #endif | |
384 | ||
d9b94f28 JL |
385 | #if defined(CONFIG_PCI) |
386 | ||
387 | #define CONFIG_NET_MULTI | |
f2cff6b1 | 388 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
d9b94f28 JL |
389 | |
390 | #undef CONFIG_EEPRO100 | |
391 | #undef CONFIG_TULIP | |
392 | ||
d9b94f28 | 393 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
f2cff6b1 | 394 | |
d9b94f28 JL |
395 | #endif /* CONFIG_PCI */ |
396 | ||
397 | ||
398 | #if defined(CONFIG_TSEC_ENET) | |
399 | ||
400 | #ifndef CONFIG_NET_MULTI | |
f2cff6b1 | 401 | #define CONFIG_NET_MULTI 1 |
d9b94f28 JL |
402 | #endif |
403 | ||
404 | #define CONFIG_MII 1 /* MII PHY management */ | |
255a3577 KP |
405 | #define CONFIG_TSEC1 1 |
406 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
407 | #define CONFIG_TSEC2 1 | |
408 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
409 | #define CONFIG_TSEC3 1 | |
410 | #define CONFIG_TSEC3_NAME "eTSEC2" | |
f2cff6b1 | 411 | #define CONFIG_TSEC4 |
255a3577 | 412 | #define CONFIG_TSEC4_NAME "eTSEC3" |
d9b94f28 JL |
413 | #undef CONFIG_MPC85XX_FEC |
414 | ||
415 | #define TSEC1_PHY_ADDR 0 | |
416 | #define TSEC2_PHY_ADDR 1 | |
417 | #define TSEC3_PHY_ADDR 2 | |
418 | #define TSEC4_PHY_ADDR 3 | |
d9b94f28 JL |
419 | |
420 | #define TSEC1_PHYIDX 0 | |
421 | #define TSEC2_PHYIDX 0 | |
422 | #define TSEC3_PHYIDX 0 | |
423 | #define TSEC4_PHYIDX 0 | |
3a79013e AF |
424 | #define TSEC1_FLAGS TSEC_GIGABIT |
425 | #define TSEC2_FLAGS TSEC_GIGABIT | |
426 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
427 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
d9b94f28 JL |
428 | |
429 | /* Options are: eTSEC[0-3] */ | |
430 | #define CONFIG_ETHPRIME "eTSEC0" | |
f2cff6b1 | 431 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
d9b94f28 JL |
432 | #endif /* CONFIG_TSEC_ENET */ |
433 | ||
434 | /* | |
435 | * Environment | |
436 | */ | |
5a1aceb0 | 437 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 438 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 JCPV |
439 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
440 | #define CONFIG_ENV_SIZE 0x2000 | |
d9b94f28 JL |
441 | |
442 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 443 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
d9b94f28 | 444 | |
659e2f67 JL |
445 | /* |
446 | * BOOTP options | |
447 | */ | |
448 | #define CONFIG_BOOTP_BOOTFILESIZE | |
449 | #define CONFIG_BOOTP_BOOTPATH | |
450 | #define CONFIG_BOOTP_GATEWAY | |
451 | #define CONFIG_BOOTP_HOSTNAME | |
452 | ||
453 | ||
2835e518 JL |
454 | /* |
455 | * Command line configuration. | |
456 | */ | |
457 | #include <config_cmd_default.h> | |
458 | ||
459 | #define CONFIG_CMD_PING | |
460 | #define CONFIG_CMD_I2C | |
461 | #define CONFIG_CMD_MII | |
82ac8c97 | 462 | #define CONFIG_CMD_ELF |
1c9aa76b KG |
463 | #define CONFIG_CMD_IRQ |
464 | #define CONFIG_CMD_SETEXPR | |
199e262e | 465 | #define CONFIG_CMD_REGINFO |
2835e518 | 466 | |
d9b94f28 | 467 | #if defined(CONFIG_PCI) |
2835e518 | 468 | #define CONFIG_CMD_PCI |
d9b94f28 | 469 | #endif |
2835e518 | 470 | |
d9b94f28 JL |
471 | |
472 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
473 | ||
474 | /* | |
475 | * Miscellaneous configurable options | |
476 | */ | |
6d0f6bcf | 477 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
478 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
479 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf JCPV |
480 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
481 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
2835e518 | 482 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 483 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
d9b94f28 | 484 | #else |
6d0f6bcf | 485 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
d9b94f28 | 486 | #endif |
6d0f6bcf JCPV |
487 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
488 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
489 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
490 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
d9b94f28 JL |
491 | |
492 | /* | |
493 | * For booting Linux, the board info and command line data | |
89188a62 | 494 | * have to be in the first 16 MB of memory, since this is |
d9b94f28 JL |
495 | * the maximum mapped by the Linux kernel during initialization. |
496 | */ | |
89188a62 | 497 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ |
7c57f3e8 | 498 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ |
d9b94f28 | 499 | |
2835e518 | 500 | #if defined(CONFIG_CMD_KGDB) |
d9b94f28 JL |
501 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
502 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
503 | #endif | |
504 | ||
505 | /* | |
506 | * Environment Configuration | |
507 | */ | |
508 | ||
509 | /* The mac addresses for all ethernet interface */ | |
510 | #if defined(CONFIG_TSEC_ENET) | |
10327dc5 | 511 | #define CONFIG_HAS_ETH0 |
f2cff6b1 | 512 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
d9b94f28 | 513 | #define CONFIG_HAS_ETH1 |
f2cff6b1 | 514 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
d9b94f28 | 515 | #define CONFIG_HAS_ETH2 |
f2cff6b1 | 516 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
09f3e09e | 517 | #define CONFIG_HAS_ETH3 |
f2cff6b1 | 518 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD |
d9b94f28 JL |
519 | #endif |
520 | ||
f2cff6b1 | 521 | #define CONFIG_IPADDR 192.168.1.253 |
d9b94f28 | 522 | |
f2cff6b1 ES |
523 | #define CONFIG_HOSTNAME unknown |
524 | #define CONFIG_ROOTPATH /nfsroot | |
525 | #define CONFIG_BOOTFILE 8548cds/uImage.uboot | |
526 | #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ | |
d9b94f28 | 527 | |
f2cff6b1 | 528 | #define CONFIG_SERVERIP 192.168.1.1 |
d9b94f28 | 529 | #define CONFIG_GATEWAYIP 192.168.1.1 |
f2cff6b1 | 530 | #define CONFIG_NETMASK 255.255.255.0 |
d9b94f28 | 531 | |
f2cff6b1 | 532 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
d9b94f28 | 533 | |
f2cff6b1 ES |
534 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
535 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
d9b94f28 JL |
536 | |
537 | #define CONFIG_BAUDRATE 115200 | |
538 | ||
f2cff6b1 ES |
539 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
540 | "netdev=eth0\0" \ | |
541 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
542 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
14d0a02a WD |
543 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
544 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
545 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
546 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
547 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
f2cff6b1 ES |
548 | "consoledev=ttyS1\0" \ |
549 | "ramdiskaddr=2000000\0" \ | |
6c543597 | 550 | "ramdiskfile=ramdisk.uboot\0" \ |
4bf4abb8 | 551 | "fdtaddr=c00000\0" \ |
22abb2d2 | 552 | "fdtfile=mpc8548cds.dtb\0" |
f2cff6b1 ES |
553 | |
554 | #define CONFIG_NFSBOOTCOMMAND \ | |
555 | "setenv bootargs root=/dev/nfs rw " \ | |
556 | "nfsroot=$serverip:$rootpath " \ | |
d9b94f28 | 557 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
f2cff6b1 ES |
558 | "console=$consoledev,$baudrate $othbootargs;" \ |
559 | "tftp $loadaddr $bootfile;" \ | |
4bf4abb8 ES |
560 | "tftp $fdtaddr $fdtfile;" \ |
561 | "bootm $loadaddr - $fdtaddr" | |
8272dc2f | 562 | |
d9b94f28 JL |
563 | |
564 | #define CONFIG_RAMBOOTCOMMAND \ | |
f2cff6b1 ES |
565 | "setenv bootargs root=/dev/ram rw " \ |
566 | "console=$consoledev,$baudrate $othbootargs;" \ | |
567 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
568 | "tftp $loadaddr $bootfile;" \ | |
4bf4abb8 ES |
569 | "tftp $fdtaddr $fdtfile;" \ |
570 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
f2cff6b1 ES |
571 | |
572 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
d9b94f28 JL |
573 | |
574 | #endif /* __CONFIG_H */ |