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d9b94f28 | 1 | /* |
8b47d7ec | 2 | * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. |
d9b94f28 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
d9b94f28 JL |
5 | */ |
6 | ||
7 | /* | |
8 | * mpc8548cds board configuration file | |
9 | * | |
10 | * Please refer to doc/README.mpc85xxcds for more info. | |
11 | * | |
12 | */ | |
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
9ae14ca2 YS |
16 | #define CONFIG_SYS_GENERIC_BOARD |
17 | #define CONFIG_DISPLAY_BOARDINFO | |
18 | ||
b76aef60 | 19 | #ifdef CONFIG_36BIT |
20 | #define CONFIG_PHYS_64BIT | |
21 | #endif | |
22 | ||
d9b94f28 JL |
23 | /* High Level Configuration Options */ |
24 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
25 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
d9b94f28 JL |
26 | #define CONFIG_MPC8548 1 /* MPC8548 specific */ |
27 | #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ | |
28 | ||
2ae18241 WD |
29 | #ifndef CONFIG_SYS_TEXT_BASE |
30 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
31 | #endif | |
32 | ||
8b47d7ec KG |
33 | #define CONFIG_SYS_SRIO |
34 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
35 | ||
f2cff6b1 ES |
36 | #define CONFIG_PCI /* enable any pci type devices */ |
37 | #define CONFIG_PCI1 /* PCI controller 1 */ | |
38 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ | |
f2cff6b1 ES |
39 | #undef CONFIG_PCI2 |
40 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
842033e6 | 41 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
8ff3de61 | 42 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
0151cbac | 43 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
f2cff6b1 ES |
44 | |
45 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
d9b94f28 | 46 | #define CONFIG_ENV_OVERWRITE |
f2cff6b1 | 47 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
2cfaa1aa | 48 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
d9b94f28 | 49 | |
25eedb2c | 50 | #define CONFIG_FSL_VIA |
25eedb2c | 51 | |
d9b94f28 JL |
52 | #ifndef __ASSEMBLY__ |
53 | extern unsigned long get_clock_freq(void); | |
54 | #endif | |
55 | #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ | |
56 | ||
57 | /* | |
58 | * These can be toggled for performance analysis, otherwise use default. | |
59 | */ | |
f2cff6b1 ES |
60 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
61 | #define CONFIG_BTB /* toggle branch predition */ | |
d9b94f28 JL |
62 | |
63 | /* | |
64 | * Only possible on E500 Version 2 or newer cores. | |
65 | */ | |
66 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
67 | ||
b76aef60 | 68 | #ifdef CONFIG_PHYS_64BIT |
69 | #define CONFIG_ADDR_MAP | |
70 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
71 | #endif | |
72 | ||
6d0f6bcf JCPV |
73 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
74 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
d9b94f28 | 75 | |
e46fedfe TT |
76 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
77 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
d9b94f28 | 78 | |
e31d2c1e | 79 | /* DDR Setup */ |
5614e71b | 80 | #define CONFIG_SYS_FSL_DDR2 |
e31d2c1e JL |
81 | #undef CONFIG_FSL_DDR_INTERACTIVE |
82 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
83 | #define CONFIG_DDR_SPD | |
e31d2c1e | 84 | |
867b06f4 | 85 | #define CONFIG_DDR_ECC |
9b0ad1b1 | 86 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
e31d2c1e JL |
87 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
88 | ||
6d0f6bcf JCPV |
89 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
90 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
d9b94f28 | 91 | |
e31d2c1e JL |
92 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
93 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
94 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
d9b94f28 | 95 | |
e31d2c1e JL |
96 | /* I2C addresses of SPD EEPROMs */ |
97 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
98 | ||
99 | /* Make sure required options are set */ | |
d9b94f28 JL |
100 | #ifndef CONFIG_SPD_EEPROM |
101 | #error ("CONFIG_SPD_EEPROM is required") | |
102 | #endif | |
103 | ||
104 | #undef CONFIG_CLOCKS_IN_MHZ | |
fff80975 | 105 | /* |
106 | * Physical Address Map | |
107 | * | |
108 | * 32bit: | |
109 | * 0x0000_0000 0x7fff_ffff DDR 2G cacheable | |
110 | * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable | |
111 | * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable | |
112 | * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable | |
113 | * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable | |
114 | * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable | |
115 | * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable | |
116 | * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable | |
117 | * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable | |
118 | * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable | |
119 | * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable | |
120 | * | |
b76aef60 | 121 | * 36bit: |
122 | * 0x00000_0000 0x07fff_ffff DDR 2G cacheable | |
123 | * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable | |
124 | * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable | |
125 | * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable | |
126 | * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable | |
127 | * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable | |
128 | * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable | |
129 | * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable | |
130 | * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable | |
131 | * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable | |
132 | * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable | |
133 | * | |
fff80975 | 134 | */ |
135 | ||
d9b94f28 | 136 | |
d9b94f28 JL |
137 | /* |
138 | * Local Bus Definitions | |
139 | */ | |
140 | ||
141 | /* | |
142 | * FLASH on the Local Bus | |
143 | * Two banks, 8M each, using the CFI driver. | |
144 | * Boot from BR0/OR0 bank at 0xff00_0000 | |
145 | * Alternate BR1/OR1 bank at 0xff80_0000 | |
146 | * | |
147 | * BR0, BR1: | |
148 | * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 | |
149 | * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 | |
150 | * Port Size = 16 bits = BRx[19:20] = 10 | |
151 | * Use GPCM = BRx[24:26] = 000 | |
152 | * Valid = BRx[31] = 1 | |
153 | * | |
f2cff6b1 ES |
154 | * 0 4 8 12 16 20 24 28 |
155 | * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 | |
156 | * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 | |
d9b94f28 JL |
157 | * |
158 | * OR0, OR1: | |
159 | * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 | |
160 | * Reserved ORx[17:18] = 11, confusion here? | |
161 | * CSNT = ORx[20] = 1 | |
162 | * ACS = half cycle delay = ORx[21:22] = 11 | |
163 | * SCY = 6 = ORx[24:27] = 0110 | |
164 | * TRLX = use relaxed timing = ORx[29] = 1 | |
165 | * EAD = use external address latch delay = OR[31] = 1 | |
166 | * | |
f2cff6b1 ES |
167 | * 0 4 8 12 16 20 24 28 |
168 | * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx | |
d9b94f28 JL |
169 | */ |
170 | ||
fff80975 | 171 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
b76aef60 | 172 | #ifdef CONFIG_PHYS_64BIT |
173 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull | |
174 | #else | |
fff80975 | 175 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
b76aef60 | 176 | #endif |
d9b94f28 | 177 | |
fff80975 | 178 | #define CONFIG_SYS_BR0_PRELIM \ |
7ee41107 | 179 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) |
fff80975 | 180 | #define CONFIG_SYS_BR1_PRELIM \ |
181 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) | |
d9b94f28 | 182 | |
6d0f6bcf JCPV |
183 | #define CONFIG_SYS_OR0_PRELIM 0xff806e65 |
184 | #define CONFIG_SYS_OR1_PRELIM 0xff806e65 | |
d9b94f28 | 185 | |
fff80975 | 186 | #define CONFIG_SYS_FLASH_BANKS_LIST \ |
187 | {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
189 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
190 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
191 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
192 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
d9b94f28 | 193 | |
14d0a02a | 194 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
d9b94f28 | 195 | |
00b1883a | 196 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_FLASH_CFI |
198 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
d9b94f28 | 199 | |
867b06f4 | 200 | #define CONFIG_HWCONFIG /* enable hwconfig */ |
d9b94f28 JL |
201 | |
202 | /* | |
203 | * SDRAM on the Local Bus | |
204 | */ | |
fff80975 | 205 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
b76aef60 | 206 | #ifdef CONFIG_PHYS_64BIT |
207 | #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull | |
208 | #else | |
fff80975 | 209 | #define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE |
b76aef60 | 210 | #endif |
6d0f6bcf | 211 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
d9b94f28 JL |
212 | |
213 | /* | |
214 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 215 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
d9b94f28 JL |
216 | * |
217 | * For BR2, need: | |
218 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
219 | * port-size = 32-bits = BR2[19:20] = 11 | |
220 | * no parity checking = BR2[21:22] = 00 | |
221 | * SDRAM for MSEL = BR2[24:26] = 011 | |
222 | * Valid = BR[31] = 1 | |
223 | * | |
f2cff6b1 | 224 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
225 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
226 | * | |
6d0f6bcf | 227 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
d9b94f28 JL |
228 | * FIXME: the top 17 bits of BR2. |
229 | */ | |
230 | ||
fff80975 | 231 | #define CONFIG_SYS_BR2_PRELIM \ |
232 | (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ | |
233 | | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V) | |
d9b94f28 JL |
234 | |
235 | /* | |
6d0f6bcf | 236 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
d9b94f28 JL |
237 | * |
238 | * For OR2, need: | |
239 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
240 | * XAM, OR2[17:18] = 11 | |
241 | * 9 columns OR2[19-21] = 010 | |
f2cff6b1 | 242 | * 13 rows OR2[23-25] = 100 |
d9b94f28 JL |
243 | * EAD set for extra time OR[31] = 1 |
244 | * | |
f2cff6b1 | 245 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
246 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
247 | */ | |
248 | ||
6d0f6bcf | 249 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
d9b94f28 | 250 | |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
252 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
253 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
254 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
d9b94f28 | 255 | |
d9b94f28 JL |
256 | /* |
257 | * Common settings for all Local Bus SDRAM commands. | |
258 | * At run time, either BSMA1516 (for CPU 1.1) | |
f2cff6b1 | 259 | * or BSMA1617 (for CPU 1.0) (old) |
d9b94f28 JL |
260 | * is OR'ed in too. |
261 | */ | |
b0fe93ed KG |
262 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ |
263 | | LSDMR_PRETOACT7 \ | |
264 | | LSDMR_ACTTORW7 \ | |
265 | | LSDMR_BL8 \ | |
266 | | LSDMR_WRC4 \ | |
267 | | LSDMR_CL3 \ | |
268 | | LSDMR_RFEN \ | |
d9b94f28 JL |
269 | ) |
270 | ||
271 | /* | |
272 | * The CADMUS registers are connected to CS3 on CDS. | |
273 | * The new memory map places CADMUS at 0xf8000000. | |
274 | * | |
275 | * For BR3, need: | |
276 | * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 | |
277 | * port-size = 8-bits = BR[19:20] = 01 | |
278 | * no parity checking = BR[21:22] = 00 | |
f2cff6b1 ES |
279 | * GPMC for MSEL = BR[24:26] = 000 |
280 | * Valid = BR[31] = 1 | |
d9b94f28 | 281 | * |
f2cff6b1 | 282 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
283 | * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 |
284 | * | |
285 | * For OR3, need: | |
f2cff6b1 | 286 | * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 |
d9b94f28 | 287 | * disable buffer ctrl OR[19] = 0 |
f2cff6b1 ES |
288 | * CSNT OR[20] = 1 |
289 | * ACS OR[21:22] = 11 | |
290 | * XACS OR[23] = 1 | |
d9b94f28 | 291 | * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe |
f2cff6b1 ES |
292 | * SETA OR[28] = 0 |
293 | * TRLX OR[29] = 1 | |
294 | * EHTR OR[30] = 1 | |
295 | * EAD extra time OR[31] = 1 | |
d9b94f28 | 296 | * |
f2cff6b1 | 297 | * 0 4 8 12 16 20 24 28 |
d9b94f28 JL |
298 | * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 |
299 | */ | |
300 | ||
25eedb2c JL |
301 | #define CONFIG_FSL_CADMUS |
302 | ||
d9b94f28 | 303 | #define CADMUS_BASE_ADDR 0xf8000000 |
b76aef60 | 304 | #ifdef CONFIG_PHYS_64BIT |
305 | #define CADMUS_BASE_ADDR_PHYS 0xff8000000ull | |
306 | #else | |
fff80975 | 307 | #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR |
b76aef60 | 308 | #endif |
fff80975 | 309 | #define CONFIG_SYS_BR3_PRELIM \ |
310 | (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V) | |
6d0f6bcf | 311 | #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 |
d9b94f28 | 312 | |
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
314 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 315 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
f2cff6b1 | 316 | |
25ddd1fb | 317 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 318 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
d9b94f28 | 319 | |
6d0f6bcf | 320 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
867b06f4 | 321 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
d9b94f28 JL |
322 | |
323 | /* Serial Port */ | |
f2cff6b1 | 324 | #define CONFIG_CONS_INDEX 2 |
6d0f6bcf JCPV |
325 | #define CONFIG_SYS_NS16550 |
326 | #define CONFIG_SYS_NS16550_SERIAL | |
327 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
328 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
d9b94f28 | 329 | |
6d0f6bcf | 330 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
d9b94f28 JL |
331 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
332 | ||
6d0f6bcf JCPV |
333 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
334 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
d9b94f28 JL |
335 | |
336 | /* Use the HUSH parser */ | |
6d0f6bcf | 337 | #define CONFIG_SYS_HUSH_PARSER |
d9b94f28 | 338 | |
40d5fa35 | 339 | /* pass open firmware flat tree */ |
b90d2549 KG |
340 | #define CONFIG_OF_LIBFDT 1 |
341 | #define CONFIG_OF_BOARD_SETUP 1 | |
342 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
40d5fa35 | 343 | |
20476726 JL |
344 | /* |
345 | * I2C | |
346 | */ | |
00f792e0 HS |
347 | #define CONFIG_SYS_I2C |
348 | #define CONFIG_SYS_I2C_FSL | |
349 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
350 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
351 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
352 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
d9b94f28 | 353 | |
e8d18541 TT |
354 | /* EEPROM */ |
355 | #define CONFIG_ID_EEPROM | |
6d0f6bcf JCPV |
356 | #define CONFIG_SYS_I2C_EEPROM_CCID |
357 | #define CONFIG_SYS_ID_EEPROM | |
358 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
359 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
e8d18541 | 360 | |
d9b94f28 JL |
361 | /* |
362 | * General PCI | |
362dd830 | 363 | * Memory space is mapped 1-1, but I/O space must start from 0. |
d9b94f28 | 364 | */ |
5af0fdd8 | 365 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
b76aef60 | 366 | #ifdef CONFIG_PHYS_64BIT |
367 | #define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000 | |
368 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull | |
369 | #else | |
10795f42 | 370 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 371 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
b76aef60 | 372 | #endif |
6d0f6bcf | 373 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 374 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 375 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
b76aef60 | 376 | #ifdef CONFIG_PHYS_64BIT |
377 | #define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull | |
378 | #else | |
6d0f6bcf | 379 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
b76aef60 | 380 | #endif |
6d0f6bcf | 381 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ |
d9b94f28 | 382 | |
f2cff6b1 | 383 | #ifdef CONFIG_PCIE1 |
f5fa8f36 | 384 | #define CONFIG_SYS_PCIE1_NAME "Slot" |
5af0fdd8 | 385 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
b76aef60 | 386 | #ifdef CONFIG_PHYS_64BIT |
387 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
388 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull | |
389 | #else | |
10795f42 | 390 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
5af0fdd8 | 391 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 |
b76aef60 | 392 | #endif |
6d0f6bcf | 393 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 394 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 |
5f91ef6a | 395 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
b76aef60 | 396 | #ifdef CONFIG_PHYS_64BIT |
397 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull | |
398 | #else | |
6d0f6bcf | 399 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 |
b76aef60 | 400 | #endif |
6d0f6bcf | 401 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ |
f2cff6b1 | 402 | #endif |
d9b94f28 | 403 | |
41fb7e0f ZR |
404 | /* |
405 | * RapidIO MMU | |
406 | */ | |
fff80975 | 407 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 |
b76aef60 | 408 | #ifdef CONFIG_PHYS_64BIT |
409 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull | |
410 | #else | |
fff80975 | 411 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000 |
b76aef60 | 412 | #endif |
8b47d7ec | 413 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ |
d9b94f28 | 414 | |
7f3f2bd2 RV |
415 | #ifdef CONFIG_LEGACY |
416 | #define BRIDGE_ID 17 | |
417 | #define VIA_ID 2 | |
418 | #else | |
419 | #define BRIDGE_ID 28 | |
420 | #define VIA_ID 4 | |
421 | #endif | |
422 | ||
d9b94f28 JL |
423 | #if defined(CONFIG_PCI) |
424 | ||
f2cff6b1 | 425 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
d9b94f28 JL |
426 | |
427 | #undef CONFIG_EEPRO100 | |
428 | #undef CONFIG_TULIP | |
429 | ||
867b06f4 | 430 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
f2cff6b1 | 431 | |
d9b94f28 JL |
432 | #endif /* CONFIG_PCI */ |
433 | ||
434 | ||
435 | #if defined(CONFIG_TSEC_ENET) | |
436 | ||
d9b94f28 | 437 | #define CONFIG_MII 1 /* MII PHY management */ |
255a3577 KP |
438 | #define CONFIG_TSEC1 1 |
439 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
440 | #define CONFIG_TSEC2 1 | |
441 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
442 | #define CONFIG_TSEC3 1 | |
443 | #define CONFIG_TSEC3_NAME "eTSEC2" | |
f2cff6b1 | 444 | #define CONFIG_TSEC4 |
255a3577 | 445 | #define CONFIG_TSEC4_NAME "eTSEC3" |
d9b94f28 JL |
446 | #undef CONFIG_MPC85XX_FEC |
447 | ||
d3701228 | 448 | #define CONFIG_PHY_MARVELL |
449 | ||
d9b94f28 JL |
450 | #define TSEC1_PHY_ADDR 0 |
451 | #define TSEC2_PHY_ADDR 1 | |
452 | #define TSEC3_PHY_ADDR 2 | |
453 | #define TSEC4_PHY_ADDR 3 | |
d9b94f28 JL |
454 | |
455 | #define TSEC1_PHYIDX 0 | |
456 | #define TSEC2_PHYIDX 0 | |
457 | #define TSEC3_PHYIDX 0 | |
458 | #define TSEC4_PHYIDX 0 | |
3a79013e AF |
459 | #define TSEC1_FLAGS TSEC_GIGABIT |
460 | #define TSEC2_FLAGS TSEC_GIGABIT | |
461 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
462 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
d9b94f28 JL |
463 | |
464 | /* Options are: eTSEC[0-3] */ | |
465 | #define CONFIG_ETHPRIME "eTSEC0" | |
f2cff6b1 | 466 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
d9b94f28 JL |
467 | #endif /* CONFIG_TSEC_ENET */ |
468 | ||
469 | /* | |
470 | * Environment | |
471 | */ | |
5a1aceb0 | 472 | #define CONFIG_ENV_IS_IN_FLASH 1 |
867b06f4 | 473 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
474 | #define CONFIG_ENV_ADDR 0xfff80000 | |
475 | #else | |
476 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
477 | #endif | |
478 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ | |
0e8d1586 | 479 | #define CONFIG_ENV_SIZE 0x2000 |
d9b94f28 JL |
480 | |
481 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 482 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
d9b94f28 | 483 | |
659e2f67 JL |
484 | /* |
485 | * BOOTP options | |
486 | */ | |
487 | #define CONFIG_BOOTP_BOOTFILESIZE | |
488 | #define CONFIG_BOOTP_BOOTPATH | |
489 | #define CONFIG_BOOTP_GATEWAY | |
490 | #define CONFIG_BOOTP_HOSTNAME | |
491 | ||
492 | ||
2835e518 JL |
493 | /* |
494 | * Command line configuration. | |
495 | */ | |
2835e518 JL |
496 | #define CONFIG_CMD_PING |
497 | #define CONFIG_CMD_I2C | |
498 | #define CONFIG_CMD_MII | |
82ac8c97 | 499 | #define CONFIG_CMD_ELF |
1c9aa76b | 500 | #define CONFIG_CMD_IRQ |
199e262e | 501 | #define CONFIG_CMD_REGINFO |
2835e518 | 502 | |
d9b94f28 | 503 | #if defined(CONFIG_PCI) |
2835e518 | 504 | #define CONFIG_CMD_PCI |
d9b94f28 | 505 | #endif |
2835e518 | 506 | |
d9b94f28 JL |
507 | |
508 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
509 | ||
510 | /* | |
511 | * Miscellaneous configurable options | |
512 | */ | |
6d0f6bcf | 513 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
514 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
515 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf | 516 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
2835e518 | 517 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 518 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
d9b94f28 | 519 | #else |
6d0f6bcf | 520 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
d9b94f28 | 521 | #endif |
6d0f6bcf JCPV |
522 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
523 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
524 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
d9b94f28 JL |
525 | |
526 | /* | |
527 | * For booting Linux, the board info and command line data | |
a832ac41 | 528 | * have to be in the first 64 MB of memory, since this is |
d9b94f28 JL |
529 | * the maximum mapped by the Linux kernel during initialization. |
530 | */ | |
a832ac41 KG |
531 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
532 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
d9b94f28 | 533 | |
2835e518 | 534 | #if defined(CONFIG_CMD_KGDB) |
d9b94f28 | 535 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
d9b94f28 JL |
536 | #endif |
537 | ||
538 | /* | |
539 | * Environment Configuration | |
540 | */ | |
d9b94f28 | 541 | #if defined(CONFIG_TSEC_ENET) |
10327dc5 | 542 | #define CONFIG_HAS_ETH0 |
d9b94f28 | 543 | #define CONFIG_HAS_ETH1 |
d9b94f28 | 544 | #define CONFIG_HAS_ETH2 |
09f3e09e | 545 | #define CONFIG_HAS_ETH3 |
d9b94f28 JL |
546 | #endif |
547 | ||
f2cff6b1 | 548 | #define CONFIG_IPADDR 192.168.1.253 |
d9b94f28 | 549 | |
f2cff6b1 | 550 | #define CONFIG_HOSTNAME unknown |
8b3637c6 | 551 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 552 | #define CONFIG_BOOTFILE "8548cds/uImage.uboot" |
f2cff6b1 | 553 | #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ |
d9b94f28 | 554 | |
f2cff6b1 | 555 | #define CONFIG_SERVERIP 192.168.1.1 |
d9b94f28 | 556 | #define CONFIG_GATEWAYIP 192.168.1.1 |
f2cff6b1 | 557 | #define CONFIG_NETMASK 255.255.255.0 |
d9b94f28 | 558 | |
f2cff6b1 | 559 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ |
d9b94f28 | 560 | |
f2cff6b1 ES |
561 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
562 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
d9b94f28 JL |
563 | |
564 | #define CONFIG_BAUDRATE 115200 | |
565 | ||
867b06f4 | 566 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
567 | "hwconfig=fsl_ddr:ecc=off\0" \ | |
568 | "netdev=eth0\0" \ | |
5368c55d | 569 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
867b06f4 | 570 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
5368c55d MV |
571 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
572 | " +$filesize; " \ | |
573 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
574 | " +$filesize; " \ | |
575 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
576 | " $filesize; " \ | |
577 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
578 | " +$filesize; " \ | |
579 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
580 | " $filesize\0" \ | |
867b06f4 | 581 | "consoledev=ttyS1\0" \ |
582 | "ramdiskaddr=2000000\0" \ | |
583 | "ramdiskfile=ramdisk.uboot\0" \ | |
584 | "fdtaddr=c00000\0" \ | |
585 | "fdtfile=mpc8548cds.dtb\0" | |
f2cff6b1 ES |
586 | |
587 | #define CONFIG_NFSBOOTCOMMAND \ | |
588 | "setenv bootargs root=/dev/nfs rw " \ | |
589 | "nfsroot=$serverip:$rootpath " \ | |
d9b94f28 | 590 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
f2cff6b1 ES |
591 | "console=$consoledev,$baudrate $othbootargs;" \ |
592 | "tftp $loadaddr $bootfile;" \ | |
4bf4abb8 ES |
593 | "tftp $fdtaddr $fdtfile;" \ |
594 | "bootm $loadaddr - $fdtaddr" | |
8272dc2f | 595 | |
d9b94f28 JL |
596 | |
597 | #define CONFIG_RAMBOOTCOMMAND \ | |
f2cff6b1 ES |
598 | "setenv bootargs root=/dev/ram rw " \ |
599 | "console=$consoledev,$baudrate $othbootargs;" \ | |
600 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
601 | "tftp $loadaddr $bootfile;" \ | |
4bf4abb8 ES |
602 | "tftp $fdtaddr $fdtfile;" \ |
603 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
f2cff6b1 ES |
604 | |
605 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
d9b94f28 JL |
606 | |
607 | #endif /* __CONFIG_H */ |