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42d1f039 | 1 | /* |
0ac6f8b7 | 2 | * Copyright 2004 Freescale Semiconductor. |
42d1f039 WD |
3 | * (C) Copyright 2002,2003 Motorola,Inc. |
4 | * Xianghua Xiao <X.Xiao@motorola.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
0ac6f8b7 WD |
25 | /* |
26 | * mpc8560ads board configuration file | |
27 | * | |
28 | * Please refer to doc/README.mpc85xx for more info. | |
29 | * | |
30 | * Make sure you change the MAC address and other network params first, | |
31 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. | |
42d1f039 WD |
32 | */ |
33 | ||
34 | #ifndef __CONFIG_H | |
35 | #define __CONFIG_H | |
36 | ||
37 | /* High Level Configuration Options */ | |
0ac6f8b7 WD |
38 | #define CONFIG_BOOKE 1 /* BOOKE */ |
39 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
40 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ | |
9c4c5ae3 | 41 | #define CONFIG_CPM2 1 /* has CPM2 */ |
0ac6f8b7 | 42 | #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ |
f060054d | 43 | #define CONFIG_MPC8560 1 |
0ac6f8b7 WD |
44 | |
45 | #define CONFIG_PCI | |
0151cbac | 46 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
53677ef1 | 47 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
ccc091aa | 48 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ |
42d1f039 | 49 | #define CONFIG_ENV_OVERWRITE |
7232a272 | 50 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
004eca0c | 51 | #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ |
42d1f039 | 52 | |
0ac6f8b7 WD |
53 | /* |
54 | * sysclk for MPC85xx | |
55 | * | |
56 | * Two valid values are: | |
57 | * 33000000 | |
58 | * 66000000 | |
59 | * | |
60 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
9aea9530 WD |
61 | * is likely the desired value here, so that is now the default. |
62 | * The board, however, can run at 66MHz. In any event, this value | |
63 | * must match the settings of some switches. Details can be found | |
64 | * in the README.mpc85xxads. | |
0ac6f8b7 WD |
65 | */ |
66 | ||
9aea9530 WD |
67 | #ifndef CONFIG_SYS_CLK_FREQ |
68 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
42d1f039 WD |
69 | #endif |
70 | ||
9aea9530 | 71 | |
0ac6f8b7 WD |
72 | /* |
73 | * These can be toggled for performance analysis, otherwise use default. | |
74 | */ | |
75 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
76 | #define CONFIG_BTB /* toggle branch predition */ | |
42d1f039 | 77 | |
6d0f6bcf | 78 | #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ |
0ac6f8b7 | 79 | |
6d0f6bcf JCPV |
80 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
81 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
42d1f039 | 82 | |
42d1f039 WD |
83 | |
84 | /* | |
85 | * Base addresses -- Note these are effective addresses where the | |
86 | * actual resources get mapped (not physical addresses) | |
87 | */ | |
6d0f6bcf JCPV |
88 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
89 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ | |
90 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
91 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
42d1f039 | 92 | |
8b625114 JL |
93 | /* DDR Setup */ |
94 | #define CONFIG_FSL_DDR1 | |
95 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
96 | #define CONFIG_DDR_SPD | |
97 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
98 | ||
99 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
9aea9530 | 100 | |
6d0f6bcf JCPV |
101 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
102 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
9aea9530 | 103 | |
8b625114 JL |
104 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
105 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
106 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
9aea9530 | 107 | |
8b625114 JL |
108 | /* I2C addresses of SPD EEPROMs */ |
109 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
9aea9530 | 110 | |
8b625114 | 111 | /* These are used when DDR doesn't use SPD. */ |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ |
113 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ | |
114 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 | |
115 | #define CONFIG_SYS_DDR_TIMING_1 0x37344321 | |
116 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
117 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ | |
118 | #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ | |
119 | #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ | |
42d1f039 | 120 | |
0ac6f8b7 WD |
121 | /* |
122 | * SDRAM on the Local Bus | |
123 | */ | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
125 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
42d1f039 | 126 | |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
128 | #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ | |
42d1f039 | 129 | |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ |
131 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
132 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ | |
133 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
134 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
135 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
0ac6f8b7 | 136 | |
6d0f6bcf | 137 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
42d1f039 | 138 | |
6d0f6bcf JCPV |
139 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
140 | #define CONFIG_SYS_RAMBOOT | |
42d1f039 | 141 | #else |
6d0f6bcf | 142 | #undef CONFIG_SYS_RAMBOOT |
42d1f039 WD |
143 | #endif |
144 | ||
00b1883a | 145 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
146 | #define CONFIG_SYS_FLASH_CFI |
147 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
0ac6f8b7 WD |
148 | |
149 | #undef CONFIG_CLOCKS_IN_MHZ | |
42d1f039 | 150 | |
42d1f039 | 151 | |
0ac6f8b7 WD |
152 | /* |
153 | * Local Bus Definitions | |
154 | */ | |
155 | ||
156 | /* | |
157 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 158 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
0ac6f8b7 WD |
159 | * |
160 | * For BR2, need: | |
161 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
162 | * port-size = 32-bits = BR2[19:20] = 11 | |
163 | * no parity checking = BR2[21:22] = 00 | |
164 | * SDRAM for MSEL = BR2[24:26] = 011 | |
165 | * Valid = BR[31] = 1 | |
166 | * | |
167 | * 0 4 8 12 16 20 24 28 | |
168 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
169 | * | |
6d0f6bcf | 170 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
0ac6f8b7 WD |
171 | * FIXME: the top 17 bits of BR2. |
172 | */ | |
173 | ||
6d0f6bcf | 174 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
0ac6f8b7 WD |
175 | |
176 | /* | |
6d0f6bcf | 177 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
0ac6f8b7 WD |
178 | * |
179 | * For OR2, need: | |
180 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
181 | * XAM, OR2[17:18] = 11 | |
182 | * 9 columns OR2[19-21] = 010 | |
183 | * 13 rows OR2[23-25] = 100 | |
184 | * EAD set for extra time OR[31] = 1 | |
185 | * | |
186 | * 0 4 8 12 16 20 24 28 | |
187 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
188 | */ | |
189 | ||
6d0f6bcf | 190 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
0ac6f8b7 | 191 | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
193 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
194 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
195 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ | |
0ac6f8b7 | 196 | |
b0fe93ed KG |
197 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ |
198 | | LSDMR_RFCR5 \ | |
199 | | LSDMR_PRETOACT3 \ | |
200 | | LSDMR_ACTTORW3 \ | |
201 | | LSDMR_BL8 \ | |
202 | | LSDMR_WRC2 \ | |
203 | | LSDMR_CL3 \ | |
204 | | LSDMR_RFEN \ | |
0ac6f8b7 WD |
205 | ) |
206 | ||
207 | /* | |
208 | * SDRAM Controller configuration sequence. | |
209 | */ | |
b0fe93ed KG |
210 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
211 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
212 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
213 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
214 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
0ac6f8b7 | 215 | |
42d1f039 | 216 | |
9aea9530 WD |
217 | /* |
218 | * 32KB, 8-bit wide for ADS config reg | |
219 | */ | |
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_BR4_PRELIM 0xf8000801 |
221 | #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 | |
222 | #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) | |
42d1f039 | 223 | |
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
225 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
226 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
42d1f039 | 227 | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
229 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
230 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
42d1f039 | 231 | |
6d0f6bcf JCPV |
232 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
233 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
42d1f039 WD |
234 | |
235 | /* Serial Port */ | |
0ac6f8b7 WD |
236 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
237 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
238 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
42d1f039 | 239 | |
53677ef1 | 240 | #define CONFIG_BAUDRATE 115200 |
42d1f039 | 241 | |
6d0f6bcf | 242 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
42d1f039 WD |
243 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
244 | ||
245 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
246 | #define CONFIG_SYS_HUSH_PARSER |
247 | #ifdef CONFIG_SYS_HUSH_PARSER | |
248 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
42d1f039 WD |
249 | #endif |
250 | ||
0e16387d | 251 | /* pass open firmware flat tree */ |
5ce71580 KG |
252 | #define CONFIG_OF_LIBFDT 1 |
253 | #define CONFIG_OF_BOARD_SETUP 1 | |
254 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
0e16387d | 255 | |
20476726 JL |
256 | /* |
257 | * I2C | |
258 | */ | |
259 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
260 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
42d1f039 | 261 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
6d0f6bcf JCPV |
262 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
263 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
264 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
265 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
42d1f039 | 266 | |
0ac6f8b7 | 267 | /* RapidIO MMU */ |
5af0fdd8 | 268 | #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ |
10795f42 | 269 | #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ |
5af0fdd8 | 270 | #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 |
6d0f6bcf | 271 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ |
0ac6f8b7 WD |
272 | |
273 | /* | |
274 | * General PCI | |
362dd830 | 275 | * Memory space is mapped 1-1, but I/O space must start from 0. |
0ac6f8b7 | 276 | */ |
5af0fdd8 | 277 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
10795f42 | 278 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 279 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
6d0f6bcf | 280 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 281 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 282 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
283 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
284 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
0ac6f8b7 WD |
285 | |
286 | #if defined(CONFIG_PCI) | |
42d1f039 | 287 | |
42d1f039 | 288 | #define CONFIG_NET_MULTI |
53677ef1 | 289 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
0ac6f8b7 WD |
290 | |
291 | #undef CONFIG_EEPRO100 | |
42d1f039 | 292 | #undef CONFIG_TULIP |
0ac6f8b7 WD |
293 | |
294 | #if !defined(CONFIG_PCI_PNP) | |
295 | #define PCI_ENET0_IOADDR 0xe0000000 | |
296 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
53677ef1 | 297 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
42d1f039 | 298 | #endif |
0ac6f8b7 WD |
299 | |
300 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 301 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
0ac6f8b7 WD |
302 | |
303 | #endif /* CONFIG_PCI */ | |
304 | ||
305 | ||
ccc091aa | 306 | #ifdef CONFIG_TSEC_ENET |
0ac6f8b7 WD |
307 | |
308 | #ifndef CONFIG_NET_MULTI | |
53677ef1 | 309 | #define CONFIG_NET_MULTI 1 |
0ac6f8b7 WD |
310 | #endif |
311 | ||
ccc091aa | 312 | #ifndef CONFIG_MII |
0ac6f8b7 | 313 | #define CONFIG_MII 1 /* MII PHY management */ |
ccc091aa | 314 | #endif |
255a3577 KP |
315 | #define CONFIG_TSEC1 1 |
316 | #define CONFIG_TSEC1_NAME "TSEC0" | |
317 | #define CONFIG_TSEC2 1 | |
318 | #define CONFIG_TSEC2_NAME "TSEC1" | |
0ac6f8b7 WD |
319 | #define TSEC1_PHY_ADDR 0 |
320 | #define TSEC2_PHY_ADDR 1 | |
321 | #define TSEC1_PHYIDX 0 | |
322 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
323 | #define TSEC1_FLAGS TSEC_GIGABIT |
324 | #define TSEC2_FLAGS TSEC_GIGABIT | |
d9b94f28 JL |
325 | |
326 | /* Options are: TSEC[0-1] */ | |
327 | #define CONFIG_ETHPRIME "TSEC0" | |
0ac6f8b7 | 328 | |
ccc091aa AF |
329 | #endif /* CONFIG_TSEC_ENET */ |
330 | ||
53677ef1 | 331 | #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ |
0ac6f8b7 | 332 | |
53677ef1 | 333 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ |
0ac6f8b7 WD |
334 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ |
335 | ||
336 | #if (CONFIG_ETHER_INDEX == 2) | |
42d1f039 WD |
337 | /* |
338 | * - Rx-CLK is CLK13 | |
339 | * - Tx-CLK is CLK14 | |
340 | * - Select bus for bd/buffers | |
341 | * - Full duplex | |
342 | */ | |
6d0f6bcf JCPV |
343 | #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
344 | #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
345 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
346 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) | |
42d1f039 | 347 | #define FETH2_RST 0x01 |
0ac6f8b7 | 348 | #elif (CONFIG_ETHER_INDEX == 3) |
42d1f039 WD |
349 | /* need more definitions here for FE3 */ |
350 | #define FETH3_RST 0x80 | |
53677ef1 | 351 | #endif /* CONFIG_ETHER_INDEX */ |
0ac6f8b7 | 352 | |
ccc091aa AF |
353 | #ifndef CONFIG_MII |
354 | #define CONFIG_MII 1 /* MII PHY management */ | |
355 | #endif | |
356 | ||
0ac6f8b7 WD |
357 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
358 | ||
42d1f039 WD |
359 | /* |
360 | * GPIO pins used for bit-banged MII communications | |
361 | */ | |
362 | #define MDIO_PORT 2 /* Port C */ | |
be225442 LCM |
363 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
364 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
365 | #define MDC_DECLARE MDIO_DECLARE | |
366 | ||
42d1f039 WD |
367 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) |
368 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) | |
369 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) | |
370 | ||
371 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ | |
372 | else iop->pdat &= ~0x00400000 | |
373 | ||
374 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ | |
375 | else iop->pdat &= ~0x00200000 | |
376 | ||
377 | #define MIIDELAY udelay(1) | |
0ac6f8b7 | 378 | |
42d1f039 WD |
379 | #endif |
380 | ||
0ac6f8b7 WD |
381 | |
382 | /* | |
383 | * Environment | |
384 | */ | |
6d0f6bcf | 385 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 386 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 387 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 JCPV |
388 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
389 | #define CONFIG_ENV_SIZE 0x2000 | |
42d1f039 | 390 | #else |
6d0f6bcf | 391 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 392 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 393 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 394 | #define CONFIG_ENV_SIZE 0x2000 |
42d1f039 WD |
395 | #endif |
396 | ||
0ac6f8b7 | 397 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
6d0f6bcf | 398 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
42d1f039 | 399 | |
659e2f67 JL |
400 | /* |
401 | * BOOTP options | |
402 | */ | |
403 | #define CONFIG_BOOTP_BOOTFILESIZE | |
404 | #define CONFIG_BOOTP_BOOTPATH | |
405 | #define CONFIG_BOOTP_GATEWAY | |
406 | #define CONFIG_BOOTP_HOSTNAME | |
407 | ||
408 | ||
2835e518 JL |
409 | /* |
410 | * Command line configuration. | |
411 | */ | |
412 | #include <config_cmd_default.h> | |
413 | ||
414 | #define CONFIG_CMD_PING | |
415 | #define CONFIG_CMD_I2C | |
82ac8c97 | 416 | #define CONFIG_CMD_ELF |
1c9aa76b KG |
417 | #define CONFIG_CMD_IRQ |
418 | #define CONFIG_CMD_SETEXPR | |
2835e518 JL |
419 | |
420 | #if defined(CONFIG_PCI) | |
421 | #define CONFIG_CMD_PCI | |
422 | #endif | |
423 | ||
424 | #if defined(CONFIG_ETHER_ON_FCC) | |
425 | #define CONFIG_CMD_MII | |
426 | #endif | |
427 | ||
6d0f6bcf | 428 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 429 | #undef CONFIG_CMD_SAVEENV |
2835e518 | 430 | #undef CONFIG_CMD_LOADS |
42d1f039 | 431 | #endif |
0ac6f8b7 | 432 | |
42d1f039 | 433 | |
0ac6f8b7 | 434 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
42d1f039 WD |
435 | |
436 | /* | |
437 | * Miscellaneous configurable options | |
438 | */ | |
6d0f6bcf | 439 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
22abb2d2 | 440 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
6d0f6bcf JCPV |
441 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ |
442 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
0ac6f8b7 | 443 | |
2835e518 | 444 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 445 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
42d1f039 | 446 | #else |
6d0f6bcf | 447 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
42d1f039 | 448 | #endif |
0ac6f8b7 | 449 | |
6d0f6bcf JCPV |
450 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
451 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
452 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
453 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
42d1f039 WD |
454 | |
455 | /* | |
456 | * For booting Linux, the board info and command line data | |
89188a62 | 457 | * have to be in the first 16 MB of memory, since this is |
42d1f039 WD |
458 | * the maximum mapped by the Linux kernel during initialization. |
459 | */ | |
89188a62 | 460 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ |
42d1f039 | 461 | |
42d1f039 WD |
462 | /* |
463 | * Internal Definitions | |
464 | * | |
465 | * Boot Flags | |
466 | */ | |
467 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
0ac6f8b7 | 468 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
42d1f039 | 469 | |
2835e518 | 470 | #if defined(CONFIG_CMD_KGDB) |
42d1f039 WD |
471 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
472 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
473 | #endif | |
474 | ||
9aea9530 WD |
475 | |
476 | /* | |
477 | * Environment Configuration | |
478 | */ | |
479 | ||
0ac6f8b7 | 480 | /* The mac addresses for all ethernet interface */ |
42d1f039 | 481 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
10327dc5 | 482 | #define CONFIG_HAS_ETH0 |
0ac6f8b7 | 483 | #define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
e2ffd59b | 484 | #define CONFIG_HAS_ETH1 |
0ac6f8b7 | 485 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
e2ffd59b | 486 | #define CONFIG_HAS_ETH2 |
0ac6f8b7 | 487 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
5ce71580 KG |
488 | #define CONFIG_HAS_ETH3 |
489 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD | |
42d1f039 WD |
490 | #endif |
491 | ||
0ac6f8b7 WD |
492 | #define CONFIG_IPADDR 192.168.1.253 |
493 | ||
494 | #define CONFIG_HOSTNAME unknown | |
495 | #define CONFIG_ROOTPATH /nfsroot | |
496 | #define CONFIG_BOOTFILE your.uImage | |
497 | ||
498 | #define CONFIG_SERVERIP 192.168.1.1 | |
499 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
500 | #define CONFIG_NETMASK 255.255.255.0 | |
501 | ||
502 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ | |
503 | ||
9aea9530 | 504 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
0ac6f8b7 WD |
505 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
506 | ||
507 | #define CONFIG_BAUDRATE 115200 | |
508 | ||
9aea9530 | 509 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
6b44a44e AF |
510 | "netdev=eth0\0" \ |
511 | "consoledev=ttyCPM\0" \ | |
512 | "ramdiskaddr=1000000\0" \ | |
513 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
514 | "fdtaddr=400000\0" \ | |
515 | "fdtfile=mpc8560ads.dtb\0" | |
0ac6f8b7 | 516 | |
9aea9530 | 517 | #define CONFIG_NFSBOOTCOMMAND \ |
6b44a44e AF |
518 | "setenv bootargs root=/dev/nfs rw " \ |
519 | "nfsroot=$serverip:$rootpath " \ | |
520 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
521 | "console=$consoledev,$baudrate $othbootargs;" \ | |
522 | "tftp $loadaddr $bootfile;" \ | |
523 | "tftp $fdtaddr $fdtfile;" \ | |
524 | "bootm $loadaddr - $fdtaddr" | |
0ac6f8b7 WD |
525 | |
526 | #define CONFIG_RAMBOOTCOMMAND \ | |
6b44a44e AF |
527 | "setenv bootargs root=/dev/ram rw " \ |
528 | "console=$consoledev,$baudrate $othbootargs;" \ | |
529 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
530 | "tftp $loadaddr $bootfile;" \ | |
531 | "tftp $fdtaddr $fdtfile;" \ | |
532 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
0ac6f8b7 WD |
533 | |
534 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
42d1f039 WD |
535 | |
536 | #endif /* __CONFIG_H */ |