[people/ms/u-boot.git] / include / configs / MPC8560ADS.h

/*
 * Copyright 2004, 2011 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * mpc8560ads board configuration file
 *
 * Please refer to doc/README.mpc85xx for more info.
 *
 * Make sure you change the MAC address and other network params first,
 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
#define CONFIG_CPM2		1	/* has CPM2 */
#define CONFIG_MPC8560ADS	1	/* MPC8560ADS board specific */
#define CONFIG_MPC8560		1

/*
 * default CCARBAR is at 0xff700000
 * assume U-Boot is less than 0.5MB
 */
#define	CONFIG_SYS_TEXT_BASE	0xfff80000

#define CONFIG_PCI
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#undef CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
#define CONFIG_RESET_PHY_R	1	/* Call reset_phy() */

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	33000000
#endif


/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00400000


/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */

/* DDR Setup */
#define CONFIG_FSL_DDR1
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE

#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* These are used when DDR doesn't use SPD.  */
#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
#define CONFIG_SYS_DDR_TIMING_1	0x37344321
#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */

#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

#undef CONFIG_CLOCKS_IN_MHZ


/*
 * Local Bus Definitions
 */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CONFIG_SYS_BR2_PRELIM		0xf0001861

/*
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/

#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
				| LSDMR_RFCR5		\
				| LSDMR_PRETOACT3	\
				| LSDMR_ACTTORW3	\
				| LSDMR_BL8		\
				| LSDMR_WRC2		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * SDRAM Controller configuration sequence.
 */
#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)


/*
 * 32KB, 8-bit wide for ADS config reg
 */
#define CONFIG_SYS_BR4_PRELIM          0xf8000801
#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_ON_SCC	/* define if console on SCC */
#undef  CONFIG_CONS_NONE	/* define if console on something else */
#define CONFIG_CONS_INDEX       1  /* which serial channel for console */

#define CONFIG_BAUDRATE		115200

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef  CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET		0x3000

/* RapidIO MMU */
#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */

#if defined(CONFIG_PCI)

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */


#ifdef CONFIG_TSEC_ENET

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

#ifndef CONFIG_MII
#define CONFIG_MII		1	/* MII PHY management */
#endif
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif /* CONFIG_TSEC_ENET */

#ifdef CONFIG_ETHER_ON_FCC		/* CPM FCC Ethernet */

#undef  CONFIG_ETHER_NONE		/* define if ether on something else */
#define CONFIG_ETHER_INDEX      2       /* which channel for ether */

#if (CONFIG_ETHER_INDEX == 2)
  /*
   * - Rx-CLK is CLK13
   * - Tx-CLK is CLK14
   * - Select bus for bd/buffers
   * - Full duplex
   */
  #define CONFIG_SYS_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  #define CONFIG_SYS_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  #define CONFIG_SYS_CPMFCR_RAMTYPE    0
  #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
  #define FETH2_RST		0x01
#elif (CONFIG_ETHER_INDEX == 3)
  /* need more definitions here for FE3 */
  #define FETH3_RST		0x80
#endif					/* CONFIG_ETHER_INDEX */

#ifndef CONFIG_MII
#define CONFIG_MII		1	/* MII PHY management */
#endif

#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */

/*
 * GPIO pins used for bit-banged MII communications
 */
#define MDIO_PORT	2		/* Port C */
#define MDIO_DECLARE	volatile ioport_t *iop = ioport_addr ( \
				(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
#define MDC_DECLARE	MDIO_DECLARE

#define MDIO_ACTIVE	(iop->pdir |=  0x00400000)
#define MDIO_TRISTATE	(iop->pdir &= ~0x00400000)
#define MDIO_READ	((iop->pdat &  0x00400000) != 0)

#define MDIO(bit)	if(bit) iop->pdat |=  0x00400000; \
			else	iop->pdat &= ~0x00400000

#define MDC(bit)	if(bit) iop->pdat |=  0x00200000; \
			else	iop->pdat &= ~0x00200000

#define MIIDELAY	udelay(1)

#endif


/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
  #define CONFIG_ENV_IS_IN_FLASH	1
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
  #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
  #define CONFIG_ENV_SIZE		0x2000
#else
  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
  #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
  #define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CONFIG_ETHER_ON_FCC)
    #define CONFIG_CMD_MII
#endif

#if defined(CONFIG_SYS_RAMBOOT)
    #undef CONFIG_CMD_SAVEENV
    #undef CONFIG_CMD_LOADS
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */

#if defined(CONFIG_CMD_KGDB)
    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif


/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
#define CONFIG_HAS_ETH3
#define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME		unknown
#define CONFIG_ROOTPATH		/nfsroot
#define CONFIG_BOOTFILE		your.uImage

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
	"netdev=eth0\0"							\
	"consoledev=ttyCPM\0"						\
	"ramdiskaddr=1000000\0"						\
	"ramdiskfile=your.ramdisk.u-boot\0"				\
	"fdtaddr=400000\0"						\
	"fdtfile=mpc8560ads.dtb\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
	"setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=$serverip:$rootpath "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
	"setenv bootargs root=/dev/ram rw "				\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
42d1f039	1	/*
7c57f3e8	2	* Copyright 2004, 2011 Freescale Semiconductor.
42d1f039 WD	3	* (C) Copyright 2002,2003 Motorola,Inc.
	4	* Xianghua Xiao <X.Xiao@motorola.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
0ac6f8b7 WD	25	/*
	26	* mpc8560ads board configuration file
	27	*
	28	* Please refer to doc/README.mpc85xx for more info.
	29	*
	30	* Make sure you change the MAC address and other network params first,
	31	* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
42d1f039 WD	32	*/
	33
	34	#ifndef __CONFIG_H
	35	#define __CONFIG_H
	36
	37	/* High Level Configuration Options */
0ac6f8b7 WD	38	#define CONFIG_BOOKE 1 /* BOOKE */
	39	#define CONFIG_E500 1 /* BOOKE e500 family */
	40	#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
9c4c5ae3	41	#define CONFIG_CPM2 1 /* has CPM2 */
0ac6f8b7	42	#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
f060054d	43	#define CONFIG_MPC8560 1
0ac6f8b7	44
2ae18241 WD	45	/*
	46	* default CCARBAR is at 0xff700000
	47	* assume U-Boot is less than 0.5MB
	48	*/
	49	#define CONFIG_SYS_TEXT_BASE 0xfff80000
	50
0ac6f8b7	51	#define CONFIG_PCI
0151cbac	52	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
53677ef1	53	#define CONFIG_TSEC_ENET /* tsec ethernet support */
ccc091aa	54	#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
42d1f039	55	#define CONFIG_ENV_OVERWRITE
7232a272	56	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
004eca0c	57	#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
42d1f039	58
0ac6f8b7 WD	59	/*
	60	* sysclk for MPC85xx
	61	*
	62	* Two valid values are:
	63	* 33000000
	64	* 66000000
	65	*
	66	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
9aea9530 WD	67	* is likely the desired value here, so that is now the default.
	68	* The board, however, can run at 66MHz. In any event, this value
	69	* must match the settings of some switches. Details can be found
	70	* in the README.mpc85xxads.
0ac6f8b7 WD	71	*/
0ac6f8b7 WD	72
9aea9530 WD	73	#ifndef CONFIG_SYS_CLK_FREQ
9aea9530 WD	74	#define CONFIG_SYS_CLK_FREQ 33000000
42d1f039 WD	75	#endif
42d1f039 WD	76
9aea9530	77
0ac6f8b7 WD	78	/*
	79	* These can be toggled for performance analysis, otherwise use default.
	80	*/
	81	#define CONFIG_L2_CACHE /* toggle L2 cache */
	82	#define CONFIG_BTB /* toggle branch predition */
42d1f039	83
6d0f6bcf	84	#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
0ac6f8b7	85
6d0f6bcf JCPV	86	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
6d0f6bcf JCPV	87	#define CONFIG_SYS_MEMTEST_END 0x00400000
42d1f039	88
42d1f039 WD	89
	90	/*
	91	* Base addresses -- Note these are effective addresses where the
	92	* actual resources get mapped (not physical addresses)
	93	*/
6d0f6bcf JCPV	94	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
	95	#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
	96	#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
	97	#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
42d1f039	98
8b625114 JL	99	/* DDR Setup */
	100	#define CONFIG_FSL_DDR1
	101	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	102	#define CONFIG_DDR_SPD
	103	#undef CONFIG_FSL_DDR_INTERACTIVE
	104
	105	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
9aea9530	106
6d0f6bcf JCPV	107	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	108	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
9aea9530	109
8b625114 JL	110	#define CONFIG_NUM_DDR_CONTROLLERS 1
	111	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	112	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
9aea9530	113
8b625114 JL	114	/* I2C addresses of SPD EEPROMs */
8b625114 JL	115	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
9aea9530	116
8b625114	117	/* These are used when DDR doesn't use SPD. */
6d0f6bcf JCPV	118	#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
	119	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
	120	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
	121	#define CONFIG_SYS_DDR_TIMING_1 0x37344321
	122	#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
	123	#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
	124	#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
	125	#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
42d1f039	126
0ac6f8b7 WD	127	/*
	128	* SDRAM on the Local Bus
	129	*/
6d0f6bcf JCPV	130	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	131	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
42d1f039	132
6d0f6bcf JCPV	133	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
6d0f6bcf JCPV	134	#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
42d1f039	135
6d0f6bcf JCPV	136	#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
	137	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	138	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
	139	#undef CONFIG_SYS_FLASH_CHECKSUM
	140	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	141	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
0ac6f8b7	142
14d0a02a	143	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
42d1f039	144
6d0f6bcf JCPV	145	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	146	#define CONFIG_SYS_RAMBOOT
42d1f039	147	#else
6d0f6bcf	148	#undef CONFIG_SYS_RAMBOOT
42d1f039 WD	149	#endif
42d1f039 WD	150
00b1883a	151	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	152	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	153	#define CONFIG_SYS_FLASH_EMPTY_INFO
0ac6f8b7 WD	154
0ac6f8b7 WD	155	#undef CONFIG_CLOCKS_IN_MHZ
42d1f039	156
42d1f039	157
0ac6f8b7 WD	158	/*
	159	* Local Bus Definitions
	160	*/
	161
	162	/*
	163	* Base Register 2 and Option Register 2 configure SDRAM.
6d0f6bcf	164	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
0ac6f8b7 WD	165	*
	166	* For BR2, need:
	167	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	168	* port-size = 32-bits = BR2[19:20] = 11
	169	* no parity checking = BR2[21:22] = 00
	170	* SDRAM for MSEL = BR2[24:26] = 011
	171	* Valid = BR[31] = 1
	172	*
	173	* 0 4 8 12 16 20 24 28
	174	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	175	*
6d0f6bcf	176	* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
0ac6f8b7 WD	177	* FIXME: the top 17 bits of BR2.
	178	*/
	179
6d0f6bcf	180	#define CONFIG_SYS_BR2_PRELIM 0xf0001861
0ac6f8b7 WD	181
0ac6f8b7 WD	182	/*
6d0f6bcf	183	* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
0ac6f8b7 WD	184	*
	185	* For OR2, need:
	186	* 64MB mask for AM, OR2[0:7] = 1111 1100
	187	* XAM, OR2[17:18] = 11
	188	* 9 columns OR2[19-21] = 010
	189	* 13 rows OR2[23-25] = 100
	190	* EAD set for extra time OR[31] = 1
	191	*
	192	* 0 4 8 12 16 20 24 28
	193	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	194	*/
	195
6d0f6bcf	196	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
0ac6f8b7	197
6d0f6bcf JCPV	198	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	199	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	200	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	201	#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
0ac6f8b7	202
b0fe93ed KG	203	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
	204	\| LSDMR_RFCR5 \
	205	\| LSDMR_PRETOACT3 \
	206	\| LSDMR_ACTTORW3 \
	207	\| LSDMR_BL8 \
	208	\| LSDMR_WRC2 \
	209	\| LSDMR_CL3 \
	210	\| LSDMR_RFEN \
0ac6f8b7 WD	211	)
	212
	213	/*
	214	* SDRAM Controller configuration sequence.
	215	*/
b0fe93ed KG	216	#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_PCHALL)
	217	#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	218	#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	219	#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_MRW)
	220	#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_NORMAL)
0ac6f8b7	221
42d1f039	222
9aea9530 WD	223	/*
	224	* 32KB, 8-bit wide for ADS config reg
	225	*/
6d0f6bcf JCPV	226	#define CONFIG_SYS_BR4_PRELIM 0xf8000801
	227	#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
	228	#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
42d1f039	229
6d0f6bcf JCPV	230	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	231	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	232	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
42d1f039	233
25ddd1fb	234	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	235	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
42d1f039	236
6d0f6bcf JCPV	237	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	238	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
42d1f039 WD	239
42d1f039 WD	240	/* Serial Port */
0ac6f8b7 WD	241	#define CONFIG_CONS_ON_SCC /* define if console on SCC */
	242	#undef CONFIG_CONS_NONE /* define if console on something else */
	243	#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
42d1f039	244
53677ef1	245	#define CONFIG_BAUDRATE 115200
42d1f039	246
6d0f6bcf	247	#define CONFIG_SYS_BAUDRATE_TABLE \
42d1f039 WD	248	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	249
	250	/* Use the HUSH parser */
6d0f6bcf JCPV	251	#define CONFIG_SYS_HUSH_PARSER
	252	#ifdef CONFIG_SYS_HUSH_PARSER
	253	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
42d1f039 WD	254	#endif
42d1f039 WD	255
0e16387d	256	/* pass open firmware flat tree */
5ce71580 KG	257	#define CONFIG_OF_LIBFDT 1
	258	#define CONFIG_OF_BOARD_SETUP 1
	259	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
0e16387d	260
20476726 JL	261	/*
	262	* I2C
	263	*/
	264	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	265	#define CONFIG_HARD_I2C /* I2C with hardware support*/
42d1f039	266	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	267	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
	268	#define CONFIG_SYS_I2C_SLAVE 0x7F
	269	#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
	270	#define CONFIG_SYS_I2C_OFFSET 0x3000
42d1f039	271
0ac6f8b7	272	/* RapidIO MMU */
5af0fdd8	273	#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
10795f42	274	#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
5af0fdd8	275	#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
6d0f6bcf	276	#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
0ac6f8b7 WD	277
	278	/*
	279	* General PCI
362dd830	280	* Memory space is mapped 1-1, but I/O space must start from 0.
0ac6f8b7	281	*/
5af0fdd8	282	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
10795f42	283	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	284	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
6d0f6bcf	285	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	286	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	287	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	288	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
6d0f6bcf JCPV	289	#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
0ac6f8b7 WD	290
0ac6f8b7 WD	291	#if defined(CONFIG_PCI)
42d1f039	292
42d1f039	293	#define CONFIG_NET_MULTI
53677ef1	294	#define CONFIG_PCI_PNP /* do pci plug-and-play */
0ac6f8b7 WD	295
0ac6f8b7 WD	296	#undef CONFIG_EEPRO100
42d1f039	297	#undef CONFIG_TULIP
0ac6f8b7 WD	298
	299	#if !defined(CONFIG_PCI_PNP)
	300	#define PCI_ENET0_IOADDR 0xe0000000
	301	#define PCI_ENET0_MEMADDR 0xe0000000
53677ef1	302	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
42d1f039	303	#endif
0ac6f8b7 WD	304
0ac6f8b7 WD	305	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	306	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
0ac6f8b7 WD	307
	308	#endif /* CONFIG_PCI */
	309
	310
ccc091aa	311	#ifdef CONFIG_TSEC_ENET
0ac6f8b7 WD	312
0ac6f8b7 WD	313	#ifndef CONFIG_NET_MULTI
53677ef1	314	#define CONFIG_NET_MULTI 1
0ac6f8b7 WD	315	#endif
0ac6f8b7 WD	316
ccc091aa	317	#ifndef CONFIG_MII
0ac6f8b7	318	#define CONFIG_MII 1 /* MII PHY management */
ccc091aa	319	#endif
255a3577 KP	320	#define CONFIG_TSEC1 1
	321	#define CONFIG_TSEC1_NAME "TSEC0"
	322	#define CONFIG_TSEC2 1
	323	#define CONFIG_TSEC2_NAME "TSEC1"
0ac6f8b7 WD	324	#define TSEC1_PHY_ADDR 0
	325	#define TSEC2_PHY_ADDR 1
	326	#define TSEC1_PHYIDX 0
	327	#define TSEC2_PHYIDX 0
3a79013e AF	328	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	329	#define TSEC2_FLAGS TSEC_GIGABIT
d9b94f28 JL	330
	331	/* Options are: TSEC[0-1] */
	332	#define CONFIG_ETHPRIME "TSEC0"
0ac6f8b7	333
ccc091aa AF	334	#endif /* CONFIG_TSEC_ENET */
ccc091aa AF	335
53677ef1	336	#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
0ac6f8b7	337
53677ef1	338	#undef CONFIG_ETHER_NONE /* define if ether on something else */
0ac6f8b7 WD	339	#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
	340
	341	#if (CONFIG_ETHER_INDEX == 2)
42d1f039 WD	342	/*
	343	* - Rx-CLK is CLK13
	344	* - Tx-CLK is CLK14
	345	* - Select bus for bd/buffers
	346	* - Full duplex
	347	*/
6d0f6bcf JCPV	348	#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
	349	#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
	350	#define CONFIG_SYS_CPMFCR_RAMTYPE 0
	351	#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
42d1f039	352	#define FETH2_RST 0x01
0ac6f8b7	353	#elif (CONFIG_ETHER_INDEX == 3)
42d1f039 WD	354	/* need more definitions here for FE3 */
42d1f039 WD	355	#define FETH3_RST 0x80
53677ef1	356	#endif /* CONFIG_ETHER_INDEX */
0ac6f8b7	357
ccc091aa AF	358	#ifndef CONFIG_MII
	359	#define CONFIG_MII 1 /* MII PHY management */
	360	#endif
	361
0ac6f8b7 WD	362	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
0ac6f8b7 WD	363
42d1f039 WD	364	/*
	365	* GPIO pins used for bit-banged MII communications
	366	*/
	367	#define MDIO_PORT 2 /* Port C */
be225442 LCM	368	#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
	369	(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
	370	#define MDC_DECLARE MDIO_DECLARE
	371
42d1f039 WD	372	#define MDIO_ACTIVE (iop->pdir \|= 0x00400000)
	373	#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
	374	#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
	375
	376	#define MDIO(bit) if(bit) iop->pdat \|= 0x00400000; \
	377	else iop->pdat &= ~0x00400000
	378
	379	#define MDC(bit) if(bit) iop->pdat \|= 0x00200000; \
	380	else iop->pdat &= ~0x00200000
	381
	382	#define MIIDELAY udelay(1)
0ac6f8b7	383
42d1f039 WD	384	#endif
42d1f039 WD	385
0ac6f8b7 WD	386
	387	/*
	388	* Environment
	389	*/
6d0f6bcf	390	#ifndef CONFIG_SYS_RAMBOOT
5a1aceb0	391	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	392	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
0e8d1586 JCPV	393	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
0e8d1586 JCPV	394	#define CONFIG_ENV_SIZE 0x2000
42d1f039	395	#else
6d0f6bcf	396	#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
93f6d725	397	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
6d0f6bcf	398	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	399	#define CONFIG_ENV_SIZE 0x2000
42d1f039 WD	400	#endif
42d1f039 WD	401
0ac6f8b7	402	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	403	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
42d1f039	404
659e2f67 JL	405	/*
	406	* BOOTP options
	407	*/
	408	#define CONFIG_BOOTP_BOOTFILESIZE
	409	#define CONFIG_BOOTP_BOOTPATH
	410	#define CONFIG_BOOTP_GATEWAY
	411	#define CONFIG_BOOTP_HOSTNAME
	412
	413
2835e518 JL	414	/*
	415	* Command line configuration.
	416	*/
	417	#include <config_cmd_default.h>
	418
	419	#define CONFIG_CMD_PING
	420	#define CONFIG_CMD_I2C
82ac8c97	421	#define CONFIG_CMD_ELF
1c9aa76b KG	422	#define CONFIG_CMD_IRQ
1c9aa76b KG	423	#define CONFIG_CMD_SETEXPR
199e262e	424	#define CONFIG_CMD_REGINFO
2835e518 JL	425
	426	#if defined(CONFIG_PCI)
	427	#define CONFIG_CMD_PCI
	428	#endif
	429
	430	#if defined(CONFIG_ETHER_ON_FCC)
	431	#define CONFIG_CMD_MII
	432	#endif
	433
6d0f6bcf	434	#if defined(CONFIG_SYS_RAMBOOT)
bdab39d3	435	#undef CONFIG_CMD_SAVEENV
2835e518	436	#undef CONFIG_CMD_LOADS
42d1f039	437	#endif
0ac6f8b7	438
42d1f039	439
0ac6f8b7	440	#undef CONFIG_WATCHDOG /* watchdog disabled */
42d1f039 WD	441
	442	/*
	443	* Miscellaneous configurable options
	444	*/
6d0f6bcf	445	#define CONFIG_SYS_LONGHELP /* undef to save memory */
5be58f5f KP	446	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
5be58f5f KP	447	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
6d0f6bcf JCPV	448	#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
6d0f6bcf JCPV	449	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
0ac6f8b7	450
2835e518	451	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	452	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
42d1f039	453	#else
6d0f6bcf	454	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
42d1f039	455	#endif
0ac6f8b7	456
6d0f6bcf JCPV	457	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	458	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	459	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	460	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
42d1f039 WD	461
	462	/*
	463	* For booting Linux, the board info and command line data
a832ac41	464	* have to be in the first 64 MB of memory, since this is
42d1f039 WD	465	* the maximum mapped by the Linux kernel during initialization.
42d1f039 WD	466	*/
a832ac41 KG	467	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	468	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
42d1f039	469
2835e518	470	#if defined(CONFIG_CMD_KGDB)
42d1f039 WD	471	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	472	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	473	#endif
	474
9aea9530 WD	475
	476	/*
	477	* Environment Configuration
	478	*/
	479
0ac6f8b7	480	/* The mac addresses for all ethernet interface */
42d1f039	481	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
10327dc5	482	#define CONFIG_HAS_ETH0
0ac6f8b7	483	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
e2ffd59b	484	#define CONFIG_HAS_ETH1
0ac6f8b7	485	#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
e2ffd59b	486	#define CONFIG_HAS_ETH2
0ac6f8b7	487	#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
5ce71580 KG	488	#define CONFIG_HAS_ETH3
5ce71580 KG	489	#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
42d1f039 WD	490	#endif
42d1f039 WD	491
0ac6f8b7 WD	492	#define CONFIG_IPADDR 192.168.1.253
	493
	494	#define CONFIG_HOSTNAME unknown
	495	#define CONFIG_ROOTPATH /nfsroot
	496	#define CONFIG_BOOTFILE your.uImage
	497
	498	#define CONFIG_SERVERIP 192.168.1.1
	499	#define CONFIG_GATEWAYIP 192.168.1.1
	500	#define CONFIG_NETMASK 255.255.255.0
	501
	502	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	503
9aea9530	504	#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
0ac6f8b7 WD	505	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	506
	507	#define CONFIG_BAUDRATE 115200
	508
9aea9530	509	#define CONFIG_EXTRA_ENV_SETTINGS \
6b44a44e AF	510	"netdev=eth0\0" \
	511	"consoledev=ttyCPM\0" \
	512	"ramdiskaddr=1000000\0" \
	513	"ramdiskfile=your.ramdisk.u-boot\0" \
	514	"fdtaddr=400000\0" \
	515	"fdtfile=mpc8560ads.dtb\0"
0ac6f8b7	516
9aea9530	517	#define CONFIG_NFSBOOTCOMMAND \
6b44a44e AF	518	"setenv bootargs root=/dev/nfs rw " \
	519	"nfsroot=$serverip:$rootpath " \
	520	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	521	"console=$consoledev,$baudrate $othbootargs;" \
	522	"tftp $loadaddr $bootfile;" \
	523	"tftp $fdtaddr $fdtfile;" \
	524	"bootm $loadaddr - $fdtaddr"
0ac6f8b7 WD	525
0ac6f8b7 WD	526	#define CONFIG_RAMBOOTCOMMAND \
6b44a44e AF	527	"setenv bootargs root=/dev/ram rw " \
	528	"console=$consoledev,$baudrate $othbootargs;" \
	529	"tftp $ramdiskaddr $ramdiskfile;" \
	530	"tftp $loadaddr $bootfile;" \
	531	"tftp $fdtaddr $fdtfile;" \
	532	"bootm $loadaddr $ramdiskaddr $fdtaddr"
0ac6f8b7 WD	533
0ac6f8b7 WD	534	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
42d1f039 WD	535
42d1f039 WD	536	#endif /* __CONFIG_H */