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42d1f039 | 1 | /* |
7c57f3e8 | 2 | * Copyright 2004, 2011 Freescale Semiconductor. |
42d1f039 WD |
3 | * (C) Copyright 2002,2003 Motorola,Inc. |
4 | * Xianghua Xiao <X.Xiao@motorola.com> | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
42d1f039 WD |
7 | */ |
8 | ||
0ac6f8b7 WD |
9 | /* |
10 | * mpc8560ads board configuration file | |
11 | * | |
12 | * Please refer to doc/README.mpc85xx for more info. | |
13 | * | |
14 | * Make sure you change the MAC address and other network params first, | |
92ac5208 | 15 | * search for CONFIG_SERVERIP, etc. in this file. |
42d1f039 WD |
16 | */ |
17 | ||
18 | #ifndef __CONFIG_H | |
19 | #define __CONFIG_H | |
20 | ||
9ae14ca2 YS |
21 | #define CONFIG_DISPLAY_BOARDINFO |
22 | ||
42d1f039 | 23 | /* High Level Configuration Options */ |
0ac6f8b7 WD |
24 | #define CONFIG_BOOKE 1 /* BOOKE */ |
25 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
9c4c5ae3 | 26 | #define CONFIG_CPM2 1 /* has CPM2 */ |
0ac6f8b7 | 27 | #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */ |
f060054d | 28 | #define CONFIG_MPC8560 1 |
0ac6f8b7 | 29 | |
2ae18241 WD |
30 | /* |
31 | * default CCARBAR is at 0xff700000 | |
32 | * assume U-Boot is less than 0.5MB | |
33 | */ | |
34 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
35 | ||
0ac6f8b7 | 36 | #define CONFIG_PCI |
842033e6 | 37 | #define CONFIG_PCI_INDIRECT_BRIDGE |
0151cbac | 38 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
53677ef1 | 39 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
ccc091aa | 40 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ |
42d1f039 | 41 | #define CONFIG_ENV_OVERWRITE |
7232a272 | 42 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
004eca0c | 43 | #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ |
42d1f039 | 44 | |
0ac6f8b7 WD |
45 | /* |
46 | * sysclk for MPC85xx | |
47 | * | |
48 | * Two valid values are: | |
49 | * 33000000 | |
50 | * 66000000 | |
51 | * | |
52 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
9aea9530 WD |
53 | * is likely the desired value here, so that is now the default. |
54 | * The board, however, can run at 66MHz. In any event, this value | |
55 | * must match the settings of some switches. Details can be found | |
56 | * in the README.mpc85xxads. | |
0ac6f8b7 WD |
57 | */ |
58 | ||
9aea9530 WD |
59 | #ifndef CONFIG_SYS_CLK_FREQ |
60 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
42d1f039 WD |
61 | #endif |
62 | ||
9aea9530 | 63 | |
0ac6f8b7 WD |
64 | /* |
65 | * These can be toggled for performance analysis, otherwise use default. | |
66 | */ | |
67 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
68 | #define CONFIG_BTB /* toggle branch predition */ | |
42d1f039 | 69 | |
6d0f6bcf | 70 | #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ |
0ac6f8b7 | 71 | |
6d0f6bcf JCPV |
72 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
73 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
42d1f039 | 74 | |
e46fedfe TT |
75 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
76 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
42d1f039 | 77 | |
8b625114 | 78 | /* DDR Setup */ |
5614e71b | 79 | #define CONFIG_SYS_FSL_DDR1 |
8b625114 JL |
80 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
81 | #define CONFIG_DDR_SPD | |
82 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
83 | ||
84 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
9aea9530 | 85 | |
6d0f6bcf JCPV |
86 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
87 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
9aea9530 | 88 | |
8b625114 JL |
89 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
90 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
91 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
9aea9530 | 92 | |
8b625114 JL |
93 | /* I2C addresses of SPD EEPROMs */ |
94 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
9aea9530 | 95 | |
8b625114 | 96 | /* These are used when DDR doesn't use SPD. */ |
6d0f6bcf JCPV |
97 | #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ |
98 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ | |
99 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 | |
100 | #define CONFIG_SYS_DDR_TIMING_1 0x37344321 | |
101 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
102 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ | |
103 | #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ | |
104 | #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ | |
42d1f039 | 105 | |
0ac6f8b7 WD |
106 | /* |
107 | * SDRAM on the Local Bus | |
108 | */ | |
6d0f6bcf JCPV |
109 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
110 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
42d1f039 | 111 | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
113 | #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ | |
42d1f039 | 114 | |
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ |
116 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
117 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ | |
118 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
119 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
120 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
0ac6f8b7 | 121 | |
14d0a02a | 122 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
42d1f039 | 123 | |
6d0f6bcf JCPV |
124 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
125 | #define CONFIG_SYS_RAMBOOT | |
42d1f039 | 126 | #else |
6d0f6bcf | 127 | #undef CONFIG_SYS_RAMBOOT |
42d1f039 WD |
128 | #endif |
129 | ||
00b1883a | 130 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
131 | #define CONFIG_SYS_FLASH_CFI |
132 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
0ac6f8b7 WD |
133 | |
134 | #undef CONFIG_CLOCKS_IN_MHZ | |
42d1f039 | 135 | |
42d1f039 | 136 | |
0ac6f8b7 WD |
137 | /* |
138 | * Local Bus Definitions | |
139 | */ | |
140 | ||
141 | /* | |
142 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 143 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
0ac6f8b7 WD |
144 | * |
145 | * For BR2, need: | |
146 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
147 | * port-size = 32-bits = BR2[19:20] = 11 | |
148 | * no parity checking = BR2[21:22] = 00 | |
149 | * SDRAM for MSEL = BR2[24:26] = 011 | |
150 | * Valid = BR[31] = 1 | |
151 | * | |
152 | * 0 4 8 12 16 20 24 28 | |
153 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
154 | * | |
6d0f6bcf | 155 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
0ac6f8b7 WD |
156 | * FIXME: the top 17 bits of BR2. |
157 | */ | |
158 | ||
6d0f6bcf | 159 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
0ac6f8b7 WD |
160 | |
161 | /* | |
6d0f6bcf | 162 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
0ac6f8b7 WD |
163 | * |
164 | * For OR2, need: | |
165 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
166 | * XAM, OR2[17:18] = 11 | |
167 | * 9 columns OR2[19-21] = 010 | |
168 | * 13 rows OR2[23-25] = 100 | |
169 | * EAD set for extra time OR[31] = 1 | |
170 | * | |
171 | * 0 4 8 12 16 20 24 28 | |
172 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
173 | */ | |
174 | ||
6d0f6bcf | 175 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
0ac6f8b7 | 176 | |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
178 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
179 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
180 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ | |
0ac6f8b7 | 181 | |
b0fe93ed KG |
182 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ |
183 | | LSDMR_RFCR5 \ | |
184 | | LSDMR_PRETOACT3 \ | |
185 | | LSDMR_ACTTORW3 \ | |
186 | | LSDMR_BL8 \ | |
187 | | LSDMR_WRC2 \ | |
188 | | LSDMR_CL3 \ | |
189 | | LSDMR_RFEN \ | |
0ac6f8b7 WD |
190 | ) |
191 | ||
192 | /* | |
193 | * SDRAM Controller configuration sequence. | |
194 | */ | |
b0fe93ed KG |
195 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
196 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
197 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
198 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
199 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
0ac6f8b7 | 200 | |
42d1f039 | 201 | |
9aea9530 WD |
202 | /* |
203 | * 32KB, 8-bit wide for ADS config reg | |
204 | */ | |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_BR4_PRELIM 0xf8000801 |
206 | #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 | |
207 | #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) | |
42d1f039 | 208 | |
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
210 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 211 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
42d1f039 | 212 | |
25ddd1fb | 213 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 214 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
42d1f039 | 215 | |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
217 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
42d1f039 WD |
218 | |
219 | /* Serial Port */ | |
0ac6f8b7 WD |
220 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
221 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
222 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
42d1f039 | 223 | |
53677ef1 | 224 | #define CONFIG_BAUDRATE 115200 |
42d1f039 | 225 | |
6d0f6bcf | 226 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
42d1f039 WD |
227 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
228 | ||
229 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_HUSH_PARSER |
231 | #ifdef CONFIG_SYS_HUSH_PARSER | |
42d1f039 WD |
232 | #endif |
233 | ||
0e16387d | 234 | /* pass open firmware flat tree */ |
5ce71580 KG |
235 | #define CONFIG_OF_LIBFDT 1 |
236 | #define CONFIG_OF_BOARD_SETUP 1 | |
237 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
0e16387d | 238 | |
20476726 JL |
239 | /* |
240 | * I2C | |
241 | */ | |
00f792e0 HS |
242 | #define CONFIG_SYS_I2C |
243 | #define CONFIG_SYS_I2C_FSL | |
244 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
245 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
246 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
247 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
42d1f039 | 248 | |
0ac6f8b7 | 249 | /* RapidIO MMU */ |
5af0fdd8 | 250 | #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ |
10795f42 | 251 | #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ |
5af0fdd8 | 252 | #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 |
6d0f6bcf | 253 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ |
0ac6f8b7 WD |
254 | |
255 | /* | |
256 | * General PCI | |
362dd830 | 257 | * Memory space is mapped 1-1, but I/O space must start from 0. |
0ac6f8b7 | 258 | */ |
5af0fdd8 | 259 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
10795f42 | 260 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 261 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
6d0f6bcf | 262 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 263 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 264 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
266 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
0ac6f8b7 WD |
267 | |
268 | #if defined(CONFIG_PCI) | |
42d1f039 | 269 | |
53677ef1 | 270 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
0ac6f8b7 WD |
271 | |
272 | #undef CONFIG_EEPRO100 | |
42d1f039 | 273 | #undef CONFIG_TULIP |
0ac6f8b7 WD |
274 | |
275 | #if !defined(CONFIG_PCI_PNP) | |
276 | #define PCI_ENET0_IOADDR 0xe0000000 | |
277 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
53677ef1 | 278 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
42d1f039 | 279 | #endif |
0ac6f8b7 WD |
280 | |
281 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 282 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
0ac6f8b7 WD |
283 | |
284 | #endif /* CONFIG_PCI */ | |
285 | ||
286 | ||
ccc091aa | 287 | #ifdef CONFIG_TSEC_ENET |
0ac6f8b7 | 288 | |
ccc091aa | 289 | #ifndef CONFIG_MII |
0ac6f8b7 | 290 | #define CONFIG_MII 1 /* MII PHY management */ |
ccc091aa | 291 | #endif |
255a3577 KP |
292 | #define CONFIG_TSEC1 1 |
293 | #define CONFIG_TSEC1_NAME "TSEC0" | |
294 | #define CONFIG_TSEC2 1 | |
295 | #define CONFIG_TSEC2_NAME "TSEC1" | |
0ac6f8b7 WD |
296 | #define TSEC1_PHY_ADDR 0 |
297 | #define TSEC2_PHY_ADDR 1 | |
298 | #define TSEC1_PHYIDX 0 | |
299 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
300 | #define TSEC1_FLAGS TSEC_GIGABIT |
301 | #define TSEC2_FLAGS TSEC_GIGABIT | |
d9b94f28 JL |
302 | |
303 | /* Options are: TSEC[0-1] */ | |
304 | #define CONFIG_ETHPRIME "TSEC0" | |
0ac6f8b7 | 305 | |
ccc091aa AF |
306 | #endif /* CONFIG_TSEC_ENET */ |
307 | ||
53677ef1 | 308 | #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ |
0ac6f8b7 | 309 | |
53677ef1 | 310 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ |
0ac6f8b7 WD |
311 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ |
312 | ||
313 | #if (CONFIG_ETHER_INDEX == 2) | |
42d1f039 WD |
314 | /* |
315 | * - Rx-CLK is CLK13 | |
316 | * - Tx-CLK is CLK14 | |
317 | * - Select bus for bd/buffers | |
318 | * - Full duplex | |
319 | */ | |
d4590da4 MF |
320 | #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
321 | #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
6d0f6bcf JCPV |
322 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
323 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) | |
42d1f039 | 324 | #define FETH2_RST 0x01 |
0ac6f8b7 | 325 | #elif (CONFIG_ETHER_INDEX == 3) |
42d1f039 WD |
326 | /* need more definitions here for FE3 */ |
327 | #define FETH3_RST 0x80 | |
53677ef1 | 328 | #endif /* CONFIG_ETHER_INDEX */ |
0ac6f8b7 | 329 | |
ccc091aa AF |
330 | #ifndef CONFIG_MII |
331 | #define CONFIG_MII 1 /* MII PHY management */ | |
332 | #endif | |
333 | ||
0ac6f8b7 WD |
334 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
335 | ||
42d1f039 WD |
336 | /* |
337 | * GPIO pins used for bit-banged MII communications | |
338 | */ | |
339 | #define MDIO_PORT 2 /* Port C */ | |
be225442 LCM |
340 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
341 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
342 | #define MDC_DECLARE MDIO_DECLARE | |
343 | ||
42d1f039 WD |
344 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) |
345 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) | |
346 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) | |
347 | ||
348 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ | |
349 | else iop->pdat &= ~0x00400000 | |
350 | ||
351 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ | |
352 | else iop->pdat &= ~0x00200000 | |
353 | ||
354 | #define MIIDELAY udelay(1) | |
0ac6f8b7 | 355 | |
42d1f039 WD |
356 | #endif |
357 | ||
0ac6f8b7 WD |
358 | |
359 | /* | |
360 | * Environment | |
361 | */ | |
6d0f6bcf | 362 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 363 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 364 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 JCPV |
365 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
366 | #define CONFIG_ENV_SIZE 0x2000 | |
42d1f039 | 367 | #else |
6d0f6bcf | 368 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 369 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 370 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 371 | #define CONFIG_ENV_SIZE 0x2000 |
42d1f039 WD |
372 | #endif |
373 | ||
0ac6f8b7 | 374 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
6d0f6bcf | 375 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
42d1f039 | 376 | |
659e2f67 JL |
377 | /* |
378 | * BOOTP options | |
379 | */ | |
380 | #define CONFIG_BOOTP_BOOTFILESIZE | |
381 | #define CONFIG_BOOTP_BOOTPATH | |
382 | #define CONFIG_BOOTP_GATEWAY | |
383 | #define CONFIG_BOOTP_HOSTNAME | |
384 | ||
385 | ||
2835e518 JL |
386 | /* |
387 | * Command line configuration. | |
388 | */ | |
2835e518 JL |
389 | #define CONFIG_CMD_PING |
390 | #define CONFIG_CMD_I2C | |
1c9aa76b | 391 | #define CONFIG_CMD_IRQ |
199e262e | 392 | #define CONFIG_CMD_REGINFO |
2835e518 JL |
393 | |
394 | #if defined(CONFIG_PCI) | |
395 | #define CONFIG_CMD_PCI | |
396 | #endif | |
397 | ||
398 | #if defined(CONFIG_ETHER_ON_FCC) | |
399 | #define CONFIG_CMD_MII | |
400 | #endif | |
401 | ||
0ac6f8b7 | 402 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
42d1f039 WD |
403 | |
404 | /* | |
405 | * Miscellaneous configurable options | |
406 | */ | |
6d0f6bcf | 407 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
408 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
409 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf | 410 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ |
0ac6f8b7 | 411 | |
2835e518 | 412 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 413 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
42d1f039 | 414 | #else |
6d0f6bcf | 415 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
42d1f039 | 416 | #endif |
0ac6f8b7 | 417 | |
6d0f6bcf JCPV |
418 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
419 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
420 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
42d1f039 WD |
421 | |
422 | /* | |
423 | * For booting Linux, the board info and command line data | |
a832ac41 | 424 | * have to be in the first 64 MB of memory, since this is |
42d1f039 WD |
425 | * the maximum mapped by the Linux kernel during initialization. |
426 | */ | |
a832ac41 KG |
427 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
428 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
42d1f039 | 429 | |
2835e518 | 430 | #if defined(CONFIG_CMD_KGDB) |
42d1f039 | 431 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
42d1f039 WD |
432 | #endif |
433 | ||
9aea9530 WD |
434 | |
435 | /* | |
436 | * Environment Configuration | |
437 | */ | |
42d1f039 | 438 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
10327dc5 | 439 | #define CONFIG_HAS_ETH0 |
e2ffd59b | 440 | #define CONFIG_HAS_ETH1 |
e2ffd59b | 441 | #define CONFIG_HAS_ETH2 |
5ce71580 | 442 | #define CONFIG_HAS_ETH3 |
42d1f039 WD |
443 | #endif |
444 | ||
0ac6f8b7 WD |
445 | #define CONFIG_IPADDR 192.168.1.253 |
446 | ||
447 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 448 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 449 | #define CONFIG_BOOTFILE "your.uImage" |
0ac6f8b7 WD |
450 | |
451 | #define CONFIG_SERVERIP 192.168.1.1 | |
452 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
453 | #define CONFIG_NETMASK 255.255.255.0 | |
454 | ||
455 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ | |
456 | ||
9aea9530 | 457 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
0ac6f8b7 WD |
458 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
459 | ||
460 | #define CONFIG_BAUDRATE 115200 | |
461 | ||
9aea9530 | 462 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
6b44a44e AF |
463 | "netdev=eth0\0" \ |
464 | "consoledev=ttyCPM\0" \ | |
465 | "ramdiskaddr=1000000\0" \ | |
466 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
467 | "fdtaddr=400000\0" \ | |
468 | "fdtfile=mpc8560ads.dtb\0" | |
0ac6f8b7 | 469 | |
9aea9530 | 470 | #define CONFIG_NFSBOOTCOMMAND \ |
6b44a44e AF |
471 | "setenv bootargs root=/dev/nfs rw " \ |
472 | "nfsroot=$serverip:$rootpath " \ | |
473 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
474 | "console=$consoledev,$baudrate $othbootargs;" \ | |
475 | "tftp $loadaddr $bootfile;" \ | |
476 | "tftp $fdtaddr $fdtfile;" \ | |
477 | "bootm $loadaddr - $fdtaddr" | |
0ac6f8b7 WD |
478 | |
479 | #define CONFIG_RAMBOOTCOMMAND \ | |
6b44a44e AF |
480 | "setenv bootargs root=/dev/ram rw " \ |
481 | "console=$consoledev,$baudrate $othbootargs;" \ | |
482 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
483 | "tftp $loadaddr $bootfile;" \ | |
484 | "tftp $fdtaddr $fdtfile;" \ | |
485 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
0ac6f8b7 WD |
486 | |
487 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
42d1f039 WD |
488 | |
489 | #endif /* __CONFIG_H */ |