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Commit | Line | Data |
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765547dc | 1 | /* |
e5fe96b1 | 2 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
765547dc | 3 | * |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
765547dc HW |
5 | */ |
6 | ||
7 | /* | |
8 | * mpc8569mds board configuration file | |
9 | */ | |
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
e5fe96b1 KG |
13 | #define CONFIG_SYS_SRIO |
14 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
15 | ||
765547dc HW |
16 | #define CONFIG_PCIE1 1 /* PCIE controller */ |
17 | #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ | |
842033e6 | 18 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
765547dc HW |
19 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
20 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
21 | #define CONFIG_QE /* Enable QE */ | |
22 | #define CONFIG_ENV_OVERWRITE | |
765547dc | 23 | |
765547dc HW |
24 | #ifndef __ASSEMBLY__ |
25 | extern unsigned long get_clock_freq(void); | |
26 | #endif | |
27 | /* Replace a call to get_clock_freq (after it is implemented)*/ | |
67351049 DL |
28 | #define CONFIG_SYS_CLK_FREQ 66666666 |
29 | #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
765547dc | 30 | |
d24f2d32 | 31 | #ifdef CONFIG_ATM |
c95d541e LY |
32 | #define CONFIG_PQ_MDS_PIB |
33 | #define CONFIG_PQ_MDS_PIB_ATM | |
34 | #endif | |
35 | ||
765547dc HW |
36 | /* |
37 | * These can be toggled for performance analysis, otherwise use default. | |
38 | */ | |
39 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
40 | #define CONFIG_BTB /* toggle branch predition */ | |
41 | ||
2ae18241 WD |
42 | #ifndef CONFIG_SYS_TEXT_BASE |
43 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
674ef7bd LY |
44 | #endif |
45 | ||
96196a1f HW |
46 | #ifndef CONFIG_SYS_MONITOR_BASE |
47 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
48 | #endif | |
49 | ||
765547dc HW |
50 | /* |
51 | * Only possible on E500 Version 2 or newer cores. | |
52 | */ | |
53 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
54 | ||
3aed5507 | 55 | #define CONFIG_BOARD_EARLY_INIT_R 1 |
7f52ed5e | 56 | #define CONFIG_HWCONFIG |
765547dc HW |
57 | |
58 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
59 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
60 | ||
674ef7bd LY |
61 | /* |
62 | * Config the L2 Cache as L2 SRAM | |
63 | */ | |
64 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
65 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
66 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
67 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
68 | ||
e46fedfe TT |
69 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
70 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
765547dc | 71 | |
8d22ddca | 72 | #if defined(CONFIG_NAND_SPL) |
e46fedfe | 73 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
674ef7bd LY |
74 | #endif |
75 | ||
765547dc | 76 | /* DDR Setup */ |
765547dc HW |
77 | #undef CONFIG_FSL_DDR_INTERACTIVE |
78 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
79 | #define CONFIG_DDR_SPD | |
765547dc HW |
80 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
81 | ||
82 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
83 | ||
84 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
85 | /* DDR is system memory*/ | |
86 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
87 | ||
765547dc HW |
88 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
89 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
90 | ||
91 | /* I2C addresses of SPD EEPROMs */ | |
c39f44dc | 92 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
765547dc HW |
93 | |
94 | /* These are used when DDR doesn't use SPD. */ | |
95 | #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ | |
96 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F | |
97 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 | |
98 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
99 | #define CONFIG_SYS_DDR_TIMING_0 0x00330004 | |
100 | #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 | |
101 | #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 | |
102 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 | |
103 | #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 | |
104 | #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 | |
105 | #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 | |
106 | #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 | |
107 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
108 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 | |
109 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
110 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
111 | #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 | |
112 | #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 | |
113 | #define CONFIG_SYS_DDR_CDR_1 0x80040000 | |
114 | #define CONFIG_SYS_DDR_CDR_2 0x00000000 | |
115 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
116 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
117 | #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ | |
118 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 | |
119 | ||
120 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
121 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
122 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
123 | ||
124 | #undef CONFIG_CLOCKS_IN_MHZ | |
125 | ||
126 | /* | |
127 | * Local Bus Definitions | |
128 | */ | |
129 | ||
130 | #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ | |
131 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
132 | ||
133 | #define CONFIG_SYS_BCSR_BASE 0xf8000000 | |
134 | #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE | |
135 | ||
136 | /*Chip select 0 - Flash*/ | |
674ef7bd LY |
137 | #define CONFIG_FLASH_BR_PRELIM 0xfe000801 |
138 | #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 | |
765547dc | 139 | |
399b53cb | 140 | /*Chip select 1 - BCSR*/ |
765547dc HW |
141 | #define CONFIG_SYS_BR1_PRELIM 0xf8000801 |
142 | #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 | |
143 | ||
399b53cb HW |
144 | /*Chip select 4 - PIB*/ |
145 | #define CONFIG_SYS_BR4_PRELIM 0xf8008801 | |
146 | #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 | |
147 | ||
148 | /*Chip select 5 - PIB*/ | |
149 | #define CONFIG_SYS_BR5_PRELIM 0xf8010801 | |
150 | #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 | |
151 | ||
765547dc HW |
152 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
153 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ | |
154 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
155 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
156 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
157 | ||
674ef7bd | 158 | #undef CONFIG_SYS_RAMBOOT |
674ef7bd | 159 | |
765547dc HW |
160 | #define CONFIG_FLASH_CFI_DRIVER |
161 | #define CONFIG_SYS_FLASH_CFI | |
162 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
163 | ||
a29155e1 | 164 | /* Chip select 3 - NAND */ |
674ef7bd | 165 | #ifndef CONFIG_NAND_SPL |
a29155e1 | 166 | #define CONFIG_SYS_NAND_BASE 0xFC000000 |
674ef7bd LY |
167 | #else |
168 | #define CONFIG_SYS_NAND_BASE 0xFFF00000 | |
169 | #endif | |
170 | ||
171 | /* NAND boot: 4K NAND loader config */ | |
172 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
173 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
174 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) | |
175 | #define CONFIG_SYS_NAND_U_BOOT_START \ | |
176 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) | |
177 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
178 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) | |
179 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
180 | ||
a29155e1 AV |
181 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
182 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } | |
183 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
a29155e1 AV |
184 | #define CONFIG_NAND_FSL_ELBC 1 |
185 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
a3055c58 | 186 | #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ |
a29155e1 AV |
187 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
188 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
189 | | BR_MS_FCM /* MSEL = FCM */ \ | |
190 | | BR_V) /* valid */ | |
a3055c58 | 191 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
a29155e1 AV |
192 | | OR_FCM_CSCT \ |
193 | | OR_FCM_CST \ | |
194 | | OR_FCM_CHT \ | |
195 | | OR_FCM_SCY_1 \ | |
196 | | OR_FCM_TRLX \ | |
197 | | OR_FCM_EHTR) | |
674ef7bd | 198 | |
674ef7bd LY |
199 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
200 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
a3055c58 MM |
201 | #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
202 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
765547dc | 203 | |
765547dc HW |
204 | #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ |
205 | #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ | |
206 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
207 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
208 | ||
209 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
210 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 211 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
765547dc | 212 | |
765547dc | 213 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
25ddd1fb | 214 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
765547dc HW |
215 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
216 | ||
217 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
fb279490 | 218 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
765547dc HW |
219 | |
220 | /* Serial Port */ | |
221 | #define CONFIG_CONS_INDEX 1 | |
765547dc HW |
222 | #define CONFIG_SYS_NS16550_SERIAL |
223 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
224 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
93341909 KG |
225 | #ifdef CONFIG_NAND_SPL |
226 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
227 | #endif | |
765547dc HW |
228 | |
229 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
230 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
231 | ||
232 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
233 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
234 | ||
765547dc HW |
235 | /* |
236 | * I2C | |
237 | */ | |
00f792e0 HS |
238 | #define CONFIG_SYS_I2C |
239 | #define CONFIG_SYS_I2C_FSL | |
240 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
241 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
242 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
243 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
244 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
245 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
246 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
765547dc HW |
247 | |
248 | /* | |
249 | * I2C2 EEPROM | |
250 | */ | |
251 | #define CONFIG_ID_EEPROM | |
252 | #ifdef CONFIG_ID_EEPROM | |
253 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
254 | #endif | |
255 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 | |
256 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
257 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
258 | ||
259 | #define PLPPAR1_I2C_BIT_MASK 0x0000000F | |
260 | #define PLPPAR1_I2C2_VAL 0x00000000 | |
7f52ed5e | 261 | #define PLPPAR1_ESDHC_VAL 0x0000000A |
765547dc HW |
262 | #define PLPDIR1_I2C_BIT_MASK 0x0000000F |
263 | #define PLPDIR1_I2C2_VAL 0x0000000F | |
7f52ed5e | 264 | #define PLPDIR1_ESDHC_VAL 0x00000006 |
c4ca10f1 AV |
265 | #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 |
266 | #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 | |
267 | #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 | |
268 | #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 | |
765547dc HW |
269 | |
270 | /* | |
271 | * General PCI | |
272 | * Memory Addresses are mapped 1-1. I/O is mapped from 0 | |
273 | */ | |
94f2bc48 | 274 | #define CONFIG_SYS_PCIE1_NAME "Slot" |
765547dc HW |
275 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
276 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 | |
277 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 | |
278 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
279 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 | |
280 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
281 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 | |
282 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
283 | ||
e5fe96b1 KG |
284 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 |
285 | #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 | |
286 | #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS | |
287 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ | |
765547dc HW |
288 | |
289 | #ifdef CONFIG_QE | |
290 | /* | |
291 | * QE UEC ethernet configuration | |
292 | */ | |
f82107f6 HW |
293 | #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ |
294 | #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ | |
765547dc HW |
295 | |
296 | #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) | |
297 | #define CONFIG_UEC_ETH | |
78b7a8ef | 298 | #define CONFIG_ETHPRIME "UEC0" |
765547dc HW |
299 | #define CONFIG_PHY_MODE_NEED_CHANGE |
300 | ||
301 | #define CONFIG_UEC_ETH1 /* GETH1 */ | |
302 | #define CONFIG_HAS_ETH0 | |
303 | ||
304 | #ifdef CONFIG_UEC_ETH1 | |
305 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ | |
306 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE | |
f82107f6 | 307 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
765547dc HW |
308 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 |
309 | #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH | |
310 | #define CONFIG_SYS_UEC1_PHY_ADDR 7 | |
865ff856 | 311 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 312 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 |
f82107f6 HW |
313 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
314 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ | |
315 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
316 | #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ | |
865ff856 | 317 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
582c55a0 | 318 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 |
f82107f6 HW |
319 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
320 | #endif /* CONFIG_UEC_ETH1 */ | |
765547dc HW |
321 | |
322 | #define CONFIG_UEC_ETH2 /* GETH2 */ | |
323 | #define CONFIG_HAS_ETH1 | |
324 | ||
325 | #ifdef CONFIG_UEC_ETH2 | |
326 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ | |
327 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE | |
f82107f6 | 328 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
765547dc HW |
329 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 |
330 | #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH | |
331 | #define CONFIG_SYS_UEC2_PHY_ADDR 1 | |
865ff856 | 332 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 333 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 |
f82107f6 HW |
334 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
335 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ | |
336 | #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH | |
337 | #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ | |
865ff856 | 338 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
582c55a0 | 339 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 |
f82107f6 HW |
340 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
341 | #endif /* CONFIG_UEC_ETH2 */ | |
765547dc | 342 | |
750098d3 HW |
343 | #define CONFIG_UEC_ETH3 /* GETH3 */ |
344 | #define CONFIG_HAS_ETH2 | |
345 | ||
346 | #ifdef CONFIG_UEC_ETH3 | |
347 | #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ | |
348 | #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE | |
f82107f6 | 349 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
750098d3 HW |
350 | #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 |
351 | #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH | |
352 | #define CONFIG_SYS_UEC3_PHY_ADDR 2 | |
865ff856 | 353 | #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 354 | #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 |
f82107f6 HW |
355 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
356 | #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ | |
357 | #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH | |
358 | #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ | |
865ff856 | 359 | #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
582c55a0 | 360 | #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 |
f82107f6 HW |
361 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
362 | #endif /* CONFIG_UEC_ETH3 */ | |
750098d3 HW |
363 | |
364 | #define CONFIG_UEC_ETH4 /* GETH4 */ | |
365 | #define CONFIG_HAS_ETH3 | |
366 | ||
367 | #ifdef CONFIG_UEC_ETH4 | |
368 | #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ | |
369 | #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE | |
f82107f6 | 370 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
750098d3 HW |
371 | #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 |
372 | #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH | |
373 | #define CONFIG_SYS_UEC4_PHY_ADDR 3 | |
865ff856 | 374 | #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 375 | #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 |
f82107f6 HW |
376 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
377 | #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ | |
378 | #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH | |
379 | #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ | |
865ff856 | 380 | #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
582c55a0 | 381 | #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 |
f82107f6 HW |
382 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
383 | #endif /* CONFIG_UEC_ETH4 */ | |
3bd8e532 HW |
384 | |
385 | #undef CONFIG_UEC_ETH6 /* GETH6 */ | |
386 | #define CONFIG_HAS_ETH5 | |
387 | ||
388 | #ifdef CONFIG_UEC_ETH6 | |
389 | #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ | |
390 | #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE | |
391 | #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE | |
392 | #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH | |
393 | #define CONFIG_SYS_UEC6_PHY_ADDR 4 | |
865ff856 | 394 | #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII |
582c55a0 | 395 | #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 |
3bd8e532 HW |
396 | #endif /* CONFIG_UEC_ETH6 */ |
397 | ||
398 | #undef CONFIG_UEC_ETH8 /* GETH8 */ | |
399 | #define CONFIG_HAS_ETH7 | |
400 | ||
401 | #ifdef CONFIG_UEC_ETH8 | |
402 | #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ | |
403 | #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE | |
404 | #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE | |
405 | #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH | |
406 | #define CONFIG_SYS_UEC8_PHY_ADDR 6 | |
865ff856 | 407 | #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII |
582c55a0 | 408 | #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 |
3bd8e532 HW |
409 | #endif /* CONFIG_UEC_ETH8 */ |
410 | ||
765547dc HW |
411 | #endif /* CONFIG_QE */ |
412 | ||
413 | #if defined(CONFIG_PCI) | |
765547dc HW |
414 | #undef CONFIG_EEPRO100 |
415 | #undef CONFIG_TULIP | |
416 | ||
417 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
418 | ||
419 | #endif /* CONFIG_PCI */ | |
420 | ||
765547dc HW |
421 | /* |
422 | * Environment | |
423 | */ | |
674ef7bd | 424 | #if defined(CONFIG_SYS_RAMBOOT) |
674ef7bd | 425 | #else |
fb279490 | 426 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
1b8e4fa1 HW |
427 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
428 | #define CONFIG_ENV_SIZE 0x2000 | |
674ef7bd | 429 | #endif |
765547dc HW |
430 | |
431 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
432 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
433 | ||
434 | /* QE microcode/firmware address */ | |
f2717b47 | 435 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
dcf1d774 | 436 | #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 |
765547dc HW |
437 | |
438 | /* | |
439 | * BOOTP options | |
440 | */ | |
441 | #define CONFIG_BOOTP_BOOTFILESIZE | |
442 | #define CONFIG_BOOTP_BOOTPATH | |
443 | #define CONFIG_BOOTP_GATEWAY | |
444 | #define CONFIG_BOOTP_HOSTNAME | |
445 | ||
765547dc HW |
446 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
447 | ||
7f52ed5e AV |
448 | #ifdef CONFIG_MMC |
449 | #define CONFIG_FSL_ESDHC | |
a6da8b81 | 450 | #define CONFIG_FSL_ESDHC_PIN_MUX |
7f52ed5e | 451 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
7f52ed5e AV |
452 | #endif |
453 | ||
765547dc HW |
454 | /* |
455 | * Miscellaneous configurable options | |
456 | */ | |
5be58f5f KP |
457 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
458 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
459 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
765547dc | 460 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
765547dc HW |
461 | #if defined(CONFIG_CMD_KGDB) |
462 | #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ | |
463 | #else | |
464 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
465 | #endif | |
765547dc HW |
466 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
467 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
468 | /* Boot Argument Buffer Size */ | |
765547dc HW |
469 | |
470 | /* | |
471 | * For booting Linux, the board info and command line data | |
a832ac41 | 472 | * have to be in the first 64 MB of memory, since this is |
765547dc HW |
473 | * the maximum mapped by the Linux kernel during initialization. |
474 | */ | |
a832ac41 KG |
475 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
476 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
765547dc | 477 | |
765547dc HW |
478 | #if defined(CONFIG_CMD_KGDB) |
479 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
765547dc HW |
480 | #endif |
481 | ||
482 | /* | |
483 | * Environment Configuration | |
484 | */ | |
485 | #define CONFIG_HOSTNAME mpc8569mds | |
8b3637c6 | 486 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 487 | #define CONFIG_BOOTFILE "your.uImage" |
765547dc HW |
488 | |
489 | #define CONFIG_SERVERIP 192.168.1.1 | |
490 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
491 | #define CONFIG_NETMASK 255.255.255.0 | |
492 | ||
493 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ | |
494 | ||
765547dc HW |
495 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
496 | "netdev=eth0\0" \ | |
497 | "consoledev=ttyS0\0" \ | |
498 | "ramdiskaddr=600000\0" \ | |
499 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
500 | "fdtaddr=400000\0" \ | |
501 | "fdtfile=your.fdt.dtb\0" \ | |
502 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
503 | "nfsroot=$serverip:$rootpath " \ | |
504 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
505 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
506 | "ramargs=setenv bootargs root=/dev/ram rw " \ | |
507 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
508 | ||
509 | #define CONFIG_NFSBOOTCOMMAND \ | |
510 | "run nfsargs;" \ | |
511 | "tftp $loadaddr $bootfile;" \ | |
512 | "tftp $fdtaddr $fdtfile;" \ | |
513 | "bootm $loadaddr - $fdtaddr" | |
514 | ||
515 | #define CONFIG_RAMBOOTCOMMAND \ | |
516 | "run ramargs;" \ | |
517 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
518 | "tftp $loadaddr $bootfile;" \ | |
519 | "bootm $loadaddr $ramdiskaddr" | |
520 | ||
521 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
522 | ||
523 | #endif /* __CONFIG_H */ |