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56523f12 | 1 | /* |
8f0b7cbe | 2 | * (C) Copyright 2003-2005 |
56523f12 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
45a212c4 | 5 | * (C) Copyright 2004-2006 |
56523f12 WD |
6 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
56523f12 WD |
30 | /* |
31 | * High Level Configuration Options | |
32 | * (easy to change) | |
33 | */ | |
34 | ||
5078cce8 WD |
35 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ |
36 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ | |
37 | #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ | |
38 | #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ | |
56523f12 | 39 | |
2ae18241 WD |
40 | /* |
41 | * Valid values for CONFIG_SYS_TEXT_BASE are: | |
42 | * 0xFC000000 boot low (standard configuration with room for | |
43 | * max 64 MByte Flash ROM) | |
44 | * 0xFFF00000 boot high (for a backup copy of U-Boot) | |
45 | * 0x00100000 boot from RAM (for testing only) | |
46 | */ | |
47 | #ifndef CONFIG_SYS_TEXT_BASE | |
48 | #define CONFIG_SYS_TEXT_BASE 0xFC000000 | |
49 | #endif | |
50 | ||
5196a7a0 | 51 | /* On a Cameron or on a FO300 board or ... */ |
6d3bc9b8 | 52 | #if !defined(CONFIG_CAM5200) && !defined(CONFIG_FO300) |
5078cce8 WD |
53 | #define CONFIG_STK52XX 1 /* ... on a STK52XX board */ |
54 | #endif | |
55 | ||
6d0f6bcf | 56 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ |
56523f12 | 57 | |
31d82672 BB |
58 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
59 | ||
56523f12 WD |
60 | /* |
61 | * Serial console configuration | |
62 | */ | |
5078cce8 WD |
63 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ |
64 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
6d0f6bcf | 65 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
bef92e21 | 66 | #define CONFIG_BOOTCOUNT_LIMIT 1 |
56523f12 | 67 | |
6d3bc9b8 | 68 | #ifdef CONFIG_FO300 |
6d0f6bcf | 69 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* enable null device */ |
6d3bc9b8 MB |
70 | #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ |
71 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */ | |
ddde6b7c | 72 | #define CONFIG_USB_BIN_FIXUP 1 /* for a buggy USB device */ |
6d3bc9b8 MB |
73 | #if 0 |
74 | #define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */ | |
75 | /* switch is closed */ | |
76 | #endif | |
77 | ||
78 | #undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */ | |
79 | /* switch is open */ | |
5196a7a0 | 80 | #endif /* CONFIG_FO300 */ |
6d3bc9b8 | 81 | |
7e6bf358 WD |
82 | #ifdef CONFIG_STK52XX |
83 | #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ | |
84 | #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ | |
85 | #define CONFIG_PS2SERIAL 6 /* .. on PSC6 */ | |
6d0f6bcf | 86 | #define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ |
7e6bf358 WD |
87 | #define CONFIG_BOARD_EARLY_INIT_R |
88 | #endif /* CONFIG_STK52XX */ | |
56523f12 | 89 | |
56523f12 WD |
90 | /* |
91 | * PCI Mapping: | |
92 | * 0x40000000 - 0x4fffffff - PCI Memory | |
93 | * 0x50000000 - 0x50ffffff - PCI IO Space | |
94 | */ | |
7e6bf358 WD |
95 | #ifdef CONFIG_STK52XX |
96 | #define CONFIG_PCI 1 | |
56523f12 | 97 | #define CONFIG_PCI_PNP 1 |
31a64923 | 98 | /* #define CONFIG_PCI_SCAN_SHOW 1 */ |
56523f12 WD |
99 | |
100 | #define CONFIG_PCI_MEM_BUS 0x40000000 | |
101 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
102 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
103 | ||
104 | #define CONFIG_PCI_IO_BUS 0x50000000 | |
105 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
106 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
107 | ||
108 | #define CONFIG_NET_MULTI 1 | |
cd65a3dc | 109 | #define CONFIG_EEPRO100 1 |
6d0f6bcf | 110 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
56523f12 | 111 | #define CONFIG_NS8382X 1 |
83e40ba7 | 112 | #endif /* CONFIG_STK52XX */ |
56523f12 | 113 | |
8f0b7cbe WD |
114 | /* |
115 | * Video console | |
116 | */ | |
5078cce8 | 117 | #ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */ |
8f0b7cbe WD |
118 | #define CONFIG_VIDEO |
119 | #define CONFIG_VIDEO_SM501 | |
120 | #define CONFIG_VIDEO_SM501_32BPP | |
121 | #define CONFIG_CFB_CONSOLE | |
122 | #define CONFIG_VIDEO_LOGO | |
6d3bc9b8 MB |
123 | |
124 | #ifndef CONFIG_FO300 | |
8f0b7cbe | 125 | #define CONFIG_CONSOLE_EXTRA_INFO |
6d3bc9b8 MB |
126 | #else |
127 | #define CONFIG_VIDEO_BMP_LOGO | |
128 | #endif | |
129 | ||
130 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
8f0b7cbe WD |
131 | #define CONFIG_VIDEO_SW_CURSOR |
132 | #define CONFIG_SPLASH_SCREEN | |
6d0f6bcf | 133 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
6d3bc9b8 | 134 | #endif /* #ifndef CONFIG_TQM5200S */ |
56523f12 | 135 | |
56523f12 WD |
136 | |
137 | /* Partitions */ | |
89c02e2c | 138 | #define CONFIG_MAC_PARTITION |
56523f12 | 139 | #define CONFIG_DOS_PARTITION |
8f0b7cbe | 140 | #define CONFIG_ISO_PARTITION |
56523f12 WD |
141 | |
142 | /* USB */ | |
6d3bc9b8 | 143 | #if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) |
7b59b3c7 | 144 | #define CONFIG_USB_OHCI_NEW |
6d0f6bcf | 145 | #define CONFIG_SYS_OHCI_BE_CONTROLLER |
56523f12 | 146 | #define CONFIG_USB_STORAGE |
afaac86f WD |
147 | #define CONFIG_CMD_FAT |
148 | #define CONFIG_CMD_USB | |
53e336e9 | 149 | |
6d0f6bcf JCPV |
150 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
151 | #define CONFIG_SYS_USB_OHCI_CPU_INIT | |
152 | #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB | |
153 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" | |
154 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
53e336e9 | 155 | |
56523f12 WD |
156 | #endif |
157 | ||
135ae006 | 158 | #ifndef CONFIG_CAM5200 |
56523f12 | 159 | /* POST support */ |
6d0f6bcf JCPV |
160 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
161 | CONFIG_SYS_POST_CPU | \ | |
162 | CONFIG_SYS_POST_I2C) | |
5078cce8 | 163 | #endif |
56523f12 WD |
164 | |
165 | #ifdef CONFIG_POST | |
56523f12 WD |
166 | /* preserve space for the post_word at end of on-chip SRAM */ |
167 | #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 | |
56523f12 WD |
168 | #endif |
169 | ||
56523f12 WD |
170 | |
171 | /* | |
a1aa0bb5 | 172 | * BOOTP options |
56523f12 | 173 | */ |
a1aa0bb5 JL |
174 | #define CONFIG_BOOTP_BOOTFILESIZE |
175 | #define CONFIG_BOOTP_BOOTPATH | |
176 | #define CONFIG_BOOTP_GATEWAY | |
177 | #define CONFIG_BOOTP_HOSTNAME | |
178 | ||
179 | ||
56523f12 | 180 | /* |
2694690e | 181 | * Command line configuration. |
56523f12 | 182 | */ |
2694690e JL |
183 | #include <config_cmd_default.h> |
184 | ||
185 | #define CONFIG_CMD_ASKENV | |
186 | #define CONFIG_CMD_DATE | |
187 | #define CONFIG_CMD_DHCP | |
188 | #define CONFIG_CMD_EEPROM | |
189 | #define CONFIG_CMD_I2C | |
190 | #define CONFIG_CMD_JFFS2 | |
191 | #define CONFIG_CMD_MII | |
192 | #define CONFIG_CMD_NFS | |
193 | #define CONFIG_CMD_PING | |
2694690e JL |
194 | #define CONFIG_CMD_REGINFO |
195 | #define CONFIG_CMD_SNTP | |
196 | #define CONFIG_CMD_BSP | |
197 | ||
198 | #ifdef CONFIG_VIDEO | |
199 | #define CONFIG_CMD_BMP | |
200 | #endif | |
201 | ||
202 | #ifdef CONFIG_PCI | |
2b2a587d | 203 | #define CONFIG_CMD_PCI |
f33fca22 | 204 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
2694690e JL |
205 | #endif |
206 | ||
207 | #if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) || defined(CONFIG_FO300) | |
208 | #define CONFIG_CMD_IDE | |
209 | #define CONFIG_CMD_FAT | |
210 | #define CONFIG_CMD_EXT2 | |
211 | #endif | |
212 | ||
213 | #if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) | |
214 | #define CONFIG_CFG_USB | |
215 | #define CONFIG_CFG_FAT | |
216 | #endif | |
217 | ||
af075ee9 JL |
218 | #ifdef CONFIG_POST |
219 | #define CONFIG_CMD_DIAG | |
220 | #endif | |
221 | ||
56523f12 | 222 | |
151ab83a WD |
223 | #define CONFIG_TIMESTAMP /* display image timestamps */ |
224 | ||
14d0a02a | 225 | #if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) |
6d0f6bcf | 226 | # define CONFIG_SYS_LOWBOOT 1 /* Boot low */ |
56523f12 WD |
227 | #endif |
228 | ||
229 | /* | |
230 | * Autobooting | |
231 | */ | |
232 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
233 | ||
81050926 | 234 | #define CONFIG_PREBOOT "echo;" \ |
4c4aca81 | 235 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
56523f12 WD |
236 | "echo" |
237 | ||
238 | #undef CONFIG_BOOTARGS | |
239 | ||
6d0f6bcf | 240 | #if defined(CONFIG_TQM5200_B) && !defined(CONFIG_SYS_LOWBOOT) |
78d620eb WD |
241 | # define ENV_UPDT \ |
242 | "update=protect off FFF00000 +${filesize};" \ | |
243 | "erase FFF00000 +${filesize};" \ | |
5078cce8 | 244 | "cp.b 200000 FFF00000 ${filesize};" \ |
78d620eb WD |
245 | "protect on FFF00000 +${filesize}\0" |
246 | #else /* default lowboot configuration */ | |
6d3bc9b8 | 247 | # define ENV_UPDT \ |
78d620eb WD |
248 | "update=protect off FC000000 +${filesize};" \ |
249 | "erase FC000000 +${filesize};" \ | |
6d3bc9b8 | 250 | "cp.b 200000 FC000000 ${filesize};" \ |
78d620eb WD |
251 | "protect on FC000000 +${filesize}\0" |
252 | #endif | |
5078cce8 | 253 | |
e1f601b5 | 254 | #if defined(CONFIG_TQM5200) |
6abaee42 | 255 | #define CUSTOM_ENV_SETTINGS \ |
e1f601b5 | 256 | "hostname=tqm5200\0" \ |
6abaee42 | 257 | "bootfile=/tftpboot/tqm5200/uImage\0" \ |
8f8416fa | 258 | "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \ |
6abaee42 | 259 | "u-boot=/tftpboot/tqm5200/u-boot.bin\0" |
e1f601b5 | 260 | #elif defined(CONFIG_CAM5200) |
1636d1c8 | 261 | #define CUSTOM_ENV_SETTINGS \ |
6abaee42 RT |
262 | "bootfile=cam5200/uImage\0" \ |
263 | "u-boot=cam5200/u-boot.bin\0" \ | |
74de7aef | 264 | "setup=tftp 200000 cam5200/setup.img; source 200000\0" |
6abaee42 RT |
265 | #endif |
266 | ||
a5cc5555 MK |
267 | #if defined(CONFIG_TQM5200_B) |
268 | #define ENV_FLASH_LAYOUT \ | |
269 | "fdt_addr=FC100000\0" \ | |
270 | "kernel_addr=FC140000\0" \ | |
271 | "ramdisk_addr=FC600000\0" | |
272 | #else /* !CONFIG_TQM5200_B */ | |
273 | #define ENV_FLASH_LAYOUT \ | |
274 | "fdt_addr=FC0A0000\0" \ | |
275 | "kernel_addr=FC0C0000\0" \ | |
276 | "ramdisk_addr=FC300000\0" | |
277 | #endif | |
278 | ||
81050926 | 279 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
56523f12 | 280 | "netdev=eth0\0" \ |
e1f601b5 | 281 | "console=ttyPSC0\0" \ |
a5cc5555 | 282 | ENV_FLASH_LAYOUT \ |
d78791ae BS |
283 | "kernel_addr_r=400000\0" \ |
284 | "fdt_addr_r=600000\0" \ | |
89c02e2c | 285 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
56523f12 | 286 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
56523f12 | 287 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b WD |
288 | "nfsroot=${serverip}:${rootpath}\0" \ |
289 | "addip=setenv bootargs ${bootargs} " \ | |
290 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
291 | ":${hostname}:${netdev}:off panic=1\0" \ | |
5078cce8 | 292 | "addcons=setenv bootargs ${bootargs} " \ |
8f8416fa | 293 | "console=${console},${baudrate}\0" \ |
e1f601b5 | 294 | "flash_self_old=sete console ttyS0; run ramargs addip addcons;" \ |
fe126d8b | 295 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
e1f601b5 BS |
296 | "flash_self=run ramargs addip addcons;" \ |
297 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
298 | "flash_nfs_old=sete console ttyS0; run nfsargs addip addcons;" \ | |
fe126d8b | 299 | "bootm ${kernel_addr}\0" \ |
e1f601b5 | 300 | "flash_nfs=run nfsargs addip addcons;" \ |
8f8416fa | 301 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
e1f601b5 BS |
302 | "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};" \ |
303 | "sete console ttyS0; run nfsargs addip addcons;bootm\0" \ | |
304 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
305 | "tftp ${fdt_addr_r} ${fdt_file}; " \ | |
306 | "run nfsargs addip addcons; " \ | |
307 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
6abaee42 | 308 | CUSTOM_ENV_SETTINGS \ |
5078cce8 WD |
309 | "load=tftp 200000 ${u-boot}\0" \ |
310 | ENV_UPDT \ | |
7e6bf358 | 311 | "" |
56523f12 WD |
312 | |
313 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
314 | ||
315 | /* | |
316 | * IPB Bus clocking configuration. | |
317 | */ | |
6d0f6bcf | 318 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
56523f12 | 319 | |
6d0f6bcf | 320 | #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200) |
56523f12 WD |
321 | /* |
322 | * PCI Bus clocking configuration | |
323 | * | |
324 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
6d0f6bcf | 325 | * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of |
c99512d6 | 326 | * 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. |
56523f12 | 327 | */ |
6d0f6bcf | 328 | #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ |
56523f12 WD |
329 | #endif |
330 | ||
331 | /* | |
332 | * I2C configuration | |
333 | */ | |
334 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
8f0b7cbe | 335 | #ifdef CONFIG_TQM5200_REV100 |
6d0f6bcf | 336 | #define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ |
56523f12 | 337 | #else |
6d0f6bcf | 338 | #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ |
56523f12 WD |
339 | #endif |
340 | ||
341 | /* | |
342 | * I2C clock frequency | |
343 | * | |
344 | * Please notice, that the resulting clock frequency could differ from the | |
345 | * configured value. This is because the I2C clock is derived from system | |
346 | * clock over a frequency divider with only a few divider values. U-boot | |
6d0f6bcf | 347 | * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated |
56523f12 WD |
348 | * approximation allways lies below the configured value, never above. |
349 | */ | |
6d0f6bcf JCPV |
350 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ |
351 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
56523f12 WD |
352 | |
353 | /* | |
354 | * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work | |
355 | * also). For other EEPROMs configuration should be verified. On Mini-FAP the | |
356 | * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the | |
357 | * same configuration could be used. | |
358 | */ | |
6d0f6bcf JCPV |
359 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ |
360 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
361 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ | |
362 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
56523f12 WD |
363 | |
364 | /* | |
365 | * HW-Monitor configuration on Mini-FAP | |
366 | */ | |
367 | #if defined (CONFIG_MINIFAP) | |
6d0f6bcf | 368 | #define CONFIG_SYS_I2C_HWMON_ADDR 0x2C |
56523f12 WD |
369 | #endif |
370 | ||
371 | /* List of I2C addresses to be verified by POST */ | |
56523f12 | 372 | #if defined (CONFIG_MINIFAP) |
60aaaa07 PT |
373 | #undef CONFIG_SYS_POST_I2C_ADDRS |
374 | #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \ | |
375 | CONFIG_SYS_I2C_HWMON_ADDR, \ | |
376 | CONFIG_SYS_I2C_SLAVE} | |
56523f12 WD |
377 | #endif |
378 | ||
379 | /* | |
380 | * Flash configuration | |
381 | */ | |
6d0f6bcf | 382 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 |
56523f12 | 383 | |
d9384de2 | 384 | #if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) |
6d0f6bcf | 385 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks |
7299712c | 386 | (= chip selects) */ |
6d0f6bcf JCPV |
387 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned int /* main flash device with */ |
388 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
389 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
390 | ||
391 | #define CONFIG_SYS_FLASH_ADDR0 0x555 | |
392 | #define CONFIG_SYS_FLASH_ADDR1 0x2AA | |
393 | #define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */ | |
394 | #define CONFIG_SYS_MAX_FLASH_SECT 128 | |
d9384de2 MB |
395 | #else |
396 | /* use CFI flash driver */ | |
6d0f6bcf | 397 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 398 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
6d0f6bcf JCPV |
399 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } |
400 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks | |
d9384de2 | 401 | (= chip selects) */ |
6d0f6bcf | 402 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ |
d9384de2 | 403 | #endif |
7299712c | 404 | |
6d0f6bcf JCPV |
405 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
406 | #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ | |
407 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
56523f12 | 408 | |
135ae006 | 409 | #if defined (CONFIG_CAM5200) |
6d0f6bcf | 410 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) |
5078cce8 | 411 | #elif defined(CONFIG_TQM5200_B) |
6d0f6bcf | 412 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00080000) |
45a212c4 | 413 | #else |
6d0f6bcf | 414 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) |
5078cce8 WD |
415 | #endif |
416 | ||
d534f5cc | 417 | /* Dynamic MTD partition support */ |
68d7d651 | 418 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
419 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
420 | #define CONFIG_FLASH_CFI_MTD | |
d534f5cc | 421 | #define MTDIDS_DEFAULT "nor0=TQM5200-0" |
5078cce8 WD |
422 | |
423 | #ifdef CONFIG_STK52XX | |
424 | # if defined(CONFIG_TQM5200_B) | |
6d0f6bcf | 425 | # if defined(CONFIG_SYS_LOWBOOT) |
5078cce8 | 426 | # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:1m(firmware)," \ |
a5cc5555 MK |
427 | "256k(dtb)," \ |
428 | "2304k(kernel)," \ | |
429 | "2560k(small-fs)," \ | |
45a212c4 | 430 | "2m(initrd)," \ |
5078cce8 WD |
431 | "8m(misc)," \ |
432 | "16m(big-fs)" | |
433 | # else /* highboot */ | |
434 | # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:2560k(kernel)," \ | |
435 | "3584k(small-fs)," \ | |
436 | "2m(initrd)," \ | |
437 | "8m(misc)," \ | |
438 | "15m(big-fs)," \ | |
439 | "1m(firmware)" | |
6d0f6bcf | 440 | # endif /* CONFIG_SYS_LOWBOOT */ |
5078cce8 WD |
441 | # else /* !CONFIG_TQM5200_B */ |
442 | # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ | |
e1f601b5 BS |
443 | "128k(dtb)," \ |
444 | "2304k(kernel)," \ | |
d534f5cc WD |
445 | "2m(initrd)," \ |
446 | "4m(small-fs)," \ | |
5078cce8 | 447 | "8m(misc)," \ |
e1f601b5 | 448 | "15m(big-fs)" |
5078cce8 | 449 | # endif /* CONFIG_TQM5200_B */ |
135ae006 | 450 | #elif defined (CONFIG_CAM5200) |
5078cce8 WD |
451 | # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \ |
452 | "1792k(kernel)," \ | |
7299712c MB |
453 | "5632k(rootfs)," \ |
454 | "24m(home)" | |
6d3bc9b8 MB |
455 | #elif defined (CONFIG_FO300) |
456 | # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ | |
457 | "1408k(kernel)," \ | |
458 | "2m(initrd)," \ | |
459 | "4m(small-fs)," \ | |
460 | "8m(misc)," \ | |
461 | "16m(big-fs)" | |
5078cce8 WD |
462 | #else |
463 | # error "Unknown Carrier Board" | |
464 | #endif /* CONFIG_STK52XX */ | |
56523f12 WD |
465 | |
466 | /* | |
467 | * Environment settings | |
468 | */ | |
5a1aceb0 | 469 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 470 | #define CONFIG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */ |
78d620eb | 471 | #if defined(CONFIG_TQM5200_B) || defined (CONFIG_CAM5200) |
0e8d1586 | 472 | #define CONFIG_ENV_SECT_SIZE 0x40000 |
45a212c4 | 473 | #else |
0e8d1586 | 474 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
5078cce8 | 475 | #endif /* CONFIG_TQM5200_B */ |
0e8d1586 JCPV |
476 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
477 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
56523f12 WD |
478 | |
479 | /* | |
480 | * Memory map | |
481 | */ | |
6d0f6bcf JCPV |
482 | #define CONFIG_SYS_MBAR 0xF0000000 |
483 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
484 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 | |
56523f12 WD |
485 | |
486 | /* Use ON-Chip SRAM until RAM will be available */ | |
6d0f6bcf | 487 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
56523f12 WD |
488 | #ifdef CONFIG_POST |
489 | /* preserve space for the post_word at end of on-chip SRAM */ | |
553f0982 | 490 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE |
56523f12 | 491 | #else |
553f0982 | 492 | #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE |
56523f12 WD |
493 | #endif |
494 | ||
495 | ||
25ddd1fb | 496 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 497 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
56523f12 | 498 | |
14d0a02a | 499 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf JCPV |
500 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
501 | # define CONFIG_SYS_RAMBOOT 1 | |
56523f12 WD |
502 | #endif |
503 | ||
135ae006 | 504 | #if defined (CONFIG_CAM5200) |
6d0f6bcf | 505 | # define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
5078cce8 | 506 | #elif defined(CONFIG_TQM5200_B) |
6d0f6bcf | 507 | # define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ |
45a212c4 | 508 | #else |
6d0f6bcf | 509 | # define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ |
5078cce8 WD |
510 | #endif |
511 | ||
6d0f6bcf JCPV |
512 | #define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */ |
513 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
56523f12 WD |
514 | |
515 | /* | |
516 | * Ethernet configuration | |
517 | */ | |
518 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 519 | #define CONFIG_MPC5xxx_FEC_MII100 |
56523f12 | 520 | /* |
86321fc1 | 521 | * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb |
56523f12 | 522 | */ |
86321fc1 | 523 | /* #define CONFIG_MPC5xxx_FEC_MII10 */ |
56523f12 WD |
524 | #define CONFIG_PHY_ADDR 0x00 |
525 | ||
526 | /* | |
527 | * GPIO configuration | |
528 | * | |
7299712c MB |
529 | * use CS1: Bit 0 (mask: 0x80000000): |
530 | * 1 -> Pin gpio_wkup_6 as second SDRAM chip select (mem_cs1). | |
56523f12 | 531 | * use ALT CAN position: Bits 2-3 (mask: 0x30000000): |
7299712c MB |
532 | * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. |
533 | * SPI on PSC3 according to PSC3 setting. Use for CAM5200. | |
534 | * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. | |
535 | * Use for REV200 STK52XX boards and FO300 boards. Do not use | |
536 | * with REV100 modules (because, there I2C1 is used as I2C bus). | |
537 | * use ATA: Bits 6-7 (mask 0x03000000): | |
538 | * 00 -> No ATA chip selects, csb_4/5 used as normal chip selects. | |
539 | * Use for CAM5200 board. | |
540 | * 01 -> ATA cs0/1 on csb_4/5. Use for the remaining boards. | |
541 | * use PSC6: Bits 9-11 (mask 0x00700000): | |
542 | * 000 -> use PSC6_0 to PSC6_3 as GPIO, PSC6 could not be used as | |
543 | * UART, CODEC or IrDA. | |
544 | * GPIO on PSC6_3 is used in post_hotkeys_pressed() to | |
545 | * enable extended POST tests. | |
546 | * Use for MINI-FAP and TQM5200_IB boards. | |
547 | * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used. | |
548 | * Extended POST test is not available. | |
549 | * Use for STK52xx, FO300 and CAM5200 boards. | |
95c44ec4 DZ |
550 | * WARNING: When the extended POST is enabled, these bits will |
551 | * be overridden by this code as GPIOs! | |
7299712c MB |
552 | * use PCI_DIS: Bit 16 (mask 0x00008000): |
553 | * 1 -> disable PCI controller (on CAM5200 board). | |
554 | * use USB: Bits 18-19 (mask 0x00003000): | |
555 | * 10 -> two UARTs (on FO300 and CAM5200). | |
556 | * use PSC3: Bits 20-23 (mask: 0x00000f00): | |
557 | * 0000 -> All PSC3 pins are GPIOs. | |
558 | * 1100 -> UART/SPI (on FO300 board). | |
559 | * 0100 -> UART (on CAM5200 board). | |
560 | * use PSC2: Bits 25:27 (mask: 0x00000030): | |
561 | * 000 -> All PSC2 pins are GPIOs. | |
562 | * 100 -> UART (on CAM5200 board). | |
563 | * 001 -> CAN1/2 on PSC2 pins. | |
95c44ec4 | 564 | * Use for REV100 STK52xx boards |
7299712c MB |
565 | * 01x -> Use AC97 (on FO300 board). |
566 | * use PSC1: Bits 29-31 (mask: 0x00000007): | |
567 | * 100 -> UART (on all boards). | |
56523f12 WD |
568 | */ |
569 | #if defined (CONFIG_MINIFAP) | |
6d0f6bcf | 570 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004 |
7e6bf358 | 571 | #elif defined (CONFIG_STK52XX) |
83e40ba7 | 572 | # if defined (CONFIG_STK52XX_REV100) |
6d0f6bcf | 573 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 |
83e40ba7 WD |
574 | # else /* STK52xx REV200 and above */ |
575 | # if defined (CONFIG_TQM5200_REV100) | |
576 | # error TQM5200 REV100 not supported on STK52XX REV200 or above | |
577 | # else/* TQM5200 REV200 and above */ | |
6d0f6bcf | 578 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x91500404 |
83e40ba7 | 579 | # endif |
8f0b7cbe | 580 | # endif |
6d3bc9b8 | 581 | #elif defined (CONFIG_FO300) |
6d0f6bcf | 582 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x91502c24 |
7299712c | 583 | #elif defined (CONFIG_CAM5200) |
6d0f6bcf | 584 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x8050A444 |
83e40ba7 | 585 | #else /* TMQ5200 Inbetriebnahme-Board */ |
6d0f6bcf | 586 | # define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004 |
56523f12 WD |
587 | #endif |
588 | ||
589 | /* | |
590 | * RTC configuration | |
591 | */ | |
4f562f14 WD |
592 | #if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100) |
593 | # define CONFIG_RTC_M41T11 1 | |
6d0f6bcf JCPV |
594 | # define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
595 | # define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* because Linux uses the same base | |
edd0b509 | 596 | year */ |
4f562f14 WD |
597 | #else |
598 | # define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ | |
599 | #endif | |
56523f12 WD |
600 | |
601 | /* | |
602 | * Miscellaneous configurable options | |
603 | */ | |
6d0f6bcf JCPV |
604 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
605 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
5078cce8 | 606 | |
2751a95a | 607 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
6d0f6bcf JCPV |
608 | #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ |
609 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
5078cce8 | 610 | |
6d0f6bcf | 611 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
2694690e | 612 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 613 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
2694690e JL |
614 | #endif |
615 | ||
616 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 617 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
56523f12 | 618 | #else |
6d0f6bcf | 619 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
56523f12 | 620 | #endif |
6d0f6bcf JCPV |
621 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
622 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
623 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
56523f12 WD |
624 | |
625 | /* Enable an alternate, more extensive memory test */ | |
6d0f6bcf | 626 | #define CONFIG_SYS_ALT_MEMTEST |
56523f12 | 627 | |
6d0f6bcf JCPV |
628 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
629 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
56523f12 | 630 | |
6d0f6bcf | 631 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
56523f12 | 632 | |
6d0f6bcf | 633 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
56523f12 WD |
634 | |
635 | /* | |
a1aa0bb5 | 636 | * Enable loopw command. |
56523f12 WD |
637 | */ |
638 | #define CONFIG_LOOPW | |
639 | ||
640 | /* | |
641 | * Various low-level settings | |
642 | */ | |
6d0f6bcf JCPV |
643 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
644 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
56523f12 | 645 | |
6d0f6bcf JCPV |
646 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
647 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
648 | #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 | |
649 | #define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ | |
56523f12 | 650 | #else |
6d0f6bcf | 651 | #define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ |
56523f12 | 652 | #endif |
6d0f6bcf JCPV |
653 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
654 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
56523f12 | 655 | |
7e6bf358 | 656 | #define CONFIG_LAST_STAGE_INIT |
7e6bf358 | 657 | |
56523f12 WD |
658 | /* |
659 | * SRAM - Do not map below 2 GB in address space, because this area is used | |
660 | * for SDRAM autosizing. | |
661 | */ | |
6d0f6bcf JCPV |
662 | #define CONFIG_SYS_CS2_START 0xE5000000 |
663 | #define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */ | |
664 | #define CONFIG_SYS_CS2_CFG 0x0004D930 | |
56523f12 WD |
665 | |
666 | /* | |
667 | * Grafic controller - Do not map below 2 GB in address space, because this | |
668 | * area is used for SDRAM autosizing. | |
669 | */ | |
8f0b7cbe | 670 | #define SM501_FB_BASE 0xE0000000 |
6d0f6bcf JCPV |
671 | #define CONFIG_SYS_CS1_START (SM501_FB_BASE) |
672 | #define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ | |
673 | #define CONFIG_SYS_CS1_CFG 0x8F48FF70 | |
674 | #define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 | |
56523f12 | 675 | |
6d0f6bcf JCPV |
676 | #define CONFIG_SYS_CS_BURST 0x00000000 |
677 | #define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ | |
56523f12 | 678 | |
7299712c | 679 | #if defined(CONFIG_CAM5200) |
6d0f6bcf JCPV |
680 | #define CONFIG_SYS_CS4_START 0xB0000000 |
681 | #define CONFIG_SYS_CS4_SIZE 0x00010000 | |
682 | #define CONFIG_SYS_CS4_CFG 0x01019C10 | |
7299712c | 683 | |
6d0f6bcf JCPV |
684 | #define CONFIG_SYS_CS5_START 0xD0000000 |
685 | #define CONFIG_SYS_CS5_SIZE 0x01208000 | |
686 | #define CONFIG_SYS_CS5_CFG 0x1414BF10 | |
7299712c MB |
687 | #endif |
688 | ||
6d0f6bcf | 689 | #define CONFIG_SYS_RESET_ADDRESS 0xff000000 |
56523f12 WD |
690 | |
691 | /*----------------------------------------------------------------------- | |
692 | * USB stuff | |
693 | *----------------------------------------------------------------------- | |
694 | */ | |
695 | #define CONFIG_USB_CLOCK 0x0001BBBB | |
696 | #define CONFIG_USB_CONFIG 0x00001000 | |
697 | ||
698 | /*----------------------------------------------------------------------- | |
699 | * IDE/ATA stuff Supports IDE harddisk | |
700 | *----------------------------------------------------------------------- | |
701 | */ | |
702 | ||
81050926 | 703 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
56523f12 | 704 | |
81050926 WD |
705 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ |
706 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
56523f12 | 707 | |
81050926 | 708 | #define CONFIG_IDE_RESET /* reset for ide supported */ |
56523f12 WD |
709 | #define CONFIG_IDE_PREINIT |
710 | ||
6d0f6bcf JCPV |
711 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
712 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ | |
56523f12 | 713 | |
6d0f6bcf | 714 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
56523f12 | 715 | |
6d0f6bcf | 716 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
56523f12 | 717 | |
95c44ec4 | 718 | /* Offset for data I/O */ |
6d0f6bcf | 719 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) |
56523f12 | 720 | |
95c44ec4 | 721 | /* Offset for normal register accesses */ |
6d0f6bcf | 722 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) |
56523f12 | 723 | |
95c44ec4 | 724 | /* Offset for alternate registers */ |
6d0f6bcf | 725 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) |
56523f12 | 726 | |
95c44ec4 | 727 | /* Interval between registers */ |
6d0f6bcf | 728 | #define CONFIG_SYS_ATA_STRIDE 4 |
56523f12 | 729 | |
33af3e66 | 730 | /* Support ATAPI devices */ |
95c44ec4 | 731 | #define CONFIG_ATAPI 1 |
33af3e66 | 732 | |
8f8416fa BS |
733 | /*----------------------------------------------------------------------- |
734 | * Open firmware flat tree support | |
735 | *----------------------------------------------------------------------- | |
736 | */ | |
cf2817a8 | 737 | #define CONFIG_OF_LIBFDT 1 |
8f8416fa BS |
738 | #define CONFIG_OF_BOARD_SETUP 1 |
739 | ||
8f8416fa BS |
740 | #define OF_CPU "PowerPC,5200@0" |
741 | #define OF_SOC "soc5200@f0000000" | |
742 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
743 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" | |
744 | ||
56523f12 | 745 | #endif /* __CONFIG_H */ |