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8993e54b | 1 | /* |
a99715b8 | 2 | * (C) Copyright 2007, 2008 DENX Software Engineering |
8993e54b RJ |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * ADS5121 board configuration file | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
8993e54b RJ |
30 | /* |
31 | * Memory map for the ADS5121 board: | |
32 | * | |
33 | * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) | |
34 | * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) | |
35 | * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) | |
36 | * 0x8200_0000 - 0x8200_001F CPLD (32 B) | |
5f91db7f JR |
37 | * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB) |
38 | * 0xA000_0000 - 0xAFFF_FFFF PCI memory space (256 MB) | |
39 | * 0xB000_0000 - 0xBFFF_FFFF PCI memory mapped I/O space (256 MB) | |
8993e54b RJ |
40 | * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) |
41 | */ | |
42 | ||
43 | /* | |
44 | * High Level Configuration Options | |
45 | */ | |
46 | #define CONFIG_E300 1 /* E300 Family */ | |
47 | #define CONFIG_MPC512X 1 /* MPC512X family */ | |
0e1bad47 YS |
48 | #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ |
49 | ||
50 | /* video */ | |
51 | #undef CONFIG_VIDEO | |
52 | ||
53 | #if defined(CONFIG_VIDEO) | |
54 | #define CONFIG_CFB_CONSOLE | |
55 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
56 | #endif | |
8993e54b | 57 | |
5f91db7f | 58 | /* CONFIG_PCI is defined at config time */ |
8993e54b RJ |
59 | |
60 | #define CFG_MPC512X_CLKIN 66000000 /* in Hz */ | |
61 | ||
62 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ | |
0e1bad47 | 63 | #define CONFIG_MISC_INIT_R |
8993e54b RJ |
64 | |
65 | #define CFG_IMMR 0x80000000 | |
0e1bad47 | 66 | #define CFG_DIU_ADDR (CFG_IMMR+0x2100) |
8993e54b RJ |
67 | |
68 | #define CFG_MEMTEST_START 0x00200000 /* memtest region */ | |
69 | #define CFG_MEMTEST_END 0x00400000 | |
70 | ||
71 | /* | |
72 | * DDR Setup - manually set all parameters as there's no SPD etc. | |
73 | */ | |
74 | #define CFG_DDR_SIZE 256 /* MB */ | |
75 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ | |
76 | #define CFG_SDRAM_BASE CFG_DDR_BASE | |
77 | ||
78 | /* DDR Controller Configuration | |
b1b54e35 WD |
79 | * |
80 | * SYS_CFG: | |
81 | * [31:31] MDDRC Soft Reset: Diabled | |
82 | * [30:30] DRAM CKE pin: Enabled | |
83 | * [29:29] DRAM CLK: Enabled | |
84 | * [28:28] Command Mode: Enabled (For initialization only) | |
85 | * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] | |
86 | * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] | |
87 | * [20:19] Read Test: DON'T USE | |
88 | * [18:18] Self Refresh: Enabled | |
89 | * [17:17] 16bit Mode: Disabled | |
90 | * [16:13] Ready Delay: 2 | |
91 | * [12:12] Half DQS Delay: Disabled | |
92 | * [11:11] Quarter DQS Delay: Disabled | |
93 | * [10:08] Write Delay: 2 | |
94 | * [07:07] Early ODT: Disabled | |
95 | * [06:06] On DIE Termination: Disabled | |
96 | * [05:05] FIFO Overflow Clear: DON'T USE here | |
97 | * [04:04] FIFO Underflow Clear: DON'T USE here | |
98 | * [03:03] FIFO Overflow Pending: DON'T USE here | |
99 | * [02:02] FIFO Underlfow Pending: DON'T USE here | |
100 | * [01:01] FIFO Overlfow Enabled: Enabled | |
101 | * [00:00] FIFO Underflow Enabled: Enabled | |
102 | * TIME_CFG0 | |
103 | * [31:16] DRAM Refresh Time: 0 CSB clocks | |
104 | * [15:8] DRAM Command Time: 0 CSB clocks | |
105 | * [07:00] DRAM Precharge Time: 0 CSB clocks | |
106 | * TIME_CFG1 | |
107 | * [31:26] DRAM tRFC: | |
108 | * [25:21] DRAM tWR1: | |
109 | * [20:17] DRAM tWRT1: | |
110 | * [16:11] DRAM tDRR: | |
111 | * [10:05] DRAM tRC: | |
112 | * [04:00] DRAM tRAS: | |
113 | * TIME_CFG2 | |
114 | * [31:28] DRAM tRCD: | |
115 | * [27:23] DRAM tFAW: | |
116 | * [22:19] DRAM tRTW1: | |
117 | * [18:15] DRAM tCCD: | |
118 | * [14:10] DRAM tRTP: | |
119 | * [09:05] DRAM tRP: | |
120 | * [04:00] DRAM tRPA | |
121 | */ | |
8993e54b | 122 | |
37e3c62f GB |
123 | #define CFG_MDDRC_SYS_CFG 0xF8604A00 |
124 | #define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00 | |
125 | #define CFG_MDDRC_SYS_CFG_EN 0xF0000000 | |
126 | #define CFG_MDDRC_TIME_CFG0 0x00003D2E | |
127 | #define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E | |
8993e54b RJ |
128 | #define CFG_MDDRC_TIME_CFG1 0x54EC1168 |
129 | #define CFG_MDDRC_TIME_CFG2 0x35210864 | |
130 | ||
131 | #define CFG_MICRON_NOP 0x01380000 | |
132 | #define CFG_MICRON_PCHG_ALL 0x01100400 | |
8993e54b RJ |
133 | #define CFG_MICRON_EM2 0x01020000 |
134 | #define CFG_MICRON_EM3 0x01030000 | |
135 | #define CFG_MICRON_EN_DLL 0x01010000 | |
8993e54b | 136 | #define CFG_MICRON_RFSH 0x01080000 |
37e3c62f | 137 | #define CFG_MICRON_INIT_DEV_OP 0x01000432 |
8993e54b | 138 | #define CFG_MICRON_OCD_DEFAULT 0x01010780 |
8993e54b RJ |
139 | |
140 | /* DDR Priority Manager Configuration */ | |
0e1bad47 YS |
141 | #define CFG_MDDRCGRP_PM_CFG1 0x00077777 |
142 | #define CFG_MDDRCGRP_PM_CFG2 0x00000000 | |
143 | #define CFG_MDDRCGRP_HIPRIO_CFG 0x00000001 | |
144 | #define CFG_MDDRCGRP_LUT0_MU 0xFFEEDDCC | |
145 | #define CFG_MDDRCGRP_LUT0_ML 0xBBAAAAAA | |
146 | #define CFG_MDDRCGRP_LUT1_MU 0x66666666 | |
147 | #define CFG_MDDRCGRP_LUT1_ML 0x55555555 | |
148 | #define CFG_MDDRCGRP_LUT2_MU 0x44444444 | |
8993e54b | 149 | #define CFG_MDDRCGRP_LUT2_ML 0x44444444 |
0e1bad47 | 150 | #define CFG_MDDRCGRP_LUT3_MU 0x55555555 |
8993e54b | 151 | #define CFG_MDDRCGRP_LUT3_ML 0x55555558 |
0e1bad47 YS |
152 | #define CFG_MDDRCGRP_LUT4_MU 0x11111111 |
153 | #define CFG_MDDRCGRP_LUT4_ML 0x11111122 | |
154 | #define CFG_MDDRCGRP_LUT0_AU 0xaaaaaaaa | |
155 | #define CFG_MDDRCGRP_LUT0_AL 0xaaaaaaaa | |
156 | #define CFG_MDDRCGRP_LUT1_AU 0x66666666 | |
157 | #define CFG_MDDRCGRP_LUT1_AL 0x66666666 | |
158 | #define CFG_MDDRCGRP_LUT2_AU 0x11111111 | |
8993e54b | 159 | #define CFG_MDDRCGRP_LUT2_AL 0x11111111 |
0e1bad47 | 160 | #define CFG_MDDRCGRP_LUT3_AU 0x11111111 |
8993e54b | 161 | #define CFG_MDDRCGRP_LUT3_AL 0x11111111 |
0e1bad47 | 162 | #define CFG_MDDRCGRP_LUT4_AU 0x11111111 |
8993e54b RJ |
163 | #define CFG_MDDRCGRP_LUT4_AL 0x11111111 |
164 | ||
165 | /* | |
166 | * NOR FLASH on the Local Bus | |
167 | */ | |
168 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ | |
169 | #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
170 | #define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */ | |
171 | #define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */ | |
172 | #define CFG_FLASH_USE_BUFFER_WRITE | |
173 | ||
174 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
53677ef1 | 175 | #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} |
8993e54b RJ |
176 | #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ |
177 | ||
178 | #undef CFG_FLASH_CHECKSUM | |
179 | ||
180 | /* | |
181 | * CPLD registers area is really only 32 bytes in size, but the smallest possible LP | |
182 | * window is 64KB | |
183 | */ | |
184 | #define CFG_CPLD_BASE 0x82000000 | |
185 | #define CFG_CPLD_SIZE 0x00010000 /* 64 KB */ | |
186 | ||
187 | #define CFG_SRAM_BASE 0x30000000 | |
188 | #define CFG_SRAM_SIZE 0x00020000 /* 128 KB */ | |
189 | ||
190 | #define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ | |
191 | #define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ | |
192 | ||
193 | /* Use SRAM for initial stack */ | |
194 | #define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */ | |
195 | #define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */ | |
196 | ||
197 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
198 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
199 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
200 | ||
201 | #define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */ | |
202 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
0e1bad47 YS |
203 | #ifdef CONFIG_FSL_DIU_FB |
204 | #define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ | |
205 | #else | |
206 | #define CFG_MALLOC_LEN (512 * 1024) | |
207 | #endif | |
8993e54b RJ |
208 | |
209 | /* | |
210 | * Serial Port | |
211 | */ | |
212 | #define CONFIG_CONS_INDEX 1 | |
213 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
214 | ||
215 | /* | |
216 | * Serial console configuration | |
217 | */ | |
218 | #define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ | |
219 | #if CONFIG_PSC_CONSOLE != 3 | |
220 | #error CONFIG_PSC_CONSOLE must be 3 | |
221 | #endif | |
222 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
223 | #define CFG_BAUDRATE_TABLE \ | |
224 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
225 | ||
226 | #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE | |
227 | #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR | |
228 | #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE | |
229 | #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR | |
230 | ||
231 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
232 | /* Use the HUSH parser */ | |
233 | #define CFG_HUSH_PARSER | |
234 | #ifdef CFG_HUSH_PARSER | |
235 | #define CFG_PROMPT_HUSH_PS2 "> " | |
236 | #endif | |
237 | ||
5f91db7f JR |
238 | /* |
239 | * PCI | |
240 | */ | |
241 | #ifdef CONFIG_PCI | |
242 | ||
243 | /* | |
244 | * General PCI | |
245 | */ | |
246 | #define CFG_PCI_MEM_BASE 0xA0000000 | |
247 | #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE | |
248 | #define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
249 | #define CFG_PCI_MMIO_BASE (CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE) | |
250 | #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE | |
251 | #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
252 | #define CFG_PCI_IO_BASE 0x00000000 | |
253 | #define CFG_PCI_IO_PHYS 0x84000000 | |
254 | #define CFG_PCI_IO_SIZE 0x01000000 /* 16M */ | |
255 | ||
256 | ||
257 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
258 | ||
259 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
260 | ||
261 | #endif | |
262 | ||
8993e54b RJ |
263 | /* I2C */ |
264 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
265 | #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ | |
266 | #define CONFIG_I2C_MULTI_BUS | |
267 | #define CONFIG_I2C_CMD_TREE | |
268 | #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ | |
269 | #define CFG_I2C_SLAVE 0x7F | |
270 | #if 0 | |
cf5933ba | 271 | #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
8993e54b RJ |
272 | #endif |
273 | ||
80020120 GB |
274 | /* |
275 | * EEPROM configuration | |
276 | */ | |
277 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ | |
278 | #define CFG_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ | |
de74b9ee | 279 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ |
80020120 GB |
280 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ |
281 | ||
8993e54b RJ |
282 | /* |
283 | * Ethernet configuration | |
284 | */ | |
285 | #define CONFIG_MPC512x_FEC 1 | |
286 | #define CONFIG_NET_MULTI | |
287 | #define CONFIG_PHY_ADDR 0x1 | |
288 | #define CONFIG_MII 1 /* MII PHY management */ | |
8993e54b RJ |
289 | |
290 | #if 0 | |
291 | /* | |
292 | * Configure on-board RTC | |
293 | */ | |
294 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
295 | #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
296 | #endif | |
297 | ||
298 | /* | |
299 | * Environment | |
300 | */ | |
301 | #define CFG_ENV_IS_IN_FLASH 1 | |
302 | /* This has to be a multiple of the Flash sector size */ | |
303 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) | |
304 | #define CFG_ENV_SIZE 0x2000 | |
305 | #define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ | |
306 | ||
307 | /* Address and size of Redundant Environment Sector */ | |
308 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) | |
309 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
310 | ||
311 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
312 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
313 | ||
e27f3a6e WD |
314 | #include <config_cmd_default.h> |
315 | ||
316 | #define CONFIG_CMD_ASKENV | |
317 | #define CONFIG_CMD_DHCP | |
318 | #define CONFIG_CMD_I2C | |
319 | #define CONFIG_CMD_MII | |
320 | #define CONFIG_CMD_NFS | |
321 | #define CONFIG_CMD_PING | |
322 | #define CONFIG_CMD_REGINFO | |
80020120 | 323 | #define CONFIG_CMD_EEPROM |
e27f3a6e | 324 | |
8993e54b | 325 | #if defined(CONFIG_PCI) |
e27f3a6e | 326 | #define CONFIG_CMD_PCI |
8993e54b RJ |
327 | #endif |
328 | ||
8993e54b RJ |
329 | /* |
330 | * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock. | |
331 | * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set | |
332 | * to 0xFFFF, watchdog timeouts after about 64s. For details refer | |
333 | * to chapter 36 of the MPC5121e Reference Manual. | |
334 | */ | |
66ffb188 | 335 | /* #define CONFIG_WATCHDOG */ /* enable watchdog */ |
8993e54b RJ |
336 | #define CFG_WATCHDOG_VALUE 0xFFFF |
337 | ||
338 | /* | |
339 | * Miscellaneous configurable options | |
340 | */ | |
341 | #define CFG_LONGHELP /* undef to save memory */ | |
342 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
343 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
344 | ||
e27f3a6e | 345 | #ifdef CONFIG_CMD_KGDB |
66ffb188 | 346 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
8993e54b | 347 | #else |
66ffb188 | 348 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
8993e54b RJ |
349 | #endif |
350 | ||
351 | ||
352 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ | |
353 | #define CFG_MAXARGS 16 /* max number of command args */ | |
354 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
355 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
356 | ||
357 | /* | |
358 | * For booting Linux, the board info and command line data | |
359 | * have to be in the first 8 MB of memory, since this is | |
360 | * the maximum mapped by the Linux kernel during initialization. | |
361 | */ | |
362 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
363 | ||
364 | /* Cache Configuration */ | |
365 | #define CFG_DCACHE_SIZE 32768 | |
366 | #define CFG_CACHELINE_SIZE 32 | |
e27f3a6e | 367 | #ifdef CONFIG_CMD_KGDB |
8993e54b RJ |
368 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
369 | #endif | |
370 | ||
371 | #define CFG_HID0_INIT 0x000000000 | |
372 | #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | |
373 | #define CFG_HID2 HID2_HBE | |
374 | ||
31d82672 BB |
375 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
376 | ||
8993e54b RJ |
377 | /* |
378 | * Internal Definitions | |
379 | * | |
380 | * Boot Flags | |
381 | */ | |
66ffb188 WD |
382 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
383 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
8993e54b | 384 | |
e27f3a6e | 385 | #ifdef CONFIG_CMD_KGDB |
8993e54b RJ |
386 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
387 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
388 | #endif | |
389 | ||
390 | /* | |
391 | * Environment Configuration | |
392 | */ | |
66ffb188 | 393 | #define CONFIG_TIMESTAMP |
8993e54b RJ |
394 | |
395 | #define CONFIG_HOSTNAME ads5121 | |
8d103071 | 396 | #define CONFIG_BOOTFILE ads5121/uImage |
5b0b2b6f | 397 | #define CONFIG_ROOTPATH /opt/eldk/pcc_6xx |
8993e54b | 398 | |
8d103071 | 399 | #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ |
8993e54b | 400 | |
e27f3a6e | 401 | #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ |
8993e54b RJ |
402 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
403 | ||
404 | #define CONFIG_BAUDRATE 115200 | |
405 | ||
406 | #define CONFIG_PREBOOT "echo;" \ | |
5b0b2b6f | 407 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
8993e54b RJ |
408 | "echo" |
409 | ||
410 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
8d103071 | 411 | "u-boot_addr_r=200000\0" \ |
5b0b2b6f | 412 | "kernel_addr_r=300000\0" \ |
8d103071 WD |
413 | "fdt_addr_r=400000\0" \ |
414 | "ramdisk_addr_r=500000\0" \ | |
415 | "u-boot_addr=FFF00000\0" \ | |
5b0b2b6f | 416 | "kernel_addr=FC040000\0" \ |
8d103071 WD |
417 | "fdt_addr=FC2C0000\0" \ |
418 | "ramdisk_addr=FC300000\0" \ | |
419 | "ramdiskfile=ads5121/uRamdisk\0" \ | |
420 | "fdtfile=ads5121/ads5121.dtb\0" \ | |
421 | "u-boot=ads5121/u-boot.bin\0" \ | |
8993e54b | 422 | "netdev=eth0\0" \ |
8d103071 | 423 | "consdev=ttyPSC0\0" \ |
8993e54b RJ |
424 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
425 | "nfsroot=${serverip}:${rootpath}\0" \ | |
426 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
427 | "addip=setenv bootargs ${bootargs} " \ | |
428 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
429 | ":${hostname}:${netdev}:off panic=1\0" \ | |
8d103071 WD |
430 | "addtty=setenv bootargs ${bootargs} " \ |
431 | "console=${consdev},${baudrate}\0" \ | |
8993e54b | 432 | "flash_nfs=run nfsargs addip addtty;" \ |
a99715b8 | 433 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ |
8993e54b | 434 | "flash_self=run ramargs addip addtty;" \ |
8d103071 WD |
435 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
436 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
437 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
438 | "run nfsargs addip addtty;" \ | |
439 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
440 | "net_self=tftp ${kernel_addr_r} ${bootfile};" \ | |
441 | "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ | |
a99715b8 | 442 | "tftp ${fdt_addr_r} ${fdtfile};" \ |
8d103071 | 443 | "run ramargs addip addtty;" \ |
5b0b2b6f | 444 | "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ |
a99715b8 | 445 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ |
8d103071 WD |
446 | "update=protect off ${u-boot_addr} +${filesize};" \ |
447 | "era ${u-boot_addr} +${filesize};" \ | |
448 | "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ | |
449 | "upd=run load update\0" \ | |
8993e54b RJ |
450 | "" |
451 | ||
8993e54b RJ |
452 | #define CONFIG_BOOTCOMMAND "run flash_self" |
453 | ||
281ff9a4 GB |
454 | #define CONFIG_OF_LIBFDT 1 |
455 | #define CONFIG_OF_BOARD_SETUP 1 | |
456 | ||
457 | #define OF_CPU "PowerPC,5121@0" | |
ac915283 JR |
458 | #define OF_SOC "soc@80000000" |
459 | #define OF_SOC_OLD "soc5121@80000000" | |
281ff9a4 | 460 | #define OF_TBCLK (bd->bi_busfreq / 4) |
ac915283 | 461 | #define OF_STDOUT_PATH "/soc@80000000/serial@11300" |
281ff9a4 | 462 | |
8993e54b | 463 | #endif /* __CONFIG_H */ |