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6ccec449 WD |
1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * Configuration settings for the ATSTK1002 CPU daughterboard | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
5d73bc7a | 27 | #include <asm/arch/hardware.h> |
a23e277c | 28 | |
e3e8d463 AB |
29 | #define CONFIG_AVR32 |
30 | #define CONFIG_AT32AP | |
31 | #define CONFIG_AT32AP7000 | |
32 | #define CONFIG_ATSTK1002 | |
33 | #define CONFIG_ATSTK1000 | |
6ccec449 | 34 | |
e3e8d463 | 35 | #define CONFIG_ATSTK1000_EXT_FLASH |
6ccec449 WD |
36 | |
37 | /* | |
38 | * Timer clock frequency. We're using the CPU-internal COUNT register | |
39 | * for this, so this is equivalent to the CPU core clock frequency | |
40 | */ | |
6d0f6bcf | 41 | #define CONFIG_SYS_HZ 1000 |
6ccec449 WD |
42 | |
43 | /* | |
a4f3aab6 EA |
44 | * Set up the PLL to run at 140 MHz, the CPU to run at the PLL |
45 | * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the | |
46 | * PLL frequency. | |
6d0f6bcf | 47 | * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz |
6ccec449 | 48 | */ |
e3e8d463 AB |
49 | #define CONFIG_PLL |
50 | #define CONFIG_SYS_POWER_MANAGER | |
6d0f6bcf JCPV |
51 | #define CONFIG_SYS_OSC0_HZ 20000000 |
52 | #define CONFIG_SYS_PLL0_DIV 1 | |
53 | #define CONFIG_SYS_PLL0_MUL 7 | |
54 | #define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16 | |
a4f3aab6 EA |
55 | /* |
56 | * Set the CPU running at: | |
6d0f6bcf | 57 | * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz |
a4f3aab6 | 58 | */ |
6d0f6bcf | 59 | #define CONFIG_SYS_CLKDIV_CPU 0 |
a4f3aab6 EA |
60 | /* |
61 | * Set the HSB running at: | |
6d0f6bcf | 62 | * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz |
a4f3aab6 | 63 | */ |
6d0f6bcf | 64 | #define CONFIG_SYS_CLKDIV_HSB 1 |
a4f3aab6 EA |
65 | /* |
66 | * Set the PBA running at: | |
6d0f6bcf | 67 | * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz |
a4f3aab6 | 68 | */ |
6d0f6bcf | 69 | #define CONFIG_SYS_CLKDIV_PBA 2 |
a4f3aab6 EA |
70 | /* |
71 | * Set the PBB running at: | |
6d0f6bcf | 72 | * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz |
a4f3aab6 | 73 | */ |
6d0f6bcf | 74 | #define CONFIG_SYS_CLKDIV_PBB 1 |
6ccec449 | 75 | |
1f36f73f HS |
76 | /* Reserve VM regions for SDRAM and NOR flash */ |
77 | #define CONFIG_SYS_NR_VM_REGIONS 2 | |
78 | ||
6ccec449 WD |
79 | /* |
80 | * The PLLOPT register controls the PLL like this: | |
81 | * icp = PLLOPT<2> | |
82 | * ivco = PLLOPT<1:0> | |
83 | * | |
84 | * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). | |
85 | */ | |
6d0f6bcf | 86 | #define CONFIG_SYS_PLL0_OPT 0x04 |
6ccec449 | 87 | |
f4278b71 AB |
88 | #define CONFIG_USART_BASE ATMEL_BASE_USART1 |
89 | #define CONFIG_USART_ID 1 | |
6ccec449 WD |
90 | |
91 | /* User serviceable stuff */ | |
e3e8d463 | 92 | #define CONFIG_DOS_PARTITION |
8e687518 | 93 | |
e3e8d463 AB |
94 | #define CONFIG_CMDLINE_TAG |
95 | #define CONFIG_SETUP_MEMORY_TAGS | |
96 | #define CONFIG_INITRD_TAG | |
6ccec449 WD |
97 | |
98 | #define CONFIG_STACKSIZE (2048) | |
99 | ||
100 | #define CONFIG_BAUDRATE 115200 | |
101 | #define CONFIG_BOOTARGS \ | |
e80e585b | 102 | "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1" |
1b804b22 HS |
103 | |
104 | #define CONFIG_BOOTCOMMAND \ | |
105 | "fsload; bootm $(fileaddr)" | |
106 | ||
107 | /* | |
108 | * Only interrupt autoboot if <space> is pressed. Otherwise, garbage | |
109 | * data on the serial line may interrupt the boot sequence. | |
110 | */ | |
696dd130 | 111 | #define CONFIG_BOOTDELAY 1 |
e3e8d463 AB |
112 | #define CONFIG_AUTOBOOT |
113 | #define CONFIG_AUTOBOOT_KEYED | |
c37207d7 WD |
114 | #define CONFIG_AUTOBOOT_PROMPT \ |
115 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay | |
1b804b22 HS |
116 | #define CONFIG_AUTOBOOT_DELAY_STR "d" |
117 | #define CONFIG_AUTOBOOT_STOP_STR " " | |
6ccec449 | 118 | |
9a24f477 | 119 | /* |
8b6684a6 HS |
120 | * After booting the board for the first time, new ethernet addresses |
121 | * should be generated and assigned to the environment variables | |
122 | * "ethaddr" and "eth1addr". This is normally done during production. | |
9a24f477 | 123 | */ |
e3e8d463 AB |
124 | #define CONFIG_OVERWRITE_ETHADDR_ONCE |
125 | #define CONFIG_NET_MULTI | |
9a24f477 | 126 | |
2fd90ce5 JL |
127 | /* |
128 | * BOOTP options | |
129 | */ | |
130 | #define CONFIG_BOOTP_SUBNETMASK | |
131 | #define CONFIG_BOOTP_GATEWAY | |
132 | ||
6ccec449 | 133 | |
0b361c91 JL |
134 | /* |
135 | * Command line configuration. | |
136 | */ | |
137 | #include <config_cmd_default.h> | |
138 | ||
139 | #define CONFIG_CMD_ASKENV | |
140 | #define CONFIG_CMD_DHCP | |
141 | #define CONFIG_CMD_EXT2 | |
142 | #define CONFIG_CMD_FAT | |
143 | #define CONFIG_CMD_JFFS2 | |
144 | #define CONFIG_CMD_MMC | |
0b361c91 | 145 | |
55ac7a74 | 146 | #undef CONFIG_CMD_FPGA |
0b361c91 | 147 | #undef CONFIG_CMD_SETGETDCR |
74de7aef | 148 | #undef CONFIG_CMD_SOURCE |
0b361c91 JL |
149 | #undef CONFIG_CMD_XIMG |
150 | ||
e3e8d463 AB |
151 | #define CONFIG_ATMEL_USART |
152 | #define CONFIG_MACB | |
153 | #define CONFIG_PORTMUX_PIO | |
6d0f6bcf | 154 | #define CONFIG_SYS_NR_PIOS 5 |
e3e8d463 AB |
155 | #define CONFIG_SYS_HSDRAMC |
156 | #define CONFIG_MMC | |
157 | #define CONFIG_ATMEL_MCI | |
6ccec449 | 158 | |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_DCACHE_LINESZ 32 |
160 | #define CONFIG_SYS_ICACHE_LINESZ 32 | |
6ccec449 WD |
161 | |
162 | #define CONFIG_NR_DRAM_BANKS 1 | |
163 | ||
164 | /* External flash on STK1000 */ | |
165 | #if 0 | |
6d0f6bcf | 166 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 167 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6ccec449 WD |
168 | #endif |
169 | ||
6d0f6bcf JCPV |
170 | #define CONFIG_SYS_FLASH_BASE 0x00000000 |
171 | #define CONFIG_SYS_FLASH_SIZE 0x800000 | |
172 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
173 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
6ccec449 | 174 | |
6d0f6bcf | 175 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
47293c18 | 176 | #define CONFIG_SYS_TEXT_BASE 0x00000000 |
6ccec449 | 177 | |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE |
179 | #define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE | |
180 | #define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE | |
6ccec449 | 181 | |
e3e8d463 | 182 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 183 | #define CONFIG_ENV_SIZE 65536 |
6d0f6bcf | 184 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE) |
6ccec449 | 185 | |
6d0f6bcf | 186 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) |
6ccec449 | 187 | |
6d0f6bcf JCPV |
188 | #define CONFIG_SYS_MALLOC_LEN (256*1024) |
189 | #define CONFIG_SYS_DMA_ALLOC_LEN (16384) | |
1f4f2121 | 190 | |
8269ab53 | 191 | /* Allow 4MB for the kernel run-time image */ |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) |
193 | #define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024) | |
6ccec449 WD |
194 | |
195 | /* Other configuration settings that shouldn't have to change all that often */ | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_PROMPT "U-Boot> " |
197 | #define CONFIG_SYS_CBSIZE 256 | |
198 | #define CONFIG_SYS_MAXARGS 16 | |
199 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
e3e8d463 | 200 | #define CONFIG_SYS_LONGHELP |
6d0f6bcf JCPV |
201 | |
202 | #define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE | |
203 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000) | |
204 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } | |
6ccec449 WD |
205 | |
206 | #endif /* __CONFIG_H */ |