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a7069ddf AB |
1 | /* |
2 | * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef _CONFIG_AXS101_H_ | |
8 | #define _CONFIG_AXS101_H_ | |
9 | ||
10 | /* | |
11 | * CPU configuration | |
12 | */ | |
a7069ddf AB |
13 | #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ |
14 | ||
a7069ddf AB |
15 | #define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 |
16 | #define ARC_APB_PERIPHERAL_BASE 0xF0000000 | |
17 | #define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000) | |
18 | #define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000) | |
19 | ||
20 | /* | |
21 | * Memory configuration | |
22 | */ | |
a7069ddf AB |
23 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
24 | ||
25 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 | |
26 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
0cdd7620 | 27 | #define CONFIG_SYS_SDRAM_SIZE 0x20000000 /* 512 Mb */ |
a7069ddf AB |
28 | |
29 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
30 | (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) | |
31 | ||
32 | #define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */ | |
33 | #define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */ | |
34 | #define CONFIG_SYS_LOAD_ADDR 0x82000000 | |
35 | ||
0241c313 AB |
36 | /* |
37 | * This board might be of different versions so handle it | |
38 | */ | |
39 | #define CONFIG_BOARD_TYPES | |
40 | #define CONFIG_BOARD_EARLY_INIT_F | |
41 | ||
a7069ddf AB |
42 | /* |
43 | * NAND Flash configuration | |
44 | */ | |
45 | #define CONFIG_SYS_NO_FLASH | |
46 | #define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000) | |
47 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
48 | ||
49 | /* | |
50 | * UART configuration | |
51 | * | |
52 | * CONFIG_CONS_INDEX = 1 - Debug UART | |
53 | * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB | |
54 | */ | |
55 | #define CONFIG_CONS_INDEX 4 | |
56 | #define CONFIG_SYS_NS16550 | |
57 | #define CONFIG_SYS_NS16550_SERIAL | |
58 | #define CONFIG_SYS_NS16550_REG_SIZE -4 | |
59 | #if (CONFIG_CONS_INDEX == 1) | |
60 | /* Debug UART */ | |
61 | # define CONFIG_SYS_NS16550_CLK 33333000 | |
62 | #else | |
63 | /* FPGA UARTs use different clock */ | |
64 | # define CONFIG_SYS_NS16550_CLK 33333333 | |
65 | #endif | |
66 | #define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000) | |
67 | #define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000) | |
68 | #define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000) | |
69 | #define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000) | |
70 | #define CONFIG_SYS_NS16550_MEM32 | |
71 | ||
72 | #define CONFIG_BAUDRATE 115200 | |
73 | /* | |
74 | * I2C configuration | |
75 | */ | |
678398b1 SR |
76 | #define CONFIG_SYS_I2C |
77 | #define CONFIG_SYS_I2C_DW | |
a7069ddf AB |
78 | #define CONFIG_I2C_ENV_EEPROM_BUS 2 |
79 | #define CONFIG_SYS_I2C_SPEED 100000 | |
678398b1 SR |
80 | #define CONFIG_SYS_I2C_SPEED1 100000 |
81 | #define CONFIG_SYS_I2C_SPEED2 100000 | |
a7069ddf | 82 | #define CONFIG_SYS_I2C_SLAVE 0 |
678398b1 SR |
83 | #define CONFIG_SYS_I2C_SLAVE1 0 |
84 | #define CONFIG_SYS_I2C_SLAVE2 0 | |
a7069ddf AB |
85 | #define CONFIG_SYS_I2C_BASE 0xE001D000 |
86 | #define CONFIG_SYS_I2C_BASE1 0xE001E000 | |
87 | #define CONFIG_SYS_I2C_BASE2 0xE001F000 | |
88 | #define CONFIG_SYS_I2C_BUS_MAX 3 | |
89 | #define IC_CLK 50 | |
90 | ||
91 | /* | |
92 | * EEPROM configuration | |
93 | */ | |
94 | #define CONFIG_SYS_I2C_MULTI_EEPROMS | |
95 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1) | |
96 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
97 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 | |
98 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
6bfa4420 | 99 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 64 |
a7069ddf AB |
100 | |
101 | /* | |
102 | * SD/MMC configuration | |
103 | */ | |
104 | #define CONFIG_MMC | |
105 | #define CONFIG_GENERIC_MMC | |
106 | #define CONFIG_DWMMC | |
107 | #define CONFIG_DOS_PARTITION | |
108 | ||
109 | /* | |
110 | * Ethernet PHY configuration | |
111 | */ | |
112 | #define CONFIG_PHYLIB | |
113 | #define CONFIG_MII | |
114 | #define CONFIG_PHY_GIGE | |
115 | ||
116 | /* | |
117 | * Ethernet configuration | |
118 | */ | |
a7069ddf | 119 | #define CONFIG_DW_AUTONEG |
a7069ddf AB |
120 | |
121 | /* | |
122 | * Command line configuration | |
123 | */ | |
a7069ddf AB |
124 | #define CONFIG_CMD_DHCP |
125 | #define CONFIG_CMD_EEPROM | |
a7069ddf AB |
126 | #define CONFIG_CMD_FAT |
127 | #define CONFIG_CMD_I2C | |
128 | #define CONFIG_CMD_MMC | |
129 | #define CONFIG_CMD_NAND | |
130 | #define CONFIG_CMD_PING | |
131 | #define CONFIG_CMD_RARP | |
132 | ||
133 | #define CONFIG_OF_LIBFDT | |
134 | ||
135 | #define CONFIG_AUTO_COMPLETE | |
136 | #define CONFIG_SYS_MAXARGS 16 | |
137 | ||
138 | /* | |
139 | * Environment settings | |
140 | */ | |
141 | #define CONFIG_ENV_IS_IN_EEPROM | |
142 | #define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */ | |
143 | #define CONFIG_ENV_OFFSET 0 | |
144 | ||
145 | /* | |
146 | * Environment configuration | |
147 | */ | |
148 | #define CONFIG_BOOTDELAY 3 | |
149 | #define CONFIG_BOOTFILE "uImage" | |
150 | #define CONFIG_BOOTARGS "console=ttyS3,115200n8" | |
151 | #define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR | |
152 | ||
153 | /* | |
154 | * Console configuration | |
155 | */ | |
156 | #define CONFIG_SYS_LONGHELP | |
a7069ddf AB |
157 | #define CONFIG_SYS_CBSIZE 256 |
158 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
159 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
160 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
161 | ||
162 | /* | |
163 | * Misc utility configuration | |
164 | */ | |
165 | #define CONFIG_BOUNCE_BUFFER | |
166 | ||
167 | #endif /* _CONFIG_AXS101_H_ */ |