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36b4e2dd | 1 | /* |
9fc376be | 2 | * (C) Copyright 2011 CompuLab, Ltd. |
36b4e2dd | 3 | * Mike Rapoport <mike@compulab.co.il> |
dccd9a0b | 4 | * Igor Grinberg <grinberg@compulab.co.il> |
36b4e2dd MR |
5 | * |
6 | * Based on omap3_beagle.h | |
7 | * (C) Copyright 2006-2008 | |
8 | * Texas Instruments. | |
9 | * Richard Woodruff <r-woodruff2@ti.com> | |
10 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
11 | * | |
b65a77a8 | 12 | * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards |
36b4e2dd | 13 | * |
1a459660 | 14 | * SPDX-License-Identifier: GPL-2.0+ |
36b4e2dd MR |
15 | */ |
16 | ||
17 | #ifndef __CONFIG_H | |
18 | #define __CONFIG_H | |
19 | ||
3709844f AA |
20 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
21 | ||
36b4e2dd MR |
22 | /* |
23 | * High Level Configuration Options | |
24 | */ | |
9fc376be | 25 | #define CONFIG_OMAP /* in a TI OMAP core */ |
308252ad | 26 | #define CONFIG_OMAP_GPIO |
9fc376be | 27 | #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ |
806d2792 | 28 | #define CONFIG_OMAP_COMMON |
c6f90e14 NM |
29 | /* Common ARM Erratas */ |
30 | #define CONFIG_ARM_ERRATA_454179 | |
31 | #define CONFIG_ARM_ERRATA_430973 | |
32 | #define CONFIG_ARM_ERRATA_621766 | |
36b4e2dd | 33 | |
36b4e2dd MR |
34 | #define CONFIG_SDRC /* The chip has SDRC controller */ |
35 | ||
36 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
987ec585 | 37 | #include <asm/arch/omap.h> |
36b4e2dd MR |
38 | |
39 | /* | |
40 | * Display CPU and Board information | |
41 | */ | |
9fc376be | 42 | #define CONFIG_DISPLAY_BOARDINFO |
36b4e2dd MR |
43 | |
44 | /* Clock Defines */ | |
45 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
46 | #define V_SCLK (V_OSCK >> 1) | |
47 | ||
36b4e2dd MR |
48 | #define CONFIG_MISC_INIT_R |
49 | ||
9fc376be NK |
50 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
51 | #define CONFIG_SETUP_MEMORY_TAGS | |
52 | #define CONFIG_INITRD_TAG | |
53 | #define CONFIG_REVISION_TAG | |
82309250 | 54 | #define CONFIG_SERIAL_TAG |
36b4e2dd MR |
55 | |
56 | /* | |
57 | * Size of malloc() pool | |
58 | */ | |
390cdcda | 59 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ |
9fc376be NK |
60 | /* Sector */ |
61 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) | |
36b4e2dd MR |
62 | |
63 | /* | |
64 | * Hardware drivers | |
65 | */ | |
66 | ||
67 | /* | |
68 | * NS16550 Configuration | |
69 | */ | |
70 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
71 | ||
36b4e2dd MR |
72 | #define CONFIG_SYS_NS16550_SERIAL |
73 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
74 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
75 | ||
76 | /* | |
77 | * select serial console configuration | |
78 | */ | |
79 | #define CONFIG_CONS_INDEX 3 | |
80 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
81 | #define CONFIG_SERIAL3 3 /* UART3 */ | |
82 | ||
83 | /* allow to overwrite serial and ethaddr */ | |
84 | #define CONFIG_ENV_OVERWRITE | |
85 | #define CONFIG_BAUDRATE 115200 | |
86 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
87 | 115200} | |
9fc376be NK |
88 | |
89 | #define CONFIG_GENERIC_MMC | |
90 | #define CONFIG_MMC | |
91 | #define CONFIG_OMAP_HSMMC | |
92 | #define CONFIG_DOS_PARTITION | |
36b4e2dd | 93 | |
36b4e2dd | 94 | /* USB */ |
9fc376be | 95 | #define CONFIG_USB_OMAP3 |
854a7836 NK |
96 | #define CONFIG_USB_EHCI |
97 | #define CONFIG_USB_EHCI_OMAP | |
95de1e2f | 98 | #define CONFIG_USB_MUSB_UDC |
9fc376be | 99 | #define CONFIG_TWL4030_USB |
36b4e2dd MR |
100 | |
101 | /* USB device configuration */ | |
9fc376be NK |
102 | #define CONFIG_USB_DEVICE |
103 | #define CONFIG_USB_TTY | |
104 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
36b4e2dd MR |
105 | |
106 | /* commands to include */ | |
36b4e2dd MR |
107 | #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ |
108 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
0b800a6b | 109 | #define CONFIG_MTD_PARTITIONS |
9fc376be NK |
110 | #define MTDIDS_DEFAULT "nand0=nand" |
111 | #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ | |
0b800a6b | 112 | "1920k(u-boot),256k(u-boot-env),"\ |
9fc376be | 113 | "4m(kernel),-(fs)" |
36b4e2dd | 114 | |
36b4e2dd | 115 | #define CONFIG_CMD_NAND /* NAND support */ |
36b4e2dd | 116 | |
36b4e2dd | 117 | #define CONFIG_SYS_NO_FLASH |
6789e84e HS |
118 | #define CONFIG_SYS_I2C |
119 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 | |
120 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
121 | #define CONFIG_SYS_I2C_OMAP34XX | |
82309250 NK |
122 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
123 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
52658fda | 124 | #define CONFIG_SYS_I2C_EEPROM_BUS 0 |
79874ae9 | 125 | #define CONFIG_I2C_MULTI_BUS |
36b4e2dd MR |
126 | |
127 | /* | |
128 | * TWL4030 | |
129 | */ | |
9fc376be NK |
130 | #define CONFIG_TWL4030_POWER |
131 | #define CONFIG_TWL4030_LED | |
36b4e2dd MR |
132 | |
133 | /* | |
134 | * Board NAND Info. | |
135 | */ | |
36b4e2dd MR |
136 | #define CONFIG_NAND_OMAP_GPMC |
137 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
138 | /* to access nand */ | |
139 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
140 | /* to access nand at */ | |
141 | /* CS0 */ | |
36b4e2dd MR |
142 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ |
143 | /* devices */ | |
7bb6e29b | 144 | |
36b4e2dd | 145 | /* Environment information */ |
36b4e2dd MR |
146 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
147 | "loadaddr=0x82000000\0" \ | |
148 | "usbtty=cdc_acm\0" \ | |
f3ef3609 | 149 | "console=ttyO2,115200n8\0" \ |
36b4e2dd MR |
150 | "mpurate=500\0" \ |
151 | "vram=12M\0" \ | |
152 | "dvimode=1024x768MR-16@60\0" \ | |
153 | "defaultdisplay=dvi\0" \ | |
154 | "mmcdev=0\0" \ | |
155 | "mmcroot=/dev/mmcblk0p2 rw\0" \ | |
0b800a6b | 156 | "mmcrootfstype=ext4 rootwait\0" \ |
36b4e2dd | 157 | "nandroot=/dev/mtdblock4 rw\0" \ |
0b800a6b | 158 | "nandrootfstype=ubifs\0" \ |
36b4e2dd MR |
159 | "mmcargs=setenv bootargs console=${console} " \ |
160 | "mpurate=${mpurate} " \ | |
161 | "vram=${vram} " \ | |
162 | "omapfb.mode=dvi:${dvimode} " \ | |
36b4e2dd MR |
163 | "omapdss.def_disp=${defaultdisplay} " \ |
164 | "root=${mmcroot} " \ | |
165 | "rootfstype=${mmcrootfstype}\0" \ | |
166 | "nandargs=setenv bootargs console=${console} " \ | |
167 | "mpurate=${mpurate} " \ | |
168 | "vram=${vram} " \ | |
169 | "omapfb.mode=dvi:${dvimode} " \ | |
36b4e2dd MR |
170 | "omapdss.def_disp=${defaultdisplay} " \ |
171 | "root=${nandroot} " \ | |
172 | "rootfstype=${nandrootfstype}\0" \ | |
173 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ | |
174 | "bootscript=echo Running bootscript from mmc ...; " \ | |
175 | "source ${loadaddr}\0" \ | |
176 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ | |
177 | "mmcboot=echo Booting from mmc ...; " \ | |
178 | "run mmcargs; " \ | |
179 | "bootm ${loadaddr}\0" \ | |
180 | "nandboot=echo Booting from nand ...; " \ | |
181 | "run nandargs; " \ | |
0b800a6b | 182 | "nand read ${loadaddr} 2a0000 400000; " \ |
36b4e2dd MR |
183 | "bootm ${loadaddr}\0" \ |
184 | ||
185 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 186 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
36b4e2dd MR |
187 | "if run loadbootscript; then " \ |
188 | "run bootscript; " \ | |
189 | "else " \ | |
190 | "if run loaduimage; then " \ | |
191 | "run mmcboot; " \ | |
192 | "else run nandboot; " \ | |
193 | "fi; " \ | |
194 | "fi; " \ | |
195 | "else run nandboot; fi" | |
196 | ||
36b4e2dd MR |
197 | /* |
198 | * Miscellaneous configurable options | |
199 | */ | |
41d7e702 IG |
200 | #define CONFIG_AUTO_COMPLETE |
201 | #define CONFIG_CMDLINE_EDITING | |
202 | #define CONFIG_TIMESTAMP | |
9fc376be | 203 | #define CONFIG_SYS_AUTOLOAD "no" |
36b4e2dd | 204 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
36b4e2dd MR |
205 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
206 | /* Print Buffer Size */ | |
207 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
208 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
209 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
210 | /* Boot Argument Buffer Size */ | |
211 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
212 | ||
213 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ | |
214 | /* works on */ | |
215 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
216 | 0x01F00000) /* 31MB */ | |
217 | ||
218 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ | |
219 | /* load address */ | |
220 | ||
221 | /* | |
222 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
223 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
224 | * This rate is divided by a local divisor. | |
225 | */ | |
226 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
227 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
36b4e2dd | 228 | |
36b4e2dd MR |
229 | /*----------------------------------------------------------------------- |
230 | * Physical Memory Map | |
231 | */ | |
232 | #define CONFIG_NR_DRAM_BANKS 1 /* CS1 is never populated */ | |
233 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
36b4e2dd | 234 | |
36b4e2dd MR |
235 | /*----------------------------------------------------------------------- |
236 | * FLASH and environment organization | |
237 | */ | |
238 | ||
239 | /* **** PISMO SUPPORT *** */ | |
36b4e2dd MR |
240 | /* Monitor at start of flash */ |
241 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
3530a35d | 242 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
36b4e2dd | 243 | |
9fc376be | 244 | #define CONFIG_ENV_IS_IN_NAND |
36b4e2dd | 245 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ |
6cbec7b3 | 246 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET |
36b4e2dd MR |
247 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET |
248 | ||
36b4e2dd | 249 | #if defined(CONFIG_CMD_NET) |
36b4e2dd MR |
250 | #define CONFIG_SMC911X |
251 | #define CONFIG_SMC911X_32_BIT | |
b65a77a8 IG |
252 | #define CM_T3X_SMC911X_BASE 0x2C000000 |
253 | #define SB_T35_SMC911X_BASE (CM_T3X_SMC911X_BASE + (16 << 20)) | |
254 | #define CONFIG_SMC911X_BASE CM_T3X_SMC911X_BASE | |
36b4e2dd MR |
255 | #endif /* (CONFIG_CMD_NET) */ |
256 | ||
257 | /* additions for new relocation code, must be added to all boards */ | |
258 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
259 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
260 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
261 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
262 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
263 | GENERATED_GBL_DATA_SIZE) | |
264 | ||
2b8754b2 | 265 | /* Status LED */ |
9fc376be NK |
266 | #define CONFIG_STATUS_LED /* Status LED enabled */ |
267 | #define CONFIG_BOARD_SPECIFIC_LED | |
ebc18afd IG |
268 | #define CONFIG_GPIO_LED |
269 | #define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ | |
270 | #define GREEN_LED_DEV 0 | |
271 | #define STATUS_LED_BIT GREEN_LED_GPIO | |
2b8754b2 IG |
272 | #define STATUS_LED_STATE STATUS_LED_ON |
273 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) | |
ebc18afd | 274 | #define STATUS_LED_BOOT GREEN_LED_DEV |
2b8754b2 | 275 | |
60e6bdcc NK |
276 | #define CONFIG_SPLASHIMAGE_GUARD |
277 | ||
2b8754b2 IG |
278 | /* GPIO banks */ |
279 | #ifdef CONFIG_STATUS_LED | |
9fc376be | 280 | #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ |
2b8754b2 IG |
281 | #endif |
282 | ||
7878ca51 NK |
283 | /* Display Configuration */ |
284 | #define CONFIG_OMAP3_GPIO_2 | |
6f72892a | 285 | #define CONFIG_OMAP3_GPIO_5 |
7878ca51 NK |
286 | #define CONFIG_VIDEO_OMAP3 |
287 | #define LCD_BPP LCD_COLOR16 | |
288 | ||
289 | #define CONFIG_LCD | |
f35034fe | 290 | #define CONFIG_SPLASH_SCREEN |
f82eb2fa | 291 | #define CONFIG_SPLASH_SOURCE |
f35034fe NK |
292 | #define CONFIG_CMD_BMP |
293 | #define CONFIG_BMP_16BPP | |
63c4f17b NK |
294 | #define CONFIG_SCF0403_LCD |
295 | ||
296 | #define CONFIG_OMAP3_SPI | |
7878ca51 | 297 | |
3e51b7c8 | 298 | /* Defines for SPL */ |
3e51b7c8 SR |
299 | #define CONFIG_SPL_FRAMEWORK |
300 | #define CONFIG_SPL_NAND_SIMPLE | |
301 | ||
302 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ | |
303 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ | |
e2ccdf89 | 304 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
205b4f33 | 305 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
3e51b7c8 SR |
306 | |
307 | #define CONFIG_SPL_BOARD_INIT | |
3e51b7c8 SR |
308 | #define CONFIG_SPL_NAND_BASE |
309 | #define CONFIG_SPL_NAND_DRIVERS | |
310 | #define CONFIG_SPL_NAND_ECC | |
3e51b7c8 SR |
311 | #define CONFIG_SPL_OMAP3_ID_NAND |
312 | #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" | |
313 | ||
314 | /* NAND boot config */ | |
315 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
316 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
317 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
318 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
319 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
320 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
321 | /* | |
322 | * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: | |
323 | * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT | |
324 | */ | |
325 | #define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ | |
326 | 10, 11, 12 } | |
327 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
328 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
329 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW | |
330 | ||
331 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
332 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
333 | ||
334 | #define CONFIG_SPL_TEXT_BASE 0x40200800 | |
fa2f81b0 TR |
335 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
336 | CONFIG_SPL_TEXT_BASE) | |
3e51b7c8 SR |
337 | |
338 | /* | |
339 | * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the | |
340 | * older x-loader implementations. And move the BSS area so that it | |
341 | * doesn't overlap with TEXT_BASE. | |
342 | */ | |
343 | #define CONFIG_SYS_TEXT_BASE 0x80008000 | |
344 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 | |
345 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ | |
346 | ||
347 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
348 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
349 | ||
bcb447e1 NK |
350 | /* EEPROM */ |
351 | #define CONFIG_CMD_EEPROM | |
352 | #define CONFIG_ENV_EEPROM_IS_ON_I2C | |
353 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
354 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
355 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
356 | #define CONFIG_SYS_EEPROM_SIZE 256 | |
357 | ||
358 | #define CONFIG_CMD_EEPROM_LAYOUT | |
359 | #define CONFIG_EEPROM_LAYOUT_HELP_STRING "legacy, v1, v2, v3" | |
360 | ||
36b4e2dd | 361 | #endif /* __CONFIG_H */ |