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b09bf723 IG |
1 | /* |
2 | * (C) Copyright 2013 CompuLab, Ltd. | |
3 | * Author: Igor Grinberg <grinberg@compulab.co.il> | |
4 | * | |
5 | * Configuration settings for the CompuLab CM-T3517 board | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | ||
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | /* | |
14 | * High Level Configuration Options | |
15 | */ | |
b09bf723 | 16 | #define CONFIG_CM_T3517 /* working with CM-T3517 */ |
b09bf723 IG |
17 | |
18 | #define CONFIG_SYS_TEXT_BASE 0x80008000 | |
19 | ||
20 | /* | |
21 | * This is needed for the DMA stuff. | |
22 | * Although the default iss 64, we still define it | |
23 | * to be on the safe side once the default is changed. | |
24 | */ | |
b09bf723 | 25 | |
b09bf723 | 26 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
987ec585 | 27 | #include <asm/arch/omap.h> |
b09bf723 | 28 | |
f3b44e8b DL |
29 | #define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517 |
30 | ||
b09bf723 IG |
31 | /* Clock Defines */ |
32 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
33 | #define V_SCLK (V_OSCK >> 1) | |
34 | ||
35 | #define CONFIG_MISC_INIT_R | |
36 | ||
b09bf723 IG |
37 | /* |
38 | * The early kernel mapping on ARM currently only maps from the base of DRAM | |
39 | * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. | |
40 | * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, | |
41 | * so that leaves DRAM base to DRAM base + 0x4000 available. | |
42 | */ | |
43 | #define CONFIG_SYS_BOOTMAPSZ 0x4000 | |
44 | ||
45 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
46 | #define CONFIG_SETUP_MEMORY_TAGS | |
47 | #define CONFIG_INITRD_TAG | |
48 | #define CONFIG_REVISION_TAG | |
49 | #define CONFIG_SERIAL_TAG | |
50 | ||
51 | /* | |
52 | * Size of malloc() pool | |
53 | */ | |
2f6e4bf8 | 54 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
b09bf723 IG |
55 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) |
56 | ||
57 | /* | |
58 | * Hardware drivers | |
59 | */ | |
60 | ||
61 | /* | |
62 | * NS16550 Configuration | |
63 | */ | |
b09bf723 IG |
64 | #define CONFIG_SYS_NS16550_SERIAL |
65 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
66 | #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
67 | ||
68 | /* | |
69 | * select serial console configuration | |
70 | */ | |
71 | #define CONFIG_CONS_INDEX 3 | |
72 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
73 | #define CONFIG_SERIAL3 3 /* UART3 */ | |
b09bf723 IG |
74 | |
75 | /* allow to overwrite serial and ethaddr */ | |
76 | #define CONFIG_ENV_OVERWRITE | |
b09bf723 IG |
77 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
78 | 115200} | |
79 | ||
011f5c13 IG |
80 | /* USB */ |
81 | #define CONFIG_USB_MUSB_AM35X | |
82 | ||
83 | #ifndef CONFIG_USB_MUSB_AM35X | |
84 | #define CONFIG_USB_OMAP3 | |
011f5c13 IG |
85 | #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146 |
86 | #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147 | |
87 | #else /* !CONFIG_USB_MUSB_AM35X */ | |
95de1e2f | 88 | #define CONFIG_USB_MUSB_PIO_ONLY |
011f5c13 IG |
89 | #endif /* CONFIG_USB_MUSB_AM35X */ |
90 | ||
b09bf723 | 91 | /* commands to include */ |
b09bf723 IG |
92 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
93 | #define CONFIG_MTD_PARTITIONS | |
94 | #define MTDIDS_DEFAULT "nand0=nand" | |
95 | #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ | |
96 | "1920k(u-boot),256k(u-boot-env),"\ | |
97 | "4m(kernel),-(fs)" | |
98 | ||
b09bf723 IG |
99 | #define CONFIG_SYS_I2C |
100 | #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 | |
101 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
b09bf723 IG |
102 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
103 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
104 | #define CONFIG_SYS_I2C_EEPROM_BUS 0 | |
105 | #define CONFIG_I2C_MULTI_BUS | |
106 | ||
107 | /* | |
108 | * Board NAND Info. | |
109 | */ | |
b09bf723 IG |
110 | #define CONFIG_NAND_OMAP_GPMC |
111 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
112 | /* to access nand */ | |
113 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
114 | /* to access nand at */ | |
115 | /* CS0 */ | |
116 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ | |
117 | /* devices */ | |
118 | ||
119 | /* Environment information */ | |
b09bf723 IG |
120 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
121 | "loadaddr=0x82000000\0" \ | |
122 | "baudrate=115200\0" \ | |
123 | "console=ttyO2,115200n8\0" \ | |
e093d0b2 | 124 | "netretry=yes\0" \ |
b09bf723 IG |
125 | "mpurate=auto\0" \ |
126 | "vram=12M\0" \ | |
127 | "dvimode=1024x768MR-16@60\0" \ | |
128 | "defaultdisplay=dvi\0" \ | |
129 | "mmcdev=0\0" \ | |
130 | "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ | |
131 | "mmcrootfstype=ext4\0" \ | |
132 | "nandroot=/dev/mtdblock4 rw\0" \ | |
133 | "nandrootfstype=ubifs\0" \ | |
134 | "mmcargs=setenv bootargs console=${console} " \ | |
135 | "mpurate=${mpurate} " \ | |
136 | "vram=${vram} " \ | |
137 | "omapfb.mode=dvi:${dvimode} " \ | |
138 | "omapdss.def_disp=${defaultdisplay} " \ | |
139 | "root=${mmcroot} " \ | |
140 | "rootfstype=${mmcrootfstype}\0" \ | |
141 | "nandargs=setenv bootargs console=${console} " \ | |
142 | "mpurate=${mpurate} " \ | |
143 | "vram=${vram} " \ | |
144 | "omapfb.mode=dvi:${dvimode} " \ | |
145 | "omapdss.def_disp=${defaultdisplay} " \ | |
146 | "root=${nandroot} " \ | |
147 | "rootfstype=${nandrootfstype}\0" \ | |
148 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ | |
149 | "bootscript=echo Running bootscript from mmc ...; " \ | |
150 | "source ${loadaddr}\0" \ | |
151 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ | |
152 | "mmcboot=echo Booting from mmc ...; " \ | |
153 | "run mmcargs; " \ | |
154 | "bootm ${loadaddr}\0" \ | |
155 | "nandboot=echo Booting from nand ...; " \ | |
156 | "run nandargs; " \ | |
157 | "nand read ${loadaddr} 2a0000 400000; " \ | |
158 | "bootm ${loadaddr}\0" \ | |
159 | ||
b09bf723 IG |
160 | #define CONFIG_BOOTCOMMAND \ |
161 | "mmc dev ${mmcdev}; if mmc rescan; then " \ | |
162 | "if run loadbootscript; then " \ | |
163 | "run bootscript; " \ | |
164 | "else " \ | |
165 | "if run loaduimage; then " \ | |
166 | "run mmcboot; " \ | |
167 | "else run nandboot; " \ | |
168 | "fi; " \ | |
169 | "fi; " \ | |
170 | "else run nandboot; fi" | |
171 | ||
172 | /* | |
173 | * Miscellaneous configurable options | |
174 | */ | |
175 | #define CONFIG_AUTO_COMPLETE | |
176 | #define CONFIG_CMDLINE_EDITING | |
177 | #define CONFIG_TIMESTAMP | |
178 | #define CONFIG_SYS_AUTOLOAD "no" | |
179 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
b09bf723 | 180 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
b09bf723 | 181 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
b09bf723 IG |
182 | |
183 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) | |
184 | ||
185 | /* | |
186 | * AM3517 has 12 GP timers, they can be driven by the system clock | |
187 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
188 | * This rate is divided by a local divisor. | |
189 | */ | |
190 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
191 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
192 | #define CONFIG_SYS_HZ 1000 | |
193 | ||
194 | /*----------------------------------------------------------------------- | |
195 | * Physical Memory Map | |
196 | */ | |
197 | #define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */ | |
198 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
199 | #define CONFIG_SYS_CS0_SIZE (256 << 20) | |
200 | ||
201 | /*----------------------------------------------------------------------- | |
202 | * FLASH and environment organization | |
203 | */ | |
204 | ||
205 | /* **** PISMO SUPPORT *** */ | |
206 | /* Monitor at start of flash */ | |
207 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
208 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ | |
209 | ||
7672d9d5 AF |
210 | #define CONFIG_ENV_OFFSET 0x260000 |
211 | #define CONFIG_ENV_ADDR 0x260000 | |
b09bf723 | 212 | |
a8a78c74 IG |
213 | #if defined(CONFIG_CMD_NET) |
214 | #define CONFIG_DRIVER_TI_EMAC | |
215 | #define CONFIG_DRIVER_TI_EMAC_USE_RMII | |
216 | #define CONFIG_MII | |
217 | #define CONFIG_SMC911X | |
218 | #define CONFIG_SMC911X_32_BIT | |
219 | #define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20)) | |
e093d0b2 DL |
220 | #define CONFIG_ARP_TIMEOUT 200UL |
221 | #define CONFIG_NET_RETRY_COUNT 5 | |
a8a78c74 IG |
222 | #endif /* CONFIG_CMD_NET */ |
223 | ||
b09bf723 IG |
224 | /* additions for new relocation code, must be added to all boards */ |
225 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
226 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
227 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
228 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
229 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
230 | GENERATED_GBL_DATA_SIZE) | |
231 | ||
232 | /* Status LED */ | |
b09bf723 | 233 | #define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */ |
b09bf723 | 234 | |
40bbd52a | 235 | /* Display Configuration */ |
40bbd52a IG |
236 | #define CONFIG_VIDEO_OMAP3 |
237 | #define LCD_BPP LCD_COLOR16 | |
238 | ||
40bbd52a IG |
239 | #define CONFIG_SPLASH_SCREEN |
240 | #define CONFIG_SPLASHIMAGE_GUARD | |
40bbd52a IG |
241 | #define CONFIG_BMP_16BPP |
242 | #define CONFIG_SCF0403_LCD | |
243 | ||
19a90ed6 | 244 | /* EEPROM */ |
19a90ed6 NK |
245 | #define CONFIG_ENV_EEPROM_IS_ON_I2C |
246 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
247 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
248 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
249 | #define CONFIG_SYS_EEPROM_SIZE 256 | |
250 | ||
b09bf723 | 251 | #endif /* __CONFIG_H */ |