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2da0fc0d DE |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
2da0fc0d DE |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
11 | #define CONFIG_405EP 1 /* this is a PPC405 CPU */ | |
2da0fc0d DE |
12 | #define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */ |
13 | ||
14 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 | |
15 | ||
16 | /* | |
17 | * Include common defines/options for all AMCC eval boards | |
18 | */ | |
19 | #define CONFIG_HOSTNAME dlvsion-10g | |
cccd4f40 | 20 | #define CONFIG_IDENT_STRING " dlvision-10g 0.06" |
2da0fc0d DE |
21 | #include "amcc-common.h" |
22 | ||
6e9e6c36 DE |
23 | #define CONFIG_BOARD_EARLY_INIT_F |
24 | #define CONFIG_BOARD_EARLY_INIT_R | |
b19bf834 | 25 | #define CONFIG_MISC_INIT_R |
2da0fc0d DE |
26 | #define CONFIG_LAST_STAGE_INIT |
27 | ||
28 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ | |
29 | ||
6cfa9eec | 30 | #undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */ |
6cfa9eec | 31 | |
2da0fc0d DE |
32 | /* |
33 | * Configure PLL | |
34 | */ | |
35 | #define PLLMR0_DEFAULT PLLMR0_266_133_66 | |
36 | #define PLLMR1_DEFAULT PLLMR1_266_133_66 | |
37 | ||
38 | /* new uImage format support */ | |
39 | #define CONFIG_FIT | |
40 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
9a4f479b | 41 | #define CONFIG_FIT_DISABLE_SHA256 |
2da0fc0d DE |
42 | |
43 | #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */ | |
44 | ||
45 | /* | |
46 | * Default environment variables | |
47 | */ | |
48 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
49 | CONFIG_AMCC_DEF_ENV \ | |
50 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
51 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
52 | "kernel_addr=fc000000\0" \ | |
53 | "fdt_addr=fc1e0000\0" \ | |
54 | "ramdisk_addr=fc200000\0" \ | |
55 | "" | |
56 | ||
57 | #define CONFIG_PHY_ADDR 4 /* PHY address */ | |
58 | #define CONFIG_HAS_ETH0 | |
59 | #define CONFIG_HAS_ETH1 | |
60 | #define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */ | |
61 | #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ | |
62 | ||
63 | /* | |
64 | * Commands additional to the ones defined in amcc-common.h | |
65 | */ | |
b19bf834 | 66 | #define CONFIG_CMD_DTT |
4fb9b41b DE |
67 | #undef CONFIG_CMD_DHCP |
68 | #undef CONFIG_CMD_DIAG | |
2da0fc0d | 69 | #undef CONFIG_CMD_EEPROM |
e1d1127a | 70 | #define CONFIG_CMD_I2C |
4fb9b41b | 71 | #undef CONFIG_CMD_IRQ |
2da0fc0d DE |
72 | |
73 | /* | |
74 | * SDRAM configuration (please see cpu/ppc/sdram.[ch]) | |
75 | */ | |
76 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
77 | ||
78 | /* SDRAM timings used in datasheet */ | |
79 | #define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */ | |
80 | #define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */ | |
81 | #define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */ | |
82 | #define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */ | |
83 | #define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */ | |
84 | ||
85 | /* | |
86 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. | |
87 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. | |
88 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD. | |
89 | * The Linux BASE_BAUD define should match this configuration. | |
90 | * baseBaud = cpuClock/(uartDivisor*16) | |
91 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, | |
92 | * set Linux BASE_BAUD to 403200. | |
93 | */ | |
94 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ | |
95 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ | |
96 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
97 | #define CONFIG_SYS_BASE_BAUD 691200 | |
98 | ||
99 | /* | |
100 | * I2C stuff | |
101 | */ | |
e313536f DE |
102 | #define CONFIG_SYS_I2C_PPC4XX |
103 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
880540de | 104 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 |
e313536f | 105 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F |
2da0fc0d | 106 | |
b46226bd | 107 | #define CONFIG_SYS_I2C_IHS |
e1d1127a | 108 | #define CONFIG_SYS_I2C_IHS_DUAL |
b46226bd DE |
109 | #define CONFIG_SYS_I2C_IHS_CH0 |
110 | #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 | |
111 | #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F | |
e1d1127a DE |
112 | #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 |
113 | #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F | |
b46226bd DE |
114 | #define CONFIG_SYS_I2C_IHS_CH1 |
115 | #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 | |
116 | #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F | |
e1d1127a DE |
117 | #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 |
118 | #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F | |
b46226bd | 119 | |
e1d1127a | 120 | #define CONFIG_SYS_SPD_BUS_NUM 4 |
b46226bd | 121 | |
2da0fc0d | 122 | /* Temp sensor/hwmon/dtt */ |
e1d1127a | 123 | #define CONFIG_SYS_DTT_BUS_NUM 4 |
2da0fc0d | 124 | #define CONFIG_DTT_LM63 1 /* National LM63 */ |
2ade7bee | 125 | #define CONFIG_DTT_SENSORS { 0x4c, 0x4e, 0x18 } /* Sensor addresses */ |
2da0fc0d | 126 | #define CONFIG_DTT_PWM_LOOKUPTABLE \ |
97ca7b3b DE |
127 | { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\ |
128 | { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } } | |
2da0fc0d DE |
129 | #define CONFIG_DTT_TACH_LIMIT 0xa10 |
130 | ||
e1d1127a DE |
131 | #define CONFIG_SYS_ICS8N3QV01_I2C {1, 3} |
132 | #define CONFIG_SYS_SIL1178_I2C {0, 2} | |
133 | #define CONFIG_SYS_DP501_I2C {0, 2} | |
e313536f | 134 | |
2da0fc0d DE |
135 | /* EBC peripherals */ |
136 | ||
137 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 | |
138 | #define CONFIG_SYS_FPGA0_BASE 0x7f100000 | |
139 | #define CONFIG_SYS_FPGA1_BASE 0x7f200000 | |
140 | #define CONFIG_SYS_LATCH_BASE 0x7f300000 | |
141 | ||
142 | #define CONFIG_SYS_FPGA_BASE(k) \ | |
143 | (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE) | |
144 | ||
145 | #define CONFIG_SYS_FPGA_DONE(k) \ | |
146 | (k ? 0x2000 : 0x1000) | |
147 | ||
148 | #define CONFIG_SYS_FPGA_COUNT 2 | |
149 | ||
aba27acf DE |
150 | #define CONFIG_SYS_FPGA_PTR { \ |
151 | (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \ | |
152 | (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE } | |
153 | ||
154 | #define CONFIG_SYS_FPGA_COMMON | |
155 | ||
2da0fc0d DE |
156 | #define CONFIG_SYS_LATCH0_RESET 0xffff |
157 | #define CONFIG_SYS_LATCH0_BOOT 0xffff | |
3e24dd2b | 158 | #define CONFIG_SYS_LATCH1_RESET 0xffbf |
2da0fc0d DE |
159 | #define CONFIG_SYS_LATCH1_BOOT 0xffff |
160 | ||
5cb4100f DE |
161 | #define CONFIG_SYS_FPGA_NO_RFL_HI |
162 | ||
2da0fc0d DE |
163 | /* |
164 | * FLASH organization | |
165 | */ | |
166 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
167 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
168 | ||
169 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
170 | ||
171 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
172 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ | |
173 | ||
174 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ | |
175 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ | |
176 | ||
177 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */ | |
2da0fc0d DE |
178 | |
179 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ | |
180 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */ | |
181 | ||
182 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
183 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ | |
184 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) | |
185 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
186 | ||
187 | /* Address and size of Redundant Environment Sector */ | |
188 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) | |
189 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
190 | #endif | |
191 | ||
192 | /* | |
193 | * PPC405 GPIO Configuration | |
194 | */ | |
195 | #define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ | |
196 | { \ | |
197 | /* GPIO Core 0 */ \ | |
198 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \ | |
199 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \ | |
200 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \ | |
201 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \ | |
202 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \ | |
203 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \ | |
204 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \ | |
205 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \ | |
206 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \ | |
207 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \ | |
208 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \ | |
209 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \ | |
210 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \ | |
211 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \ | |
212 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \ | |
213 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \ | |
214 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \ | |
215 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \ | |
216 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \ | |
217 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \ | |
218 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \ | |
219 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \ | |
220 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \ | |
221 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \ | |
222 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \ | |
223 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \ | |
224 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \ | |
225 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \ | |
226 | { GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \ | |
227 | { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \ | |
228 | { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \ | |
229 | { GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \ | |
230 | } \ | |
231 | } | |
232 | ||
233 | /* | |
234 | * Definitions for initial stack pointer and data area (in data cache) | |
235 | */ | |
236 | /* use on chip memory (OCM) for temperary stack until sdram is tested */ | |
237 | #define CONFIG_SYS_TEMP_STACK_OCM 1 | |
238 | ||
239 | /* On Chip Memory location */ | |
240 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 | |
241 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
242 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */ | |
243 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */ | |
244 | ||
2da0fc0d | 245 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
627b73e2 | 246 | (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE) |
2da0fc0d DE |
247 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
248 | ||
249 | /* | |
250 | * External Bus Controller (EBC) Setup | |
251 | */ | |
252 | ||
253 | /* Memory Bank 0 (NOR-flash) */ | |
254 | #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \ | |
255 | EBC_BXAP_FWT_ENCODE(8) | \ | |
256 | EBC_BXAP_BWT_ENCODE(7) | \ | |
257 | EBC_BXAP_BCE_DISABLE | \ | |
258 | EBC_BXAP_BCT_2TRANS | \ | |
259 | EBC_BXAP_CSN_ENCODE(0) | \ | |
260 | EBC_BXAP_OEN_ENCODE(2) | \ | |
261 | EBC_BXAP_WBN_ENCODE(2) | \ | |
262 | EBC_BXAP_WBF_ENCODE(2) | \ | |
263 | EBC_BXAP_TH_ENCODE(4) | \ | |
264 | EBC_BXAP_RE_DISABLED | \ | |
265 | EBC_BXAP_SOR_NONDELAYED | \ | |
266 | EBC_BXAP_BEM_WRITEONLY | \ | |
267 | EBC_BXAP_PEN_DISABLED) | |
268 | #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ | |
269 | EBC_BXCR_BS_64MB | \ | |
270 | EBC_BXCR_BU_RW | \ | |
271 | EBC_BXCR_BW_16BIT) | |
272 | ||
273 | /* Memory Bank 1 (FPGA0) */ | |
274 | #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ | |
275 | EBC_BXAP_TWT_ENCODE(5) | \ | |
276 | EBC_BXAP_BCE_DISABLE | \ | |
277 | EBC_BXAP_BCT_2TRANS | \ | |
278 | EBC_BXAP_CSN_ENCODE(0) | \ | |
279 | EBC_BXAP_OEN_ENCODE(2) | \ | |
280 | EBC_BXAP_WBN_ENCODE(1) | \ | |
281 | EBC_BXAP_WBF_ENCODE(1) | \ | |
282 | EBC_BXAP_TH_ENCODE(0) | \ | |
283 | EBC_BXAP_RE_DISABLED | \ | |
284 | EBC_BXAP_SOR_NONDELAYED | \ | |
285 | EBC_BXAP_BEM_WRITEONLY | \ | |
286 | EBC_BXAP_PEN_DISABLED) | |
287 | #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \ | |
288 | EBC_BXCR_BS_1MB | \ | |
289 | EBC_BXCR_BU_RW | \ | |
290 | EBC_BXCR_BW_16BIT) | |
291 | ||
292 | /* Memory Bank 2 (FPGA1) */ | |
293 | #define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \ | |
294 | EBC_BXAP_TWT_ENCODE(6) | \ | |
295 | EBC_BXAP_BCE_DISABLE | \ | |
296 | EBC_BXAP_BCT_2TRANS | \ | |
297 | EBC_BXAP_CSN_ENCODE(0) | \ | |
298 | EBC_BXAP_OEN_ENCODE(2) | \ | |
299 | EBC_BXAP_WBN_ENCODE(1) | \ | |
300 | EBC_BXAP_WBF_ENCODE(1) | \ | |
301 | EBC_BXAP_TH_ENCODE(0) | \ | |
302 | EBC_BXAP_RE_DISABLED | \ | |
303 | EBC_BXAP_SOR_NONDELAYED | \ | |
304 | EBC_BXAP_BEM_WRITEONLY | \ | |
305 | EBC_BXAP_PEN_DISABLED) | |
306 | #define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \ | |
307 | EBC_BXCR_BS_1MB | \ | |
308 | EBC_BXCR_BU_RW | \ | |
309 | EBC_BXCR_BW_16BIT) | |
310 | ||
311 | /* Memory Bank 3 (Latches) */ | |
312 | #define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \ | |
313 | EBC_BXAP_FWT_ENCODE(8) | \ | |
314 | EBC_BXAP_BWT_ENCODE(4) | \ | |
315 | EBC_BXAP_BCE_DISABLE | \ | |
316 | EBC_BXAP_BCT_2TRANS | \ | |
317 | EBC_BXAP_CSN_ENCODE(0) | \ | |
318 | EBC_BXAP_OEN_ENCODE(1) | \ | |
319 | EBC_BXAP_WBN_ENCODE(1) | \ | |
320 | EBC_BXAP_WBF_ENCODE(1) | \ | |
321 | EBC_BXAP_TH_ENCODE(2) | \ | |
322 | EBC_BXAP_RE_DISABLED | \ | |
323 | EBC_BXAP_SOR_NONDELAYED | \ | |
324 | EBC_BXAP_BEM_WRITEONLY | \ | |
325 | EBC_BXAP_PEN_DISABLED) | |
326 | #define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \ | |
327 | EBC_BXCR_BS_1MB | \ | |
328 | EBC_BXCR_BU_RW | \ | |
329 | EBC_BXCR_BW_16BIT) | |
330 | ||
331 | /* | |
332 | * OSD Setup | |
333 | */ | |
7749c84e | 334 | #define CONFIG_SYS_MPC92469AC |
2da0fc0d | 335 | #define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT |
e1d1127a DE |
336 | #define CONFIG_SYS_DP501_DIFFERENTIAL |
337 | #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ | |
2da0fc0d DE |
338 | |
339 | #endif /* __CONFIG_H */ |