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53d4a498 BS |
1 | /* |
2 | * (C) Copyright 2003-2007 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * Based on PRO Motion board config file by Andy Joseph, andy@promessdev.com | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
53d4a498 BS |
29 | /* |
30 | * High Level Configuration Options | |
31 | */ | |
32 | ||
53d4a498 BS |
33 | /* CPU and board */ |
34 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
35 | #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ | |
36 | #define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ | |
37 | ||
31d82672 | 38 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
53d4a498 | 39 | |
079a136c JL |
40 | /* |
41 | * BOOTP options | |
42 | */ | |
43 | #define CONFIG_BOOTP_BOOTFILESIZE | |
44 | #define CONFIG_BOOTP_BOOTPATH | |
45 | #define CONFIG_BOOTP_GATEWAY | |
46 | #define CONFIG_BOOTP_HOSTNAME | |
47 | ||
48 | ||
53d4a498 | 49 | /* |
5dc11a51 | 50 | * Command line configuration. |
53d4a498 | 51 | */ |
5dc11a51 | 52 | #include <config_cmd_default.h> |
53d4a498 | 53 | |
5dc11a51 JL |
54 | #define CONFIG_CMD_ASKENV |
55 | #define CONFIG_CMD_DHCP | |
56 | #define CONFIG_CMD_REGINFO | |
57 | #define CONFIG_CMD_IMMAP | |
58 | #define CONFIG_CMD_ELF | |
59 | #define CONFIG_CMD_MII | |
60 | #define CONFIG_CMD_BEDBUG | |
61 | #define CONFIG_CMD_NET | |
62 | #define CONFIG_CMD_PING | |
63 | #define CONFIG_CMD_IDE | |
64 | #define CONFIG_CMD_FAT | |
65 | #define CONFIG_CMD_JFFS2 | |
66 | #define CONFIG_CMD_I2C | |
67 | #define CONFIG_CMD_DATE | |
68 | #define CONFIG_CMD_EEPROM | |
69 | #define CONFIG_CMD_DTT | |
53d4a498 BS |
70 | |
71 | ||
72 | /* | |
73 | * Serial console configuration | |
74 | */ | |
75 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
76 | #define CONFIG_NETCONSOLE 1 /* network console */ | |
77 | #define CONFIG_BAUDRATE 115200 | |
6d0f6bcf | 78 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
53d4a498 BS |
79 | |
80 | ||
81 | /* | |
82 | * Ethernet configuration | |
83 | */ | |
84 | #define CONFIG_MPC5xxx_FEC 1 | |
86321fc1 | 85 | #define CONFIG_MPC5xxx_FEC_MII100 |
53d4a498 BS |
86 | #define CONFIG_PHY_ADDR 0x2 |
87 | #define CONFIG_PHY_TYPE 0x79c874 | |
c00125e0 | 88 | #define CONFIG_RESET_PHY_R 1 |
53d4a498 BS |
89 | |
90 | /* | |
91 | * Autobooting | |
92 | */ | |
93 | #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ | |
94 | #define CONFIG_AUTOBOOT_KEYED | |
95 | #define CONFIG_AUTOBOOT_STOP_STR "\x1b\x1b" | |
96 | #define DEBUG_BOOTKEYS 0 | |
97 | #undef CONFIG_AUTOBOOT_DELAY_STR | |
98 | #undef CONFIG_BOOTARGS | |
99 | #define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ | |
c37207d7 | 100 | "press \"<Esc><Esc>\" to stop\n", bootdelay |
53d4a498 BS |
101 | |
102 | #define CONFIG_ETHADDR 00:50:C2:40:10:00 | |
103 | #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 | |
104 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
105 | ||
106 | ||
107 | /* | |
108 | * Default environment settings | |
109 | */ | |
110 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
53d4a498 BS |
111 | "netdev=eth0\0" \ |
112 | "hostname=motionpro\0" \ | |
113 | "netmask=255.255.0.0\0" \ | |
114 | "ipaddr=192.168.160.22\0" \ | |
115 | "serverip=192.168.1.1\0" \ | |
116 | "gatewayip=192.168.1.1\0" \ | |
1f1369c3 | 117 | "console=ttyPSC0,115200\0" \ |
53d4a498 | 118 | "u-boot_addr=100000\0" \ |
1f1369c3 BS |
119 | "kernel_addr=200000\0" \ |
120 | "fdt_addr=400000\0" \ | |
121 | "ramdisk_addr=500000\0" \ | |
fa5c2ba1 | 122 | "multi_image_addr=800000\0" \ |
53d4a498 | 123 | "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ |
53d4a498 | 124 | "u-boot=/tftpboot/motionpro/u-boot.bin\0" \ |
1f1369c3 BS |
125 | "bootfile=/tftpboot/motionpro/uImage\0" \ |
126 | "fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \ | |
127 | "ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \ | |
fa5c2ba1 | 128 | "multi_image_file=kernel+initrd+dtb.img\0" \ |
7049288f | 129 | "load=tftp ${u-boot_addr} ${u-boot}\0" \ |
53d4a498 | 130 | "update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; " \ |
7049288f | 131 | "cp.b ${u-boot_addr} fff00000 ${filesize};" \ |
53d4a498 BS |
132 | "prot on fff00000 fff3ffff\0" \ |
133 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
53d4a498 | 134 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
7049288f | 135 | "nfsroot=${serverip}:${rootpath}\0" \ |
fa5c2ba1 | 136 | "fat_args=setenv bootargs rw\0" \ |
7049288f BS |
137 | "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ |
138 | "addip=setenv bootargs ${bootargs} " \ | |
139 | "ip=${ipaddr}:${serverip}:${gatewayip}:" \ | |
140 | "${netmask}:${hostname}:${netdev}:off panic=1 " \ | |
141 | "console=${console}\0" \ | |
142 | "net_nfs=tftp ${kernel_addr} ${bootfile}; " \ | |
143 | "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip; " \ | |
144 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
145 | "net_self=tftp ${kernel_addr} ${bootfile}; " \ | |
146 | "tftp ${fdt_addr} ${fdt_file}; " \ | |
147 | "tftp ${ramdisk_addr} ${ramdisk_file}; " \ | |
1f1369c3 | 148 | "run ramargs addip; " \ |
7049288f | 149 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
fa5c2ba1 BS |
150 | "fat_multi=run fat_args addip; fatload ide 0:1 " \ |
151 | "${multi_image_addr} ${multi_image_file}; " \ | |
152 | "bootm ${multi_image_addr}\0" \ | |
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153 | "" |
154 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
155 | ||
53d4a498 BS |
156 | /* |
157 | * do board-specific init | |
158 | */ | |
159 | #define CONFIG_BOARD_EARLY_INIT_R 1 | |
160 | ||
161 | ||
162 | /* | |
163 | * Low level configuration | |
164 | */ | |
165 | ||
166 | ||
167 | /* | |
d3afa1ee | 168 | * Clock configuration: SYS_XTALIN = 33MHz |
53d4a498 | 169 | */ |
6d0f6bcf | 170 | #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 |
53d4a498 | 171 | |
06241d50 BS |
172 | |
173 | /* | |
c99512d6 | 174 | * Set IPB speed to 100MHz |
06241d50 | 175 | */ |
6d0f6bcf | 176 | #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK |
06241d50 BS |
177 | |
178 | ||
53d4a498 BS |
179 | /* |
180 | * Memory map | |
181 | */ | |
182 | /* | |
183 | * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000. | |
184 | * Setting MBAR to otherwise will cause system hang when using SmartDMA such | |
185 | * as network commands. | |
186 | */ | |
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_MBAR 0xf0000000 |
188 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 | |
53d4a498 BS |
189 | |
190 | /* | |
191 | * If building for running out of SDRAM, then MBAR has been set up beforehand | |
192 | * (e.g., by the BDI). Otherwise we must specify the default boot-up value of | |
193 | * MBAR, as given in the doccumentation. | |
194 | */ | |
195 | #if TEXT_BASE == 0x00100000 | |
6d0f6bcf | 196 | #define CONFIG_SYS_DEFAULT_MBAR 0xf0000000 |
53d4a498 | 197 | #else /* TEXT_BASE != 0x00100000 */ |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_DEFAULT_MBAR 0x80000000 |
199 | #define CONFIG_SYS_LOWBOOT 1 | |
53d4a498 BS |
200 | #endif /* TEXT_BASE == 0x00100000 */ |
201 | ||
202 | /* Use SRAM until RAM will be available */ | |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM |
204 | #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE | |
53d4a498 | 205 | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for initial data */ |
207 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
208 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
53d4a498 | 209 | |
6d0f6bcf JCPV |
210 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
211 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
212 | #define CONFIG_SYS_RAMBOOT 1 | |
53d4a498 BS |
213 | #endif |
214 | ||
6d0f6bcf JCPV |
215 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for Monitor */ |
216 | #define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* 1 MiB for malloc() */ | |
217 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ | |
53d4a498 BS |
218 | |
219 | ||
220 | /* | |
221 | * Chip selects configuration | |
222 | */ | |
223 | /* Boot Chipselect */ | |
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE |
225 | #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE | |
226 | #define CONFIG_SYS_BOOTCS_CFG 0x00045D00 | |
53d4a498 BS |
227 | |
228 | /* Flash memory addressing */ | |
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE |
230 | #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE | |
231 | #define CONFIG_SYS_CS0_CFG CONFIG_SYS_BOOTCS_CFG | |
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232 | |
233 | /* Dual Port SRAM -- Kollmorgen Drive memory addressing */ | |
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_CS1_START 0x50000000 |
235 | #define CONFIG_SYS_CS1_SIZE 0x10000 | |
236 | #define CONFIG_SYS_CS1_CFG 0x05055800 | |
53d4a498 BS |
237 | |
238 | /* Local register access */ | |
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_CS2_START 0x50010000 |
240 | #define CONFIG_SYS_CS2_SIZE 0x10000 | |
241 | #define CONFIG_SYS_CS2_CFG 0x05055800 | |
53d4a498 BS |
242 | |
243 | /* Anybus CompactCom Module memory addressing */ | |
6d0f6bcf JCPV |
244 | #define CONFIG_SYS_CS3_START 0x50020000 |
245 | #define CONFIG_SYS_CS3_SIZE 0x10000 | |
246 | #define CONFIG_SYS_CS3_CFG 0x05055800 | |
53d4a498 BS |
247 | |
248 | /* No burst and dead cycle = 2 for all CSs */ | |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_CS_BURST 0x00000000 |
250 | #define CONFIG_SYS_CS_DEADCYCLE 0x22222222 | |
53d4a498 BS |
251 | |
252 | ||
253 | /* | |
254 | * SDRAM configuration | |
255 | */ | |
d3afa1ee BS |
256 | /* 2 x MT48LC16M16A2BG-75 IT:D, CASL 3, 32 bit data bus */ |
257 | #define SDRAM_CONFIG1 0x62322900 | |
258 | #define SDRAM_CONFIG2 0x88c70000 | |
259 | #define SDRAM_CONTROL 0x504f0000 | |
260 | #define SDRAM_MODE 0x00cd0000 | |
53d4a498 BS |
261 | |
262 | ||
263 | /* | |
264 | * Flash configuration | |
265 | */ | |
6d0f6bcf | 266 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
00b1883a | 267 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
268 | #define CONFIG_SYS_FLASH_BASE 0xff000000 |
269 | #define CONFIG_SYS_FLASH_SIZE 0x01000000 | |
270 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ | |
271 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
272 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ | |
53d4a498 BS |
273 | #define CONFIG_FLASH_16BIT /* Flash is 16-bit */ |
274 | ||
7d98ba77 PK |
275 | /* |
276 | * MTD configuration | |
277 | */ | |
68d7d651 | 278 | #define CONFIG_CMD_MTDPARTS |
942556a9 SR |
279 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
280 | #define CONFIG_FLASH_CFI_MTD | |
7d98ba77 PK |
281 | #define MTDIDS_DEFAULT "nor0=motionpro-0" |
282 | #define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \ | |
283 | "13m(fs),2m(kernel),256k(uboot)," \ | |
d3afa1ee BS |
284 | "128k(env),128k(redund_env)," \ |
285 | "128k(dtb),-(user_data)" | |
53d4a498 | 286 | |
fa5c2ba1 BS |
287 | /* |
288 | * IDE/ATA configuration | |
289 | */ | |
6d0f6bcf JCPV |
290 | #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA |
291 | #define CONFIG_SYS_IDE_MAXBUS 1 | |
292 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
fa5c2ba1 BS |
293 | #define CONFIG_IDE_PREINIT |
294 | ||
6d0f6bcf JCPV |
295 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 |
296 | #define CONFIG_SYS_ATA_REG_OFFSET CONFIG_SYS_ATA_DATA_OFFSET | |
297 | #define CONFIG_SYS_ATA_STRIDE 4 | |
fa5c2ba1 BS |
298 | #define CONFIG_DOS_PARTITION |
299 | ||
300 | ||
de1de02a PK |
301 | /* |
302 | * I2C configuration | |
303 | */ | |
304 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
6d0f6bcf JCPV |
305 | #define CONFIG_SYS_I2C_MODULE 2 /* select I2C module #2 */ |
306 | #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ | |
307 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
de1de02a PK |
308 | |
309 | ||
310 | /* | |
311 | * EEPROM configuration | |
312 | */ | |
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
314 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 1 /* 2 bytes per write cycle */ | |
315 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */ | |
316 | #define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* 2 EEPROMs (addr:50,52) */ | |
de1de02a PK |
317 | |
318 | ||
319 | /* | |
320 | * RTC configuration | |
321 | */ | |
322 | #define CONFIG_RTC_DS1337 1 | |
6d0f6bcf | 323 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
de1de02a PK |
324 | |
325 | ||
a11c0b85 BS |
326 | /* |
327 | * Status LED configuration | |
328 | */ | |
329 | #define CONFIG_STATUS_LED /* Status LED enabled */ | |
330 | #define CONFIG_BOARD_SPECIFIC_LED | |
331 | ||
332 | #define ENABLE_GPIO_OUT 0x00000024 | |
333 | #define LED_ON 0x00000010 | |
334 | ||
335 | #ifndef __ASSEMBLY__ | |
336 | /* | |
337 | * In case of Motion-PRO, a LED is identified by its corresponding | |
338 | * GPT Enable and Mode Select Register. | |
339 | */ | |
340 | typedef volatile unsigned long * led_id_t; | |
341 | ||
342 | extern void __led_init(led_id_t id, int state); | |
343 | extern void __led_toggle(led_id_t id); | |
344 | extern void __led_set(led_id_t id, int state); | |
345 | #endif /* __ASSEMBLY__ */ | |
346 | ||
347 | ||
93b78f53 BS |
348 | /* |
349 | * Temperature sensor | |
350 | */ | |
351 | #define CONFIG_DTT_LM75 1 | |
352 | #define CONFIG_DTT_SENSORS { 0x49 } | |
353 | ||
354 | ||
53d4a498 BS |
355 | /* |
356 | * Environment settings | |
357 | */ | |
5a1aceb0 | 358 | #define CONFIG_ENV_IS_IN_FLASH 1 |
53d4a498 | 359 | /* This has to be a multiple of the Flash sector size */ |
6d0f6bcf | 360 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 JCPV |
361 | #define CONFIG_ENV_SIZE 0x1000 |
362 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
53d4a498 | 363 | |
4520fd4d | 364 | /* Configuration of redundant environment */ |
0e8d1586 JCPV |
365 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
366 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
53d4a498 BS |
367 | |
368 | /* | |
369 | * Pin multiplexing configuration | |
370 | */ | |
371 | ||
372 | /* PSC1: UART1 | |
373 | * PSC2: GPIO (default) | |
374 | * PSC3: GPIO (default) | |
375 | * USB: 2xUART4/5 | |
376 | * Ethernet: Ethernet 100Mbit with MD | |
377 | * Timer: CAN2/GPIO | |
378 | * PSC6/IRDA: GPIO (default) | |
379 | */ | |
6d0f6bcf | 380 | #define CONFIG_SYS_GPS_PORT_CONFIG 0x1105a004 |
53d4a498 BS |
381 | |
382 | ||
c75e6396 BS |
383 | /* |
384 | * Motion-PRO's CPLD revision control register | |
385 | */ | |
6d0f6bcf | 386 | #define CPLD_REV_REGISTER (CONFIG_SYS_CS2_START + 0x06) |
c75e6396 BS |
387 | |
388 | ||
53d4a498 BS |
389 | /* |
390 | * Miscellaneous configurable options | |
391 | */ | |
6d0f6bcf JCPV |
392 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
393 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
394 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
395 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
396 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
397 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
53d4a498 | 398 | |
6d0f6bcf JCPV |
399 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
400 | #define CONFIG_SYS_MEMTEST_END 0x03e00000 /* 1 ... 62 MiB in DRAM */ | |
401 | #define CONFIG_SYS_ALT_MEMTEST | |
53d4a498 | 402 | |
6d0f6bcf | 403 | #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default kernel load addr */ |
53d4a498 | 404 | |
6d0f6bcf | 405 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
53d4a498 BS |
406 | |
407 | ||
408 | /* | |
409 | * Various low-level settings | |
410 | */ | |
6d0f6bcf JCPV |
411 | #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI |
412 | #define CONFIG_SYS_HID0_FINAL HID0_ICE | |
53d4a498 BS |
413 | |
414 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
415 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
416 | ||
6d0f6bcf | 417 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
53d4a498 BS |
418 | |
419 | ||
420 | /* Not needed for MPC 5xxx U-Boot, but used by tools/updater */ | |
6d0f6bcf | 421 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 |
53d4a498 | 422 | |
1f1369c3 | 423 | /* pass open firmware flat tree */ |
cf2817a8 | 424 | #define CONFIG_OF_LIBFDT 1 |
1f1369c3 BS |
425 | #define CONFIG_OF_BOARD_SETUP 1 |
426 | ||
1f1369c3 BS |
427 | #define OF_CPU "PowerPC,5200@0" |
428 | #define OF_SOC "soc5200@f0000000" | |
429 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
7049288f | 430 | #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" |
1f1369c3 | 431 | |
53d4a498 | 432 | #endif /* __CONFIG_H */ |