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imx6: move MXC_GPIO define to mx6_common.h
[people/ms/u-boot.git] / include / configs / sequoia.h
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887e2ec9 1/*
fc84a849 2 * (C) Copyright 2006-2008
887e2ec9
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3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
8 *
1a459660 9 * SPDX-License-Identifier: GPL-2.0+
887e2ec9
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10 */
11
214398d9 12/*
e802594b 13 * sequoia.h - configuration for Sequoia & Rainier boards
214398d9 14 */
887e2ec9
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15#ifndef __CONFIG_H
16#define __CONFIG_H
17
214398d9 18/*
887e2ec9 19 * High Level Configuration Options
214398d9 20 */
e802594b 21/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
854bc8da 22#ifndef CONFIG_RAINIER
214398d9 23#define CONFIG_440EPX 1 /* Specific PPC440EPx */
72675dc6 24#define CONFIG_HOSTNAME sequoia
854bc8da 25#else
214398d9 26#define CONFIG_440GRX 1 /* Specific PPC440GRx */
72675dc6 27#define CONFIG_HOSTNAME rainier
854bc8da 28#endif
214398d9 29#define CONFIG_440 1 /* ... PPC440 family */
72675dc6 30
2ae18241
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31#ifndef CONFIG_SYS_TEXT_BASE
32#define CONFIG_SYS_TEXT_BASE 0xFFF80000
33#endif
34
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35/*
36 * Include common defines/options for all AMCC eval boards
37 */
38#include "amcc-common.h"
39
e3b8c78b 40/* Detect Sequoia PLL input clock automatically via CPLD bit */
6d0f6bcf 41#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
193b4a3b 42 33333333 : 33000000)
887e2ec9 43
bc778812
AG
44/*
45 * Define this if you want support for video console with radeon 9200 pci card
14d0a02a 46 * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
bc778812
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47 */
48#undef CONFIG_VIDEO
49
50#ifdef CONFIG_VIDEO
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51/*
52 * 44x dcache supported is working now on sequoia, but we don't enable
53 * it yet since it needs further testing
54 */
214398d9 55#define CONFIG_4xx_DCACHE /* enable dcache */
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56#endif
57
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58#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
59#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
887e2ec9 60
214398d9
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61/*
62 * Base addresses -- Note these are effective addresses where the actual
63 * resources get mapped (not physical addresses).
64 */
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65#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003
66#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
67#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
68#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
69#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
70#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
71#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
72#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
73#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
74#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
75#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
887e2ec9 76
6d0f6bcf
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77#define CONFIG_SYS_USB2D0_BASE 0xe0000100
78#define CONFIG_SYS_USB_DEVICE 0xe0000000
79#define CONFIG_SYS_USB_HOST 0xe0000400
80#define CONFIG_SYS_BCSR_BASE 0xc0000000
887e2ec9 81
214398d9 82/*
887e2ec9 83 * Initial RAM & stack pointer
214398d9 84 */
887e2ec9 85/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
6d0f6bcf 86#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
553f0982 87#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
25ddd1fb 88#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
800eb096 89#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
887e2ec9 90
214398d9 91/*
887e2ec9 92 * Serial Port
214398d9 93 */
550650dd 94#define CONFIG_CONS_INDEX 1 /* Use UART0 */
6d0f6bcf 95#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
887e2ec9 96
214398d9 97/*
887e2ec9 98 * Environment
214398d9 99 */
345b77ba 100#if defined(CONFIG_SYS_RAMBOOT)
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101#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
102#define CONFIG_ENV_SIZE (8 << 10)
103/*
104 * In RAM-booting version, we have no environment storage. So we need to
105 * provide at least preliminary MAC addresses for the 4xx EMAC driver to
106 * register the interfaces. Those two addresses are generated via the
107 * tools/gen_eth_addr tool and should only be used in a closed laboratory
108 * environment.
109 */
110#define CONFIG_ETHADDR 4a:56:49:22:3e:43
111#define CONFIG_ETH1ADDR 02:93:53:d5:06:98
887e2ec9 112#else
d873133f 113#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */
887e2ec9 114#endif
887e2ec9 115
d873133f 116#if defined(CONFIG_CMD_FLASH)
214398d9 117/*
887e2ec9 118 * FLASH related
214398d9 119 */
6d0f6bcf 120#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a 121#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
887e2ec9 122
6d0f6bcf 123#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
887e2ec9 124
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125#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
126#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
887e2ec9 127
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128#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
129#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
887e2ec9 130
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131#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
132#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
887e2ec9 133
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134#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
135#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
887e2ec9 136
5a1aceb0 137#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586 138#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
6d0f6bcf 139#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
0e8d1586 140#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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141
142/* Address and size of Redundant Environment Sector */
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143#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
144#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
887e2ec9 145#endif
d873133f 146#endif /* CONFIG_CMD_FLASH */
887e2ec9 147
214398d9 148/*
887e2ec9 149 * DDR SDRAM
214398d9 150 */
6d0f6bcf 151#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
345b77ba 152#if !defined(CONFIG_SYS_RAMBOOT)
214398d9 153#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
02388983 154#endif
6d0f6bcf 155#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
14f73ca6 156 /* 440EPx errata CHIP 11 */
887e2ec9 157
214398d9 158/*
887e2ec9 159 * I2C
214398d9 160 */
880540de 161#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
887e2ec9 162
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163#define CONFIG_SYS_I2C_MULTI_EEPROMS
164#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
165#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
166#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
167#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
887e2ec9 168
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169/* I2C bootstrap EEPROM */
170#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
171#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
172#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
173
887e2ec9 174/* I2C SYSMON (LM75, AD7414 is almost compatible) */
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175#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
176#define CONFIG_DTT_AD7414 1 /* use AD7414 */
177#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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178#define CONFIG_SYS_DTT_MAX_TEMP 70
179#define CONFIG_SYS_DTT_LOW_TEMP -30
180#define CONFIG_SYS_DTT_HYSTERESIS 3
887e2ec9 181
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182/*
183 * Default environment variables
184 */
887e2ec9 185#define CONFIG_EXTRA_ENV_SETTINGS \
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186 CONFIG_AMCC_DEF_ENV \
187 CONFIG_AMCC_DEF_ENV_POWERPC \
188 CONFIG_AMCC_DEF_ENV_PPC_OLD \
189 CONFIG_AMCC_DEF_ENV_NOR_UPD \
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190 "kernel_addr=FC000000\0" \
191 "ramdisk_addr=FC180000\0" \
887e2ec9 192 ""
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193
194#define CONFIG_M88E1111_PHY 1
195#define CONFIG_IBM_EMAC4_V4 1
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196#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
197
214398d9 198#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
887e2ec9
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199#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
200
201#define CONFIG_HAS_ETH0
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202#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
203#define CONFIG_PHY1_ADDR 1
204
205/* USB */
854bc8da 206#ifdef CONFIG_440EPX
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207
208#undef CONFIG_USB_EHCI /* OHCI by default */
209
210#ifdef CONFIG_USB_EHCI
211#define CONFIG_USB_EHCI_PPC4XX
212#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
213#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
214#define CONFIG_EHCI_MMIO_BIG_ENDIAN
215#define CONFIG_EHCI_DESC_BIG_ENDIAN
559e2c87 216#else /* CONFIG_USB_EHCI */
2d146843 217#define CONFIG_USB_OHCI_NEW
6d0f6bcf 218#define CONFIG_SYS_OHCI_BE_CONTROLLER
2d146843 219
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220#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
221#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
222#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
223#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
224#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
559e2c87 225#endif
887e2ec9 226
559e2c87 227#define CONFIG_USB_STORAGE
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228/* Comment this out to enable USB 1.1 device */
229#define USB_2_0_DEVICE
230
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231#endif /* CONFIG_440EPX */
232
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233/* Partitions */
234#define CONFIG_MAC_PARTITION
235#define CONFIG_DOS_PARTITION
236#define CONFIG_ISO_PARTITION
237
079a136c 238/*
72675dc6 239 * Commands additional to the ones defined in amcc-common.h
079a136c 240 */
cfc25874 241#define CONFIG_CMD_CHIP_CONFIG
46da1e96 242#define CONFIG_CMD_DTT
46da1e96 243#define CONFIG_CMD_FAT
46da1e96 244#define CONFIG_CMD_NAND
46da1e96 245#define CONFIG_CMD_PCI
46da1e96
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246#define CONFIG_CMD_SDRAM
247
248#ifdef CONFIG_440EPX
249#define CONFIG_CMD_USB
250#endif
251
9de469bd 252#ifndef CONFIG_RAINIER
6d0f6bcf 253#define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU
9de469bd 254#else
6d0f6bcf 255#define CONFIG_SYS_POST_FPU_ON 0
9de469bd 256#endif
887e2ec9 257
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258/*
259 * Don't run the memory POST on the NAND-booting version. It will
260 * overwrite part of the U-Boot image which is already loaded from NAND
261 * to SDRAM.
262 */
345b77ba 263#if defined(CONFIG_SYS_RAMBOOT)
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264#define CONFIG_SYS_POST_MEMORY_ON 0
265#else
266#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
267#endif
268
a11e0696 269/* POST support */
6d0f6bcf
JCPV
270#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
271 CONFIG_SYS_POST_CPU | \
272 CONFIG_SYS_POST_ETHER | \
9a929170 273 CONFIG_SYS_POST_FPU_ON | \
6d0f6bcf 274 CONFIG_SYS_POST_I2C | \
9a929170 275 CONFIG_SYS_POST_MEMORY_ON | \
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276 CONFIG_SYS_POST_SPR | \
277 CONFIG_SYS_POST_UART)
278
a11e0696 279#define CONFIG_LOGBUFFER
6d0f6bcf 280#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
a11e0696 281
6d0f6bcf 282#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
a11e0696 283
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284#define CONFIG_SUPPORT_VFAT
285
214398d9 286/*
887e2ec9 287 * PCI stuff
214398d9 288 */
887e2ec9 289/* General PCI */
214398d9 290#define CONFIG_PCI /* include pci support */
842033e6 291#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
214398d9 292#define CONFIG_PCI_PNP /* do pci plug-and-play */
6d0f6bcf 293#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
214398d9 294#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf
JCPV
295#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
296 /* CONFIG_SYS_PCI_MEMBASE */
887e2ec9 297/* Board-specific PCI */
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JCPV
298#define CONFIG_SYS_PCI_TARGET_INIT
299#define CONFIG_SYS_PCI_MASTER_INIT
a760b020 300#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
887e2ec9 301
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JCPV
302#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
303#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
887e2ec9 304
214398d9 305/*
887e2ec9 306 * External Bus Controller (EBC) Setup
214398d9 307 */
887e2ec9
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308
309/*
310 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
311 */
345b77ba 312#if !defined(CONFIG_SYS_RAMBOOT)
6d0f6bcf 313#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
214398d9 314/* Memory Bank 0 (NOR-FLASH) initialization */
6d0f6bcf
JCPV
315#define CONFIG_SYS_EBC_PB0AP 0x03017200
316#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
887e2ec9 317
214398d9 318/* Memory Bank 3 (NAND-FLASH) initialization */
6d0f6bcf
JCPV
319#define CONFIG_SYS_EBC_PB3AP 0x018003c0
320#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
887e2ec9 321#else
6d0f6bcf 322#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
214398d9 323/* Memory Bank 3 (NOR-FLASH) initialization */
6d0f6bcf
JCPV
324#define CONFIG_SYS_EBC_PB3AP 0x03017200
325#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE | 0xda000)
887e2ec9 326
214398d9 327/* Memory Bank 0 (NAND-FLASH) initialization */
6d0f6bcf
JCPV
328#define CONFIG_SYS_EBC_PB0AP 0x018003c0
329#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
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330#endif
331
214398d9 332/* Memory Bank 2 (CPLD) initialization */
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333#define CONFIG_SYS_EBC_PB2AP 0x24814580
334#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x38000)
887e2ec9 335
6d0f6bcf 336#define CONFIG_SYS_BCSR5_PCI66EN 0x80
5a5958b7 337
214398d9 338/*
43a2b0e7 339 * NAND FLASH
214398d9 340 */
6d0f6bcf 341#define CONFIG_SYS_MAX_NAND_DEVICE 1
6d0f6bcf
JCPV
342#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
343#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
43a2b0e7 344
214398d9 345/*
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346 * PPC440 GPIO Configuration
347 */
348/* test-only: take GPIO init from pcs440ep ???? in config file */
6d0f6bcf 349#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
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LJ
350{ \
351/* GPIO Core 0 */ \
352{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
353{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
354{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
355{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
356{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
357{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
358{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
359{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
360{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
361{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
362{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
363{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
364{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
365{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
366{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \
367{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
368{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
369{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
370{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
371{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
372{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
373{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
374{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
375{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
376{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
377{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
378{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
379{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
380{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \
381{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
382{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
383{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
384}, \
385{ \
386/* GPIO Core 1 */ \
387{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
388{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
eab10073
SF
389{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
390{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
391{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \
392{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
393{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \
394{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \
b05e8bf5
LJ
395{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
396{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
397{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
398{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
399{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
400{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
401{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
402{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
403{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
404{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
405{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
406{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
407{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
408{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
409{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
410{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
411{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
412{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
413{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
414{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
415{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
416{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
417{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
418{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
419} \
420}
421
bc778812
AG
422#ifdef CONFIG_VIDEO
423#define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */
424#define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
425#define VIDEO_IO_OFFSET 0xe8000000
6d0f6bcf 426#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
bc778812
AG
427#define CONFIG_VIDEO_SW_CURSOR
428#define CONFIG_VIDEO_LOGO
429#define CONFIG_CFB_CONSOLE
430#define CONFIG_SPLASH_SCREEN
431#define CONFIG_VGA_AS_SINGLE_DEVICE
432#define CONFIG_CMD_BMP
433#endif
434
214398d9 435#endif /* __CONFIG_H */