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fdt: remove unaligned access in fdt_fixup_ethernet()
[people/ms/u-boot.git] / include / configs / sequoia.h
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887e2ec9 1/*
fc84a849 2 * (C) Copyright 2006-2008
887e2ec9
SR		 3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
214398d9 25/*
e802594b 26 * sequoia.h - configuration for Sequoia & Rainier boards
214398d9 27 */
887e2ec9
SR		 28#ifndef __CONFIG_H
29#define __CONFIG_H
30
214398d9 31/*
887e2ec9 32 * High Level Configuration Options
214398d9 33 */
e802594b 34/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
854bc8da 35#ifndef CONFIG_RAINIER
214398d9 36#define CONFIG_440EPX 1 /* Specific PPC440EPx */
72675dc6 37#define CONFIG_HOSTNAME sequoia
854bc8da 38#else
214398d9 39#define CONFIG_440GRX 1 /* Specific PPC440GRx */
72675dc6 40#define CONFIG_HOSTNAME rainier
854bc8da 41#endif
214398d9
LJ		 42#define CONFIG_440 1 /* ... PPC440 family */
43#define CONFIG_4xx 1 /* ... PPC4xx family */
72675dc6 44
2ae18241
WD		 45#ifndef CONFIG_SYS_TEXT_BASE
46#define CONFIG_SYS_TEXT_BASE 0xFFF80000
47#endif
48
72675dc6
SR		 49/*
50 * Include common defines/options for all AMCC eval boards
51 */
52#include "amcc-common.h"
53
e3b8c78b 54/* Detect Sequoia PLL input clock automatically via CPLD bit */
6d0f6bcf 55#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
193b4a3b 56 33333333 : 33000000)
887e2ec9 57
bc778812
AG		 58/*
59 * Define this if you want support for video console with radeon 9200 pci card
14d0a02a 60 * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
bc778812
AG		 61 */
62#undef CONFIG_VIDEO
63
64#ifdef CONFIG_VIDEO
d25dfe08
SR		 65/*
66 * 44x dcache supported is working now on sequoia, but we don't enable
67 * it yet since it needs further testing
68 */
214398d9 69#define CONFIG_4xx_DCACHE /* enable dcache */
d25dfe08
SR		 70#endif
71
214398d9
LJ		 72#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
73#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
887e2ec9 74
214398d9
LJ		 75/*
76 * Base addresses -- Note these are effective addresses where the actual
77 * resources get mapped (not physical addresses).
78 */
6d0f6bcf
JCPV		 79#define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0x0003
80#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
81#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
82#define CONFIG_SYS_NAND_ADDR 0xd0000000 /* NAND Flash */
83#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
84#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
85#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
86#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
87#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
88#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
89#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
887e2ec9 90
6d0f6bcf
JCPV		 91#define CONFIG_SYS_USB2D0_BASE 0xe0000100
92#define CONFIG_SYS_USB_DEVICE 0xe0000000
93#define CONFIG_SYS_USB_HOST 0xe0000400
94#define CONFIG_SYS_BCSR_BASE 0xc0000000
887e2ec9 95
214398d9 96/*
887e2ec9 97 * Initial RAM & stack pointer
214398d9 98 */
887e2ec9 99/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
6d0f6bcf 100#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
553f0982 101#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
25ddd1fb 102#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
800eb096 103#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
887e2ec9 104
214398d9 105/*
887e2ec9 106 * Serial Port
214398d9 107 */
550650dd 108#define CONFIG_CONS_INDEX 1 /* Use UART0 */
6d0f6bcf 109#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
887e2ec9 110
214398d9 111/*
887e2ec9 112 * Environment
214398d9 113 */
d873133f
SR		 114#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
115#define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */
116#define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */
117#elif defined(CONFIG_SYS_RAMBOOT)
118#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
119#define CONFIG_ENV_SIZE (8 << 10)
120/*
121 * In RAM-booting version, we have no environment storage. So we need to
122 * provide at least preliminary MAC addresses for the 4xx EMAC driver to
123 * register the interfaces. Those two addresses are generated via the
124 * tools/gen_eth_addr tool and should only be used in a closed laboratory
125 * environment.
126 */
127#define CONFIG_ETHADDR 4a:56:49:22:3e:43
128#define CONFIG_ETH1ADDR 02:93:53:d5:06:98
887e2ec9 129#else
d873133f 130#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */
887e2ec9 131#endif
887e2ec9 132
d873133f 133#if defined(CONFIG_CMD_FLASH)
214398d9 134/*
887e2ec9 135 * FLASH related
214398d9 136 */
6d0f6bcf 137#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a 138#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
887e2ec9 139
6d0f6bcf 140#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
887e2ec9 141
6d0f6bcf
JCPV		 142#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
143#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
887e2ec9 144
6d0f6bcf
JCPV		 145#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
146#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
887e2ec9 147
6d0f6bcf
JCPV		 148#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
149#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
887e2ec9 150
6d0f6bcf
JCPV		 151#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
152#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
887e2ec9 153
5a1aceb0 154#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586 155#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
6d0f6bcf 156#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
0e8d1586 157#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
887e2ec9
SR		 158
159/* Address and size of Redundant Environment Sector */
0e8d1586
JCPV		 160#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
161#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
887e2ec9 162#endif
d873133f 163#endif /* CONFIG_CMD_FLASH */
887e2ec9 164
887e2ec9
SR		 165/*
166 * IPL (Initial Program Loader, integrated inside CPU)
167 * Will load first 4k from NAND (SPL) into cache and execute it from there.
168 *
169 * SPL (Secondary Program Loader)
170 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
171 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
172 * controller and the NAND controller so that the special U-Boot image can be
173 * loaded from NAND to SDRAM.
174 *
175 * NUB (NAND U-Boot)
176 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
177 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
178 *
179 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
180 * set up. While still running from cache, I experienced problems accessing
181 * the NAND controller. sr - 2006-08-25
182 */
6d0f6bcf
JCPV		 183#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
184#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
185#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
186#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
187#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */
214398d9 188 /* this addr */
6d0f6bcf 189#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
887e2ec9
SR		 190
191/*
192 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
193 */
6d0f6bcf
JCPV		 194#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
195#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
887e2ec9
SR		 196
197/*
198 * Now the NAND chip has to be defined (no autodetection used!)
199 */
6d0f6bcf
JCPV		 200#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
201#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
202#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
203#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
204#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
205
206#define CONFIG_SYS_NAND_ECCSIZE 256
207#define CONFIG_SYS_NAND_ECCBYTES 3
6d0f6bcf 208#define CONFIG_SYS_NAND_OOBSIZE 16
6d0f6bcf 209#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
9d909604 210
51bfee19 211#ifdef CONFIG_ENV_IS_IN_NAND
d12ae808
SR		 212/*
213 * For NAND booting the environment is embedded in the U-Boot image. Please take
214 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
215 */
6d0f6bcf
JCPV		 216#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
217#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
0e8d1586 218#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
887e2ec9
SR		 219#endif
220
214398d9 221/*
887e2ec9 222 * DDR SDRAM
214398d9 223 */
6d0f6bcf 224#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
d873133f
SR		 225#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
226 !defined(CONFIG_SYS_RAMBOOT)
214398d9 227#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
02388983 228#endif
6d0f6bcf 229#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
14f73ca6 230 /* 440EPx errata CHIP 11 */
887e2ec9 231
214398d9 232/*
887e2ec9 233 * I2C
214398d9 234 */
6d0f6bcf 235#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
887e2ec9 236
6d0f6bcf
JCPV		 237#define CONFIG_SYS_I2C_MULTI_EEPROMS
238#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
239#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
240#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
241#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
887e2ec9 242
cfc25874
SR		 243/* I2C bootstrap EEPROM */
244#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
245#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
246#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
247
887e2ec9 248/* I2C SYSMON (LM75, AD7414 is almost compatible) */
214398d9
LJ		 249#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
250#define CONFIG_DTT_AD7414 1 /* use AD7414 */
251#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
6d0f6bcf
JCPV		 252#define CONFIG_SYS_DTT_MAX_TEMP 70
253#define CONFIG_SYS_DTT_LOW_TEMP -30
254#define CONFIG_SYS_DTT_HYSTERESIS 3
887e2ec9 255
72675dc6
SR		 256/*
257 * Default environment variables
258 */
887e2ec9 259#define CONFIG_EXTRA_ENV_SETTINGS \
72675dc6
SR		 260 CONFIG_AMCC_DEF_ENV \
261 CONFIG_AMCC_DEF_ENV_POWERPC \
262 CONFIG_AMCC_DEF_ENV_PPC_OLD \
263 CONFIG_AMCC_DEF_ENV_NOR_UPD \
264 CONFIG_AMCC_DEF_ENV_NAND_UPD \
4ef62514
SR		 265 "kernel_addr=FC000000\0" \
266 "ramdisk_addr=FC180000\0" \
887e2ec9 267 ""
887e2ec9
SR		 268
269#define CONFIG_M88E1111_PHY 1
270#define CONFIG_IBM_EMAC4_V4 1
887e2ec9
SR		 271#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
272
214398d9 273#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
887e2ec9
SR		 274#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
275
276#define CONFIG_HAS_ETH0
887e2ec9
SR		 277#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
278#define CONFIG_PHY1_ADDR 1
279
280/* USB */
854bc8da 281#ifdef CONFIG_440EPX
559e2c87
CZ		 282
283#undef CONFIG_USB_EHCI /* OHCI by default */
284
285#ifdef CONFIG_USB_EHCI
286#define CONFIG_USB_EHCI_PPC4XX
287#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
288#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
289#define CONFIG_EHCI_MMIO_BIG_ENDIAN
290#define CONFIG_EHCI_DESC_BIG_ENDIAN
559e2c87 291#else /* CONFIG_USB_EHCI */
2d146843 292#define CONFIG_USB_OHCI_NEW
6d0f6bcf 293#define CONFIG_SYS_OHCI_BE_CONTROLLER
2d146843 294
6d0f6bcf
JCPV		 295#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
296#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
297#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
298#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
299#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
559e2c87 300#endif
887e2ec9 301
559e2c87 302#define CONFIG_USB_STORAGE
887e2ec9
SR		 303/* Comment this out to enable USB 1.1 device */
304#define USB_2_0_DEVICE
305
854bc8da
SR		 306#endif /* CONFIG_440EPX */
307
887e2ec9
SR		 308/* Partitions */
309#define CONFIG_MAC_PARTITION
310#define CONFIG_DOS_PARTITION
311#define CONFIG_ISO_PARTITION
312
079a136c 313/*
72675dc6 314 * Commands additional to the ones defined in amcc-common.h
079a136c 315 */
cfc25874 316#define CONFIG_CMD_CHIP_CONFIG
46da1e96 317#define CONFIG_CMD_DTT
46da1e96 318#define CONFIG_CMD_FAT
46da1e96 319#define CONFIG_CMD_NAND
46da1e96 320#define CONFIG_CMD_PCI
46da1e96
JL		 321#define CONFIG_CMD_SDRAM
322
323#ifdef CONFIG_440EPX
324#define CONFIG_CMD_USB
325#endif
326
9de469bd 327#ifndef CONFIG_RAINIER
6d0f6bcf 328#define CONFIG_SYS_POST_FPU_ON CONFIG_SYS_POST_FPU
9de469bd 329#else
6d0f6bcf 330#define CONFIG_SYS_POST_FPU_ON 0
9de469bd 331#endif
887e2ec9 332
9a929170
SR		 333/*
334 * Don't run the memory POST on the NAND-booting version. It will
335 * overwrite part of the U-Boot image which is already loaded from NAND
336 * to SDRAM.
337 */
d873133f 338#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
9a929170
SR		 339#define CONFIG_SYS_POST_MEMORY_ON 0
340#else
341#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
342#endif
343
a11e0696 344/* POST support */
6d0f6bcf
JCPV		 345#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
346 CONFIG_SYS_POST_CPU | \
347 CONFIG_SYS_POST_ETHER | \
9a929170 348 CONFIG_SYS_POST_FPU_ON | \
6d0f6bcf 349 CONFIG_SYS_POST_I2C | \
9a929170 350 CONFIG_SYS_POST_MEMORY_ON | \
6d0f6bcf
JCPV		 351 CONFIG_SYS_POST_SPR | \
352 CONFIG_SYS_POST_UART)
353
a11e0696 354#define CONFIG_LOGBUFFER
6d0f6bcf 355#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
a11e0696 356
6d0f6bcf 357#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
a11e0696 358
887e2ec9
SR		 359#define CONFIG_SUPPORT_VFAT
360
214398d9 361/*
887e2ec9 362 * PCI stuff
214398d9 363 */
887e2ec9 364/* General PCI */
214398d9
LJ		 365#define CONFIG_PCI /* include pci support */
366#define CONFIG_PCI_PNP /* do pci plug-and-play */
6d0f6bcf 367#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
214398d9 368#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf
JCPV		 369#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
370 /* CONFIG_SYS_PCI_MEMBASE */
887e2ec9 371/* Board-specific PCI */
6d0f6bcf
JCPV		 372#define CONFIG_SYS_PCI_TARGET_INIT
373#define CONFIG_SYS_PCI_MASTER_INIT
a760b020 374#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
887e2ec9 375
6d0f6bcf
JCPV		 376#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
377#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
887e2ec9 378
214398d9 379/*
887e2ec9 380 * External Bus Controller (EBC) Setup
214398d9 381 */
887e2ec9
SR		 382
383/*
384 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
385 */
d873133f
SR		 386#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
387 !defined(CONFIG_SYS_RAMBOOT)
6d0f6bcf 388#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
214398d9 389/* Memory Bank 0 (NOR-FLASH) initialization */
6d0f6bcf
JCPV		 390#define CONFIG_SYS_EBC_PB0AP 0x03017200
391#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
887e2ec9 392
214398d9 393/* Memory Bank 3 (NAND-FLASH) initialization */
6d0f6bcf
JCPV		 394#define CONFIG_SYS_EBC_PB3AP 0x018003c0
395#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
887e2ec9 396#else
6d0f6bcf 397#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
214398d9 398/* Memory Bank 3 (NOR-FLASH) initialization */
6d0f6bcf
JCPV		 399#define CONFIG_SYS_EBC_PB3AP 0x03017200
400#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FLASH_BASE | 0xda000)
887e2ec9 401
214398d9 402/* Memory Bank 0 (NAND-FLASH) initialization */
6d0f6bcf
JCPV		 403#define CONFIG_SYS_EBC_PB0AP 0x018003c0
404#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
887e2ec9
SR		 405#endif
406
214398d9 407/* Memory Bank 2 (CPLD) initialization */
6d0f6bcf
JCPV		 408#define CONFIG_SYS_EBC_PB2AP 0x24814580
409#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x38000)
887e2ec9 410
6d0f6bcf 411#define CONFIG_SYS_BCSR5_PCI66EN 0x80
5a5958b7 412
214398d9 413/*
43a2b0e7 414 * NAND FLASH
214398d9 415 */
6d0f6bcf 416#define CONFIG_SYS_MAX_NAND_DEVICE 1
6d0f6bcf
JCPV		 417#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
418#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
43a2b0e7 419
214398d9 420/*
b05e8bf5
LJ		 421 * PPC440 GPIO Configuration
422 */
423/* test-only: take GPIO init from pcs440ep ???? in config file */
6d0f6bcf 424#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
b05e8bf5
LJ		 425{ \
426/* GPIO Core 0 */ \
427{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
428{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
429{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
430{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
431{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
432{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
433{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
434{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
435{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
436{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
437{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
438{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
439{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
440{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
441{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \
442{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
443{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
444{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
445{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
446{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
447{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
448{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
449{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
450{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
451{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
452{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
453{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
454{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
455{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \
456{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
457{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
458{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
459}, \
460{ \
461/* GPIO Core 1 */ \
462{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
463{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
eab10073
SF		 464{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
465{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
466{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \
467{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
468{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \
469{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \
b05e8bf5
LJ		 470{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
471{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
472{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
473{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
474{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
475{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
476{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
477{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
478{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
479{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
480{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
481{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
482{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
483{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
484{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
485{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
486{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
487{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
488{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
489{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
490{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
491{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
492{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
493{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
494} \
495}
496
bc778812
AG		 497#ifdef CONFIG_VIDEO
498#define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */
499#define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
500#define VIDEO_IO_OFFSET 0xe8000000
6d0f6bcf 501#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
bc778812
AG		 502#define CONFIG_VIDEO_SW_CURSOR
503#define CONFIG_VIDEO_LOGO
504#define CONFIG_CFB_CONSOLE
505#define CONFIG_SPLASH_SCREEN
506#define CONFIG_VGA_AS_SINGLE_DEVICE
507#define CONFIG_CMD_BMP
508#endif
509
214398d9 510#endif /* __CONFIG_H */
"Das U-Boot" Source Tree