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887e2ec9 | 1 | /* |
e802594b | 2 | * (C) Copyright 2006-2007 |
887e2ec9 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
7 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
214398d9 | 25 | /* |
e802594b | 26 | * sequoia.h - configuration for Sequoia & Rainier boards |
214398d9 | 27 | */ |
887e2ec9 SR |
28 | #ifndef __CONFIG_H |
29 | #define __CONFIG_H | |
30 | ||
214398d9 | 31 | /* |
887e2ec9 | 32 | * High Level Configuration Options |
214398d9 | 33 | */ |
e802594b | 34 | /* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ |
854bc8da | 35 | #ifndef CONFIG_RAINIER |
214398d9 | 36 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ |
854bc8da | 37 | #else |
214398d9 | 38 | #define CONFIG_440GRX 1 /* Specific PPC440GRx */ |
854bc8da | 39 | #endif |
214398d9 LJ |
40 | #define CONFIG_440 1 /* ... PPC440 family */ |
41 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
e3b8c78b JM |
42 | /* Detect Sequoia PLL input clock automatically via CPLD bit */ |
43 | #define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \ | |
193b4a3b | 44 | 33333333 : 33000000) |
887e2ec9 | 45 | |
bc778812 AG |
46 | /* |
47 | * Define this if you want support for video console with radeon 9200 pci card | |
48 | * Also set TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case | |
49 | */ | |
50 | #undef CONFIG_VIDEO | |
51 | ||
52 | #ifdef CONFIG_VIDEO | |
d25dfe08 SR |
53 | /* |
54 | * 44x dcache supported is working now on sequoia, but we don't enable | |
55 | * it yet since it needs further testing | |
56 | */ | |
214398d9 | 57 | #define CONFIG_4xx_DCACHE /* enable dcache */ |
d25dfe08 SR |
58 | #endif |
59 | ||
214398d9 LJ |
60 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
61 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
887e2ec9 | 62 | |
214398d9 LJ |
63 | /* |
64 | * Base addresses -- Note these are effective addresses where the actual | |
65 | * resources get mapped (not physical addresses). | |
66 | */ | |
bc778812 | 67 | #ifndef CONFIG_VIDEO |
214398d9 LJ |
68 | #define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */ |
69 | #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */ | |
bc778812 AG |
70 | #else |
71 | #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ | |
72 | #define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ | |
73 | #endif | |
887e2ec9 | 74 | |
4d332dbe | 75 | #define CFG_TLB_FOR_BOOT_FLASH 0x0003 |
887e2ec9 SR |
76 | #define CFG_BOOT_BASE_ADDR 0xf0000000 |
77 | #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
4ef62514 | 78 | #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ |
887e2ec9 | 79 | #define CFG_MONITOR_BASE TEXT_BASE |
214398d9 LJ |
80 | #define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ |
81 | #define CFG_OCM_BASE 0xe0010000 /* ocm */ | |
a11e0696 | 82 | #define CFG_OCM_DATA_ADDR CFG_OCM_BASE |
214398d9 | 83 | #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ |
887e2ec9 SR |
84 | #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
85 | #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 | |
86 | #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 | |
87 | #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 | |
88 | ||
89 | /* Don't change either of these */ | |
90 | #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ | |
91 | ||
92 | #define CFG_USB2D0_BASE 0xe0000100 | |
93 | #define CFG_USB_DEVICE 0xe0000000 | |
94 | #define CFG_USB_HOST 0xe0000400 | |
95 | #define CFG_BCSR_BASE 0xc0000000 | |
96 | ||
214398d9 | 97 | /* |
887e2ec9 | 98 | * Initial RAM & stack pointer |
214398d9 | 99 | */ |
887e2ec9 | 100 | /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ |
887e2ec9 | 101 | #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ |
887e2ec9 | 102 | #define CFG_INIT_RAM_END (4 << 10) |
214398d9 | 103 | #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ |
887e2ec9 | 104 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
a11e0696 | 105 | #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR |
887e2ec9 | 106 | |
214398d9 | 107 | /* |
887e2ec9 | 108 | * Serial Port |
214398d9 | 109 | */ |
887e2ec9 SR |
110 | #define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ |
111 | #define CONFIG_BAUDRATE 115200 | |
214398d9 | 112 | #define CONFIG_SERIAL_MULTI 1 |
887e2ec9 SR |
113 | /* define this if you want console on UART1 */ |
114 | #undef CONFIG_UART1_CONSOLE | |
115 | ||
116 | #define CFG_BAUDRATE_TABLE \ | |
117 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
118 | ||
214398d9 | 119 | /* |
887e2ec9 | 120 | * Environment |
214398d9 | 121 | */ |
d12ae808 | 122 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
214398d9 | 123 | #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */ |
887e2ec9 | 124 | #else |
214398d9 LJ |
125 | #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environ vars */ |
126 | #define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ | |
887e2ec9 | 127 | #endif |
887e2ec9 | 128 | |
214398d9 | 129 | /* |
887e2ec9 | 130 | * FLASH related |
214398d9 LJ |
131 | */ |
132 | #define CFG_FLASH_CFI /* The flash is CFI compatible */ | |
133 | #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
887e2ec9 SR |
134 | |
135 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } | |
136 | ||
214398d9 LJ |
137 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
138 | #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
887e2ec9 | 139 | |
214398d9 LJ |
140 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
141 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
887e2ec9 | 142 | |
214398d9 LJ |
143 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
144 | #define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ | |
887e2ec9 | 145 | |
214398d9 LJ |
146 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
147 | #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
887e2ec9 SR |
148 | |
149 | #ifdef CFG_ENV_IS_IN_FLASH | |
214398d9 | 150 | #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
887e2ec9 | 151 | #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) |
214398d9 | 152 | #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
887e2ec9 SR |
153 | |
154 | /* Address and size of Redundant Environment Sector */ | |
155 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) | |
156 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
157 | #endif | |
158 | ||
887e2ec9 SR |
159 | /* |
160 | * IPL (Initial Program Loader, integrated inside CPU) | |
161 | * Will load first 4k from NAND (SPL) into cache and execute it from there. | |
162 | * | |
163 | * SPL (Secondary Program Loader) | |
164 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL | |
165 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM | |
166 | * controller and the NAND controller so that the special U-Boot image can be | |
167 | * loaded from NAND to SDRAM. | |
168 | * | |
169 | * NUB (NAND U-Boot) | |
170 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started | |
171 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. | |
172 | * | |
173 | * On 440EPx the SPL is copied to SDRAM before the NAND controller is | |
174 | * set up. While still running from cache, I experienced problems accessing | |
175 | * the NAND controller. sr - 2006-08-25 | |
176 | */ | |
214398d9 LJ |
177 | #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ |
178 | #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ | |
179 | #define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */ | |
180 | #define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ | |
181 | #define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from */ | |
182 | /* this addr */ | |
887e2ec9 SR |
183 | #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) |
184 | ||
185 | /* | |
186 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) | |
187 | */ | |
214398d9 LJ |
188 | #define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ |
189 | #define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ | |
887e2ec9 SR |
190 | |
191 | /* | |
192 | * Now the NAND chip has to be defined (no autodetection used!) | |
193 | */ | |
214398d9 LJ |
194 | #define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */ |
195 | #define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
196 | #define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */ | |
197 | #define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ | |
198 | #undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ | |
887e2ec9 | 199 | |
9d909604 SR |
200 | #define CFG_NAND_ECCSIZE 256 |
201 | #define CFG_NAND_ECCBYTES 3 | |
202 | #define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) | |
203 | #define CFG_NAND_OOBSIZE 16 | |
204 | #define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) | |
205 | #define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} | |
206 | ||
887e2ec9 | 207 | #ifdef CFG_ENV_IS_IN_NAND |
d12ae808 SR |
208 | /* |
209 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
210 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. | |
211 | */ | |
212 | #define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE | |
213 | #define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) | |
887e2ec9 SR |
214 | #define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) |
215 | #endif | |
216 | ||
214398d9 | 217 | /* |
887e2ec9 | 218 | * DDR SDRAM |
214398d9 LJ |
219 | */ |
220 | #define CFG_MBYTES_SDRAM (256) /* 256MB */ | |
02388983 | 221 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
214398d9 | 222 | #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ |
02388983 | 223 | #endif |
887e2ec9 | 224 | |
214398d9 | 225 | /* |
887e2ec9 | 226 | * I2C |
214398d9 LJ |
227 | */ |
228 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
229 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
230 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
887e2ec9 SR |
231 | #define CFG_I2C_SLAVE 0x7F |
232 | ||
233 | #define CFG_I2C_MULTI_EEPROMS | |
234 | #define CFG_I2C_EEPROM_ADDR (0xa8>>1) | |
235 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
236 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
237 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 | |
238 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
239 | ||
887e2ec9 | 240 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
214398d9 LJ |
241 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
242 | #define CONFIG_DTT_AD7414 1 /* use AD7414 */ | |
243 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
887e2ec9 SR |
244 | #define CFG_DTT_MAX_TEMP 70 |
245 | #define CFG_DTT_LOW_TEMP -30 | |
246 | #define CFG_DTT_HYSTERESIS 3 | |
247 | ||
248 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 249 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
887e2ec9 SR |
250 | "echo" |
251 | ||
252 | #undef CONFIG_BOOTARGS | |
253 | ||
e802594b SR |
254 | /* Setup some board specific values for the default environment variables */ |
255 | #ifndef CONFIG_RAINIER | |
256 | #define CONFIG_HOSTNAME sequoia | |
257 | #define CFG_BOOTFILE "bootfile=/tftpboot/sequoia/uImage\0" | |
258 | #define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" | |
259 | #else | |
260 | #define CONFIG_HOSTNAME rainier | |
261 | #define CFG_BOOTFILE "bootfile=/tftpboot/rainier/uImage\0" | |
262 | #define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" | |
263 | #endif | |
264 | ||
887e2ec9 | 265 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
e802594b SR |
266 | CFG_BOOTFILE \ |
267 | CFG_ROOTPATH \ | |
887e2ec9 | 268 | "netdev=eth0\0" \ |
887e2ec9 SR |
269 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
270 | "nfsroot=${serverip}:${rootpath}\0" \ | |
271 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
272 | "addip=setenv bootargs ${bootargs} " \ | |
273 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
274 | ":${hostname}:${netdev}:off panic=1\0" \ | |
275 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
276 | "flash_nfs=run nfsargs addip addtty;" \ | |
277 | "bootm ${kernel_addr}\0" \ | |
278 | "flash_self=run ramargs addip addtty;" \ | |
279 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
280 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
281 | "bootm\0" \ | |
4ef62514 SR |
282 | "kernel_addr=FC000000\0" \ |
283 | "ramdisk_addr=FC180000\0" \ | |
e802594b | 284 | "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ |
887e2ec9 | 285 | "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ |
e802594b | 286 | "cp.b 200000 FFFA0000 60000\0" \ |
d8ab58b2 | 287 | "upd=run load update\0" \ |
887e2ec9 SR |
288 | "" |
289 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
290 | ||
291 | #if 0 | |
292 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
293 | #else | |
294 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
295 | #endif | |
296 | ||
297 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
298 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
299 | ||
300 | #define CONFIG_M88E1111_PHY 1 | |
301 | #define CONFIG_IBM_EMAC4_V4 1 | |
302 | #define CONFIG_MII 1 /* MII PHY management */ | |
303 | #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ | |
304 | ||
214398d9 | 305 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
887e2ec9 SR |
306 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
307 | ||
308 | #define CONFIG_HAS_ETH0 | |
214398d9 LJ |
309 | #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */ |
310 | /* buffers & descriptors */ | |
887e2ec9 SR |
311 | #define CONFIG_NET_MULTI 1 |
312 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ | |
313 | #define CONFIG_PHY1_ADDR 1 | |
314 | ||
315 | /* USB */ | |
854bc8da | 316 | #ifdef CONFIG_440EPX |
2d146843 | 317 | #define CONFIG_USB_OHCI_NEW |
887e2ec9 | 318 | #define CONFIG_USB_STORAGE |
2d146843 MF |
319 | #define CFG_OHCI_BE_CONTROLLER |
320 | ||
321 | #undef CFG_USB_OHCI_BOARD_INIT | |
322 | #define CFG_USB_OHCI_CPU_INIT 1 | |
323 | #define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST | |
324 | #define CFG_USB_OHCI_SLOT_NAME "ppc440" | |
325 | #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 | |
887e2ec9 SR |
326 | |
327 | /* Comment this out to enable USB 1.1 device */ | |
328 | #define USB_2_0_DEVICE | |
329 | ||
854bc8da SR |
330 | #endif /* CONFIG_440EPX */ |
331 | ||
887e2ec9 SR |
332 | /* Partitions */ |
333 | #define CONFIG_MAC_PARTITION | |
334 | #define CONFIG_DOS_PARTITION | |
335 | #define CONFIG_ISO_PARTITION | |
336 | ||
079a136c JL |
337 | /* |
338 | * BOOTP options | |
339 | */ | |
340 | #define CONFIG_BOOTP_BOOTFILESIZE | |
341 | #define CONFIG_BOOTP_BOOTPATH | |
342 | #define CONFIG_BOOTP_GATEWAY | |
343 | #define CONFIG_BOOTP_HOSTNAME | |
052440b0 | 344 | #define CONFIG_BOOTP_SUBNETMASK |
079a136c | 345 | |
46da1e96 JL |
346 | /* |
347 | * Command line configuration. | |
348 | */ | |
349 | #include <config_cmd_default.h> | |
350 | ||
351 | #define CONFIG_CMD_ASKENV | |
352 | #define CONFIG_CMD_DHCP | |
353 | #define CONFIG_CMD_DTT | |
354 | #define CONFIG_CMD_DIAG | |
355 | #define CONFIG_CMD_EEPROM | |
356 | #define CONFIG_CMD_ELF | |
357 | #define CONFIG_CMD_FAT | |
358 | #define CONFIG_CMD_I2C | |
359 | #define CONFIG_CMD_IRQ | |
360 | #define CONFIG_CMD_MII | |
361 | #define CONFIG_CMD_NAND | |
362 | #define CONFIG_CMD_NET | |
363 | #define CONFIG_CMD_NFS | |
364 | #define CONFIG_CMD_PCI | |
365 | #define CONFIG_CMD_PING | |
366 | #define CONFIG_CMD_REGINFO | |
367 | #define CONFIG_CMD_SDRAM | |
368 | ||
369 | #ifdef CONFIG_440EPX | |
370 | #define CONFIG_CMD_USB | |
371 | #endif | |
372 | ||
9de469bd SR |
373 | #ifndef CONFIG_RAINIER |
374 | #define CFG_POST_FPU_ON CFG_POST_FPU | |
375 | #else | |
376 | #define CFG_POST_FPU_ON 0 | |
377 | #endif | |
887e2ec9 | 378 | |
a11e0696 | 379 | /* POST support */ |
214398d9 | 380 | #define CONFIG_POST (CFG_POST_CACHE | \ |
a11e0696 | 381 | CFG_POST_CPU | \ |
b4489621 | 382 | CFG_POST_ETHER | \ |
214398d9 LJ |
383 | CFG_POST_FPU_ON | \ |
384 | CFG_POST_I2C | \ | |
385 | CFG_POST_MEMORY | \ | |
386 | CFG_POST_SPR | \ | |
387 | CFG_POST_UART) | |
a11e0696 IL |
388 | |
389 | #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) | |
390 | #define CONFIG_LOGBUFFER | |
214398d9 | 391 | #define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ |
a11e0696 | 392 | |
214398d9 | 393 | #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ |
a11e0696 | 394 | |
887e2ec9 SR |
395 | #define CONFIG_SUPPORT_VFAT |
396 | ||
214398d9 | 397 | /* |
887e2ec9 | 398 | * Miscellaneous configurable options |
214398d9 | 399 | */ |
887e2ec9 SR |
400 | #define CFG_LONGHELP /* undef to save memory */ |
401 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
46da1e96 | 402 | #if defined(CONFIG_CMD_KGDB) |
887e2ec9 SR |
403 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
404 | #else | |
405 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
406 | #endif | |
214398d9 LJ |
407 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) |
408 | /* Print Buffer Size */ | |
887e2ec9 SR |
409 | #define CFG_MAXARGS 16 /* max number of command args */ |
410 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
411 | ||
412 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
413 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
414 | ||
415 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
214398d9 | 416 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
887e2ec9 SR |
417 | |
418 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
419 | ||
420 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
214398d9 LJ |
421 | #define CONFIG_LOOPW 1 /* enable loopw command */ |
422 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
887e2ec9 | 423 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
214398d9 | 424 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
887e2ec9 | 425 | |
214398d9 | 426 | /* |
887e2ec9 | 427 | * PCI stuff |
214398d9 | 428 | */ |
887e2ec9 | 429 | /* General PCI */ |
214398d9 LJ |
430 | #define CONFIG_PCI /* include pci support */ |
431 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
432 | #define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ | |
433 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
434 | #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */ | |
435 | /* CFG_PCI_MEMBASE */ | |
887e2ec9 | 436 | /* Board-specific PCI */ |
887e2ec9 SR |
437 | #define CFG_PCI_TARGET_INIT |
438 | #define CFG_PCI_MASTER_INIT | |
439 | ||
440 | #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ | |
441 | #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
442 | ||
443 | /* | |
214398d9 LJ |
444 | * For booting Linux, the board info and command line data have to be in the |
445 | * first 8 MB of memory, since this is the maximum mapped by the Linux kernel | |
446 | * during initialization. | |
887e2ec9 | 447 | */ |
214398d9 | 448 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
887e2ec9 | 449 | |
214398d9 | 450 | /* |
887e2ec9 | 451 | * External Bus Controller (EBC) Setup |
214398d9 | 452 | */ |
887e2ec9 SR |
453 | |
454 | /* | |
455 | * On Sequoia CS0 and CS3 are switched when configuring for NAND booting | |
456 | */ | |
457 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
214398d9 LJ |
458 | #define CFG_NAND_CS 3 /* NAND chip connected to CSx */ |
459 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
4be23a12 | 460 | #define CFG_EBC_PB0AP 0x03017200 |
2db63365 | 461 | #define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000) |
887e2ec9 | 462 | |
214398d9 | 463 | /* Memory Bank 3 (NAND-FLASH) initialization */ |
887e2ec9 | 464 | #define CFG_EBC_PB3AP 0x018003c0 |
2db63365 | 465 | #define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000) |
887e2ec9 | 466 | #else |
214398d9 LJ |
467 | #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ |
468 | /* Memory Bank 3 (NOR-FLASH) initialization */ | |
4be23a12 | 469 | #define CFG_EBC_PB3AP 0x03017200 |
2db63365 | 470 | #define CFG_EBC_PB3CR (CFG_FLASH_BASE | 0xda000) |
887e2ec9 | 471 | |
214398d9 | 472 | /* Memory Bank 0 (NAND-FLASH) initialization */ |
887e2ec9 | 473 | #define CFG_EBC_PB0AP 0x018003c0 |
2db63365 | 474 | #define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000) |
887e2ec9 SR |
475 | #endif |
476 | ||
214398d9 | 477 | /* Memory Bank 2 (CPLD) initialization */ |
887e2ec9 | 478 | #define CFG_EBC_PB2AP 0x24814580 |
2db63365 | 479 | #define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000) |
887e2ec9 | 480 | |
5a5958b7 SR |
481 | #define CFG_BCSR5_PCI66EN 0x80 |
482 | ||
214398d9 | 483 | /* |
43a2b0e7 | 484 | * NAND FLASH |
214398d9 | 485 | */ |
43a2b0e7 SR |
486 | #define CFG_MAX_NAND_DEVICE 1 |
487 | #define NAND_MAX_CHIPS 1 | |
488 | #define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) | |
214398d9 | 489 | #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ |
43a2b0e7 | 490 | |
214398d9 | 491 | /* |
b05e8bf5 LJ |
492 | * PPC440 GPIO Configuration |
493 | */ | |
494 | /* test-only: take GPIO init from pcs440ep ???? in config file */ | |
495 | #define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ | |
496 | { \ | |
497 | /* GPIO Core 0 */ \ | |
498 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ | |
499 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ | |
500 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ | |
501 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ | |
502 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ | |
503 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ | |
504 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ | |
505 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ | |
506 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ | |
507 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ | |
508 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ | |
509 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ | |
510 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ | |
511 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ | |
512 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \ | |
513 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ | |
514 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \ | |
515 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \ | |
516 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \ | |
517 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \ | |
518 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ | |
519 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ | |
520 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ | |
521 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ | |
522 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \ | |
523 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \ | |
524 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ | |
525 | {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ | |
526 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \ | |
527 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ | |
528 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ | |
529 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ | |
530 | }, \ | |
531 | { \ | |
532 | /* GPIO Core 1 */ \ | |
533 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ | |
534 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ | |
535 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ | |
536 | {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ | |
537 | {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \ | |
538 | {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ | |
539 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ | |
540 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ | |
541 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ | |
542 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ | |
543 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ | |
544 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ | |
545 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ | |
546 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ | |
547 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ | |
548 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ | |
549 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ | |
550 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ | |
551 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ | |
552 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ | |
553 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ | |
554 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ | |
555 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ | |
556 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \ | |
557 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ | |
558 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ | |
559 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ | |
560 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ | |
561 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ | |
562 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ | |
563 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ | |
564 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ | |
565 | } \ | |
566 | } | |
567 | ||
887e2ec9 SR |
568 | /* |
569 | * Internal Definitions | |
570 | * | |
571 | * Boot Flags | |
572 | */ | |
214398d9 LJ |
573 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
574 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
887e2ec9 | 575 | |
46da1e96 | 576 | #if defined(CONFIG_CMD_KGDB) |
214398d9 LJ |
577 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
578 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
887e2ec9 | 579 | #endif |
13628884 SR |
580 | |
581 | /* pass open firmware flat tree */ | |
582 | #define CONFIG_OF_LIBFDT 1 | |
583 | #define CONFIG_OF_BOARD_SETUP 1 | |
13628884 | 584 | |
bc778812 AG |
585 | #ifdef CONFIG_VIDEO |
586 | #define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */ | |
587 | #define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */ | |
588 | #define VIDEO_IO_OFFSET 0xe8000000 | |
589 | #define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET | |
590 | #define CONFIG_VIDEO_SW_CURSOR | |
591 | #define CONFIG_VIDEO_LOGO | |
592 | #define CONFIG_CFB_CONSOLE | |
593 | #define CONFIG_SPLASH_SCREEN | |
594 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
595 | #define CONFIG_CMD_BMP | |
596 | #endif | |
597 | ||
214398d9 | 598 | #endif /* __CONFIG_H */ |