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887e2ec9 | 1 | /* |
fc84a849 | 2 | * (C) Copyright 2006-2008 |
887e2ec9 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
7 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
214398d9 | 25 | /* |
e802594b | 26 | * sequoia.h - configuration for Sequoia & Rainier boards |
214398d9 | 27 | */ |
887e2ec9 SR |
28 | #ifndef __CONFIG_H |
29 | #define __CONFIG_H | |
30 | ||
214398d9 | 31 | /* |
887e2ec9 | 32 | * High Level Configuration Options |
214398d9 | 33 | */ |
e802594b | 34 | /* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ |
854bc8da | 35 | #ifndef CONFIG_RAINIER |
214398d9 | 36 | #define CONFIG_440EPX 1 /* Specific PPC440EPx */ |
72675dc6 | 37 | #define CONFIG_HOSTNAME sequoia |
854bc8da | 38 | #else |
214398d9 | 39 | #define CONFIG_440GRX 1 /* Specific PPC440GRx */ |
72675dc6 | 40 | #define CONFIG_HOSTNAME rainier |
854bc8da | 41 | #endif |
214398d9 LJ |
42 | #define CONFIG_440 1 /* ... PPC440 family */ |
43 | #define CONFIG_4xx 1 /* ... PPC4xx family */ | |
72675dc6 SR |
44 | |
45 | /* | |
46 | * Include common defines/options for all AMCC eval boards | |
47 | */ | |
48 | #include "amcc-common.h" | |
49 | ||
e3b8c78b JM |
50 | /* Detect Sequoia PLL input clock automatically via CPLD bit */ |
51 | #define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \ | |
193b4a3b | 52 | 33333333 : 33000000) |
887e2ec9 | 53 | |
bc778812 AG |
54 | /* |
55 | * Define this if you want support for video console with radeon 9200 pci card | |
56 | * Also set TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case | |
57 | */ | |
58 | #undef CONFIG_VIDEO | |
59 | ||
60 | #ifdef CONFIG_VIDEO | |
d25dfe08 SR |
61 | /* |
62 | * 44x dcache supported is working now on sequoia, but we don't enable | |
63 | * it yet since it needs further testing | |
64 | */ | |
214398d9 | 65 | #define CONFIG_4xx_DCACHE /* enable dcache */ |
d25dfe08 SR |
66 | #endif |
67 | ||
214398d9 LJ |
68 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
69 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
887e2ec9 | 70 | |
214398d9 LJ |
71 | /* |
72 | * Base addresses -- Note these are effective addresses where the actual | |
73 | * resources get mapped (not physical addresses). | |
74 | */ | |
4d332dbe | 75 | #define CFG_TLB_FOR_BOOT_FLASH 0x0003 |
887e2ec9 | 76 | #define CFG_BOOT_BASE_ADDR 0xf0000000 |
4ef62514 | 77 | #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ |
214398d9 LJ |
78 | #define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ |
79 | #define CFG_OCM_BASE 0xe0010000 /* ocm */ | |
a11e0696 | 80 | #define CFG_OCM_DATA_ADDR CFG_OCM_BASE |
214398d9 | 81 | #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ |
887e2ec9 SR |
82 | #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
83 | #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 | |
84 | #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 | |
85 | #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 | |
86 | ||
87 | /* Don't change either of these */ | |
88 | #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ | |
89 | ||
90 | #define CFG_USB2D0_BASE 0xe0000100 | |
91 | #define CFG_USB_DEVICE 0xe0000000 | |
92 | #define CFG_USB_HOST 0xe0000400 | |
93 | #define CFG_BCSR_BASE 0xc0000000 | |
94 | ||
214398d9 | 95 | /* |
887e2ec9 | 96 | * Initial RAM & stack pointer |
214398d9 | 97 | */ |
887e2ec9 | 98 | /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ |
887e2ec9 | 99 | #define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ |
887e2ec9 | 100 | #define CFG_INIT_RAM_END (4 << 10) |
214398d9 | 101 | #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ |
887e2ec9 | 102 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
a11e0696 | 103 | #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR |
887e2ec9 | 104 | |
214398d9 | 105 | /* |
887e2ec9 | 106 | * Serial Port |
214398d9 | 107 | */ |
887e2ec9 | 108 | #define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ |
887e2ec9 SR |
109 | /* define this if you want console on UART1 */ |
110 | #undef CONFIG_UART1_CONSOLE | |
111 | ||
214398d9 | 112 | /* |
887e2ec9 | 113 | * Environment |
214398d9 | 114 | */ |
d12ae808 | 115 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
5a1aceb0 | 116 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */ |
887e2ec9 | 117 | #else |
51bfee19 | 118 | #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environ vars */ |
0e8d1586 | 119 | #define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ |
887e2ec9 | 120 | #endif |
887e2ec9 | 121 | |
214398d9 | 122 | /* |
887e2ec9 | 123 | * FLASH related |
214398d9 LJ |
124 | */ |
125 | #define CFG_FLASH_CFI /* The flash is CFI compatible */ | |
00b1883a | 126 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
887e2ec9 SR |
127 | |
128 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } | |
129 | ||
214398d9 LJ |
130 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
131 | #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
887e2ec9 | 132 | |
214398d9 LJ |
133 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
134 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
887e2ec9 | 135 | |
214398d9 LJ |
136 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
137 | #define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ | |
887e2ec9 | 138 | |
214398d9 LJ |
139 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
140 | #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ | |
887e2ec9 | 141 | |
5a1aceb0 | 142 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
143 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
144 | #define CONFIG_ENV_ADDR ((-CFG_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) | |
145 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
887e2ec9 SR |
146 | |
147 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
148 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
149 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
887e2ec9 SR |
150 | #endif |
151 | ||
887e2ec9 SR |
152 | /* |
153 | * IPL (Initial Program Loader, integrated inside CPU) | |
154 | * Will load first 4k from NAND (SPL) into cache and execute it from there. | |
155 | * | |
156 | * SPL (Secondary Program Loader) | |
157 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL | |
158 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM | |
159 | * controller and the NAND controller so that the special U-Boot image can be | |
160 | * loaded from NAND to SDRAM. | |
161 | * | |
162 | * NUB (NAND U-Boot) | |
163 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started | |
164 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. | |
165 | * | |
166 | * On 440EPx the SPL is copied to SDRAM before the NAND controller is | |
167 | * set up. While still running from cache, I experienced problems accessing | |
168 | * the NAND controller. sr - 2006-08-25 | |
169 | */ | |
214398d9 LJ |
170 | #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ |
171 | #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ | |
172 | #define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */ | |
173 | #define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ | |
174 | #define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from */ | |
175 | /* this addr */ | |
887e2ec9 SR |
176 | #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) |
177 | ||
178 | /* | |
179 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) | |
180 | */ | |
214398d9 | 181 | #define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ |
3d4a746e | 182 | #define CFG_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */ |
887e2ec9 SR |
183 | |
184 | /* | |
185 | * Now the NAND chip has to be defined (no autodetection used!) | |
186 | */ | |
214398d9 LJ |
187 | #define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */ |
188 | #define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
189 | #define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */ | |
190 | #define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ | |
191 | #undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ | |
887e2ec9 | 192 | |
9d909604 SR |
193 | #define CFG_NAND_ECCSIZE 256 |
194 | #define CFG_NAND_ECCBYTES 3 | |
195 | #define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) | |
196 | #define CFG_NAND_OOBSIZE 16 | |
197 | #define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) | |
198 | #define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} | |
199 | ||
51bfee19 | 200 | #ifdef CONFIG_ENV_IS_IN_NAND |
d12ae808 SR |
201 | /* |
202 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
203 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. | |
204 | */ | |
0e8d1586 JCPV |
205 | #define CONFIG_ENV_SIZE CFG_NAND_BLOCK_SIZE |
206 | #define CONFIG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) | |
207 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) | |
887e2ec9 SR |
208 | #endif |
209 | ||
214398d9 | 210 | /* |
887e2ec9 | 211 | * DDR SDRAM |
214398d9 LJ |
212 | */ |
213 | #define CFG_MBYTES_SDRAM (256) /* 256MB */ | |
02388983 | 214 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
214398d9 | 215 | #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ |
02388983 | 216 | #endif |
14f73ca6 SR |
217 | #define CFG_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ |
218 | /* 440EPx errata CHIP 11 */ | |
887e2ec9 | 219 | |
214398d9 | 220 | /* |
887e2ec9 | 221 | * I2C |
214398d9 | 222 | */ |
214398d9 | 223 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
887e2ec9 SR |
224 | |
225 | #define CFG_I2C_MULTI_EEPROMS | |
226 | #define CFG_I2C_EEPROM_ADDR (0xa8>>1) | |
227 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
228 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
229 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 | |
230 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
231 | ||
887e2ec9 | 232 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
214398d9 LJ |
233 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ |
234 | #define CONFIG_DTT_AD7414 1 /* use AD7414 */ | |
235 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
887e2ec9 SR |
236 | #define CFG_DTT_MAX_TEMP 70 |
237 | #define CFG_DTT_LOW_TEMP -30 | |
238 | #define CFG_DTT_HYSTERESIS 3 | |
239 | ||
72675dc6 SR |
240 | /* |
241 | * Default environment variables | |
242 | */ | |
887e2ec9 | 243 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
72675dc6 SR |
244 | CONFIG_AMCC_DEF_ENV \ |
245 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
246 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
247 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
248 | CONFIG_AMCC_DEF_ENV_NAND_UPD \ | |
4ef62514 SR |
249 | "kernel_addr=FC000000\0" \ |
250 | "ramdisk_addr=FC180000\0" \ | |
887e2ec9 | 251 | "" |
887e2ec9 SR |
252 | |
253 | #define CONFIG_M88E1111_PHY 1 | |
254 | #define CONFIG_IBM_EMAC4_V4 1 | |
887e2ec9 SR |
255 | #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ |
256 | ||
214398d9 | 257 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
887e2ec9 SR |
258 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
259 | ||
260 | #define CONFIG_HAS_ETH0 | |
887e2ec9 SR |
261 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
262 | #define CONFIG_PHY1_ADDR 1 | |
263 | ||
264 | /* USB */ | |
854bc8da | 265 | #ifdef CONFIG_440EPX |
2d146843 | 266 | #define CONFIG_USB_OHCI_NEW |
887e2ec9 | 267 | #define CONFIG_USB_STORAGE |
2d146843 MF |
268 | #define CFG_OHCI_BE_CONTROLLER |
269 | ||
270 | #undef CFG_USB_OHCI_BOARD_INIT | |
271 | #define CFG_USB_OHCI_CPU_INIT 1 | |
272 | #define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST | |
273 | #define CFG_USB_OHCI_SLOT_NAME "ppc440" | |
274 | #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 | |
887e2ec9 SR |
275 | |
276 | /* Comment this out to enable USB 1.1 device */ | |
277 | #define USB_2_0_DEVICE | |
278 | ||
854bc8da SR |
279 | #endif /* CONFIG_440EPX */ |
280 | ||
887e2ec9 SR |
281 | /* Partitions */ |
282 | #define CONFIG_MAC_PARTITION | |
283 | #define CONFIG_DOS_PARTITION | |
284 | #define CONFIG_ISO_PARTITION | |
285 | ||
079a136c | 286 | /* |
72675dc6 | 287 | * Commands additional to the ones defined in amcc-common.h |
079a136c | 288 | */ |
46da1e96 | 289 | #define CONFIG_CMD_DTT |
46da1e96 | 290 | #define CONFIG_CMD_FAT |
46da1e96 | 291 | #define CONFIG_CMD_NAND |
46da1e96 | 292 | #define CONFIG_CMD_PCI |
46da1e96 JL |
293 | #define CONFIG_CMD_SDRAM |
294 | ||
295 | #ifdef CONFIG_440EPX | |
296 | #define CONFIG_CMD_USB | |
297 | #endif | |
298 | ||
9de469bd SR |
299 | #ifndef CONFIG_RAINIER |
300 | #define CFG_POST_FPU_ON CFG_POST_FPU | |
301 | #else | |
302 | #define CFG_POST_FPU_ON 0 | |
303 | #endif | |
887e2ec9 | 304 | |
a11e0696 | 305 | /* POST support */ |
214398d9 | 306 | #define CONFIG_POST (CFG_POST_CACHE | \ |
a11e0696 | 307 | CFG_POST_CPU | \ |
b4489621 | 308 | CFG_POST_ETHER | \ |
214398d9 LJ |
309 | CFG_POST_FPU_ON | \ |
310 | CFG_POST_I2C | \ | |
311 | CFG_POST_MEMORY | \ | |
312 | CFG_POST_SPR | \ | |
313 | CFG_POST_UART) | |
a11e0696 IL |
314 | |
315 | #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) | |
316 | #define CONFIG_LOGBUFFER | |
214398d9 | 317 | #define CFG_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */ |
a11e0696 | 318 | |
214398d9 | 319 | #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ |
a11e0696 | 320 | |
887e2ec9 SR |
321 | #define CONFIG_SUPPORT_VFAT |
322 | ||
214398d9 | 323 | /* |
887e2ec9 | 324 | * PCI stuff |
214398d9 | 325 | */ |
887e2ec9 | 326 | /* General PCI */ |
214398d9 LJ |
327 | #define CONFIG_PCI /* include pci support */ |
328 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
329 | #define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */ | |
330 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
53677ef1 | 331 | #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */ |
214398d9 | 332 | /* CFG_PCI_MEMBASE */ |
887e2ec9 | 333 | /* Board-specific PCI */ |
887e2ec9 SR |
334 | #define CFG_PCI_TARGET_INIT |
335 | #define CFG_PCI_MASTER_INIT | |
336 | ||
337 | #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ | |
338 | #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
339 | ||
214398d9 | 340 | /* |
887e2ec9 | 341 | * External Bus Controller (EBC) Setup |
214398d9 | 342 | */ |
887e2ec9 SR |
343 | |
344 | /* | |
345 | * On Sequoia CS0 and CS3 are switched when configuring for NAND booting | |
346 | */ | |
347 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
214398d9 LJ |
348 | #define CFG_NAND_CS 3 /* NAND chip connected to CSx */ |
349 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
4be23a12 | 350 | #define CFG_EBC_PB0AP 0x03017200 |
2db63365 | 351 | #define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000) |
887e2ec9 | 352 | |
214398d9 | 353 | /* Memory Bank 3 (NAND-FLASH) initialization */ |
887e2ec9 | 354 | #define CFG_EBC_PB3AP 0x018003c0 |
2db63365 | 355 | #define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000) |
887e2ec9 | 356 | #else |
214398d9 LJ |
357 | #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ |
358 | /* Memory Bank 3 (NOR-FLASH) initialization */ | |
4be23a12 | 359 | #define CFG_EBC_PB3AP 0x03017200 |
2db63365 | 360 | #define CFG_EBC_PB3CR (CFG_FLASH_BASE | 0xda000) |
887e2ec9 | 361 | |
214398d9 | 362 | /* Memory Bank 0 (NAND-FLASH) initialization */ |
887e2ec9 | 363 | #define CFG_EBC_PB0AP 0x018003c0 |
2db63365 | 364 | #define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000) |
887e2ec9 SR |
365 | #endif |
366 | ||
214398d9 | 367 | /* Memory Bank 2 (CPLD) initialization */ |
887e2ec9 | 368 | #define CFG_EBC_PB2AP 0x24814580 |
2db63365 | 369 | #define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000) |
887e2ec9 | 370 | |
5a5958b7 SR |
371 | #define CFG_BCSR5_PCI66EN 0x80 |
372 | ||
214398d9 | 373 | /* |
43a2b0e7 | 374 | * NAND FLASH |
214398d9 | 375 | */ |
43a2b0e7 SR |
376 | #define CFG_MAX_NAND_DEVICE 1 |
377 | #define NAND_MAX_CHIPS 1 | |
378 | #define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) | |
214398d9 | 379 | #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ |
43a2b0e7 | 380 | |
214398d9 | 381 | /* |
b05e8bf5 LJ |
382 | * PPC440 GPIO Configuration |
383 | */ | |
384 | /* test-only: take GPIO init from pcs440ep ???? in config file */ | |
385 | #define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ | |
386 | { \ | |
387 | /* GPIO Core 0 */ \ | |
388 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ | |
389 | {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ | |
390 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ | |
391 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ | |
392 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ | |
393 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ | |
394 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ | |
395 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ | |
396 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ | |
397 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ | |
398 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ | |
399 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ | |
400 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ | |
401 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ | |
402 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14 */ \ | |
403 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ | |
404 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \ | |
405 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \ | |
406 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \ | |
407 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \ | |
408 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ | |
409 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ | |
410 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ | |
411 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ | |
412 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \ | |
413 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \ | |
414 | {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ | |
415 | {GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ | |
416 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28 USB2D_TXVALID */ \ | |
417 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ | |
418 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ | |
419 | {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ | |
420 | }, \ | |
421 | { \ | |
422 | /* GPIO Core 1 */ \ | |
423 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ | |
424 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ | |
eab10073 SF |
425 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ |
426 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ | |
427 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N EBC_DATA(0) UART3_SIN*/ \ | |
428 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ | |
429 | {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT */ \ | |
430 | {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN */ \ | |
b05e8bf5 LJ |
431 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ |
432 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ | |
433 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ | |
434 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ | |
435 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ | |
436 | {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ | |
437 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ | |
438 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ | |
439 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ | |
440 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ | |
441 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ | |
442 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ | |
443 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ | |
444 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \ | |
445 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ | |
446 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \ | |
447 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ | |
448 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ | |
449 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ | |
450 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ | |
451 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ | |
452 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ | |
453 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ | |
454 | {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ | |
455 | } \ | |
456 | } | |
457 | ||
bc778812 AG |
458 | #ifdef CONFIG_VIDEO |
459 | #define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */ | |
460 | #define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */ | |
461 | #define VIDEO_IO_OFFSET 0xe8000000 | |
462 | #define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET | |
463 | #define CONFIG_VIDEO_SW_CURSOR | |
464 | #define CONFIG_VIDEO_LOGO | |
465 | #define CONFIG_CFB_CONSOLE | |
466 | #define CONFIG_SPLASH_SCREEN | |
467 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
468 | #define CONFIG_CMD_BMP | |
469 | #endif | |
470 | ||
214398d9 | 471 | #endif /* __CONFIG_H */ |