[people/ms/u-boot.git] / include / configs / tam3517-common.h

/*
 * Copyright (C) 2011
 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
 *
 * Copyright (C) 2009 TechNexion Ltd.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __TAM3517_H
#define __TAM3517_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		/* in a TI OMAP core */
#define CONFIG_OMAP_GPIO
#define CONFIG_OMAP_COMMON
#define CONFIG_SYS_GENERIC_BOARD

#define CONFIG_SYS_TEXT_BASE 0x80008000

#define CONFIG_SYS_CACHELINE_SIZE	64

#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
					2 * 1024 * 1024)
/*
 * DDR related
 */
#define CONFIG_OMAP3_MICRON_DDR		/* Micron DDR */
#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
#define CONFIG_SERIAL1			/* UART1 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION

/* EHCI */
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_USB_ULPI
#define CONFIG_USB_ULPI_VIEWPORT_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_STORAGE

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_EEPROM

#undef CONFIG_CMD_FLASH		/* only NAND on the SOM */
#undef CONFIG_CMD_IMLS

#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	400000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_SYS_I2C_OMAP34XX
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50		/* base address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1		/* bytes of address */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access */
							/* nand at CS0 */

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
							/* NAND devices */

#define CONFIG_AUTO_COMPLETE

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */

/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
#define CONFIG_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */

/* Redundant Environment */
#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
						2 * CONFIG_SYS_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/*
 * ethernet support, EMAC
 *
 */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_EMAC_MDIO_PHY_NUM	0
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_CONSOLE
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */

#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT	16
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
					 48, 49, 50, 51, 52, 53, 54, 55,\
					 56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE		256
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_SW

#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000

#define CONFIG_OF_LIBFDT
#define CONFIG_FIT
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_MTDPARTS

/* Setup MTD for NAND on the SOM */
#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO)," \
				"1m(u-boot),256k(env1)," \
				"256k(env2),6m(kernel),-(rootfs)"

#define	CONFIG_TAM3517_SETTINGS						\
	"netdev=eth0\0"							\
	"nandargs=setenv bootargs root=${nandroot} "			\
		"rootfstype=${nandrootfstype}\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip_sta=setenv bootargs ${bootargs} "			\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
		"else run addip_sta;fi\0"				\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=ttyO0,${baudrate}\0"				\
	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
	"loadaddr=82000000\0"						\
	"kernel_addr_r=82000000\0"					\
	"hostname=" __stringify(CONFIG_HOSTNAME) "\0"			\
	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0"		\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr}\0"				\
	"nandboot=run nandargs addip addtty addmtd addmisc;"		\
		"nand read ${kernel_addr_r} kernel\0"			\
		"bootm ${kernel_addr_r}\0"				\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r}\0"				\
	"net_self=if run net_self_load;then "				\
		"run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
		"else echo Images not loades;fi\0"			\
	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0"		\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0"			\
	"uboot_addr=0x80000\0"						\
	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
	"updatemlo=nandecc hw;nand erase 0 20000;"			\
		"nand write ${loadaddr} 0 20000\0"			\
	"upd=if run load;then echo Updating u-boot;if run update;"	\
		"then echo U-Boot updated;"				\
			"else echo Error updating u-boot !;"		\
			"echo Board without bootloader !!;"		\
		"fi;"							\
		"else echo U-Boot not downloaded..exiting;fi\0"		\


/*
 * this is common code for all TAM3517 boards.
 * MAC address is stored from manufacturer in
 * I2C EEPROM
 */
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
/*
 * The I2C EEPROM on the TAM3517 contains
 * mac address and production data
 */
struct tam3517_module_info {
	char customer[48];
	char product[48];

	/*
	 * bit 0~47  : sequence number
	 * bit 48~55 : week of year, from 0.
	 * bit 56~63 : year
	 */
	unsigned long long sequence_number;

	/*
	 * bit 0~7   : revision fixed
	 * bit 8~15  : revision major
	 * bit 16~31 : TNxxx
	 */
	unsigned int revision;
	unsigned char eth_addr[4][8];
	unsigned char _rev[100];
};

#define TAM3517_READ_EEPROM(info, ret) \
do {								\
	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,		\
		(void *)info, sizeof(*info)))			\
		ret = 1;					\
	else							\
		ret = 0;					\
} while (0)

#define TAM3517_READ_MAC_FROM_EEPROM(info)			\
do {								\
	char buf[80], ethname[20];				\
	int i;							\
	memset(buf, 0, sizeof(buf));				\
	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) {	\
		sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X",	\
			(info)->eth_addr[i][5],			\
			(info)->eth_addr[i][4],			\
			(info)->eth_addr[i][3],			\
			(info)->eth_addr[i][2],			\
			(info)->eth_addr[i][1],			\
			(info)->eth_addr[i][0]);			\
								\
		if (i)						\
			sprintf(ethname, "eth%daddr", i);	\
		else						\
			sprintf(ethname, "ethaddr");		\
		printf("Setting %s from EEPROM with %s\n", ethname, buf);\
		setenv(ethname, buf);				\
	}							\
} while (0)

/* The following macros are taken from Technexion's documentation */
#define TAM3517_sequence_number(info) \
	((info)->sequence_number % 0x1000000000000LL)
#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
#define TAM3517_year(info) ((info)->sequence_number >> 56)
#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
#define TAM3517_revision_tn(info) ((info)->revision >> 16)

#define TAM3517_PRINT_SOM_INFO(info)				\
do {								\
	printf("Vendor:%s\n", (info)->customer);		\
	printf("SOM:   %s\n", (info)->product);			\
	printf("SeqNr: %02llu%02llu%012llu\n",			\
		TAM3517_year(info),				\
		TAM3517_week_of_year(info),			\
		TAM3517_sequence_number(info));			\
	printf("Rev:   TN%u %u.%u\n",				\
		TAM3517_revision_tn(info),			\
		TAM3517_revision_major(info),			\
		TAM3517_revision_fixed(info));			\
} while (0)

#endif

#endif /* __TAM3517_H */
Commit	Line	Data
f9c6fac4 SB	1	/*
	2	* Copyright (C) 2011
	3	* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
	4	*
	5	* Copyright (C) 2009 TechNexion Ltd.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
f9c6fac4 SB	8	*/
	9
	10	#ifndef __TAM3517_H
	11	#define __TAM3517_H
	12
	13	/*
	14	* High Level Configuration Options
	15	*/
	16	#define CONFIG_OMAP /* in a TI OMAP core */
308252ad	17	#define CONFIG_OMAP_GPIO
806d2792	18	#define CONFIG_OMAP_COMMON
457baf54	19	#define CONFIG_SYS_GENERIC_BOARD
f9c6fac4 SB	20
	21	#define CONFIG_SYS_TEXT_BASE 0x80008000
	22
	23	#define CONFIG_SYS_CACHELINE_SIZE 64
	24
	25	#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
	26
	27	#include <asm/arch/cpu.h> /* get chip and board defs */
	28	#include <asm/arch/omap3.h>
	29
	30	/*
	31	* Display CPU and Board information
	32	*/
	33	#define CONFIG_DISPLAY_CPUINFO
	34	#define CONFIG_DISPLAY_BOARDINFO
	35
	36	/* Clock Defines */
	37	#define V_OSCK 26000000 /* Clock output from T2 */
	38	#define V_SCLK (V_OSCK >> 1)
	39
f9c6fac4 SB	40	#define CONFIG_MISC_INIT_R
	41
	42	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	43	#define CONFIG_SETUP_MEMORY_TAGS
	44	#define CONFIG_INITRD_TAG
	45	#define CONFIG_REVISION_TAG
	46
	47	/*
	48	* Size of malloc() pool
	49	*/
	50	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
	51	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
	52	2 * 1024 * 1024)
	53	/*
	54	* DDR related
	55	*/
	56	#define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */
	57	#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
	58
	59	/*
	60	* Hardware drivers
	61	*/
	62
	63	/*
	64	* NS16550 Configuration
	65	*/
	66	#define CONFIG_SYS_NS16550
	67	#define CONFIG_SYS_NS16550_SERIAL
	68	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	69	#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	70
	71	/*
	72	* select serial console configuration
	73	*/
	74	#define CONFIG_CONS_INDEX 1
	75	#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
	76	#define CONFIG_SERIAL1 /* UART1 */
	77
	78	/* allow to overwrite serial and ethaddr */
	79	#define CONFIG_ENV_OVERWRITE
	80	#define CONFIG_BAUDRATE 115200
	81	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	82	115200}
	83	#define CONFIG_MMC
	84	#define CONFIG_OMAP_HSMMC
	85	#define CONFIG_GENERIC_MMC
	86	#define CONFIG_DOS_PARTITION
	87
	88	/* EHCI */
	89	#define CONFIG_OMAP3_GPIO_5
	90	#define CONFIG_USB_EHCI
	91	#define CONFIG_USB_EHCI_OMAP
8c589d6f SB	92	#define CONFIG_USB_ULPI
8c589d6f SB	93	#define CONFIG_USB_ULPI_VIEWPORT_OMAP
f9c6fac4 SB	94	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
	95	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
	96	#define CONFIG_USB_STORAGE
	97
f9c6fac4 SB	98	/* commands to include */
	99	#include <config_cmd_default.h>
	100
	101	#define CONFIG_CMD_CACHE
	102	#define CONFIG_CMD_DHCP
	103	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	104	#define CONFIG_CMD_FAT /* FAT support */
	105	#define CONFIG_CMD_GPIO
	106	#define CONFIG_CMD_I2C /* I2C serial bus support */
	107	#define CONFIG_CMD_MII
	108	#define CONFIG_CMD_MMC /* MMC support */
	109	#define CONFIG_CMD_NET
	110	#define CONFIG_CMD_NFS
	111	#define CONFIG_CMD_NAND /* NAND support */
	112	#define CONFIG_CMD_PING
	113	#define CONFIG_CMD_USB
8103c6f0	114	#define CONFIG_CMD_EEPROM
f9c6fac4 SB	115
	116	#undef CONFIG_CMD_FLASH /* only NAND on the SOM */
	117	#undef CONFIG_CMD_IMLS
	118
	119	#define CONFIG_SYS_NO_FLASH
6789e84e HS	120	#define CONFIG_SYS_I2C
	121	#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
	122	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	123	#define CONFIG_SYS_I2C_OMAP34XX
8103c6f0 SB	124	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
	125	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
	126	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
f9c6fac4 SB	127
	128	/*
	129	* Board NAND Info.
	130	*/
	131	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	132	/* to access */
	133	/* nand at CS0 */
	134
	135	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	136	/* NAND devices */
f9c6fac4 SB	137
	138	#define CONFIG_AUTO_COMPLETE
	139
	140	/*
	141	* Miscellaneous configurable options
	142	*/
	143	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	144	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
f9c6fac4 SB	145	#define CONFIG_CMDLINE_EDITING
	146	#define CONFIG_AUTO_COMPLETE
	147	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	148
	149	/* Print Buffer Size */
	150	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	151	sizeof(CONFIG_SYS_PROMPT) + 16)
	152	#define CONFIG_SYS_MAXARGS 32 /* max number of command */
	153	/* args */
	154	/* Boot Argument Buffer Size */
	155	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	156	/* memtest works on */
	157	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	158	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	159	0x01F00000) /* 31MB */
	160
	161	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	162	/* address */
	163
	164	/*
	165	* AM3517 has 12 GP timers, they can be driven by the system clock
	166	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	167	* This rate is divided by a local divisor.
	168	*/
	169	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	170	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
f9c6fac4	171
f9c6fac4 SB	172	/*
	173	* Physical Memory Map
	174	*/
	175	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	176	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
f9c6fac4 SB	177	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	178
	179	/*
	180	* FLASH and environment organization
	181	*/
	182
	183	/* ** PISMO SUPPORT * */
0970051d	184	#define CONFIG_NAND
f9c6fac4	185	#define CONFIG_NAND_OMAP_GPMC
f9c6fac4 SB	186	#define CONFIG_ENV_IS_IN_NAND
	187	#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
	188
	189	/* Redundant Environment */
	190	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	191	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	192	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
	193	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
	194	2 * CONFIG_SYS_ENV_SECT_SIZE)
	195	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	196
	197	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	198	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	199	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	200	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	201	CONFIG_SYS_INIT_RAM_SIZE - \
	202	GENERATED_GBL_DATA_SIZE)
	203
	204	/*
	205	* ethernet support, EMAC
	206	*
	207	*/
	208	#define CONFIG_DRIVER_TI_EMAC
	209	#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	210	#define CONFIG_MII
	211	#define CONFIG_EMAC_MDIO_PHY_NUM 0
f9c6fac4 SB	212	#define CONFIG_BOOTP_DNS
	213	#define CONFIG_BOOTP_DNS2
	214	#define CONFIG_BOOTP_SEND_HOSTNAME
	215	#define CONFIG_NET_RETRY_COUNT 10
f9c6fac4 SB	216
f9c6fac4 SB	217	/* Defines for SPL */
47f7bcae	218	#define CONFIG_SPL_FRAMEWORK
d7cb93b2	219	#define CONFIG_SPL_BOARD_INIT
f9c6fac4 SB	220	#define CONFIG_SPL_CONSOLE
f9c6fac4 SB	221	#define CONFIG_SPL_NAND_SIMPLE
8ad59c9a	222	#define CONFIG_SPL_NAND_SOFTECC
f9c6fac4 SB	223	#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
	224
	225	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	226	#define CONFIG_SPL_LIBDISK_SUPPORT
	227	#define CONFIG_SPL_I2C_SUPPORT
	228	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	229	#define CONFIG_SPL_SERIAL_SUPPORT
16e41c85	230	#define CONFIG_SPL_GPIO_SUPPORT
f9c6fac4 SB	231	#define CONFIG_SPL_POWER_SUPPORT
f9c6fac4 SB	232	#define CONFIG_SPL_NAND_SUPPORT
6f2f01b9 SW	233	#define CONFIG_SPL_NAND_BASE
	234	#define CONFIG_SPL_NAND_DRIVERS
	235	#define CONFIG_SPL_NAND_ECC
f9c6fac4 SB	236	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	237
	238	#define CONFIG_SPL_TEXT_BASE 0x40200000 /CONFIG_SYS_SRAM_START/
e0820ccc	239	#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
f9c6fac4 SB	240	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
	241
	242	#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
	243	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	244	#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
	245	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	246
	247	/* NAND boot config */
b80a6603	248	#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
f9c6fac4 SB	249	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	250	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	251	#define CONFIG_SYS_NAND_OOBSIZE 64
	252	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	253	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	254	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	255	#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
	256	48, 49, 50, 51, 52, 53, 54, 55,\
	257	56, 57, 58, 59, 60, 61, 62, 63}
	258	#define CONFIG_SYS_NAND_ECCSIZE 256
	259	#define CONFIG_SYS_NAND_ECCBYTES 3
3f719069	260	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
f9c6fac4	261
f9c6fac4 SB	262	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	263
	264	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	265	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
	266
	267	#define CONFIG_OF_LIBFDT
	268	#define CONFIG_FIT
	269	#define CONFIG_CMD_UBI
	270	#define CONFIG_CMD_UBIFS
	271	#define CONFIG_RBTREE
	272	#define CONFIG_LZO
	273	#define CONFIG_MTD_PARTITIONS
	274	#define CONFIG_MTD_DEVICE
	275	#define CONFIG_CMD_MTDPARTS
	276
	277	/* Setup MTD for NAND on the SOM */
	278	#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
	279	#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
1fdabedd SB	280	"1m(u-boot),256k(env1)," \
1fdabedd SB	281	"256k(env2),6m(kernel),-(rootfs)"
f9c6fac4	282
f9c6fac4 SB	283	#define CONFIG_TAM3517_SETTINGS \
	284	"netdev=eth0\0" \
	285	"nandargs=setenv bootargs root=${nandroot} " \
	286	"rootfstype=${nandrootfstype}\0" \
	287	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	288	"nfsroot=${serverip}:${rootpath}\0" \
	289	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	290	"addip_sta=setenv bootargs ${bootargs} " \
	291	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	292	":${hostname}:${netdev}:off panic=1\0" \
	293	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
	294	"addip=if test -n ${ipdyn};then run addip_dyn;" \
	295	"else run addip_sta;fi\0" \
	296	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	297	"addtty=setenv bootargs ${bootargs}" \
	298	" console=ttyO0,${baudrate}\0" \
	299	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
	300	"loadaddr=82000000\0" \
	301	"kernel_addr_r=82000000\0" \
93ea89f0 MV	302	"hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
93ea89f0 MV	303	"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
f9c6fac4 SB	304	"flash_self=run ramargs addip addtty addmtd addmisc;" \
	305	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	306	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
	307	"bootm ${kernel_addr}\0" \
	308	"nandboot=run nandargs addip addtty addmtd addmisc;" \
	309	"nand read ${kernel_addr_r} kernel\0" \
	310	"bootm ${kernel_addr_r}\0" \
	311	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	312	"run nfsargs addip addtty addmtd addmisc;" \
	313	"bootm ${kernel_addr_r}\0" \
	314	"net_self=if run net_self_load;then " \
	315	"run ramargs addip addtty addmtd addmisc;" \
	316	"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
	317	"else echo Images not loades;fi\0" \
93ea89f0	318	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
f9c6fac4 SB	319	"load=tftp ${loadaddr} ${u-boot}\0" \
f9c6fac4 SB	320	"loadmlo=tftp ${loadaddr} ${mlo}\0" \
93ea89f0	321	"mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
f9c6fac4 SB	322	"uboot_addr=0x80000\0" \
	323	"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
	324	"nand write ${loadaddr} ${uboot_addr} 80000\0" \
	325	"updatemlo=nandecc hw;nand erase 0 20000;" \
	326	"nand write ${loadaddr} 0 20000\0" \
	327	"upd=if run load;then echo Updating u-boot;if run update;" \
	328	"then echo U-Boot updated;" \
	329	"else echo Error updating u-boot !;" \
	330	"echo Board without bootloader !!;" \
	331	"fi;" \
	332	"else echo U-Boot not downloaded..exiting;fi\0" \
	333
8103c6f0 SB	334
	335	/*
	336	* this is common code for all TAM3517 boards.
	337	* MAC address is stored from manufacturer in
	338	* I2C EEPROM
	339	*/
	340	#if !(defined(__KERNEL_STRICT_NAMES) \|\| defined(__ASSEMBLY__))
8103c6f0 SB	341	/*
	342	* The I2C EEPROM on the TAM3517 contains
	343	* mac address and production data
	344	*/
	345	struct tam3517_module_info {
	346	char customer[48];
	347	char product[48];
	348
	349	/*
	350	* bit 0~47 : sequence number
	351	* bit 48~55 : week of year, from 0.
	352	* bit 56~63 : year
	353	*/
	354	unsigned long long sequence_number;
	355
	356	/*
	357	* bit 0~7 : revision fixed
	358	* bit 8~15 : revision major
	359	* bit 16~31 : TNxxx
	360	*/
	361	unsigned int revision;
	362	unsigned char eth_addr[4][8];
	363	unsigned char _rev[100];
	364	};
	365
31f5b651 SB	366	#define TAM3517_READ_EEPROM(info, ret) \
31f5b651 SB	367	do { \
6789e84e	368	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); \
8103c6f0	369	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, \
31f5b651 SB	370	(void )info, sizeof(info))) \
	371	ret = 1; \
	372	else \
	373	ret = 0; \
	374	} while (0)
	375
	376	#define TAM3517_READ_MAC_FROM_EEPROM(info) \
	377	do { \
	378	char buf[80], ethname[20]; \
	379	int i; \
8103c6f0	380	memset(buf, 0, sizeof(buf)); \
31f5b651	381	for (i = 0 ; i < ARRAY_SIZE((info)->eth_addr); i++) { \
8103c6f0	382	sprintf(buf, "%02X:%02X:%02X:%02X:%02X:%02X", \
31f5b651 SB	383	(info)->eth_addr[i][5], \
	384	(info)->eth_addr[i][4], \
	385	(info)->eth_addr[i][3], \
	386	(info)->eth_addr[i][2], \
	387	(info)->eth_addr[i][1], \
	388	(info)->eth_addr[i][0]); \
8103c6f0 SB	389	\
	390	if (i) \
	391	sprintf(ethname, "eth%daddr", i); \
	392	else \
	393	sprintf(ethname, "ethaddr"); \
	394	printf("Setting %s from EEPROM with %s\n", ethname, buf);\
	395	setenv(ethname, buf); \
	396	} \
	397	} while (0)
31f5b651 SB	398
	399	/* The following macros are taken from Technexion's documentation */
	400	#define TAM3517_sequence_number(info) \
	401	((info)->sequence_number % 0x1000000000000LL)
	402	#define TAM3517_week_of_year(info) (((info)->sequence_number >> 48) % 0x100)
	403	#define TAM3517_year(info) ((info)->sequence_number >> 56)
	404	#define TAM3517_revision_fixed(info) ((info)->revision % 0x100)
	405	#define TAM3517_revision_major(info) (((info)->revision >> 8) % 0x100)
	406	#define TAM3517_revision_tn(info) ((info)->revision >> 16)
	407
	408	#define TAM3517_PRINT_SOM_INFO(info) \
	409	do { \
	410	printf("Vendor:%s\n", (info)->customer); \
	411	printf("SOM: %s\n", (info)->product); \
	412	printf("SeqNr: %02llu%02llu%012llu\n", \
	413	TAM3517_year(info), \
	414	TAM3517_week_of_year(info), \
	415	TAM3517_sequence_number(info)); \
	416	printf("Rev: TN%u %u.%u\n", \
	417	TAM3517_revision_tn(info), \
	418	TAM3517_revision_major(info), \
	419	TAM3517_revision_fixed(info)); \
	420	} while (0)
	421
8103c6f0 SB	422	#endif
8103c6f0 SB	423
f9c6fac4	424	#endif /* __TAM3517_H */