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c157d8e2 | 1 | /* |
700200c6 | 2 | * (C) Copyright 2005-2007 |
84286386 | 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
c157d8e2 SR |
4 | * |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /************************************************************************ | |
700200c6 | 25 | * yosemite.h - configuration for Yosemite & Yellowstone boards |
c157d8e2 SR |
26 | ***********************************************************************/ |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /*----------------------------------------------------------------------- | |
31 | * High Level Configuration Options | |
32 | *----------------------------------------------------------------------*/ | |
700200c6 SR |
33 | /* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/ |
34 | #ifndef CONFIG_YELLOWSTONE | |
700200c6 SR |
35 | #define CONFIG_440EP 1 /* Specific PPC440EP support */ |
36 | #define CONFIG_HOSTNAME yosemite | |
37 | #else | |
38 | #define CONFIG_440GR 1 /* Specific PPC440GR support */ | |
39 | #define CONFIG_HOSTNAME yellowstone | |
40 | #endif | |
efa35cf1 | 41 | #define CONFIG_440 1 /* ... PPC440 family */ |
700200c6 | 42 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
c157d8e2 SR |
43 | #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ |
44 | ||
2ae18241 WD |
45 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
46 | ||
72675dc6 SR |
47 | /* |
48 | * Include common defines/options for all AMCC eval boards | |
49 | */ | |
50 | #include "amcc-common.h" | |
51 | ||
84286386 SR |
52 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
53 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
f3443867 | 54 | #define CONFIG_BOARD_RESET 1 /* call board_reset() */ |
84286386 | 55 | |
c157d8e2 SR |
56 | /*----------------------------------------------------------------------- |
57 | * Base addresses -- Note these are effective addresses where the | |
58 | * actual resources get mapped (not physical addresses) | |
59 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
60 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ |
61 | #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ | |
62 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 | |
63 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 | |
64 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 | |
c157d8e2 SR |
65 | |
66 | /*Don't change either of these*/ | |
6d0f6bcf | 67 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ |
c157d8e2 SR |
68 | /*Don't change either of these*/ |
69 | ||
6d0f6bcf JCPV |
70 | #define CONFIG_SYS_USB_DEVICE 0x50000000 |
71 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000 | |
72 | #define CONFIG_SYS_BCSR_BASE (CONFIG_SYS_NVRAM_BASE_ADDR | 0x2000) | |
73 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 | |
c157d8e2 SR |
74 | |
75 | /*----------------------------------------------------------------------- | |
76 | * Initial RAM & stack pointer (placed in SDRAM) | |
77 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
78 | #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
79 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ | |
553f0982 | 80 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
25ddd1fb | 81 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 82 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
c157d8e2 | 83 | |
c157d8e2 SR |
84 | /*----------------------------------------------------------------------- |
85 | * Serial Port | |
86 | *----------------------------------------------------------------------*/ | |
550650dd | 87 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
6d0f6bcf | 88 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ |
c157d8e2 | 89 | |
c157d8e2 | 90 | /*----------------------------------------------------------------------- |
84286386 | 91 | * Environment |
c157d8e2 | 92 | *----------------------------------------------------------------------*/ |
84286386 SR |
93 | /* |
94 | * Define here the location of the environment variables (FLASH or EEPROM). | |
95 | * Note: DENX encourages to use redundant environment in FLASH. | |
96 | */ | |
97 | #if 1 | |
5a1aceb0 | 98 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
84286386 | 99 | #else |
bb1f8b4f | 100 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
84286386 | 101 | #endif |
c157d8e2 SR |
102 | |
103 | /*----------------------------------------------------------------------- | |
104 | * FLASH related | |
105 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 106 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 107 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
6d0f6bcf | 108 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ |
c157d8e2 | 109 | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
111 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
c157d8e2 | 112 | |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
114 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
c157d8e2 | 115 | |
6d0f6bcf | 116 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
278bc4b3 | 117 | |
6d0f6bcf | 118 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
84286386 | 119 | |
5a1aceb0 | 120 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 121 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
6d0f6bcf | 122 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 123 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
84286386 SR |
124 | |
125 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
126 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
127 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5a1aceb0 | 128 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
c157d8e2 SR |
129 | |
130 | /*----------------------------------------------------------------------- | |
131 | * DDR SDRAM | |
132 | *----------------------------------------------------------------------*/ | |
095b8a37 | 133 | #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ |
135 | #define CONFIG_SYS_SDRAM_BANKS (2) | |
84286386 | 136 | |
c157d8e2 SR |
137 | /*----------------------------------------------------------------------- |
138 | * I2C | |
139 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 140 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
c157d8e2 | 141 | |
6d0f6bcf JCPV |
142 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
143 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) | |
144 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
145 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
146 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
c157d8e2 | 147 | |
bb1f8b4f | 148 | #ifdef CONFIG_ENV_IS_IN_EEPROM |
0e8d1586 JCPV |
149 | #define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */ |
150 | #define CONFIG_ENV_OFFSET 0x0 | |
bb1f8b4f | 151 | #endif /* CONFIG_ENV_IS_IN_EEPROM */ |
84286386 | 152 | |
a90921f7 SR |
153 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
154 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ | |
155 | #define CONFIG_DTT_AD7414 1 /* use AD7414 */ | |
156 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
6d0f6bcf JCPV |
157 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
158 | #define CONFIG_SYS_DTT_LOW_TEMP -30 | |
159 | #define CONFIG_SYS_DTT_HYSTERESIS 3 | |
a90921f7 | 160 | |
72675dc6 SR |
161 | /* |
162 | * Default environment variables | |
163 | */ | |
84286386 | 164 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
72675dc6 SR |
165 | CONFIG_AMCC_DEF_ENV \ |
166 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
167 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
168 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
84286386 | 169 | "kernel_addr=fc000000\0" \ |
56ced709 | 170 | "ramdisk_addr=fc180000\0" \ |
84286386 | 171 | "" |
c157d8e2 | 172 | |
4adb3023 | 173 | #define CONFIG_HAS_ETH0 1 /* add support for "ethaddr" */ |
c157d8e2 SR |
174 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
175 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ | |
72675dc6 | 176 | #define CONFIG_PHY1_ADDR 3 |
c157d8e2 SR |
177 | |
178 | /* Partitions */ | |
179 | #define CONFIG_MAC_PARTITION | |
180 | #define CONFIG_DOS_PARTITION | |
181 | #define CONFIG_ISO_PARTITION | |
182 | ||
846b0dd2 | 183 | #ifdef CONFIG_440EP |
c157d8e2 | 184 | /* USB */ |
7b59b3c7 | 185 | #define CONFIG_USB_OHCI_NEW |
c157d8e2 | 186 | #define CONFIG_USB_STORAGE |
6d0f6bcf | 187 | #define CONFIG_SYS_OHCI_BE_CONTROLLER |
c157d8e2 | 188 | |
6d0f6bcf JCPV |
189 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
190 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | |
191 | #define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_PERIPHERAL_BASE | 0x1000) | |
192 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" | |
193 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
53e336e9 | 194 | |
700200c6 | 195 | /* Comment this out to enable USB 1.1 device */ |
c157d8e2 | 196 | #define USB_2_0_DEVICE |
700200c6 | 197 | |
700200c6 | 198 | #define CONFIG_SUPPORT_VFAT |
700200c6 | 199 | #endif /* CONFIG_440EP */ |
c157d8e2 SR |
200 | |
201 | #ifdef DEBUG | |
202 | #define CONFIG_PANIC_HANG | |
203 | #else | |
204 | #define CONFIG_HW_WATCHDOG /* watchdog */ | |
205 | #endif | |
206 | ||
079a136c | 207 | /* |
72675dc6 | 208 | * Commands additional to the ones defined in amcc-common.h |
079a136c | 209 | */ |
a90921f7 | 210 | #define CONFIG_CMD_DTT |
dca3b3d6 | 211 | #define CONFIG_CMD_PCI |
dca3b3d6 JL |
212 | |
213 | #ifdef CONFIG_440EP | |
214 | #define CONFIG_CMD_USB | |
215 | #define CONFIG_CMD_FAT | |
216 | #define CONFIG_CMD_EXT2 | |
217 | #endif | |
218 | ||
c157d8e2 SR |
219 | /*----------------------------------------------------------------------- |
220 | * PCI stuff | |
221 | *----------------------------------------------------------------------- | |
222 | */ | |
223 | /* General PCI */ | |
84286386 SR |
224 | #define CONFIG_PCI /* include pci support */ |
225 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ | |
226 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 227 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/ |
c157d8e2 SR |
228 | |
229 | /* Board-specific PCI */ | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_PCI_TARGET_INIT |
231 | #define CONFIG_SYS_PCI_MASTER_INIT | |
c157d8e2 | 232 | |
6d0f6bcf JCPV |
233 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
234 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
c157d8e2 | 235 | |
36adff36 SR |
236 | /*----------------------------------------------------------------------- |
237 | * External Bus Controller (EBC) Setup | |
238 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE |
240 | #define CONFIG_SYS_CPLD 0x80000000 | |
36adff36 SR |
241 | |
242 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_EBC_PB0AP 0x03017300 |
244 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) | |
36adff36 SR |
245 | |
246 | /* Memory Bank 2 (CPLD) initialization */ | |
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_EBC_PB2AP 0x04814500 |
248 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD | 0x18000) | |
36adff36 | 249 | |
6d0f6bcf | 250 | #define CONFIG_SYS_BCSR5_PCI66EN 0x80 |
5a5958b7 | 251 | |
c157d8e2 | 252 | #endif /* __CONFIG_H */ |