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c157d8e2 | 1 | /* |
700200c6 | 2 | * (C) Copyright 2005-2007 |
84286386 | 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
c157d8e2 | 4 | * |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
c157d8e2 SR |
6 | */ |
7 | ||
8 | /************************************************************************ | |
700200c6 | 9 | * yosemite.h - configuration for Yosemite & Yellowstone boards |
c157d8e2 SR |
10 | ***********************************************************************/ |
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /*----------------------------------------------------------------------- | |
15 | * High Level Configuration Options | |
16 | *----------------------------------------------------------------------*/ | |
700200c6 SR |
17 | /* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/ |
18 | #ifndef CONFIG_YELLOWSTONE | |
700200c6 SR |
19 | #define CONFIG_440EP 1 /* Specific PPC440EP support */ |
20 | #define CONFIG_HOSTNAME yosemite | |
21 | #else | |
22 | #define CONFIG_440GR 1 /* Specific PPC440GR support */ | |
23 | #define CONFIG_HOSTNAME yellowstone | |
24 | #endif | |
efa35cf1 | 25 | #define CONFIG_440 1 /* ... PPC440 family */ |
c157d8e2 SR |
26 | #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ |
27 | ||
2ae18241 WD |
28 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
29 | ||
72675dc6 SR |
30 | /* |
31 | * Include common defines/options for all AMCC eval boards | |
32 | */ | |
33 | #include "amcc-common.h" | |
34 | ||
84286386 | 35 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
f3443867 | 36 | #define CONFIG_BOARD_RESET 1 /* call board_reset() */ |
84286386 | 37 | |
c157d8e2 SR |
38 | /*----------------------------------------------------------------------- |
39 | * Base addresses -- Note these are effective addresses where the | |
40 | * actual resources get mapped (not physical addresses) | |
41 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
42 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ |
43 | #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ | |
44 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 | |
45 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 | |
46 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 | |
c157d8e2 SR |
47 | |
48 | /*Don't change either of these*/ | |
6d0f6bcf | 49 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ |
c157d8e2 SR |
50 | /*Don't change either of these*/ |
51 | ||
6d0f6bcf JCPV |
52 | #define CONFIG_SYS_USB_DEVICE 0x50000000 |
53 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000 | |
54 | #define CONFIG_SYS_BCSR_BASE (CONFIG_SYS_NVRAM_BASE_ADDR | 0x2000) | |
55 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 | |
c157d8e2 SR |
56 | |
57 | /*----------------------------------------------------------------------- | |
58 | * Initial RAM & stack pointer (placed in SDRAM) | |
59 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
60 | #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
61 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ | |
553f0982 | 62 | #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) |
25ddd1fb | 63 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 64 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
c157d8e2 | 65 | |
c157d8e2 SR |
66 | /*----------------------------------------------------------------------- |
67 | * Serial Port | |
68 | *----------------------------------------------------------------------*/ | |
550650dd | 69 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
6d0f6bcf | 70 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ |
c157d8e2 | 71 | |
c157d8e2 | 72 | /*----------------------------------------------------------------------- |
84286386 | 73 | * Environment |
c157d8e2 | 74 | *----------------------------------------------------------------------*/ |
84286386 SR |
75 | /* |
76 | * Define here the location of the environment variables (FLASH or EEPROM). | |
77 | * Note: DENX encourages to use redundant environment in FLASH. | |
78 | */ | |
79 | #if 1 | |
5a1aceb0 | 80 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
84286386 | 81 | #else |
bb1f8b4f | 82 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
84286386 | 83 | #endif |
c157d8e2 SR |
84 | |
85 | /*----------------------------------------------------------------------- | |
86 | * FLASH related | |
87 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 88 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ |
00b1883a | 89 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
6d0f6bcf | 90 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ |
c157d8e2 | 91 | |
6d0f6bcf JCPV |
92 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
93 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
c157d8e2 | 94 | |
6d0f6bcf JCPV |
95 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
96 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
c157d8e2 | 97 | |
6d0f6bcf | 98 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
278bc4b3 | 99 | |
6d0f6bcf | 100 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
84286386 | 101 | |
5a1aceb0 | 102 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 103 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
6d0f6bcf | 104 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 105 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
84286386 SR |
106 | |
107 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
108 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
109 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5a1aceb0 | 110 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
c157d8e2 SR |
111 | |
112 | /*----------------------------------------------------------------------- | |
113 | * DDR SDRAM | |
114 | *----------------------------------------------------------------------*/ | |
095b8a37 | 115 | #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ |
6d0f6bcf JCPV |
116 | #define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ |
117 | #define CONFIG_SYS_SDRAM_BANKS (2) | |
84286386 | 118 | |
c157d8e2 SR |
119 | /*----------------------------------------------------------------------- |
120 | * I2C | |
121 | *----------------------------------------------------------------------*/ | |
880540de | 122 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 |
c157d8e2 | 123 | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) |
125 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
126 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
127 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
c157d8e2 | 128 | |
bb1f8b4f | 129 | #ifdef CONFIG_ENV_IS_IN_EEPROM |
0e8d1586 JCPV |
130 | #define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */ |
131 | #define CONFIG_ENV_OFFSET 0x0 | |
bb1f8b4f | 132 | #endif /* CONFIG_ENV_IS_IN_EEPROM */ |
84286386 | 133 | |
a90921f7 SR |
134 | /* I2C SYSMON (LM75, AD7414 is almost compatible) */ |
135 | #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ | |
136 | #define CONFIG_DTT_AD7414 1 /* use AD7414 */ | |
137 | #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ | |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_DTT_MAX_TEMP 70 |
139 | #define CONFIG_SYS_DTT_LOW_TEMP -30 | |
140 | #define CONFIG_SYS_DTT_HYSTERESIS 3 | |
a90921f7 | 141 | |
72675dc6 SR |
142 | /* |
143 | * Default environment variables | |
144 | */ | |
84286386 | 145 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
72675dc6 SR |
146 | CONFIG_AMCC_DEF_ENV \ |
147 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
148 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
149 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
84286386 | 150 | "kernel_addr=fc000000\0" \ |
56ced709 | 151 | "ramdisk_addr=fc180000\0" \ |
84286386 | 152 | "" |
c157d8e2 | 153 | |
4adb3023 | 154 | #define CONFIG_HAS_ETH0 1 /* add support for "ethaddr" */ |
c157d8e2 SR |
155 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
156 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ | |
72675dc6 | 157 | #define CONFIG_PHY1_ADDR 3 |
c157d8e2 SR |
158 | |
159 | /* Partitions */ | |
c157d8e2 | 160 | |
846b0dd2 | 161 | #ifdef CONFIG_440EP |
c157d8e2 | 162 | /* USB */ |
7b59b3c7 | 163 | #define CONFIG_USB_OHCI_NEW |
6d0f6bcf | 164 | #define CONFIG_SYS_OHCI_BE_CONTROLLER |
c157d8e2 | 165 | |
6d0f6bcf JCPV |
166 | #undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
167 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | |
168 | #define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_PERIPHERAL_BASE | 0x1000) | |
169 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" | |
170 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
53e336e9 | 171 | |
700200c6 | 172 | /* Comment this out to enable USB 1.1 device */ |
c157d8e2 | 173 | #define USB_2_0_DEVICE |
700200c6 | 174 | |
700200c6 | 175 | #define CONFIG_SUPPORT_VFAT |
700200c6 | 176 | #endif /* CONFIG_440EP */ |
c157d8e2 SR |
177 | |
178 | #ifdef DEBUG | |
179 | #define CONFIG_PANIC_HANG | |
180 | #else | |
181 | #define CONFIG_HW_WATCHDOG /* watchdog */ | |
182 | #endif | |
183 | ||
079a136c | 184 | /* |
72675dc6 | 185 | * Commands additional to the ones defined in amcc-common.h |
079a136c | 186 | */ |
a90921f7 | 187 | #define CONFIG_CMD_DTT |
dca3b3d6 | 188 | #define CONFIG_CMD_PCI |
dca3b3d6 JL |
189 | |
190 | #ifdef CONFIG_440EP | |
dca3b3d6 JL |
191 | #endif |
192 | ||
c157d8e2 SR |
193 | /*----------------------------------------------------------------------- |
194 | * PCI stuff | |
195 | *----------------------------------------------------------------------- | |
196 | */ | |
197 | /* General PCI */ | |
842033e6 | 198 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
84286386 | 199 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 200 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/ |
c157d8e2 SR |
201 | |
202 | /* Board-specific PCI */ | |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_PCI_TARGET_INIT |
204 | #define CONFIG_SYS_PCI_MASTER_INIT | |
c157d8e2 | 205 | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
207 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
c157d8e2 | 208 | |
36adff36 SR |
209 | /*----------------------------------------------------------------------- |
210 | * External Bus Controller (EBC) Setup | |
211 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
212 | #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE |
213 | #define CONFIG_SYS_CPLD 0x80000000 | |
36adff36 SR |
214 | |
215 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_EBC_PB0AP 0x03017300 |
217 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) | |
36adff36 SR |
218 | |
219 | /* Memory Bank 2 (CPLD) initialization */ | |
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_EBC_PB2AP 0x04814500 |
221 | #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD | 0x18000) | |
36adff36 | 222 | |
6d0f6bcf | 223 | #define CONFIG_SYS_BCSR5_PCI66EN 0x80 |
5a5958b7 | 224 | |
c157d8e2 | 225 | #endif /* __CONFIG_H */ |