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Commit | Line | Data |
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c157d8e2 | 1 | /* |
700200c6 | 2 | * (C) Copyright 2005-2007 |
84286386 | 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
c157d8e2 SR |
4 | * |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /************************************************************************ | |
700200c6 | 25 | * yosemite.h - configuration for Yosemite & Yellowstone boards |
c157d8e2 SR |
26 | ***********************************************************************/ |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /*----------------------------------------------------------------------- | |
31 | * High Level Configuration Options | |
32 | *----------------------------------------------------------------------*/ | |
700200c6 SR |
33 | /* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/ |
34 | #ifndef CONFIG_YELLOWSTONE | |
700200c6 SR |
35 | #define CONFIG_440EP 1 /* Specific PPC440EP support */ |
36 | #define CONFIG_HOSTNAME yosemite | |
37 | #else | |
38 | #define CONFIG_440GR 1 /* Specific PPC440GR support */ | |
39 | #define CONFIG_HOSTNAME yellowstone | |
40 | #endif | |
efa35cf1 | 41 | #define CONFIG_440 1 /* ... PPC440 family */ |
700200c6 | 42 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
c157d8e2 SR |
43 | #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ |
44 | ||
84286386 SR |
45 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
46 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ | |
f3443867 | 47 | #define CONFIG_BOARD_RESET 1 /* call board_reset() */ |
84286386 | 48 | |
c157d8e2 SR |
49 | /*----------------------------------------------------------------------- |
50 | * Base addresses -- Note these are effective addresses where the | |
51 | * actual resources get mapped (not physical addresses) | |
52 | *----------------------------------------------------------------------*/ | |
84286386 SR |
53 | #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ |
54 | #define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ | |
55 | #define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) | |
56 | #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ | |
57 | #define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ | |
58 | #define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ | |
59 | #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 | |
60 | #define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 | |
61 | #define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 | |
c157d8e2 SR |
62 | |
63 | /*Don't change either of these*/ | |
84286386 SR |
64 | #define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ |
65 | #define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/ | |
c157d8e2 SR |
66 | /*Don't change either of these*/ |
67 | ||
84286386 SR |
68 | #define CFG_USB_DEVICE 0x50000000 |
69 | #define CFG_NVRAM_BASE_ADDR 0x80000000 | |
70 | #define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) | |
71 | #define CFG_BOOT_BASE_ADDR 0xf0000000 | |
c157d8e2 SR |
72 | |
73 | /*----------------------------------------------------------------------- | |
74 | * Initial RAM & stack pointer (placed in SDRAM) | |
75 | *----------------------------------------------------------------------*/ | |
887e2ec9 | 76 | #define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
84286386 SR |
77 | #define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ |
78 | #define CFG_INIT_RAM_END (8 << 10) | |
79 | #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ | |
c157d8e2 SR |
80 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
81 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
82 | ||
c157d8e2 SR |
83 | /*----------------------------------------------------------------------- |
84 | * Serial Port | |
85 | *----------------------------------------------------------------------*/ | |
c157d8e2 | 86 | #define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ |
84286386 SR |
87 | #define CONFIG_BAUDRATE 115200 |
88 | #define CONFIG_SERIAL_MULTI 1 | |
c157d8e2 SR |
89 | /*define this if you want console on UART1*/ |
90 | #undef CONFIG_UART1_CONSOLE | |
91 | ||
92 | #define CFG_BAUDRATE_TABLE \ | |
93 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
94 | ||
95 | /*----------------------------------------------------------------------- | |
84286386 | 96 | * Environment |
c157d8e2 | 97 | *----------------------------------------------------------------------*/ |
84286386 SR |
98 | /* |
99 | * Define here the location of the environment variables (FLASH or EEPROM). | |
100 | * Note: DENX encourages to use redundant environment in FLASH. | |
101 | */ | |
102 | #if 1 | |
103 | #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ | |
104 | #else | |
105 | #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ | |
106 | #endif | |
c157d8e2 SR |
107 | |
108 | /*----------------------------------------------------------------------- | |
109 | * FLASH related | |
110 | *----------------------------------------------------------------------*/ | |
095b8a37 WD |
111 | #define CFG_FLASH_CFI /* The flash is CFI compatible */ |
112 | #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ | |
113 | #define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ | |
c157d8e2 SR |
114 | |
115 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
116 | #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ | |
117 | ||
118 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
119 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
120 | ||
278bc4b3 SR |
121 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
122 | ||
c157d8e2 | 123 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
84286386 SR |
124 | |
125 | #ifdef CFG_ENV_IS_IN_FLASH | |
1636d1c8 | 126 | #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
84286386 SR |
127 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) |
128 | #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
129 | ||
130 | /* Address and size of Redundant Environment Sector */ | |
131 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) | |
132 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
133 | #endif /* CFG_ENV_IS_IN_FLASH */ | |
c157d8e2 SR |
134 | |
135 | /*----------------------------------------------------------------------- | |
136 | * DDR SDRAM | |
137 | *----------------------------------------------------------------------*/ | |
095b8a37 | 138 | #undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ |
84286386 SR |
139 | #define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */ |
140 | #define CFG_SDRAM_BANKS (2) | |
141 | ||
c157d8e2 SR |
142 | |
143 | /*----------------------------------------------------------------------- | |
144 | * I2C | |
145 | *----------------------------------------------------------------------*/ | |
146 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
147 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
148 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
149 | #define CFG_I2C_SLAVE 0x7F | |
150 | ||
c157d8e2 | 151 | #define CFG_I2C_MULTI_EEPROMS |
c157d8e2 SR |
152 | #define CFG_I2C_EEPROM_ADDR (0xa8>>1) |
153 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
154 | #define CFG_EEPROM_PAGE_WRITE_ENABLE | |
155 | #define CFG_EEPROM_PAGE_WRITE_BITS 3 | |
156 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
157 | ||
84286386 SR |
158 | #ifdef CFG_ENV_IS_IN_EEPROM |
159 | #define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ | |
160 | #define CFG_ENV_OFFSET 0x0 | |
161 | #endif /* CFG_ENV_IS_IN_EEPROM */ | |
162 | ||
163 | #define CONFIG_PREBOOT "echo;" \ | |
164 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
165 | "echo" | |
166 | ||
167 | #undef CONFIG_BOOTARGS | |
168 | ||
700200c6 SR |
169 | /* Setup some board specific values for the default environment variables */ |
170 | #ifndef CONFIG_YELLOWSTONE | |
171 | #define CONFIG_HOSTNAME yosemite | |
172 | #define CFG_BOOTFILE "bootfile=/tftpboot/yosemite/uImage\0" | |
173 | #define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" | |
174 | #else | |
175 | #define CONFIG_HOSTNAME yellowstone | |
176 | #define CFG_BOOTFILE "bootfile=/tftpboot/yellowstone/uImage\0" | |
177 | #define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" | |
178 | #endif | |
179 | ||
84286386 | 180 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
700200c6 SR |
181 | CFG_BOOTFILE \ |
182 | CFG_ROOTPATH \ | |
84286386 | 183 | "netdev=eth0\0" \ |
84286386 | 184 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b | 185 | "nfsroot=${serverip}:${rootpath}\0" \ |
84286386 | 186 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
187 | "addip=setenv bootargs ${bootargs} " \ |
188 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
189 | ":${hostname}:${netdev}:off panic=1\0" \ | |
190 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
84286386 | 191 | "flash_nfs=run nfsargs addip addtty;" \ |
fe126d8b | 192 | "bootm ${kernel_addr}\0" \ |
84286386 | 193 | "flash_self=run ramargs addip addtty;" \ |
fe126d8b WD |
194 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
195 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
84286386 | 196 | "bootm\0" \ |
700200c6 | 197 | "bootfile=/tftpboot/${hostname}/uImage\0" \ |
84286386 | 198 | "kernel_addr=fc000000\0" \ |
56ced709 | 199 | "ramdisk_addr=fc180000\0" \ |
700200c6 | 200 | "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ |
84286386 | 201 | "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ |
700200c6 | 202 | "cp.b 200000 fff80000 80000;" \ |
84286386 SR |
203 | "setenv filesize;saveenv\0" \ |
204 | "upd=run load;run update\0" \ | |
205 | "" | |
206 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
207 | ||
208 | #if 0 | |
209 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
210 | #else | |
211 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
212 | #endif | |
c157d8e2 | 213 | |
84286386 SR |
214 | #define CONFIG_BAUDRATE 115200 |
215 | ||
216 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
c157d8e2 SR |
217 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
218 | ||
84286386 SR |
219 | #define CONFIG_MII 1 /* MII PHY management */ |
220 | #define CONFIG_NET_MULTI 1 /* required for netconsole */ | |
221 | #define CONFIG_PHY1_ADDR 3 | |
c157d8e2 SR |
222 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
223 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ | |
c157d8e2 | 224 | |
1e25f957 SR |
225 | #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ |
226 | ||
227 | #define CONFIG_NETCONSOLE /* include NetConsole support */ | |
c157d8e2 SR |
228 | |
229 | /* Partitions */ | |
230 | #define CONFIG_MAC_PARTITION | |
231 | #define CONFIG_DOS_PARTITION | |
232 | #define CONFIG_ISO_PARTITION | |
233 | ||
846b0dd2 | 234 | #ifdef CONFIG_440EP |
c157d8e2 | 235 | /* USB */ |
7b59b3c7 | 236 | #define CONFIG_USB_OHCI_NEW |
c157d8e2 | 237 | #define CONFIG_USB_STORAGE |
dace45ac | 238 | #define CFG_OHCI_BE_CONTROLLER |
c157d8e2 | 239 | |
53e336e9 MK |
240 | #undef CFG_USB_OHCI_BOARD_INIT |
241 | #define CFG_USB_OHCI_CPU_INIT 1 | |
242 | #define CFG_USB_OHCI_REGS_BASE (CFG_PERIPHERAL_BASE | 0x1000) | |
243 | #define CFG_USB_OHCI_SLOT_NAME "ppc440" | |
244 | #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 | |
245 | ||
700200c6 | 246 | /* Comment this out to enable USB 1.1 device */ |
c157d8e2 | 247 | #define USB_2_0_DEVICE |
700200c6 | 248 | |
700200c6 | 249 | #define CONFIG_SUPPORT_VFAT |
700200c6 | 250 | #endif /* CONFIG_440EP */ |
c157d8e2 SR |
251 | |
252 | #ifdef DEBUG | |
253 | #define CONFIG_PANIC_HANG | |
254 | #else | |
255 | #define CONFIG_HW_WATCHDOG /* watchdog */ | |
256 | #endif | |
257 | ||
dca3b3d6 | 258 | |
079a136c JL |
259 | /* |
260 | * BOOTP options | |
261 | */ | |
262 | #define CONFIG_BOOTP_BOOTFILESIZE | |
263 | #define CONFIG_BOOTP_BOOTPATH | |
264 | #define CONFIG_BOOTP_GATEWAY | |
265 | #define CONFIG_BOOTP_HOSTNAME | |
266 | ||
267 | ||
dca3b3d6 JL |
268 | /* |
269 | * Command line configuration. | |
270 | */ | |
271 | #include <config_cmd_default.h> | |
272 | ||
273 | #define CONFIG_CMD_ASKENV | |
274 | #define CONFIG_CMD_DHCP | |
275 | #define CONFIG_CMD_DIAG | |
276 | #define CONFIG_CMD_ELF | |
277 | #define CONFIG_CMD_EEPROM | |
278 | #define CONFIG_CMD_I2C | |
279 | #define CONFIG_CMD_IRQ | |
280 | #define CONFIG_CMD_MII | |
281 | #define CONFIG_CMD_NET | |
282 | #define CONFIG_CMD_NFS | |
283 | #define CONFIG_CMD_PCI | |
284 | #define CONFIG_CMD_PING | |
285 | #define CONFIG_CMD_REGINFO | |
286 | #define CONFIG_CMD_SDRAM | |
287 | ||
288 | #ifdef CONFIG_440EP | |
289 | #define CONFIG_CMD_USB | |
290 | #define CONFIG_CMD_FAT | |
291 | #define CONFIG_CMD_EXT2 | |
292 | #endif | |
293 | ||
c157d8e2 SR |
294 | |
295 | /* | |
296 | * Miscellaneous configurable options | |
297 | */ | |
298 | #define CFG_LONGHELP /* undef to save memory */ | |
84286386 | 299 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
dca3b3d6 | 300 | #if defined(CONFIG_CMD_KGDB) |
84286386 | 301 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
c157d8e2 | 302 | #else |
84286386 | 303 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
c157d8e2 | 304 | #endif |
84286386 SR |
305 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
306 | #define CFG_MAXARGS 16 /* max number of command args */ | |
307 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
c157d8e2 | 308 | |
84286386 SR |
309 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
310 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
c157d8e2 SR |
311 | |
312 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
84286386 SR |
313 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
314 | #define CONFIG_LYNXKDI 1 /* support kdi files */ | |
c157d8e2 | 315 | |
84286386 | 316 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
c157d8e2 | 317 | |
4f92ed5f SR |
318 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
319 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
320 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ | |
321 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
322 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
323 | ||
c157d8e2 SR |
324 | /*----------------------------------------------------------------------- |
325 | * PCI stuff | |
326 | *----------------------------------------------------------------------- | |
327 | */ | |
328 | /* General PCI */ | |
84286386 SR |
329 | #define CONFIG_PCI /* include pci support */ |
330 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ | |
331 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
332 | #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ | |
c157d8e2 SR |
333 | |
334 | /* Board-specific PCI */ | |
c157d8e2 SR |
335 | #define CFG_PCI_TARGET_INIT |
336 | #define CFG_PCI_MASTER_INIT | |
337 | ||
84286386 SR |
338 | #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
339 | #define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
c157d8e2 SR |
340 | |
341 | /* | |
342 | * For booting Linux, the board info and command line data | |
343 | * have to be in the first 8 MB of memory, since this is | |
344 | * the maximum mapped by the Linux kernel during initialization. | |
345 | */ | |
346 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
84286386 | 347 | |
36adff36 SR |
348 | /*----------------------------------------------------------------------- |
349 | * External Bus Controller (EBC) Setup | |
350 | *----------------------------------------------------------------------*/ | |
351 | #define CFG_FLASH CFG_FLASH_BASE | |
352 | #define CFG_CPLD 0x80000000 | |
353 | ||
354 | /* Memory Bank 0 (NOR-FLASH) initialization */ | |
355 | #define CFG_EBC_PB0AP 0x03017300 | |
356 | #define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) | |
357 | ||
358 | /* Memory Bank 2 (CPLD) initialization */ | |
359 | #define CFG_EBC_PB2AP 0x04814500 | |
360 | #define CFG_EBC_PB2CR (CFG_CPLD | 0x18000) | |
361 | ||
5a5958b7 SR |
362 | #define CFG_BCSR5_PCI66EN 0x80 |
363 | ||
c157d8e2 SR |
364 | /*----------------------------------------------------------------------- |
365 | * Cache Configuration | |
366 | */ | |
0c8721a4 | 367 | #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ |
c157d8e2 | 368 | #define CFG_CACHELINE_SIZE 32 /* ... */ |
dca3b3d6 | 369 | #if defined(CONFIG_CMD_KGDB) |
c157d8e2 SR |
370 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
371 | #endif | |
372 | ||
373 | /* | |
374 | * Internal Definitions | |
375 | * | |
376 | * Boot Flags | |
377 | */ | |
378 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
379 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
380 | ||
dca3b3d6 | 381 | #if defined(CONFIG_CMD_KGDB) |
c157d8e2 SR |
382 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
383 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
384 | #endif | |
84286386 | 385 | |
c157d8e2 | 386 | #endif /* __CONFIG_H */ |