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Commit | Line | Data |
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71f95118 | 1 | /* |
4a6ee172 | 2 | * Copyright 2008,2010 Freescale Semiconductor, Inc |
272cc70b AF |
3 | * Andy Fleming |
4 | * | |
5 | * Based (loosely) on the Linux code | |
71f95118 | 6 | * |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
71f95118 WD |
8 | */ |
9 | ||
10 | #ifndef _MMC_H_ | |
11 | #define _MMC_H_ | |
71f95118 | 12 | |
272cc70b | 13 | #include <linux/list.h> |
0d986e61 | 14 | #include <linux/compiler.h> |
07a2d42c | 15 | #include <part.h> |
272cc70b | 16 | |
4b7cee53 PA |
17 | /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */ |
18 | #define SD_VERSION_SD (1U << 31) | |
19 | #define MMC_VERSION_MMC (1U << 30) | |
20 | ||
21 | #define MAKE_SDMMC_VERSION(a, b, c) \ | |
22 | ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c)) | |
23 | #define MAKE_SD_VERSION(a, b, c) \ | |
24 | (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c)) | |
25 | #define MAKE_MMC_VERSION(a, b, c) \ | |
26 | (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c)) | |
27 | ||
28 | #define EXTRACT_SDMMC_MAJOR_VERSION(x) \ | |
29 | (((u32)(x) >> 16) & 0xff) | |
30 | #define EXTRACT_SDMMC_MINOR_VERSION(x) \ | |
31 | (((u32)(x) >> 8) & 0xff) | |
32 | #define EXTRACT_SDMMC_CHANGE_VERSION(x) \ | |
33 | ((u32)(x) & 0xff) | |
34 | ||
35 | #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0) | |
36 | #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0) | |
37 | #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0) | |
38 | #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0) | |
39 | ||
40 | #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0) | |
41 | #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0) | |
42 | #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0) | |
43 | #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0) | |
44 | #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0) | |
45 | #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0) | |
46 | #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0) | |
47 | #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0) | |
48 | #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0) | |
49 | #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1) | |
50 | #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) | |
51 | #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) | |
1a3619cf | 52 | #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0) |
272cc70b | 53 | |
8caf46d1 JC |
54 | #define MMC_MODE_HS (1 << 0) |
55 | #define MMC_MODE_HS_52MHz (1 << 1) | |
56 | #define MMC_MODE_4BIT (1 << 2) | |
57 | #define MMC_MODE_8BIT (1 << 3) | |
58 | #define MMC_MODE_SPI (1 << 4) | |
5a20397b | 59 | #define MMC_MODE_DDR_52MHz (1 << 5) |
62722036 | 60 | |
272cc70b AF |
61 | #define SD_DATA_4BIT 0x00040000 |
62 | ||
4b7cee53 | 63 | #define IS_SD(x) ((x)->version & SD_VERSION_SD) |
3f2da751 | 64 | #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC) |
272cc70b AF |
65 | |
66 | #define MMC_DATA_READ 1 | |
67 | #define MMC_DATA_WRITE 2 | |
68 | ||
341188b9 HS |
69 | #define MMC_CMD_GO_IDLE_STATE 0 |
70 | #define MMC_CMD_SEND_OP_COND 1 | |
71 | #define MMC_CMD_ALL_SEND_CID 2 | |
72 | #define MMC_CMD_SET_RELATIVE_ADDR 3 | |
73 | #define MMC_CMD_SET_DSR 4 | |
272cc70b | 74 | #define MMC_CMD_SWITCH 6 |
341188b9 | 75 | #define MMC_CMD_SELECT_CARD 7 |
272cc70b | 76 | #define MMC_CMD_SEND_EXT_CSD 8 |
341188b9 HS |
77 | #define MMC_CMD_SEND_CSD 9 |
78 | #define MMC_CMD_SEND_CID 10 | |
272cc70b | 79 | #define MMC_CMD_STOP_TRANSMISSION 12 |
341188b9 HS |
80 | #define MMC_CMD_SEND_STATUS 13 |
81 | #define MMC_CMD_SET_BLOCKLEN 16 | |
82 | #define MMC_CMD_READ_SINGLE_BLOCK 17 | |
83 | #define MMC_CMD_READ_MULTIPLE_BLOCK 18 | |
91fdabc6 | 84 | #define MMC_CMD_SET_BLOCK_COUNT 23 |
272cc70b AF |
85 | #define MMC_CMD_WRITE_SINGLE_BLOCK 24 |
86 | #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 | |
e6f99a56 LW |
87 | #define MMC_CMD_ERASE_GROUP_START 35 |
88 | #define MMC_CMD_ERASE_GROUP_END 36 | |
89 | #define MMC_CMD_ERASE 38 | |
341188b9 | 90 | #define MMC_CMD_APP_CMD 55 |
d52ebf10 TC |
91 | #define MMC_CMD_SPI_READ_OCR 58 |
92 | #define MMC_CMD_SPI_CRC_ON_OFF 59 | |
3690d6d6 A |
93 | #define MMC_CMD_RES_MAN 62 |
94 | ||
95 | #define MMC_CMD62_ARG1 0xefac62ec | |
96 | #define MMC_CMD62_ARG2 0xcbaea7 | |
97 | ||
341188b9 | 98 | |
341188b9 | 99 | #define SD_CMD_SEND_RELATIVE_ADDR 3 |
272cc70b | 100 | #define SD_CMD_SWITCH_FUNC 6 |
341188b9 | 101 | #define SD_CMD_SEND_IF_COND 8 |
f022d36e | 102 | #define SD_CMD_SWITCH_UHS18V 11 |
341188b9 HS |
103 | |
104 | #define SD_CMD_APP_SET_BUS_WIDTH 6 | |
e6f99a56 LW |
105 | #define SD_CMD_ERASE_WR_BLK_START 32 |
106 | #define SD_CMD_ERASE_WR_BLK_END 33 | |
341188b9 | 107 | #define SD_CMD_APP_SEND_OP_COND 41 |
272cc70b AF |
108 | #define SD_CMD_APP_SEND_SCR 51 |
109 | ||
110 | /* SCR definitions in different words */ | |
111 | #define SD_HIGHSPEED_BUSY 0x00020000 | |
112 | #define SD_HIGHSPEED_SUPPORTED 0x00020000 | |
113 | ||
abe2c93f TC |
114 | #define OCR_BUSY 0x80000000 |
115 | #define OCR_HCS 0x40000000 | |
31cacbab RR |
116 | #define OCR_VOLTAGE_MASK 0x007FFF80 |
117 | #define OCR_ACCESS_MODE 0x60000000 | |
272cc70b | 118 | |
1aa2d074 EN |
119 | #define MMC_ERASE_ARG 0x00000000 |
120 | #define MMC_SECURE_ERASE_ARG 0x80000000 | |
121 | #define MMC_TRIM_ARG 0x00000001 | |
122 | #define MMC_DISCARD_ARG 0x00000003 | |
123 | #define MMC_SECURE_TRIM1_ARG 0x80000001 | |
124 | #define MMC_SECURE_TRIM2_ARG 0x80008000 | |
e6f99a56 | 125 | |
5d4fc8d9 | 126 | #define MMC_STATUS_MASK (~0x0206BF7F) |
6b2221b0 | 127 | #define MMC_STATUS_SWITCH_ERROR (1 << 7) |
abe2c93f TC |
128 | #define MMC_STATUS_RDY_FOR_DATA (1 << 8) |
129 | #define MMC_STATUS_CURR_STATE (0xf << 9) | |
ed018b21 | 130 | #define MMC_STATUS_ERROR (1 << 19) |
5d4fc8d9 | 131 | |
d617c426 JK |
132 | #define MMC_STATE_PRG (7 << 9) |
133 | ||
272cc70b AF |
134 | #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ |
135 | #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ | |
136 | #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ | |
137 | #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ | |
138 | #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ | |
139 | #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ | |
140 | #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ | |
141 | #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ | |
142 | #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ | |
143 | #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ | |
144 | #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ | |
145 | #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ | |
146 | #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ | |
147 | #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ | |
148 | #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ | |
149 | #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ | |
150 | #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ | |
151 | ||
152 | #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ | |
153 | #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte | |
154 | addressed by index which are | |
155 | 1 in value field */ | |
156 | #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte | |
157 | addressed by index, which are | |
158 | 1 in value field */ | |
159 | #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ | |
160 | ||
161 | #define SD_SWITCH_CHECK 0 | |
162 | #define SD_SWITCH_SWITCH 1 | |
163 | ||
164 | /* | |
165 | * EXT_CSD fields | |
166 | */ | |
a7f852b6 DSC |
167 | #define EXT_CSD_ENH_START_ADDR 136 /* R/W */ |
168 | #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */ | |
f866a46d | 169 | #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ |
d7b29129 | 170 | #define EXT_CSD_PARTITION_SETTING 155 /* R/W */ |
1937e5aa | 171 | #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ |
ac9da0e0 | 172 | #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */ |
0560db18 | 173 | #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */ |
33ace362 | 174 | #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ |
8dda5b0e DSC |
175 | #define EXT_CSD_WR_REL_PARAM 166 /* R */ |
176 | #define EXT_CSD_WR_REL_SET 167 /* R/W */ | |
f866a46d | 177 | #define EXT_CSD_RPMB_MULT 168 /* RO */ |
0560db18 | 178 | #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ |
3690d6d6 | 179 | #define EXT_CSD_BOOT_BUS_WIDTH 177 |
0560db18 LW |
180 | #define EXT_CSD_PART_CONF 179 /* R/W */ |
181 | #define EXT_CSD_BUS_WIDTH 183 /* R/W */ | |
182 | #define EXT_CSD_HS_TIMING 185 /* R/W */ | |
183 | #define EXT_CSD_REV 192 /* RO */ | |
184 | #define EXT_CSD_CARD_TYPE 196 /* RO */ | |
185 | #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ | |
f866a46d | 186 | #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ |
0560db18 | 187 | #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ |
8948ea83 | 188 | #define EXT_CSD_BOOT_MULT 226 /* RO */ |
272cc70b AF |
189 | |
190 | /* | |
191 | * EXT_CSD field definitions | |
192 | */ | |
193 | ||
abe2c93f TC |
194 | #define EXT_CSD_CMD_SET_NORMAL (1 << 0) |
195 | #define EXT_CSD_CMD_SET_SECURE (1 << 1) | |
196 | #define EXT_CSD_CMD_SET_CPSECURE (1 << 2) | |
272cc70b | 197 | |
abe2c93f TC |
198 | #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */ |
199 | #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */ | |
d22e3d46 JC |
200 | #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2) |
201 | #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3) | |
202 | #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ | |
203 | | EXT_CSD_CARD_TYPE_DDR_1_2V) | |
272cc70b AF |
204 | |
205 | #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ | |
206 | #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ | |
207 | #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ | |
d22e3d46 JC |
208 | #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ |
209 | #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ | |
341188b9 | 210 | |
3690d6d6 A |
211 | #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6) |
212 | #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3) | |
213 | #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0) | |
214 | #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0) | |
215 | ||
216 | #define EXT_CSD_BOOT_ACK(x) (x << 6) | |
217 | #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) | |
218 | #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) | |
219 | ||
5a99b9de TR |
220 | #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) |
221 | #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) | |
222 | #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) | |
3690d6d6 | 223 | |
d7b29129 MN |
224 | #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0) |
225 | ||
c3dbb4f9 DSC |
226 | #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */ |
227 | #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */ | |
228 | ||
8dda5b0e DSC |
229 | #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */ |
230 | ||
231 | #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */ | |
232 | #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */ | |
233 | ||
1de97f98 AF |
234 | #define R1_ILLEGAL_COMMAND (1 << 22) |
235 | #define R1_APP_CMD (1 << 5) | |
236 | ||
272cc70b | 237 | #define MMC_RSP_PRESENT (1 << 0) |
abe2c93f TC |
238 | #define MMC_RSP_136 (1 << 1) /* 136 bit response */ |
239 | #define MMC_RSP_CRC (1 << 2) /* expect valid crc */ | |
240 | #define MMC_RSP_BUSY (1 << 3) /* card may send busy */ | |
241 | #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ | |
272cc70b | 242 | |
abe2c93f TC |
243 | #define MMC_RSP_NONE (0) |
244 | #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
272cc70b AF |
245 | #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ |
246 | MMC_RSP_BUSY) | |
abe2c93f TC |
247 | #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) |
248 | #define MMC_RSP_R3 (MMC_RSP_PRESENT) | |
249 | #define MMC_RSP_R4 (MMC_RSP_PRESENT) | |
250 | #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
251 | #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
252 | #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) | |
272cc70b | 253 | |
bc897b1d LW |
254 | #define MMCPART_NOAVAILABLE (0xff) |
255 | #define PART_ACCESS_MASK (0x7) | |
256 | #define PART_SUPPORT (0x1) | |
c3dbb4f9 | 257 | #define ENHNCD_SUPPORT (0x2) |
1937e5aa | 258 | #define PART_ENH_ATTRIB (0x1f) |
71f95118 | 259 | |
8bfa195e SG |
260 | /* Maximum block size for MMC */ |
261 | #define MMC_MAX_BLOCK_LEN 512 | |
262 | ||
3690d6d6 A |
263 | /* The number of MMC physical partitions. These consist of: |
264 | * boot partitions (2), general purpose partitions (4) in MMC v4.4. | |
265 | */ | |
266 | #define MMC_NUM_BOOT_PARTITION 2 | |
91fdabc6 | 267 | #define MMC_PART_RPMB 3 /* RPMB partition number */ |
3690d6d6 | 268 | |
e7ecf7cb SG |
269 | /* Driver model support */ |
270 | ||
271 | /** | |
272 | * struct mmc_uclass_priv - Holds information about a device used by the uclass | |
273 | */ | |
274 | struct mmc_uclass_priv { | |
275 | struct mmc *mmc; | |
276 | }; | |
277 | ||
278 | /** | |
279 | * mmc_get_mmc_dev() - get the MMC struct pointer for a device | |
280 | * | |
281 | * Provided that the device is already probed and ready for use, this value | |
282 | * will be available. | |
283 | * | |
284 | * @dev: Device | |
285 | * @return associated mmc struct pointer if available, else NULL | |
286 | */ | |
287 | struct mmc *mmc_get_mmc_dev(struct udevice *dev); | |
288 | ||
289 | /* End of driver model support */ | |
290 | ||
1de97f98 AF |
291 | struct mmc_cid { |
292 | unsigned long psn; | |
293 | unsigned short oid; | |
294 | unsigned char mid; | |
295 | unsigned char prv; | |
296 | unsigned char mdt; | |
297 | char pnm[7]; | |
298 | }; | |
299 | ||
272cc70b AF |
300 | struct mmc_cmd { |
301 | ushort cmdidx; | |
302 | uint resp_type; | |
303 | uint cmdarg; | |
0b453ffe | 304 | uint response[4]; |
272cc70b AF |
305 | }; |
306 | ||
307 | struct mmc_data { | |
308 | union { | |
309 | char *dest; | |
310 | const char *src; /* src buffers don't get written to */ | |
311 | }; | |
312 | uint flags; | |
313 | uint blocks; | |
314 | uint blocksize; | |
315 | }; | |
316 | ||
ab769f22 PA |
317 | /* forward decl. */ |
318 | struct mmc; | |
319 | ||
8ca51e51 SG |
320 | #ifdef CONFIG_DM_MMC_OPS |
321 | struct dm_mmc_ops { | |
322 | /** | |
323 | * send_cmd() - Send a command to the MMC device | |
324 | * | |
325 | * @dev: Device to receive the command | |
326 | * @cmd: Command to send | |
327 | * @data: Additional data to send/receive | |
328 | * @return 0 if OK, -ve on error | |
329 | */ | |
330 | int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd, | |
331 | struct mmc_data *data); | |
332 | ||
333 | /** | |
334 | * set_ios() - Set the I/O speed/width for an MMC device | |
335 | * | |
336 | * @dev: Device to update | |
337 | * @return 0 if OK, -ve on error | |
338 | */ | |
339 | int (*set_ios)(struct udevice *dev); | |
340 | ||
341 | /** | |
342 | * get_cd() - See whether a card is present | |
343 | * | |
344 | * @dev: Device to check | |
345 | * @return 0 if not present, 1 if present, -ve on error | |
346 | */ | |
347 | int (*get_cd)(struct udevice *dev); | |
348 | ||
349 | /** | |
350 | * get_wp() - See whether a card has write-protect enabled | |
351 | * | |
352 | * @dev: Device to check | |
353 | * @return 0 if write-enabled, 1 if write-protected, -ve on error | |
354 | */ | |
355 | int (*get_wp)(struct udevice *dev); | |
356 | }; | |
357 | ||
358 | #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops) | |
359 | ||
360 | int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, | |
361 | struct mmc_data *data); | |
362 | int dm_mmc_set_ios(struct udevice *dev); | |
363 | int dm_mmc_get_cd(struct udevice *dev); | |
364 | int dm_mmc_get_wp(struct udevice *dev); | |
365 | ||
366 | /* Transition functions for compatibility */ | |
367 | int mmc_set_ios(struct mmc *mmc); | |
368 | int mmc_getcd(struct mmc *mmc); | |
369 | int mmc_getwp(struct mmc *mmc); | |
370 | ||
371 | #else | |
ab769f22 PA |
372 | struct mmc_ops { |
373 | int (*send_cmd)(struct mmc *mmc, | |
374 | struct mmc_cmd *cmd, struct mmc_data *data); | |
375 | void (*set_ios)(struct mmc *mmc); | |
376 | int (*init)(struct mmc *mmc); | |
377 | int (*getcd)(struct mmc *mmc); | |
378 | int (*getwp)(struct mmc *mmc); | |
379 | }; | |
8ca51e51 | 380 | #endif |
ab769f22 | 381 | |
93bfd616 PA |
382 | struct mmc_config { |
383 | const char *name; | |
8ca51e51 | 384 | #ifndef CONFIG_DM_MMC_OPS |
93bfd616 | 385 | const struct mmc_ops *ops; |
8ca51e51 | 386 | #endif |
93bfd616 PA |
387 | uint host_caps; |
388 | uint voltages; | |
389 | uint f_min; | |
390 | uint f_max; | |
391 | uint b_max; | |
392 | unsigned char part_type; | |
393 | }; | |
394 | ||
8ca51e51 SG |
395 | /* |
396 | * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device | |
397 | * with mmc_get_mmc_dev(). | |
398 | * | |
399 | * TODO struct mmc should be in mmc_private but it's hard to fix right now | |
400 | */ | |
272cc70b | 401 | struct mmc { |
33fb211d | 402 | #ifndef CONFIG_BLK |
272cc70b | 403 | struct list_head link; |
33fb211d | 404 | #endif |
93bfd616 | 405 | const struct mmc_config *cfg; /* provided configuration */ |
272cc70b | 406 | uint version; |
93bfd616 | 407 | void *priv; |
bc897b1d | 408 | uint has_init; |
272cc70b AF |
409 | int high_capacity; |
410 | uint bus_width; | |
411 | uint clock; | |
412 | uint card_caps; | |
272cc70b | 413 | uint ocr; |
ab71188c MN |
414 | uint dsr; |
415 | uint dsr_imp; | |
272cc70b AF |
416 | uint scr[2]; |
417 | uint csd[4]; | |
0b453ffe | 418 | uint cid[4]; |
272cc70b | 419 | ushort rca; |
c3dbb4f9 DSC |
420 | u8 part_support; |
421 | u8 part_attr; | |
9e41a00b | 422 | u8 wr_rel_set; |
bc897b1d | 423 | char part_config; |
272cc70b AF |
424 | uint tran_speed; |
425 | uint read_bl_len; | |
426 | uint write_bl_len; | |
a4ff9f83 | 427 | uint erase_grp_size; /* in 512-byte sectors */ |
037dc0ab | 428 | uint hc_wp_grp_size; /* in 512-byte sectors */ |
272cc70b | 429 | u64 capacity; |
f866a46d SW |
430 | u64 capacity_user; |
431 | u64 capacity_boot; | |
432 | u64 capacity_rpmb; | |
433 | u64 capacity_gp[4]; | |
a7f852b6 DSC |
434 | u64 enh_user_start; |
435 | u64 enh_user_size; | |
33fb211d | 436 | #ifndef CONFIG_BLK |
4101f687 | 437 | struct blk_desc block_dev; |
33fb211d | 438 | #endif |
e9550449 CLC |
439 | char op_cond_pending; /* 1 if we are waiting on an op_cond command */ |
440 | char init_in_progress; /* 1 if we have done mmc_start_init() */ | |
441 | char preinit; /* start init as early as possible */ | |
786e8f81 | 442 | int ddr_mode; |
cffe5d86 SG |
443 | #ifdef CONFIG_DM_MMC |
444 | struct udevice *dev; /* Device for this MMC controller */ | |
445 | #endif | |
272cc70b AF |
446 | }; |
447 | ||
ac9da0e0 DSC |
448 | struct mmc_hwpart_conf { |
449 | struct { | |
450 | uint enh_start; /* in 512-byte sectors */ | |
451 | uint enh_size; /* in 512-byte sectors, if 0 no enh area */ | |
8dda5b0e DSC |
452 | unsigned wr_rel_change : 1; |
453 | unsigned wr_rel_set : 1; | |
ac9da0e0 DSC |
454 | } user; |
455 | struct { | |
456 | uint size; /* in 512-byte sectors */ | |
8dda5b0e DSC |
457 | unsigned enhanced : 1; |
458 | unsigned wr_rel_change : 1; | |
459 | unsigned wr_rel_set : 1; | |
ac9da0e0 DSC |
460 | } gp_part[4]; |
461 | }; | |
462 | ||
463 | enum mmc_hwpart_conf_mode { | |
464 | MMC_HWPART_CONF_CHECK, | |
465 | MMC_HWPART_CONF_SET, | |
466 | MMC_HWPART_CONF_COMPLETE, | |
467 | }; | |
468 | ||
93bfd616 | 469 | struct mmc *mmc_create(const struct mmc_config *cfg, void *priv); |
ad27dd5e SG |
470 | |
471 | /** | |
472 | * mmc_bind() - Set up a new MMC device ready for probing | |
473 | * | |
474 | * A child block device is bound with the IF_TYPE_MMC interface type. This | |
475 | * allows the device to be used with CONFIG_BLK | |
476 | * | |
477 | * @dev: MMC device to set up | |
478 | * @mmc: MMC struct | |
479 | * @cfg: MMC configuration | |
480 | * @return 0 if OK, -ve on error | |
481 | */ | |
482 | int mmc_bind(struct udevice *dev, struct mmc *mmc, | |
483 | const struct mmc_config *cfg); | |
93bfd616 | 484 | void mmc_destroy(struct mmc *mmc); |
ad27dd5e SG |
485 | |
486 | /** | |
487 | * mmc_unbind() - Unbind a MMC device's child block device | |
488 | * | |
489 | * @dev: MMC device | |
490 | * @return 0 if OK, -ve on error | |
491 | */ | |
492 | int mmc_unbind(struct udevice *dev); | |
272cc70b AF |
493 | int mmc_initialize(bd_t *bis); |
494 | int mmc_init(struct mmc *mmc); | |
495 | int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); | |
4a6ee172 | 496 | void mmc_set_clock(struct mmc *mmc, uint clock); |
272cc70b | 497 | struct mmc *find_mmc_device(int dev_num); |
89716964 | 498 | int mmc_set_dev(int dev_num); |
272cc70b | 499 | void print_mmc_devices(char separator); |
46683f3d KY |
500 | |
501 | /** | |
502 | * get_mmc_num() - get the total MMC device number | |
503 | * | |
504 | * @return 0 if there is no MMC device, else the number of devices | |
505 | */ | |
ea6ebe21 | 506 | int get_mmc_num(void); |
ac9da0e0 DSC |
507 | int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, |
508 | enum mmc_hwpart_conf_mode mode); | |
8ca51e51 SG |
509 | |
510 | #ifndef CONFIG_DM_MMC_OPS | |
48972d90 | 511 | int mmc_getcd(struct mmc *mmc); |
750121c3 | 512 | int board_mmc_getcd(struct mmc *mmc); |
d23d8d7e | 513 | int mmc_getwp(struct mmc *mmc); |
750121c3 | 514 | int board_mmc_getwp(struct mmc *mmc); |
8ca51e51 SG |
515 | #endif |
516 | ||
ab71188c | 517 | int mmc_set_dsr(struct mmc *mmc, u16 val); |
3690d6d6 A |
518 | /* Function to change the size of boot partition and rpmb partitions */ |
519 | int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, | |
520 | unsigned long rpmbsize); | |
792970b0 TR |
521 | /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ |
522 | int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); | |
5a99b9de TR |
523 | /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ |
524 | int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); | |
33ace362 TR |
525 | /* Function to modify the RST_n_FUNCTION field of EXT_CSD */ |
526 | int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); | |
91fdabc6 PA |
527 | /* Functions to read / write the RPMB partition */ |
528 | int mmc_rpmb_set_key(struct mmc *mmc, void *key); | |
529 | int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter); | |
530 | int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, | |
531 | unsigned short cnt, unsigned char *key); | |
532 | int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, | |
533 | unsigned short cnt, unsigned char *key); | |
e9550449 CLC |
534 | /** |
535 | * Start device initialization and return immediately; it does not block on | |
536 | * polling OCR (operation condition register) status. Then you should call | |
537 | * mmc_init, which would block on polling OCR status and complete the device | |
538 | * initializatin. | |
539 | * | |
540 | * @param mmc Pointer to a MMC device struct | |
541 | * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. | |
542 | */ | |
543 | int mmc_start_init(struct mmc *mmc); | |
544 | ||
545 | /** | |
546 | * Set preinit flag of mmc device. | |
547 | * | |
548 | * This will cause the device to be pre-inited during mmc_initialize(), | |
549 | * which may save boot time if the device is not accessed until later. | |
550 | * Some eMMC devices take 200-300ms to init, but unfortunately they | |
551 | * must be sent a series of commands to even get them to start preparing | |
552 | * for operation. | |
553 | * | |
554 | * @param mmc Pointer to a MMC device struct | |
555 | * @param preinit preinit flag value | |
556 | */ | |
557 | void mmc_set_preinit(struct mmc *mmc, int preinit); | |
558 | ||
8687d5c8 | 559 | #ifdef CONFIG_MMC_SPI |
0b2da7e2 | 560 | #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI) |
8687d5c8 PB |
561 | #else |
562 | #define mmc_host_is_spi(mmc) 0 | |
563 | #endif | |
d52ebf10 | 564 | struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode); |
1592ef85 | 565 | |
95de9ab2 | 566 | void board_mmc_power_init(void); |
3c7ca967 | 567 | int board_mmc_init(bd_t *bis); |
750121c3 | 568 | int cpu_mmc_init(bd_t *bis); |
aeb80555 | 569 | int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); |
aa844fe1 | 570 | int mmc_get_env_dev(void); |
3c7ca967 | 571 | |
91785f70 SG |
572 | struct pci_device_id; |
573 | ||
574 | /** | |
575 | * pci_mmc_init() - set up PCI MMC devices | |
576 | * | |
577 | * This finds all the matching PCI IDs and sets them up as MMC devices. | |
578 | * | |
579 | * @name: Name to use for devices | |
4abe8e40 | 580 | * @mmc_supported: PCI IDs to search for, terminated by {0, 0} |
91785f70 | 581 | */ |
4abe8e40 | 582 | int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported); |
91785f70 | 583 | |
93bfd616 PA |
584 | /* Set block count limit because of 16 bit register limit on some hardware*/ |
585 | #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT | |
586 | #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 | |
587 | #endif | |
588 | ||
cb5ec33d SG |
589 | /** |
590 | * mmc_get_blk_desc() - Get the block descriptor for an MMC device | |
591 | * | |
592 | * @mmc: MMC device | |
593 | * @return block device if found, else NULL | |
594 | */ | |
595 | struct blk_desc *mmc_get_blk_desc(struct mmc *mmc); | |
596 | ||
71f95118 | 597 | #endif /* _MMC_H_ */ |