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71f95118 1/*
4a6ee172 2 * Copyright 2008,2010 Freescale Semiconductor, Inc
272cc70b
AF
3 * Andy Fleming
4 *
5 * Based (loosely) on the Linux code
71f95118 6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
71f95118
WD
8 */
9
10#ifndef _MMC_H_
11#define _MMC_H_
71f95118 12
272cc70b 13#include <linux/list.h>
0d986e61 14#include <linux/compiler.h>
07a2d42c 15#include <part.h>
272cc70b 16
4b7cee53
PA
17/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
18#define SD_VERSION_SD (1U << 31)
19#define MMC_VERSION_MMC (1U << 30)
20
21#define MAKE_SDMMC_VERSION(a, b, c) \
22 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
23#define MAKE_SD_VERSION(a, b, c) \
24 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
25#define MAKE_MMC_VERSION(a, b, c) \
26 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
27
28#define EXTRACT_SDMMC_MAJOR_VERSION(x) \
29 (((u32)(x) >> 16) & 0xff)
30#define EXTRACT_SDMMC_MINOR_VERSION(x) \
31 (((u32)(x) >> 8) & 0xff)
32#define EXTRACT_SDMMC_CHANGE_VERSION(x) \
33 ((u32)(x) & 0xff)
34
35#define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
36#define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
37#define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
38#define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
39
40#define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
41#define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
42#define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
43#define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
44#define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
45#define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
46#define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
47#define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
48#define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
49#define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
50#define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
51#define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
1a3619cf 52#define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
272cc70b 53
8caf46d1
JC
54#define MMC_MODE_HS (1 << 0)
55#define MMC_MODE_HS_52MHz (1 << 1)
56#define MMC_MODE_4BIT (1 << 2)
57#define MMC_MODE_8BIT (1 << 3)
58#define MMC_MODE_SPI (1 << 4)
5a20397b 59#define MMC_MODE_DDR_52MHz (1 << 5)
62722036 60
272cc70b
AF
61#define SD_DATA_4BIT 0x00040000
62
4b7cee53 63#define IS_SD(x) ((x)->version & SD_VERSION_SD)
3f2da751 64#define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
272cc70b
AF
65
66#define MMC_DATA_READ 1
67#define MMC_DATA_WRITE 2
68
69#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
70#define UNUSABLE_ERR -17 /* Unusable Card */
71#define COMM_ERR -18 /* Communications Error */
72#define TIMEOUT -19
bd47c135 73#define SWITCH_ERR -20 /* Card reports failure to switch mode */
272cc70b 74
341188b9
HS
75#define MMC_CMD_GO_IDLE_STATE 0
76#define MMC_CMD_SEND_OP_COND 1
77#define MMC_CMD_ALL_SEND_CID 2
78#define MMC_CMD_SET_RELATIVE_ADDR 3
79#define MMC_CMD_SET_DSR 4
272cc70b 80#define MMC_CMD_SWITCH 6
341188b9 81#define MMC_CMD_SELECT_CARD 7
272cc70b 82#define MMC_CMD_SEND_EXT_CSD 8
341188b9
HS
83#define MMC_CMD_SEND_CSD 9
84#define MMC_CMD_SEND_CID 10
272cc70b 85#define MMC_CMD_STOP_TRANSMISSION 12
341188b9
HS
86#define MMC_CMD_SEND_STATUS 13
87#define MMC_CMD_SET_BLOCKLEN 16
88#define MMC_CMD_READ_SINGLE_BLOCK 17
89#define MMC_CMD_READ_MULTIPLE_BLOCK 18
91fdabc6 90#define MMC_CMD_SET_BLOCK_COUNT 23
272cc70b
AF
91#define MMC_CMD_WRITE_SINGLE_BLOCK 24
92#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
e6f99a56
LW
93#define MMC_CMD_ERASE_GROUP_START 35
94#define MMC_CMD_ERASE_GROUP_END 36
95#define MMC_CMD_ERASE 38
341188b9 96#define MMC_CMD_APP_CMD 55
d52ebf10
TC
97#define MMC_CMD_SPI_READ_OCR 58
98#define MMC_CMD_SPI_CRC_ON_OFF 59
3690d6d6
A
99#define MMC_CMD_RES_MAN 62
100
101#define MMC_CMD62_ARG1 0xefac62ec
102#define MMC_CMD62_ARG2 0xcbaea7
103
341188b9 104
341188b9 105#define SD_CMD_SEND_RELATIVE_ADDR 3
272cc70b 106#define SD_CMD_SWITCH_FUNC 6
341188b9 107#define SD_CMD_SEND_IF_COND 8
f022d36e 108#define SD_CMD_SWITCH_UHS18V 11
341188b9
HS
109
110#define SD_CMD_APP_SET_BUS_WIDTH 6
e6f99a56
LW
111#define SD_CMD_ERASE_WR_BLK_START 32
112#define SD_CMD_ERASE_WR_BLK_END 33
341188b9 113#define SD_CMD_APP_SEND_OP_COND 41
272cc70b
AF
114#define SD_CMD_APP_SEND_SCR 51
115
116/* SCR definitions in different words */
117#define SD_HIGHSPEED_BUSY 0x00020000
118#define SD_HIGHSPEED_SUPPORTED 0x00020000
119
abe2c93f
TC
120#define OCR_BUSY 0x80000000
121#define OCR_HCS 0x40000000
31cacbab
RR
122#define OCR_VOLTAGE_MASK 0x007FFF80
123#define OCR_ACCESS_MODE 0x60000000
272cc70b 124
1aa2d074
EN
125#define MMC_ERASE_ARG 0x00000000
126#define MMC_SECURE_ERASE_ARG 0x80000000
127#define MMC_TRIM_ARG 0x00000001
128#define MMC_DISCARD_ARG 0x00000003
129#define MMC_SECURE_TRIM1_ARG 0x80000001
130#define MMC_SECURE_TRIM2_ARG 0x80008000
e6f99a56 131
5d4fc8d9 132#define MMC_STATUS_MASK (~0x0206BF7F)
6b2221b0 133#define MMC_STATUS_SWITCH_ERROR (1 << 7)
abe2c93f
TC
134#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
135#define MMC_STATUS_CURR_STATE (0xf << 9)
ed018b21 136#define MMC_STATUS_ERROR (1 << 19)
5d4fc8d9 137
d617c426
JK
138#define MMC_STATE_PRG (7 << 9)
139
272cc70b
AF
140#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
141#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
142#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
143#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
144#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
145#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
146#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
147#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
148#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
149#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
150#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
151#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
152#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
153#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
154#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
155#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
156#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
157
158#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
159#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
160 addressed by index which are
161 1 in value field */
162#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
163 addressed by index, which are
164 1 in value field */
165#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
166
167#define SD_SWITCH_CHECK 0
168#define SD_SWITCH_SWITCH 1
169
170/*
171 * EXT_CSD fields
172 */
a7f852b6
DSC
173#define EXT_CSD_ENH_START_ADDR 136 /* R/W */
174#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
f866a46d 175#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
d7b29129 176#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
1937e5aa 177#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
ac9da0e0 178#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
0560db18 179#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
33ace362 180#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
8dda5b0e
DSC
181#define EXT_CSD_WR_REL_PARAM 166 /* R */
182#define EXT_CSD_WR_REL_SET 167 /* R/W */
f866a46d 183#define EXT_CSD_RPMB_MULT 168 /* RO */
0560db18 184#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
3690d6d6 185#define EXT_CSD_BOOT_BUS_WIDTH 177
0560db18
LW
186#define EXT_CSD_PART_CONF 179 /* R/W */
187#define EXT_CSD_BUS_WIDTH 183 /* R/W */
188#define EXT_CSD_HS_TIMING 185 /* R/W */
189#define EXT_CSD_REV 192 /* RO */
190#define EXT_CSD_CARD_TYPE 196 /* RO */
191#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
f866a46d 192#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
0560db18 193#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
8948ea83 194#define EXT_CSD_BOOT_MULT 226 /* RO */
272cc70b
AF
195
196/*
197 * EXT_CSD field definitions
198 */
199
abe2c93f
TC
200#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
201#define EXT_CSD_CMD_SET_SECURE (1 << 1)
202#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
272cc70b 203
abe2c93f
TC
204#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
205#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
d22e3d46
JC
206#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
207#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
208#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
209 | EXT_CSD_CARD_TYPE_DDR_1_2V)
272cc70b
AF
210
211#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
212#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
213#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
d22e3d46
JC
214#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
215#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
341188b9 216
3690d6d6
A
217#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
218#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
219#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
220#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
221
222#define EXT_CSD_BOOT_ACK(x) (x << 6)
223#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
224#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
225
5a99b9de
TR
226#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
227#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
228#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
3690d6d6 229
d7b29129
MN
230#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
231
c3dbb4f9
DSC
232#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
233#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
234
8dda5b0e
DSC
235#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
236
237#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
238#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
239
1de97f98
AF
240#define R1_ILLEGAL_COMMAND (1 << 22)
241#define R1_APP_CMD (1 << 5)
242
272cc70b 243#define MMC_RSP_PRESENT (1 << 0)
abe2c93f
TC
244#define MMC_RSP_136 (1 << 1) /* 136 bit response */
245#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
246#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
247#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
272cc70b 248
abe2c93f
TC
249#define MMC_RSP_NONE (0)
250#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
272cc70b
AF
251#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
252 MMC_RSP_BUSY)
abe2c93f
TC
253#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
254#define MMC_RSP_R3 (MMC_RSP_PRESENT)
255#define MMC_RSP_R4 (MMC_RSP_PRESENT)
256#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
257#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
258#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
272cc70b 259
bc897b1d
LW
260#define MMCPART_NOAVAILABLE (0xff)
261#define PART_ACCESS_MASK (0x7)
262#define PART_SUPPORT (0x1)
c3dbb4f9 263#define ENHNCD_SUPPORT (0x2)
1937e5aa 264#define PART_ENH_ATTRIB (0x1f)
71f95118 265
8bfa195e
SG
266/* Maximum block size for MMC */
267#define MMC_MAX_BLOCK_LEN 512
268
3690d6d6
A
269/* The number of MMC physical partitions. These consist of:
270 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
271 */
272#define MMC_NUM_BOOT_PARTITION 2
91fdabc6 273#define MMC_PART_RPMB 3 /* RPMB partition number */
3690d6d6 274
e7ecf7cb
SG
275/* Driver model support */
276
277/**
278 * struct mmc_uclass_priv - Holds information about a device used by the uclass
279 */
280struct mmc_uclass_priv {
281 struct mmc *mmc;
282};
283
284/**
285 * mmc_get_mmc_dev() - get the MMC struct pointer for a device
286 *
287 * Provided that the device is already probed and ready for use, this value
288 * will be available.
289 *
290 * @dev: Device
291 * @return associated mmc struct pointer if available, else NULL
292 */
293struct mmc *mmc_get_mmc_dev(struct udevice *dev);
294
295/* End of driver model support */
296
1de97f98
AF
297struct mmc_cid {
298 unsigned long psn;
299 unsigned short oid;
300 unsigned char mid;
301 unsigned char prv;
302 unsigned char mdt;
303 char pnm[7];
304};
305
272cc70b
AF
306struct mmc_cmd {
307 ushort cmdidx;
308 uint resp_type;
309 uint cmdarg;
0b453ffe 310 uint response[4];
272cc70b
AF
311};
312
313struct mmc_data {
314 union {
315 char *dest;
316 const char *src; /* src buffers don't get written to */
317 };
318 uint flags;
319 uint blocks;
320 uint blocksize;
321};
322
ab769f22
PA
323/* forward decl. */
324struct mmc;
325
8ca51e51
SG
326#ifdef CONFIG_DM_MMC_OPS
327struct dm_mmc_ops {
328 /**
329 * send_cmd() - Send a command to the MMC device
330 *
331 * @dev: Device to receive the command
332 * @cmd: Command to send
333 * @data: Additional data to send/receive
334 * @return 0 if OK, -ve on error
335 */
336 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
337 struct mmc_data *data);
338
339 /**
340 * set_ios() - Set the I/O speed/width for an MMC device
341 *
342 * @dev: Device to update
343 * @return 0 if OK, -ve on error
344 */
345 int (*set_ios)(struct udevice *dev);
346
347 /**
348 * get_cd() - See whether a card is present
349 *
350 * @dev: Device to check
351 * @return 0 if not present, 1 if present, -ve on error
352 */
353 int (*get_cd)(struct udevice *dev);
354
355 /**
356 * get_wp() - See whether a card has write-protect enabled
357 *
358 * @dev: Device to check
359 * @return 0 if write-enabled, 1 if write-protected, -ve on error
360 */
361 int (*get_wp)(struct udevice *dev);
362};
363
364#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
365
366int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
367 struct mmc_data *data);
368int dm_mmc_set_ios(struct udevice *dev);
369int dm_mmc_get_cd(struct udevice *dev);
370int dm_mmc_get_wp(struct udevice *dev);
371
372/* Transition functions for compatibility */
373int mmc_set_ios(struct mmc *mmc);
374int mmc_getcd(struct mmc *mmc);
375int mmc_getwp(struct mmc *mmc);
376
377#else
ab769f22
PA
378struct mmc_ops {
379 int (*send_cmd)(struct mmc *mmc,
380 struct mmc_cmd *cmd, struct mmc_data *data);
381 void (*set_ios)(struct mmc *mmc);
382 int (*init)(struct mmc *mmc);
383 int (*getcd)(struct mmc *mmc);
384 int (*getwp)(struct mmc *mmc);
385};
8ca51e51 386#endif
ab769f22 387
93bfd616
PA
388struct mmc_config {
389 const char *name;
8ca51e51 390#ifndef CONFIG_DM_MMC_OPS
93bfd616 391 const struct mmc_ops *ops;
8ca51e51 392#endif
93bfd616
PA
393 uint host_caps;
394 uint voltages;
395 uint f_min;
396 uint f_max;
397 uint b_max;
398 unsigned char part_type;
399};
400
8ca51e51
SG
401/*
402 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
403 * with mmc_get_mmc_dev().
404 *
405 * TODO struct mmc should be in mmc_private but it's hard to fix right now
406 */
272cc70b 407struct mmc {
33fb211d 408#ifndef CONFIG_BLK
272cc70b 409 struct list_head link;
33fb211d 410#endif
93bfd616 411 const struct mmc_config *cfg; /* provided configuration */
272cc70b 412 uint version;
93bfd616 413 void *priv;
bc897b1d 414 uint has_init;
272cc70b
AF
415 int high_capacity;
416 uint bus_width;
417 uint clock;
418 uint card_caps;
272cc70b 419 uint ocr;
ab71188c
MN
420 uint dsr;
421 uint dsr_imp;
272cc70b
AF
422 uint scr[2];
423 uint csd[4];
0b453ffe 424 uint cid[4];
272cc70b 425 ushort rca;
c3dbb4f9
DSC
426 u8 part_support;
427 u8 part_attr;
9e41a00b 428 u8 wr_rel_set;
bc897b1d 429 char part_config;
272cc70b
AF
430 uint tran_speed;
431 uint read_bl_len;
432 uint write_bl_len;
a4ff9f83 433 uint erase_grp_size; /* in 512-byte sectors */
037dc0ab 434 uint hc_wp_grp_size; /* in 512-byte sectors */
272cc70b 435 u64 capacity;
f866a46d
SW
436 u64 capacity_user;
437 u64 capacity_boot;
438 u64 capacity_rpmb;
439 u64 capacity_gp[4];
a7f852b6
DSC
440 u64 enh_user_start;
441 u64 enh_user_size;
33fb211d 442#ifndef CONFIG_BLK
4101f687 443 struct blk_desc block_dev;
33fb211d 444#endif
e9550449
CLC
445 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
446 char init_in_progress; /* 1 if we have done mmc_start_init() */
447 char preinit; /* start init as early as possible */
786e8f81 448 int ddr_mode;
cffe5d86
SG
449#ifdef CONFIG_DM_MMC
450 struct udevice *dev; /* Device for this MMC controller */
451#endif
272cc70b
AF
452};
453
ac9da0e0
DSC
454struct mmc_hwpart_conf {
455 struct {
456 uint enh_start; /* in 512-byte sectors */
457 uint enh_size; /* in 512-byte sectors, if 0 no enh area */
8dda5b0e
DSC
458 unsigned wr_rel_change : 1;
459 unsigned wr_rel_set : 1;
ac9da0e0
DSC
460 } user;
461 struct {
462 uint size; /* in 512-byte sectors */
8dda5b0e
DSC
463 unsigned enhanced : 1;
464 unsigned wr_rel_change : 1;
465 unsigned wr_rel_set : 1;
ac9da0e0
DSC
466 } gp_part[4];
467};
468
469enum mmc_hwpart_conf_mode {
470 MMC_HWPART_CONF_CHECK,
471 MMC_HWPART_CONF_SET,
472 MMC_HWPART_CONF_COMPLETE,
473};
474
93bfd616 475struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
ad27dd5e
SG
476
477/**
478 * mmc_bind() - Set up a new MMC device ready for probing
479 *
480 * A child block device is bound with the IF_TYPE_MMC interface type. This
481 * allows the device to be used with CONFIG_BLK
482 *
483 * @dev: MMC device to set up
484 * @mmc: MMC struct
485 * @cfg: MMC configuration
486 * @return 0 if OK, -ve on error
487 */
488int mmc_bind(struct udevice *dev, struct mmc *mmc,
489 const struct mmc_config *cfg);
93bfd616 490void mmc_destroy(struct mmc *mmc);
ad27dd5e
SG
491
492/**
493 * mmc_unbind() - Unbind a MMC device's child block device
494 *
495 * @dev: MMC device
496 * @return 0 if OK, -ve on error
497 */
498int mmc_unbind(struct udevice *dev);
272cc70b
AF
499int mmc_initialize(bd_t *bis);
500int mmc_init(struct mmc *mmc);
501int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
4a6ee172 502void mmc_set_clock(struct mmc *mmc, uint clock);
272cc70b 503struct mmc *find_mmc_device(int dev_num);
89716964 504int mmc_set_dev(int dev_num);
272cc70b 505void print_mmc_devices(char separator);
46683f3d
KY
506
507/**
508 * get_mmc_num() - get the total MMC device number
509 *
510 * @return 0 if there is no MMC device, else the number of devices
511 */
ea6ebe21 512int get_mmc_num(void);
ac9da0e0
DSC
513int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
514 enum mmc_hwpart_conf_mode mode);
8ca51e51
SG
515
516#ifndef CONFIG_DM_MMC_OPS
48972d90 517int mmc_getcd(struct mmc *mmc);
750121c3 518int board_mmc_getcd(struct mmc *mmc);
d23d8d7e 519int mmc_getwp(struct mmc *mmc);
750121c3 520int board_mmc_getwp(struct mmc *mmc);
8ca51e51
SG
521#endif
522
ab71188c 523int mmc_set_dsr(struct mmc *mmc, u16 val);
3690d6d6
A
524/* Function to change the size of boot partition and rpmb partitions */
525int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
526 unsigned long rpmbsize);
792970b0
TR
527/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
528int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
5a99b9de
TR
529/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
530int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
33ace362
TR
531/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
532int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
91fdabc6
PA
533/* Functions to read / write the RPMB partition */
534int mmc_rpmb_set_key(struct mmc *mmc, void *key);
535int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
536int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
537 unsigned short cnt, unsigned char *key);
538int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
539 unsigned short cnt, unsigned char *key);
e9550449
CLC
540/**
541 * Start device initialization and return immediately; it does not block on
542 * polling OCR (operation condition register) status. Then you should call
543 * mmc_init, which would block on polling OCR status and complete the device
544 * initializatin.
545 *
546 * @param mmc Pointer to a MMC device struct
547 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
548 */
549int mmc_start_init(struct mmc *mmc);
550
551/**
552 * Set preinit flag of mmc device.
553 *
554 * This will cause the device to be pre-inited during mmc_initialize(),
555 * which may save boot time if the device is not accessed until later.
556 * Some eMMC devices take 200-300ms to init, but unfortunately they
557 * must be sent a series of commands to even get them to start preparing
558 * for operation.
559 *
560 * @param mmc Pointer to a MMC device struct
561 * @param preinit preinit flag value
562 */
563void mmc_set_preinit(struct mmc *mmc, int preinit);
564
8687d5c8 565#ifdef CONFIG_MMC_SPI
0b2da7e2 566#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
8687d5c8
PB
567#else
568#define mmc_host_is_spi(mmc) 0
569#endif
d52ebf10 570struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
1592ef85 571
95de9ab2 572void board_mmc_power_init(void);
3c7ca967 573int board_mmc_init(bd_t *bis);
750121c3 574int cpu_mmc_init(bd_t *bis);
aeb80555 575int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
aa844fe1 576int mmc_get_env_dev(void);
3c7ca967 577
91785f70
SG
578struct pci_device_id;
579
580/**
581 * pci_mmc_init() - set up PCI MMC devices
582 *
583 * This finds all the matching PCI IDs and sets them up as MMC devices.
584 *
585 * @name: Name to use for devices
4abe8e40 586 * @mmc_supported: PCI IDs to search for, terminated by {0, 0}
91785f70 587 */
4abe8e40 588int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported);
91785f70 589
93bfd616
PA
590/* Set block count limit because of 16 bit register limit on some hardware*/
591#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
592#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
593#endif
594
cb5ec33d
SG
595/**
596 * mmc_get_blk_desc() - Get the block descriptor for an MMC device
597 *
598 * @mmc: MMC device
599 * @return block device if found, else NULL
600 */
601struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
602
71f95118 603#endif /* _MMC_H_ */