]>
Commit | Line | Data |
---|---|---|
a06ea964 NC |
1 | /* AArch64 assembler/disassembler support. |
2 | ||
fd67aa11 | 3 | Copyright (C) 2009-2024 Free Software Foundation, Inc. |
a06ea964 NC |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GNU Binutils. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the license, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; see the file COPYING3. If not, | |
20 | see <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #ifndef OPCODE_AARCH64_H | |
23 | #define OPCODE_AARCH64_H | |
24 | ||
25 | #include "bfd.h" | |
3dfb1b6d | 26 | #include <stdint.h> |
a06ea964 NC |
27 | #include <assert.h> |
28 | #include <stdlib.h> | |
29 | ||
76a4c1e0 AB |
30 | #include "dis-asm.h" |
31 | ||
d3e12b29 YQ |
32 | #ifdef __cplusplus |
33 | extern "C" { | |
34 | #endif | |
35 | ||
a06ea964 NC |
36 | /* The offset for pc-relative addressing is currently defined to be 0. */ |
37 | #define AARCH64_PCREL_OFFSET 0 | |
38 | ||
39 | typedef uint32_t aarch64_insn; | |
40 | ||
4abb672a RS |
41 | /* An enum containing all known CPU features. The values act as bit positions |
42 | into aarch64_feature_set. */ | |
43 | enum aarch64_feature_bit { | |
44 | /* All processors. */ | |
45 | AARCH64_FEATURE_V8, | |
46 | /* ARMv8.6 processors. */ | |
47 | AARCH64_FEATURE_V8_6A, | |
48 | /* Bfloat16 insns. */ | |
49 | AARCH64_FEATURE_BFLOAT16, | |
50 | /* Armv8-A processors. */ | |
51 | AARCH64_FEATURE_V8A, | |
52 | /* SVE2 instructions. */ | |
53 | AARCH64_FEATURE_SVE2, | |
54 | /* ARMv8.2 processors. */ | |
55 | AARCH64_FEATURE_V8_2A, | |
56 | /* ARMv8.3 processors. */ | |
57 | AARCH64_FEATURE_V8_3A, | |
58 | AARCH64_FEATURE_SVE2_AES, | |
59 | AARCH64_FEATURE_SVE2_BITPERM, | |
60 | AARCH64_FEATURE_SVE2_SM4, | |
61 | AARCH64_FEATURE_SVE2_SHA3, | |
62 | /* ARMv8.4 processors. */ | |
63 | AARCH64_FEATURE_V8_4A, | |
64 | /* Armv8-R processors. */ | |
65 | AARCH64_FEATURE_V8R, | |
66 | /* Armv8.7 processors. */ | |
67 | AARCH64_FEATURE_V8_7A, | |
68 | /* Scalable Matrix Extension. */ | |
69 | AARCH64_FEATURE_SME, | |
70 | /* Atomic 64-byte load/store. */ | |
71 | AARCH64_FEATURE_LS64, | |
72 | /* v8.3 Pointer Authentication. */ | |
73 | AARCH64_FEATURE_PAC, | |
74 | /* FP instructions. */ | |
75 | AARCH64_FEATURE_FP, | |
76 | /* SIMD instructions. */ | |
77 | AARCH64_FEATURE_SIMD, | |
78 | /* CRC instructions. */ | |
79 | AARCH64_FEATURE_CRC, | |
80 | /* LSE instructions. */ | |
81 | AARCH64_FEATURE_LSE, | |
82 | /* PAN instructions. */ | |
83 | AARCH64_FEATURE_PAN, | |
84 | /* LOR instructions. */ | |
85 | AARCH64_FEATURE_LOR, | |
86 | /* v8.1 SIMD instructions. */ | |
87 | AARCH64_FEATURE_RDMA, | |
88 | /* v8.1 features. */ | |
89 | AARCH64_FEATURE_V8_1A, | |
90 | /* v8.2 FP16 instructions. */ | |
91 | AARCH64_FEATURE_F16, | |
92 | /* RAS Extensions. */ | |
93 | AARCH64_FEATURE_RAS, | |
94 | /* Statistical Profiling. */ | |
95 | AARCH64_FEATURE_PROFILE, | |
96 | /* SVE instructions. */ | |
97 | AARCH64_FEATURE_SVE, | |
98 | /* RCPC instructions. */ | |
99 | AARCH64_FEATURE_RCPC, | |
36891070 AC |
100 | /* RCPC2 instructions. */ |
101 | AARCH64_FEATURE_RCPC2, | |
4abb672a RS |
102 | /* Complex # instructions. */ |
103 | AARCH64_FEATURE_COMPNUM, | |
227af30e AC |
104 | /* JavaScript conversion instructions. */ |
105 | AARCH64_FEATURE_JSCVT, | |
4abb672a RS |
106 | /* Dot Product instructions. */ |
107 | AARCH64_FEATURE_DOTPROD, | |
108 | /* SM3 & SM4 instructions. */ | |
109 | AARCH64_FEATURE_SM4, | |
110 | /* SHA2 instructions. */ | |
111 | AARCH64_FEATURE_SHA2, | |
112 | /* SHA3 instructions. */ | |
113 | AARCH64_FEATURE_SHA3, | |
114 | /* AES instructions. */ | |
115 | AARCH64_FEATURE_AES, | |
116 | /* v8.2 FP16FML ins. */ | |
117 | AARCH64_FEATURE_F16_FML, | |
118 | /* ARMv8.5 processors. */ | |
119 | AARCH64_FEATURE_V8_5A, | |
120 | /* v8.5 Flag Manipulation version 2. */ | |
121 | AARCH64_FEATURE_FLAGMANIP, | |
122 | /* FRINT[32,64][Z,X] insns. */ | |
123 | AARCH64_FEATURE_FRINTTS, | |
124 | /* SB instruction. */ | |
125 | AARCH64_FEATURE_SB, | |
126 | /* Execution and Data Prediction Restriction instructions. */ | |
127 | AARCH64_FEATURE_PREDRES, | |
128 | /* DC CVADP. */ | |
129 | AARCH64_FEATURE_CVADP, | |
130 | /* Random Number instructions. */ | |
131 | AARCH64_FEATURE_RNG, | |
132 | /* BTI instructions. */ | |
133 | AARCH64_FEATURE_BTI, | |
134 | /* SCXTNUM_ELx. */ | |
135 | AARCH64_FEATURE_SCXTNUM, | |
136 | /* ID_PFR2 instructions. */ | |
137 | AARCH64_FEATURE_ID_PFR2, | |
138 | /* SSBS mechanism enabled. */ | |
139 | AARCH64_FEATURE_SSBS, | |
140 | /* Memory Tagging Extension. */ | |
141 | AARCH64_FEATURE_MEMTAG, | |
142 | /* Transactional Memory Extension. */ | |
143 | AARCH64_FEATURE_TME, | |
144 | /* Standardization of memory operations. */ | |
145 | AARCH64_FEATURE_MOPS, | |
146 | /* Hinted conditional branches. */ | |
147 | AARCH64_FEATURE_HBC, | |
148 | /* Matrix Multiply instructions. */ | |
149 | AARCH64_FEATURE_I8MM, | |
150 | AARCH64_FEATURE_F32MM, | |
151 | AARCH64_FEATURE_F64MM, | |
152 | /* v8.4 Flag Manipulation. */ | |
153 | AARCH64_FEATURE_FLAGM, | |
154 | /* Armv9.0-A processors. */ | |
155 | AARCH64_FEATURE_V9A, | |
156 | /* SME F64F64. */ | |
157 | AARCH64_FEATURE_SME_F64F64, | |
158 | /* SME I16I64. */ | |
159 | AARCH64_FEATURE_SME_I16I64, | |
160 | /* Armv8.8 processors. */ | |
161 | AARCH64_FEATURE_V8_8A, | |
162 | /* Common Short Sequence Compression instructions. */ | |
163 | AARCH64_FEATURE_CSSC, | |
8cee11ca | 164 | /* Armv8.9-A processors. */ |
165 | AARCH64_FEATURE_V8_9A, | |
6c0ecdba SP |
166 | /* Check Feature Status Extension. */ |
167 | AARCH64_FEATURE_CHK, | |
f985c251 | 168 | /* Guarded Control Stack. */ |
169 | AARCH64_FEATURE_GCS, | |
43e228e9 SP |
170 | /* SPE Call Return branch records. */ |
171 | AARCH64_FEATURE_SPE_CRR, | |
172 | /* SPE Filter by data source. */ | |
173 | AARCH64_FEATURE_SPE_FDS, | |
174 | /* Additional SPE events. */ | |
175 | AARCH64_FEATURE_SPEv1p4, | |
4abb672a | 176 | /* SME2. */ |
d86dbbea | 177 | AARCH64_FEATURE_SME2, |
9203a155 VDN |
178 | /* Translation Hardening Extension. */ |
179 | AARCH64_FEATURE_THE, | |
f0d70d8e VDN |
180 | /* LSE128. */ |
181 | AARCH64_FEATURE_LSE128, | |
311276f1 SP |
182 | /* ARMv8.9-A RAS Extensions. */ |
183 | AARCH64_FEATURE_RASv2, | |
184 | /* System Control Register2. */ | |
185 | AARCH64_FEATURE_SCTLR2, | |
186 | /* Fine Grained Traps. */ | |
187 | AARCH64_FEATURE_FGT2, | |
188 | /* Physical Fault Address. */ | |
189 | AARCH64_FEATURE_PFAR, | |
281fda33 SP |
190 | /* Address Translate Stage 1. */ |
191 | AARCH64_FEATURE_ATS1A, | |
44167ca8 SP |
192 | /* Memory Attribute Index Enhancement. */ |
193 | AARCH64_FEATURE_AIE, | |
194 | /* Stage 1 Permission Indirection Extension. */ | |
195 | AARCH64_FEATURE_S1PIE, | |
196 | /* Stage 2 Permission Indirection Extension. */ | |
197 | AARCH64_FEATURE_S2PIE, | |
198 | /* Stage 1 Permission Overlay Extension. */ | |
199 | AARCH64_FEATURE_S1POE, | |
200 | /* Stage 2 Permission Overlay Extension. */ | |
201 | AARCH64_FEATURE_S2POE, | |
202 | /* Extension to Translation Control Registers. */ | |
203 | AARCH64_FEATURE_TCR2, | |
88b5a8ae AC |
204 | /* Speculation Prediction Restriction instructions. */ |
205 | AARCH64_FEATURE_PREDRES2, | |
d645278c AC |
206 | /* Instrumentation Extension. */ |
207 | AARCH64_FEATURE_ITE, | |
7b08cc32 VDN |
208 | /* 128-bit page table descriptor, system registers |
209 | and isntructions. */ | |
210 | AARCH64_FEATURE_D128, | |
15f3b5ba SJ |
211 | /* Armv8.9-A/Armv9.4-A architecture Debug extension. */ |
212 | AARCH64_FEATURE_DEBUGv8p9, | |
213 | /* Performance Monitors Extension. */ | |
214 | AARCH64_FEATURE_PMUv3p9, | |
215 | /* Performance Monitors Snapshots Extension. */ | |
216 | AARCH64_FEATURE_PMUv3_SS, | |
217 | /* Performance Monitors Instruction Counter Extension. */ | |
218 | AARCH64_FEATURE_PMUv3_ICNTR, | |
219 | /* Performance Monitors Synchronous-Exception-Based Event Extension. */ | |
220 | AARCH64_FEATURE_SEBEP, | |
d86dbbea | 221 | AARCH64_NUM_FEATURES |
4abb672a RS |
222 | }; |
223 | ||
224 | /* These macros take an initial argument X that gives the index into | |
225 | an aarch64_feature_set. The macros then return the bitmask for | |
226 | that array index. */ | |
227 | ||
228 | /* A mask in which feature bit BIT is set and all other bits are clear. */ | |
229 | #define AARCH64_UINT64_BIT(X, BIT) \ | |
230 | ((X) == (BIT) / 64 ? 1ULL << (BIT) % 64 : 0) | |
231 | ||
232 | /* A mask that includes only AARCH64_FEATURE_<NAME>. */ | |
233 | #define AARCH64_FEATBIT(X, NAME) \ | |
234 | AARCH64_UINT64_BIT (X, AARCH64_FEATURE_##NAME) | |
235 | ||
236 | /* A mask of the features that are enabled by each architecture version, | |
237 | excluding those that are inherited from other architecture versions. */ | |
238 | #define AARCH64_ARCH_V8A_FEATURES(X) (AARCH64_FEATBIT (X, V8A) \ | |
239 | | AARCH64_FEATBIT (X, FP) \ | |
240 | | AARCH64_FEATBIT (X, RAS) \ | |
6c0ecdba SP |
241 | | AARCH64_FEATBIT (X, SIMD) \ |
242 | | AARCH64_FEATBIT (X, CHK)) | |
4abb672a RS |
243 | #define AARCH64_ARCH_V8_1A_FEATURES(X) (AARCH64_FEATBIT (X, V8_1A) \ |
244 | | AARCH64_FEATBIT (X, CRC) \ | |
245 | | AARCH64_FEATBIT (X, LSE) \ | |
246 | | AARCH64_FEATBIT (X, PAN) \ | |
247 | | AARCH64_FEATBIT (X, LOR) \ | |
248 | | AARCH64_FEATBIT (X, RDMA)) | |
249 | #define AARCH64_ARCH_V8_2A_FEATURES(X) (AARCH64_FEATBIT (X, V8_2A)) | |
250 | #define AARCH64_ARCH_V8_3A_FEATURES(X) (AARCH64_FEATBIT (X, V8_3A) \ | |
251 | | AARCH64_FEATBIT (X, PAC) \ | |
252 | | AARCH64_FEATBIT (X, RCPC) \ | |
227af30e AC |
253 | | AARCH64_FEATBIT (X, COMPNUM) \ |
254 | | AARCH64_FEATBIT (X, JSCVT)) | |
4abb672a | 255 | #define AARCH64_ARCH_V8_4A_FEATURES(X) (AARCH64_FEATBIT (X, V8_4A) \ |
36891070 | 256 | | AARCH64_FEATBIT (X, RCPC2) \ |
4abb672a RS |
257 | | AARCH64_FEATBIT (X, DOTPROD) \ |
258 | | AARCH64_FEATBIT (X, FLAGM) \ | |
259 | | AARCH64_FEATBIT (X, F16_FML)) | |
260 | #define AARCH64_ARCH_V8_5A_FEATURES(X) (AARCH64_FEATBIT (X, V8_5A) \ | |
261 | | AARCH64_FEATBIT (X, FLAGMANIP) \ | |
262 | | AARCH64_FEATBIT (X, FRINTTS) \ | |
263 | | AARCH64_FEATBIT (X, SB) \ | |
264 | | AARCH64_FEATBIT (X, PREDRES) \ | |
265 | | AARCH64_FEATBIT (X, CVADP) \ | |
266 | | AARCH64_FEATBIT (X, BTI) \ | |
267 | | AARCH64_FEATBIT (X, SCXTNUM) \ | |
268 | | AARCH64_FEATBIT (X, ID_PFR2) \ | |
269 | | AARCH64_FEATBIT (X, SSBS)) | |
270 | #define AARCH64_ARCH_V8_6A_FEATURES(X) (AARCH64_FEATBIT (X, V8_6A) \ | |
271 | | AARCH64_FEATBIT (X, BFLOAT16) \ | |
272 | | AARCH64_FEATBIT (X, I8MM)) | |
273 | #define AARCH64_ARCH_V8_7A_FEATURES(X) (AARCH64_FEATBIT (X, V8_7A) \ | |
274 | | AARCH64_FEATBIT (X, LS64)) | |
275 | #define AARCH64_ARCH_V8_8A_FEATURES(X) (AARCH64_FEATBIT (X, V8_8A) \ | |
276 | | AARCH64_FEATBIT (X, MOPS) \ | |
277 | | AARCH64_FEATBIT (X, HBC)) | |
43e228e9 SP |
278 | #define AARCH64_ARCH_V8_9A_FEATURES(X) (AARCH64_FEATBIT (X, V8_9A) \ |
279 | | AARCH64_FEATBIT (X, SPEv1p4) \ | |
280 | | AARCH64_FEATBIT (X, SPE_CRR) \ | |
311276f1 SP |
281 | | AARCH64_FEATBIT (X, SPE_FDS) \ |
282 | | AARCH64_FEATBIT (X, RASv2) \ | |
283 | | AARCH64_FEATBIT (X, SCTLR2) \ | |
284 | | AARCH64_FEATBIT (X, FGT2) \ | |
281fda33 | 285 | | AARCH64_FEATBIT (X, PFAR) \ |
44167ca8 SP |
286 | | AARCH64_FEATBIT (X, ATS1A) \ |
287 | | AARCH64_FEATBIT (X, AIE) \ | |
288 | | AARCH64_FEATBIT (X, S1PIE) \ | |
289 | | AARCH64_FEATBIT (X, S2PIE) \ | |
290 | | AARCH64_FEATBIT (X, S1POE) \ | |
291 | | AARCH64_FEATBIT (X, S2POE) \ | |
292 | | AARCH64_FEATBIT (X, TCR2) \ | |
15f3b5ba SJ |
293 | | AARCH64_FEATBIT (X, DEBUGv8p9) \ |
294 | | AARCH64_FEATBIT (X, PMUv3p9) \ | |
295 | | AARCH64_FEATBIT (X, PMUv3_SS) \ | |
296 | | AARCH64_FEATBIT (X, PMUv3_ICNTR) \ | |
297 | | AARCH64_FEATBIT (X, SEBEP) \ | |
44167ca8 | 298 | ) |
4abb672a RS |
299 | |
300 | #define AARCH64_ARCH_V9A_FEATURES(X) (AARCH64_FEATBIT (X, V9A) \ | |
301 | | AARCH64_FEATBIT (X, F16) \ | |
302 | | AARCH64_FEATBIT (X, SVE) \ | |
303 | | AARCH64_FEATBIT (X, SVE2)) | |
304 | #define AARCH64_ARCH_V9_1A_FEATURES(X) AARCH64_ARCH_V8_6A_FEATURES (X) | |
305 | #define AARCH64_ARCH_V9_2A_FEATURES(X) AARCH64_ARCH_V8_7A_FEATURES (X) | |
306 | #define AARCH64_ARCH_V9_3A_FEATURES(X) AARCH64_ARCH_V8_8A_FEATURES (X) | |
88b5a8ae AC |
307 | #define AARCH64_ARCH_V9_4A_FEATURES(X) (AARCH64_ARCH_V8_9A_FEATURES (X) \ |
308 | | AARCH64_FEATBIT (X, PREDRES2)) | |
35180222 | 309 | |
a06ea964 | 310 | /* Architectures are the sum of the base and extensions. */ |
4abb672a RS |
311 | #define AARCH64_ARCH_V8A(X) (AARCH64_FEATBIT (X, V8) \ |
312 | | AARCH64_ARCH_V8A_FEATURES (X)) | |
313 | #define AARCH64_ARCH_V8_1A(X) (AARCH64_ARCH_V8A (X) \ | |
314 | | AARCH64_ARCH_V8_1A_FEATURES (X)) | |
315 | #define AARCH64_ARCH_V8_2A(X) (AARCH64_ARCH_V8_1A (X) \ | |
316 | | AARCH64_ARCH_V8_2A_FEATURES (X)) | |
317 | #define AARCH64_ARCH_V8_3A(X) (AARCH64_ARCH_V8_2A (X) \ | |
318 | | AARCH64_ARCH_V8_3A_FEATURES (X)) | |
319 | #define AARCH64_ARCH_V8_4A(X) (AARCH64_ARCH_V8_3A (X) \ | |
320 | | AARCH64_ARCH_V8_4A_FEATURES (X)) | |
321 | #define AARCH64_ARCH_V8_5A(X) (AARCH64_ARCH_V8_4A (X) \ | |
322 | | AARCH64_ARCH_V8_5A_FEATURES (X)) | |
323 | #define AARCH64_ARCH_V8_6A(X) (AARCH64_ARCH_V8_5A (X) \ | |
324 | | AARCH64_ARCH_V8_6A_FEATURES (X)) | |
325 | #define AARCH64_ARCH_V8_7A(X) (AARCH64_ARCH_V8_6A (X) \ | |
326 | | AARCH64_ARCH_V8_7A_FEATURES (X)) | |
327 | #define AARCH64_ARCH_V8_8A(X) (AARCH64_ARCH_V8_7A (X) \ | |
328 | | AARCH64_ARCH_V8_8A_FEATURES (X)) | |
8cee11ca | 329 | #define AARCH64_ARCH_V8_9A(X) (AARCH64_ARCH_V8_8A (X) \ |
330 | | AARCH64_ARCH_V8_9A_FEATURES (X)) | |
4abb672a RS |
331 | #define AARCH64_ARCH_V8R(X) ((AARCH64_ARCH_V8_4A (X) \ |
332 | | AARCH64_FEATBIT (X, V8R)) \ | |
333 | & ~AARCH64_FEATBIT (X, V8A) \ | |
334 | & ~AARCH64_FEATBIT (X, LOR)) | |
335 | ||
336 | #define AARCH64_ARCH_V9A(X) (AARCH64_ARCH_V8_5A (X) \ | |
337 | | AARCH64_ARCH_V9A_FEATURES (X)) | |
338 | #define AARCH64_ARCH_V9_1A(X) (AARCH64_ARCH_V9A (X) \ | |
339 | | AARCH64_ARCH_V9_1A_FEATURES (X)) | |
340 | #define AARCH64_ARCH_V9_2A(X) (AARCH64_ARCH_V9_1A (X) \ | |
341 | | AARCH64_ARCH_V9_2A_FEATURES (X)) | |
342 | #define AARCH64_ARCH_V9_3A(X) (AARCH64_ARCH_V9_2A (X) \ | |
343 | | AARCH64_ARCH_V9_3A_FEATURES (X)) | |
8cee11ca | 344 | #define AARCH64_ARCH_V9_4A(X) (AARCH64_ARCH_V9_3A (X) \ |
345 | | AARCH64_ARCH_V9_4A_FEATURES (X)) | |
4abb672a RS |
346 | |
347 | #define AARCH64_ARCH_NONE(X) 0 | |
a06ea964 NC |
348 | |
349 | /* CPU-specific features. */ | |
d86dbbea RS |
350 | typedef struct { |
351 | uint64_t flags[(AARCH64_NUM_FEATURES + 63) / 64]; | |
352 | } aarch64_feature_set; | |
a06ea964 | 353 | |
4abb672a | 354 | #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \ |
d86dbbea RS |
355 | ((~(CPU).flags[0] & AARCH64_FEATBIT (0, FEAT)) == 0 \ |
356 | && (~(CPU).flags[1] & AARCH64_FEATBIT (1, FEAT)) == 0) | |
4abb672a | 357 | |
93d8990c | 358 | #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \ |
d86dbbea RS |
359 | ((~(CPU).flags[0] & (FEAT).flags[0]) == 0 \ |
360 | && (~(CPU).flags[1] & (FEAT).flags[1]) == 0) | |
93d8990c SN |
361 | |
362 | #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \ | |
d86dbbea RS |
363 | (((CPU).flags[0] & (FEAT).flags[0]) != 0 \ |
364 | || ((CPU).flags[1] & (FEAT).flags[1]) != 0) | |
a06ea964 | 365 | |
4abb672a | 366 | #define AARCH64_SET_FEATURE(DEST, FEAT) \ |
d86dbbea RS |
367 | ((DEST).flags[0] = FEAT (0), \ |
368 | (DEST).flags[1] = FEAT (1)) | |
4abb672a RS |
369 | |
370 | #define AARCH64_CLEAR_FEATURE(DEST, SRC, FEAT) \ | |
d86dbbea RS |
371 | ((DEST).flags[0] = (SRC).flags[0] & ~AARCH64_FEATBIT (0, FEAT), \ |
372 | (DEST).flags[1] = (SRC).flags[1] & ~AARCH64_FEATBIT (1, FEAT)) | |
373 | ||
374 | #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \ | |
375 | do \ | |
376 | { \ | |
377 | (TARG).flags[0] = (F1).flags[0] | (F2).flags[0]; \ | |
378 | (TARG).flags[1] = (F1).flags[1] | (F2).flags[1]; \ | |
379 | } \ | |
a06ea964 NC |
380 | while (0) |
381 | ||
d86dbbea RS |
382 | #define AARCH64_CLEAR_FEATURES(TARG,F1,F2) \ |
383 | do \ | |
384 | { \ | |
385 | (TARG).flags[0] = (F1).flags[0] &~ (F2).flags[0]; \ | |
386 | (TARG).flags[1] = (F1).flags[1] &~ (F2).flags[1]; \ | |
387 | } \ | |
a06ea964 NC |
388 | while (0) |
389 | ||
4abb672a RS |
390 | /* aarch64_feature_set initializers for no features and all features, |
391 | respectively. */ | |
d86dbbea RS |
392 | #define AARCH64_NO_FEATURES { { 0, 0 } } |
393 | #define AARCH64_ALL_FEATURES { { -1, -1 } } | |
4abb672a RS |
394 | |
395 | /* An aarch64_feature_set initializer for a single feature, | |
396 | AARCH64_FEATURE_<FEAT>. */ | |
d86dbbea RS |
397 | #define AARCH64_FEATURE(FEAT) \ |
398 | { { AARCH64_FEATBIT (0, FEAT), AARCH64_FEATBIT (1, FEAT) } } | |
4abb672a RS |
399 | |
400 | /* An aarch64_feature_set initializer for a specific architecture version, | |
401 | including all the features that are enabled by default for that architecture | |
402 | version. */ | |
d86dbbea RS |
403 | #define AARCH64_ARCH_FEATURES(ARCH) \ |
404 | { { AARCH64_ARCH_##ARCH (0), AARCH64_ARCH_##ARCH (1) } } | |
4abb672a RS |
405 | |
406 | /* Used by AARCH64_CPU_FEATURES. */ | |
407 | #define AARCH64_OR_FEATURES_1(X, ARCH, F1) \ | |
408 | (AARCH64_FEATBIT (X, F1) | AARCH64_ARCH_##ARCH (X)) | |
409 | #define AARCH64_OR_FEATURES_2(X, ARCH, F1, F2) \ | |
410 | (AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_1 (X, ARCH, F2)) | |
411 | #define AARCH64_OR_FEATURES_3(X, ARCH, F1, ...) \ | |
412 | (AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_2 (X, ARCH, __VA_ARGS__)) | |
413 | #define AARCH64_OR_FEATURES_4(X, ARCH, F1, ...) \ | |
414 | (AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_3 (X, ARCH, __VA_ARGS__)) | |
415 | #define AARCH64_OR_FEATURES_5(X, ARCH, F1, ...) \ | |
416 | (AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_4 (X, ARCH, __VA_ARGS__)) | |
417 | #define AARCH64_OR_FEATURES_6(X, ARCH, F1, ...) \ | |
418 | (AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_5 (X, ARCH, __VA_ARGS__)) | |
419 | #define AARCH64_OR_FEATURES_7(X, ARCH, F1, ...) \ | |
420 | (AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_6 (X, ARCH, __VA_ARGS__)) | |
421 | #define AARCH64_OR_FEATURES_8(X, ARCH, F1, ...) \ | |
422 | (AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_7 (X, ARCH, __VA_ARGS__)) | |
423 | #define AARCH64_OR_FEATURES_9(X, ARCH, F1, ...) \ | |
424 | (AARCH64_FEATBIT (X, F1) | AARCH64_OR_FEATURES_8 (X, ARCH, __VA_ARGS__)) | |
425 | ||
426 | /* An aarch64_feature_set initializer for a CPU that implements architecture | |
427 | version ARCH, and additionally provides the N features listed in "...". */ | |
428 | #define AARCH64_CPU_FEATURES(ARCH, N, ...) \ | |
d86dbbea RS |
429 | { { AARCH64_OR_FEATURES_##N (0, ARCH, __VA_ARGS__), \ |
430 | AARCH64_OR_FEATURES_##N (1, ARCH, __VA_ARGS__) } } | |
4abb672a RS |
431 | |
432 | /* An aarch64_feature_set initializer for the N features listed in "...". */ | |
433 | #define AARCH64_FEATURES(N, ...) \ | |
434 | AARCH64_CPU_FEATURES (NONE, N, __VA_ARGS__) | |
a06ea964 | 435 | |
a06ea964 NC |
436 | enum aarch64_operand_class |
437 | { | |
438 | AARCH64_OPND_CLASS_NIL, | |
439 | AARCH64_OPND_CLASS_INT_REG, | |
440 | AARCH64_OPND_CLASS_MODIFIED_REG, | |
441 | AARCH64_OPND_CLASS_FP_REG, | |
442 | AARCH64_OPND_CLASS_SIMD_REG, | |
443 | AARCH64_OPND_CLASS_SIMD_ELEMENT, | |
444 | AARCH64_OPND_CLASS_SISD_REG, | |
445 | AARCH64_OPND_CLASS_SIMD_REGLIST, | |
f11ad6bc | 446 | AARCH64_OPND_CLASS_SVE_REG, |
db3c06bf | 447 | AARCH64_OPND_CLASS_SVE_REGLIST, |
f11ad6bc | 448 | AARCH64_OPND_CLASS_PRED_REG, |
ff60bcbf | 449 | AARCH64_OPND_CLASS_ZA_ACCESS, |
a06ea964 NC |
450 | AARCH64_OPND_CLASS_ADDRESS, |
451 | AARCH64_OPND_CLASS_IMMEDIATE, | |
452 | AARCH64_OPND_CLASS_SYSTEM, | |
68a64283 | 453 | AARCH64_OPND_CLASS_COND, |
a06ea964 NC |
454 | }; |
455 | ||
456 | /* Operand code that helps both parsing and coding. | |
457 | Keep AARCH64_OPERANDS synced. */ | |
458 | ||
459 | enum aarch64_opnd | |
460 | { | |
461 | AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/ | |
462 | ||
463 | AARCH64_OPND_Rd, /* Integer register as destination. */ | |
464 | AARCH64_OPND_Rn, /* Integer register as source. */ | |
465 | AARCH64_OPND_Rm, /* Integer register as source. */ | |
466 | AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */ | |
467 | AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */ | |
6c0ecdba | 468 | AARCH64_OPND_X16, /* Integer register x16 in chkfeat instruction. */ |
8edca81e | 469 | AARCH64_OPND_Rt_LS64, /* Integer register used in LS64 instructions. */ |
bd7ceb8d | 470 | AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */ |
a06ea964 NC |
471 | AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */ |
472 | AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */ | |
473 | AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */ | |
474 | ||
475 | AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */ | |
476 | AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */ | |
c84364ec | 477 | AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */ |
ee804238 | 478 | AARCH64_OPND_PAIRREG, /* Paired register operand. */ |
d30eb38d | 479 | AARCH64_OPND_PAIRREG_OR_XZR, /* Paired register operand, optionally xzr. */ |
a06ea964 NC |
480 | AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */ |
481 | AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */ | |
482 | ||
483 | AARCH64_OPND_Fd, /* Floating-point Fd. */ | |
484 | AARCH64_OPND_Fn, /* Floating-point Fn. */ | |
485 | AARCH64_OPND_Fm, /* Floating-point Fm. */ | |
486 | AARCH64_OPND_Fa, /* Floating-point Fa. */ | |
487 | AARCH64_OPND_Ft, /* Floating-point Ft. */ | |
488 | AARCH64_OPND_Ft2, /* Floating-point Ft2. */ | |
489 | ||
490 | AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */ | |
491 | AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */ | |
492 | AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */ | |
493 | ||
f42f1a1d | 494 | AARCH64_OPND_Va, /* AdvSIMD Vector Va. */ |
a06ea964 NC |
495 | AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */ |
496 | AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */ | |
497 | AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */ | |
498 | AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */ | |
499 | AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */ | |
500 | AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */ | |
501 | AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */ | |
502 | AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */ | |
369c9167 TC |
503 | AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when |
504 | qualifier is S_H. */ | |
a06ea964 NC |
505 | AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */ |
506 | AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */ | |
507 | AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single | |
508 | structure to all lanes. */ | |
509 | AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */ | |
510 | ||
a6a51754 RL |
511 | AARCH64_OPND_CRn, /* Co-processor register in CRn field. */ |
512 | AARCH64_OPND_CRm, /* Co-processor register in CRm field. */ | |
a06ea964 NC |
513 | |
514 | AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */ | |
f42f1a1d | 515 | AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */ |
a06ea964 NC |
516 | AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */ |
517 | AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */ | |
518 | AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */ | |
519 | AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */ | |
520 | AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */ | |
521 | AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction | |
522 | (no encoding). */ | |
523 | AARCH64_OPND_IMM0, /* Immediate for #0. */ | |
524 | AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */ | |
525 | AARCH64_OPND_FPIMM, /* Floating-point Immediate. */ | |
526 | AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */ | |
527 | AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */ | |
528 | AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */ | |
529 | AARCH64_OPND_IMM, /* Immediate. */ | |
f42f1a1d | 530 | AARCH64_OPND_IMM_2, /* Immediate. */ |
a06ea964 NC |
531 | AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */ |
532 | AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */ | |
533 | AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */ | |
193614f2 | 534 | AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */ |
a06ea964 | 535 | AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */ |
193614f2 | 536 | AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */ |
a06ea964 NC |
537 | AARCH64_OPND_BIT_NUM, /* Immediate. */ |
538 | AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */ | |
09c1e68a | 539 | AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */ |
a06ea964 | 540 | AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ |
e950b345 | 541 | AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ |
a06ea964 NC |
542 | AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for |
543 | each condition flag. */ | |
544 | ||
545 | AARCH64_OPND_LIMM, /* Logical Immediate. */ | |
546 | AARCH64_OPND_AIMM, /* Arithmetic immediate. */ | |
547 | AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */ | |
548 | AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */ | |
549 | AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */ | |
c2c4ff8d SN |
550 | AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */ |
551 | AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */ | |
552 | AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */ | |
a06ea964 NC |
553 | |
554 | AARCH64_OPND_COND, /* Standard condition as the last operand. */ | |
68a64283 | 555 | AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */ |
a06ea964 NC |
556 | |
557 | AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */ | |
558 | AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */ | |
559 | AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */ | |
560 | AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */ | |
561 | AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */ | |
562 | ||
563 | AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */ | |
564 | AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */ | |
565 | AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */ | |
566 | AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */ | |
567 | AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is | |
568 | negative or unaligned and there is | |
569 | no writeback allowed. This operand code | |
570 | is only used to support the programmer- | |
571 | friendly feature of using LDR/STR as the | |
572 | the mnemonic name for LDUR/STUR instructions | |
573 | wherever there is no ambiguity. */ | |
3f06e550 | 574 | AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */ |
fb3265b3 SD |
575 | AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of |
576 | 16) immediate. */ | |
a06ea964 | 577 | AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */ |
fb3265b3 SD |
578 | AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of |
579 | 16) immediate. */ | |
a06ea964 | 580 | AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */ |
f42f1a1d | 581 | AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */ |
a06ea964 NC |
582 | AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */ |
583 | ||
584 | AARCH64_OPND_SYSREG, /* System register operand. */ | |
9af8f671 | 585 | AARCH64_OPND_SYSREG128, /* 128-bit system register operand. */ |
a06ea964 NC |
586 | AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */ |
587 | AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */ | |
588 | AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ | |
589 | AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ | |
590 | AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ | |
a9e2cefd | 591 | AARCH64_OPND_SYSREG_TLBIP, /* System register <tlbip_op> operand. */ |
2ac435d4 | 592 | AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */ |
a06ea964 | 593 | AARCH64_OPND_BARRIER, /* Barrier operand. */ |
fd195909 | 594 | AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */ |
a06ea964 NC |
595 | AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ |
596 | AARCH64_OPND_PRFOP, /* Prefetch operation. */ | |
8ff42920 | 597 | AARCH64_OPND_RPRFMOP, /* Range prefetch operation. */ |
1e6f4800 | 598 | AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ |
c58f84d8 | 599 | AARCH64_OPND_BARRIER_GCSB, /* Barrier operand for GCSB. */ |
ff605452 | 600 | AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */ |
6219f9da VDN |
601 | AARCH64_OPND_LSE128_Rt, /* LSE128 <Xt1>. */ |
602 | AARCH64_OPND_LSE128_Rt2, /* LSE128 <Xt2>. */ | |
582e12bf | 603 | AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */ |
8382113f | 604 | AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */ |
98907a70 RS |
605 | AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */ |
606 | AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */ | |
607 | AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */ | |
608 | AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */ | |
609 | AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */ | |
610 | AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */ | |
4df068de RS |
611 | AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */ |
612 | AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */ | |
613 | AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */ | |
614 | AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */ | |
c8d59609 | 615 | AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */ |
4df068de RS |
616 | AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */ |
617 | AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */ | |
618 | AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */ | |
619 | AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */ | |
01a4d082 | 620 | AARCH64_OPND_SVE_ADDR_RR_LSL4, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #4]. */ |
4df068de RS |
621 | AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */ |
622 | AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */ | |
623 | AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */ | |
624 | AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */ | |
c469c864 | 625 | AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.<T>{, <Xm>}]. */ |
4df068de RS |
626 | AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */ |
627 | AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */ | |
628 | AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */ | |
629 | AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */ | |
630 | AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. | |
631 | Bit 14 controls S/U choice. */ | |
632 | AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW]. | |
633 | Bit 22 controls S/U choice. */ | |
634 | AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. | |
635 | Bit 14 controls S/U choice. */ | |
636 | AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1]. | |
637 | Bit 22 controls S/U choice. */ | |
638 | AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. | |
639 | Bit 14 controls S/U choice. */ | |
640 | AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2]. | |
641 | Bit 22 controls S/U choice. */ | |
642 | AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. | |
643 | Bit 14 controls S/U choice. */ | |
644 | AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3]. | |
645 | Bit 22 controls S/U choice. */ | |
646 | AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */ | |
647 | AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */ | |
648 | AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */ | |
649 | AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */ | |
650 | AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */ | |
651 | AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */ | |
652 | AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */ | |
e950b345 RS |
653 | AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */ |
654 | AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */ | |
165d4950 RS |
655 | AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */ |
656 | AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */ | |
657 | AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */ | |
658 | AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */ | |
582e12bf RS |
659 | AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */ |
660 | AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */ | |
adccc507 | 661 | AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */ |
e950b345 RS |
662 | AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */ |
663 | AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */ | |
664 | AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */ | |
245d2e3f | 665 | AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */ |
2442d846 | 666 | AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */ |
245d2e3f | 667 | AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */ |
f11ad6bc | 668 | AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */ |
503fae12 | 669 | AARCH64_OPND_SVE_PNd, /* SVE pn0-pn15 in Pd. */ |
f11ad6bc RS |
670 | AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */ |
671 | AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */ | |
672 | AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */ | |
503fae12 | 673 | AARCH64_OPND_SVE_PNg4_10, /* SVE pn0-pn15 in Pg, bits [13,10]. */ |
f11ad6bc RS |
674 | AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */ |
675 | AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */ | |
676 | AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */ | |
503fae12 | 677 | AARCH64_OPND_SVE_PNn, /* SVE pn0-pn15 in Pn. */ |
f11ad6bc | 678 | AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */ |
503fae12 | 679 | AARCH64_OPND_SVE_PNt, /* SVE pn0-pn15 in Pt. */ |
047cd301 RS |
680 | AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */ |
681 | AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */ | |
e950b345 RS |
682 | AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */ |
683 | AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */ | |
28ed815a | 684 | AARCH64_OPND_SVE_SHLIMM_UNPRED_22, /* SVE 3 bit shift left unpred. */ |
e950b345 RS |
685 | AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */ |
686 | AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */ | |
3c17238b | 687 | AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */ |
e950b345 RS |
688 | AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */ |
689 | AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */ | |
690 | AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */ | |
691 | AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */ | |
692 | AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */ | |
693 | AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */ | |
694 | AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */ | |
695 | AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */ | |
047cd301 RS |
696 | AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */ |
697 | AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */ | |
698 | AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */ | |
699 | AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */ | |
f11ad6bc RS |
700 | AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */ |
701 | AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */ | |
702 | AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */ | |
703 | AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */ | |
704 | AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */ | |
582e12bf | 705 | AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */ |
116adc27 | 706 | AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */ |
dfc12f9f RS |
707 | AARCH64_OPND_SVE_Zm3_19_INDEX, /* z0-z7[0-3] in Zm3_INDEX plus bit 19. */ |
708 | AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ | |
31e36ab3 | 709 | AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */ |
582e12bf | 710 | AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ |
f11ad6bc RS |
711 | AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ |
712 | AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ | |
713 | AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ | |
714 | AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ | |
715 | AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ | |
d8773a8a RS |
716 | AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */ |
717 | AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */ | |
e87ff672 | 718 | AARCH64_OPND_SME_Zm, /* SVE vector register list in 4-bit Zm. */ |
99e01a66 RS |
719 | AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */ |
720 | AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */ | |
d8773a8a RS |
721 | AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */ |
722 | AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */ | |
b408ebbf RS |
723 | AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */ |
724 | AARCH64_OPND_SME_Ztx4_STRIDED, /* SVE vector register list in [4:0]&19. */ | |
971eda73 PW |
725 | AARCH64_OPND_SME_ZAda_2b, /* SME <ZAda>.S, 2-bits. */ |
726 | AARCH64_OPND_SME_ZAda_3b, /* SME <ZAda>.D, 3-bits. */ | |
7bb5f07c | 727 | AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */ |
d8773a8a | 728 | AARCH64_OPND_SME_ZA_HV_idx_srcxN, /* SME N source ZA tile vectors. */ |
7bb5f07c | 729 | AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */ |
d8773a8a | 730 | AARCH64_OPND_SME_ZA_HV_idx_destxN, /* SME N dest ZA tile vectors. */ |
99e01a66 RS |
731 | AARCH64_OPND_SME_Pdx2, /* Predicate register list in [3:1]. */ |
732 | AARCH64_OPND_SME_PdxN, /* Predicate register list in [3:0]. */ | |
971eda73 | 733 | AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */ |
99e01a66 | 734 | AARCH64_OPND_SME_PNd3, /* Predicate-as-counter register, bits [3:0]. */ |
b408ebbf | 735 | AARCH64_OPND_SME_PNg3, /* Predicate-as-counter register, bits [12:10]. */ |
99e01a66 RS |
736 | AARCH64_OPND_SME_PNn, /* Predicate-as-counter register, bits [8:5]. */ |
737 | AARCH64_OPND_SME_PNn3_INDEX1, /* Indexed pred-as-counter reg, bits [8:5]. */ | |
738 | AARCH64_OPND_SME_PNn3_INDEX2, /* Indexed pred-as-counter reg, bits [9:5]. */ | |
1cad938d | 739 | AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */ |
90cd80f8 | 740 | AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */ |
a8cb21aa | 741 | AARCH64_OPND_SME_ZA_array_off1x4, /* SME ZA[<Wv>, #<imm1>*4:<imm1>*4+3]. */ |
ed429b33 | 742 | AARCH64_OPND_SME_ZA_array_off2x2, /* SME ZA[<Wv>, #<imm2>*2:<imm2>*2+1]. */ |
a8cb21aa | 743 | AARCH64_OPND_SME_ZA_array_off2x4, /* SME ZA[<Wv>, #<imm2>*4:<imm2>*4+3]. */ |
d8773a8a RS |
744 | AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[<Wv>{, #<imm3>}]. */ |
745 | AARCH64_OPND_SME_ZA_array_off3_5, /* SME ZA[<Wv>{, #<imm3>}]. */ | |
ed429b33 | 746 | AARCH64_OPND_SME_ZA_array_off3x2, /* SME ZA[<Wv>, #<imm3>*2:<imm3>*2+1]. */ |
90cd80f8 | 747 | AARCH64_OPND_SME_ZA_array_off4, /* SME ZA[<Wv>{, #<imm>}]. */ |
01a4d082 | 748 | AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */ |
3dd032c5 | 749 | AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ |
90cd80f8 | 750 | AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */ |
6efa6601 RS |
751 | AARCH64_OPND_SME_SHRIMM4, /* 4-bit right shift, bits [19:16]. */ |
752 | AARCH64_OPND_SME_SHRIMM5, /* size + 5-bit right shift, bits [23:22,20:16]. */ | |
80752eb0 RS |
753 | AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */ |
754 | AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */ | |
a8cb21aa | 755 | AARCH64_OPND_SME_Zm_INDEX3_1, /* Zn.T[index], bits [19:16,10,2:1]. */ |
ed429b33 RS |
756 | AARCH64_OPND_SME_Zm_INDEX3_2, /* Zn.T[index], bits [19:16,11:10,2]. */ |
757 | AARCH64_OPND_SME_Zm_INDEX3_10, /* Zn.T[index], bits [19:16,15,11:10]. */ | |
a8cb21aa RS |
758 | AARCH64_OPND_SME_Zm_INDEX4_1, /* Zn.T[index], bits [19:16,11:10,2:1]. */ |
759 | AARCH64_OPND_SME_Zm_INDEX4_10, /* Zn.T[index], bits [19:16,15,12:10]. */ | |
cbd11b88 RS |
760 | AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */ |
761 | AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */ | |
762 | AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */ | |
763 | AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */ | |
764 | AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */ | |
765 | AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */ | |
99e01a66 RS |
766 | AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */ |
767 | AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */ | |
cbd11b88 RS |
768 | AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */ |
769 | AARCH64_OPND_SME_ZT0_INDEX, /* ZT0[<imm>], bits [14:12]. */ | |
770 | AARCH64_OPND_SME_ZT0_LIST, /* { zt0/ZT0 } (not encoded). */ | |
b83b4b13 | 771 | AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ |
f42f1a1d | 772 | AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ |
6327658e RS |
773 | AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */ |
774 | AARCH64_OPND_MOPS_ADDR_Rs, /* [Rs]!, in bits [16, 20]. */ | |
1f7b42d5 AV |
775 | AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */ |
776 | AARCH64_OPND_CSSC_SIMM8, /* CSSC signed 8-bit immediate. */ | |
777 | AARCH64_OPND_CSSC_UIMM8, /* CSSC unsigned 8-bit immediate. */ | |
a06ea964 NC |
778 | }; |
779 | ||
780 | /* Qualifier constrains an operand. It either specifies a variant of an | |
781 | operand type or limits values available to an operand type. | |
782 | ||
783 | N.B. Order is important; keep aarch64_opnd_qualifiers synced. */ | |
784 | ||
785 | enum aarch64_opnd_qualifier | |
786 | { | |
787 | /* Indicating no further qualification on an operand. */ | |
788 | AARCH64_OPND_QLF_NIL, | |
789 | ||
790 | /* Qualifying an operand which is a general purpose (integer) register; | |
791 | indicating the operand data size or a specific register. */ | |
792 | AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */ | |
793 | AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */ | |
794 | AARCH64_OPND_QLF_WSP, /* WSP. */ | |
795 | AARCH64_OPND_QLF_SP, /* SP. */ | |
796 | ||
797 | /* Qualifying an operand which is a floating-point register, a SIMD | |
798 | vector element or a SIMD vector element list; indicating operand data | |
799 | size or the size of each SIMD vector element in the case of a SIMD | |
800 | vector element list. | |
801 | These qualifiers are also used to qualify an address operand to | |
802 | indicate the size of data element a load/store instruction is | |
803 | accessing. | |
804 | They are also used for the immediate shift operand in e.g. SSHR. Such | |
805 | a use is only for the ease of operand encoding/decoding and qualifier | |
806 | sequence matching; such a use should not be applied widely; use the value | |
807 | constraint qualifiers for immediate operands wherever possible. */ | |
808 | AARCH64_OPND_QLF_S_B, | |
809 | AARCH64_OPND_QLF_S_H, | |
810 | AARCH64_OPND_QLF_S_S, | |
811 | AARCH64_OPND_QLF_S_D, | |
812 | AARCH64_OPND_QLF_S_Q, | |
df678013 MM |
813 | /* These type qualifiers have a special meaning in that they mean 4 x 1 byte |
814 | or 2 x 2 byte are selected by the instruction. Other than that they have | |
815 | no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely | |
816 | for syntactical reasons and is an exception from normal AArch64 | |
817 | disassembly scheme. */ | |
00c2093f | 818 | AARCH64_OPND_QLF_S_4B, |
df678013 | 819 | AARCH64_OPND_QLF_S_2H, |
a06ea964 NC |
820 | |
821 | /* Qualifying an operand which is a SIMD vector register or a SIMD vector | |
822 | register list; indicating register shape. | |
823 | They are also used for the immediate shift operand in e.g. SSHR. Such | |
824 | a use is only for the ease of operand encoding/decoding and qualifier | |
825 | sequence matching; such a use should not be applied widely; use the value | |
826 | constraint qualifiers for immediate operands wherever possible. */ | |
a3b3345a | 827 | AARCH64_OPND_QLF_V_4B, |
a06ea964 NC |
828 | AARCH64_OPND_QLF_V_8B, |
829 | AARCH64_OPND_QLF_V_16B, | |
3067d3b9 | 830 | AARCH64_OPND_QLF_V_2H, |
a06ea964 NC |
831 | AARCH64_OPND_QLF_V_4H, |
832 | AARCH64_OPND_QLF_V_8H, | |
833 | AARCH64_OPND_QLF_V_2S, | |
834 | AARCH64_OPND_QLF_V_4S, | |
835 | AARCH64_OPND_QLF_V_1D, | |
836 | AARCH64_OPND_QLF_V_2D, | |
837 | AARCH64_OPND_QLF_V_1Q, | |
838 | ||
d50c751e RS |
839 | AARCH64_OPND_QLF_P_Z, |
840 | AARCH64_OPND_QLF_P_M, | |
fb3265b3 SD |
841 | |
842 | /* Used in scaled signed immediate that are scaled by a Tag granule | |
843 | like in stg, st2g, etc. */ | |
844 | AARCH64_OPND_QLF_imm_tag, | |
d50c751e | 845 | |
a06ea964 | 846 | /* Constraint on value. */ |
a6a51754 | 847 | AARCH64_OPND_QLF_CR, /* CRn, CRm. */ |
a06ea964 NC |
848 | AARCH64_OPND_QLF_imm_0_7, |
849 | AARCH64_OPND_QLF_imm_0_15, | |
850 | AARCH64_OPND_QLF_imm_0_31, | |
851 | AARCH64_OPND_QLF_imm_0_63, | |
852 | AARCH64_OPND_QLF_imm_1_32, | |
853 | AARCH64_OPND_QLF_imm_1_64, | |
854 | ||
855 | /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros | |
856 | or shift-ones. */ | |
857 | AARCH64_OPND_QLF_LSL, | |
858 | AARCH64_OPND_QLF_MSL, | |
859 | ||
860 | /* Special qualifier helping retrieve qualifier information during the | |
861 | decoding time (currently not in use). */ | |
862 | AARCH64_OPND_QLF_RETRIEVE, | |
863 | }; | |
864 | \f | |
865 | /* Instruction class. */ | |
866 | ||
867 | enum aarch64_insn_class | |
868 | { | |
8382113f | 869 | aarch64_misc, |
a06ea964 NC |
870 | addsub_carry, |
871 | addsub_ext, | |
872 | addsub_imm, | |
873 | addsub_shift, | |
874 | asimdall, | |
875 | asimddiff, | |
876 | asimdelem, | |
877 | asimdext, | |
878 | asimdimm, | |
879 | asimdins, | |
880 | asimdmisc, | |
881 | asimdperm, | |
882 | asimdsame, | |
883 | asimdshf, | |
884 | asimdtbl, | |
885 | asisddiff, | |
886 | asisdelem, | |
887 | asisdlse, | |
888 | asisdlsep, | |
889 | asisdlso, | |
890 | asisdlsop, | |
891 | asisdmisc, | |
892 | asisdone, | |
893 | asisdpair, | |
894 | asisdsame, | |
895 | asisdshf, | |
896 | bitfield, | |
897 | branch_imm, | |
898 | branch_reg, | |
899 | compbranch, | |
900 | condbranch, | |
901 | condcmp_imm, | |
902 | condcmp_reg, | |
903 | condsel, | |
904 | cryptoaes, | |
905 | cryptosha2, | |
906 | cryptosha3, | |
907 | dp_1src, | |
908 | dp_2src, | |
909 | dp_3src, | |
910 | exception, | |
911 | extract, | |
912 | float2fix, | |
913 | float2int, | |
914 | floatccmp, | |
915 | floatcmp, | |
916 | floatdp1, | |
917 | floatdp2, | |
918 | floatdp3, | |
919 | floatimm, | |
920 | floatsel, | |
921 | ldst_immpost, | |
922 | ldst_immpre, | |
923 | ldst_imm9, /* immpost or immpre */ | |
3f06e550 | 924 | ldst_imm10, /* LDRAA/LDRAB */ |
a06ea964 NC |
925 | ldst_pos, |
926 | ldst_regoff, | |
927 | ldst_unpriv, | |
928 | ldst_unscaled, | |
929 | ldstexcl, | |
930 | ldstnapair_offs, | |
931 | ldstpair_off, | |
932 | ldstpair_indexed, | |
933 | loadlit, | |
934 | log_imm, | |
935 | log_shift, | |
ee804238 | 936 | lse_atomic, |
f0d70d8e | 937 | lse128_atomic, |
a06ea964 NC |
938 | movewide, |
939 | pcreladdr, | |
940 | ic_system, | |
e87ff672 RS |
941 | sme_fp_sd, |
942 | sme_int_sd, | |
971eda73 | 943 | sme_misc, |
a5791d58 | 944 | sme_mov, |
01a4d082 | 945 | sme_ldr, |
a5791d58 | 946 | sme_psel, |
6efa6601 | 947 | sme_shift, |
cbd11b88 RS |
948 | sme_size_12_bhs, |
949 | sme_size_12_hs, | |
d8773a8a | 950 | sme_size_22, |
27f6a0bd | 951 | sme_size_22_hsd, |
ce623e7a | 952 | sme_sz_23, |
01a4d082 | 953 | sme_str, |
3dd032c5 PW |
954 | sme_start, |
955 | sme_stop, | |
d8773a8a | 956 | sme2_mov, |
116b6019 RS |
957 | sve_cpy, |
958 | sve_index, | |
959 | sve_limm, | |
960 | sve_misc, | |
961 | sve_movprfx, | |
962 | sve_pred_zm, | |
963 | sve_shift_pred, | |
964 | sve_shift_unpred, | |
965 | sve_size_bhs, | |
966 | sve_size_bhsd, | |
967 | sve_size_hsd, | |
3bd82c86 | 968 | sve_size_hsd2, |
116b6019 | 969 | sve_size_sd, |
3c705960 | 970 | sve_size_bh, |
0a57e14f | 971 | sve_size_sd2, |
41be57ca | 972 | sve_size_13, |
3c17238b | 973 | sve_shift_tsz_hsd, |
1be5f94f | 974 | sve_shift_tsz_bhsd, |
fd1dc4a0 | 975 | sve_size_tsz_bhs, |
a06ea964 | 976 | testbranch, |
f42f1a1d TC |
977 | cryptosm3, |
978 | cryptosm4, | |
65a55fbb | 979 | dotproduct, |
df678013 | 980 | bfloat16, |
1f7b42d5 | 981 | cssc, |
f985c251 | 982 | gcs, |
e318eb09 | 983 | the, |
a06ea964 NC |
984 | }; |
985 | ||
986 | /* Opcode enumerators. */ | |
987 | ||
988 | enum aarch64_op | |
989 | { | |
990 | OP_NIL, | |
991 | OP_STRB_POS, | |
992 | OP_LDRB_POS, | |
993 | OP_LDRSB_POS, | |
994 | OP_STRH_POS, | |
995 | OP_LDRH_POS, | |
996 | OP_LDRSH_POS, | |
997 | OP_STR_POS, | |
998 | OP_LDR_POS, | |
999 | OP_STRF_POS, | |
1000 | OP_LDRF_POS, | |
1001 | OP_LDRSW_POS, | |
1002 | OP_PRFM_POS, | |
1003 | ||
1004 | OP_STURB, | |
1005 | OP_LDURB, | |
1006 | OP_LDURSB, | |
1007 | OP_STURH, | |
1008 | OP_LDURH, | |
1009 | OP_LDURSH, | |
1010 | OP_STUR, | |
1011 | OP_LDUR, | |
1012 | OP_STURV, | |
1013 | OP_LDURV, | |
1014 | OP_LDURSW, | |
1015 | OP_PRFUM, | |
1016 | ||
1017 | OP_LDR_LIT, | |
1018 | OP_LDRV_LIT, | |
1019 | OP_LDRSW_LIT, | |
1020 | OP_PRFM_LIT, | |
1021 | ||
1022 | OP_ADD, | |
1023 | OP_B, | |
1024 | OP_BL, | |
1025 | ||
1026 | OP_MOVN, | |
1027 | OP_MOVZ, | |
1028 | OP_MOVK, | |
1029 | ||
1030 | OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */ | |
1031 | OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */ | |
1032 | OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */ | |
1033 | ||
1034 | OP_MOV_V, /* MOV alias for moving vector register. */ | |
1035 | ||
1036 | OP_ASR_IMM, | |
1037 | OP_LSR_IMM, | |
1038 | OP_LSL_IMM, | |
1039 | ||
1040 | OP_BIC, | |
1041 | ||
1042 | OP_UBFX, | |
1043 | OP_BFXIL, | |
1044 | OP_SBFX, | |
1045 | OP_SBFIZ, | |
1046 | OP_BFI, | |
d685192a | 1047 | OP_BFC, /* ARMv8.2. */ |
a06ea964 NC |
1048 | OP_UBFIZ, |
1049 | OP_UXTB, | |
1050 | OP_UXTH, | |
1051 | OP_UXTW, | |
1052 | ||
a06ea964 NC |
1053 | OP_CINC, |
1054 | OP_CINV, | |
1055 | OP_CNEG, | |
1056 | OP_CSET, | |
1057 | OP_CSETM, | |
1058 | ||
1059 | OP_FCVT, | |
1060 | OP_FCVTN, | |
1061 | OP_FCVTN2, | |
1062 | OP_FCVTL, | |
1063 | OP_FCVTL2, | |
1064 | OP_FCVTXN_S, /* Scalar version. */ | |
1065 | ||
1066 | OP_ROR_IMM, | |
1067 | ||
e30181a5 YZ |
1068 | OP_SXTL, |
1069 | OP_SXTL2, | |
1070 | OP_UXTL, | |
1071 | OP_UXTL2, | |
1072 | ||
c0890d26 | 1073 | OP_MOV_P_P, |
503fae12 | 1074 | OP_MOV_PN_PN, |
c0890d26 RS |
1075 | OP_MOV_Z_P_Z, |
1076 | OP_MOV_Z_V, | |
1077 | OP_MOV_Z_Z, | |
1078 | OP_MOV_Z_Zi, | |
1079 | OP_MOVM_P_P_P, | |
1080 | OP_MOVS_P_P, | |
1081 | OP_MOVZS_P_P_P, | |
1082 | OP_MOVZ_P_P_P, | |
1083 | OP_NOTS_P_P_P_Z, | |
1084 | OP_NOT_P_P_P_Z, | |
1085 | ||
c2c4ff8d SN |
1086 | OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */ |
1087 | ||
a06ea964 NC |
1088 | OP_TOTAL_NUM, /* Pseudo. */ |
1089 | }; | |
1090 | ||
1d482394 TC |
1091 | /* Error types. */ |
1092 | enum err_type | |
1093 | { | |
1094 | ERR_OK, | |
1095 | ERR_UND, | |
1096 | ERR_UNP, | |
1097 | ERR_NYI, | |
a68f4cd2 | 1098 | ERR_VFI, |
1d482394 TC |
1099 | ERR_NR_ENTRIES |
1100 | }; | |
1101 | ||
a06ea964 | 1102 | /* Maximum number of operands an instruction can have. */ |
2ec6065a | 1103 | #define AARCH64_MAX_OPND_NUM 7 |
a06ea964 NC |
1104 | /* Maximum number of qualifier sequences an instruction can have. */ |
1105 | #define AARCH64_MAX_QLF_SEQ_NUM 10 | |
1106 | /* Operand qualifier typedef; optimized for the size. */ | |
1107 | typedef unsigned char aarch64_opnd_qualifier_t; | |
1108 | /* Operand qualifier sequence typedef. */ | |
1109 | typedef aarch64_opnd_qualifier_t \ | |
1110 | aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM]; | |
1111 | ||
1112 | /* FIXME: improve the efficiency. */ | |
9193bc42 | 1113 | static inline bool |
a06ea964 NC |
1114 | empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers) |
1115 | { | |
1116 | int i; | |
1117 | for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i) | |
1118 | if (qualifiers[i] != AARCH64_OPND_QLF_NIL) | |
9193bc42 AM |
1119 | return false; |
1120 | return true; | |
a06ea964 NC |
1121 | } |
1122 | ||
7e84b55d TC |
1123 | /* Forward declare error reporting type. */ |
1124 | typedef struct aarch64_operand_error aarch64_operand_error; | |
1125 | /* Forward declare instruction sequence type. */ | |
1126 | typedef struct aarch64_instr_sequence aarch64_instr_sequence; | |
1127 | /* Forward declare instruction definition. */ | |
1128 | typedef struct aarch64_inst aarch64_inst; | |
1129 | ||
a06ea964 NC |
1130 | /* This structure holds information for a particular opcode. */ |
1131 | ||
1132 | struct aarch64_opcode | |
1133 | { | |
1134 | /* The name of the mnemonic. */ | |
1135 | const char *name; | |
1136 | ||
1137 | /* The opcode itself. Those bits which will be filled in with | |
1138 | operands are zeroes. */ | |
1139 | aarch64_insn opcode; | |
1140 | ||
1141 | /* The opcode mask. This is used by the disassembler. This is a | |
1142 | mask containing ones indicating those bits which must match the | |
1143 | opcode field, and zeroes indicating those bits which need not | |
1144 | match (and are presumably filled in by operands). */ | |
1145 | aarch64_insn mask; | |
1146 | ||
1147 | /* Instruction class. */ | |
1148 | enum aarch64_insn_class iclass; | |
1149 | ||
1150 | /* Enumerator identifier. */ | |
1151 | enum aarch64_op op; | |
1152 | ||
1153 | /* Which architecture variant provides this instruction. */ | |
1154 | const aarch64_feature_set *avariant; | |
1155 | ||
1156 | /* An array of operand codes. Each code is an index into the | |
1157 | operand table. They appear in the order which the operands must | |
1158 | appear in assembly code, and are terminated by a zero. */ | |
1159 | enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM]; | |
1160 | ||
1161 | /* A list of operand qualifier code sequence. Each operand qualifier | |
1162 | code qualifies the corresponding operand code. Each operand | |
1163 | qualifier sequence specifies a valid opcode variant and related | |
1164 | constraint on operands. */ | |
1165 | aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM]; | |
1166 | ||
1167 | /* Flags providing information about this instruction */ | |
eae424ae TC |
1168 | uint64_t flags; |
1169 | ||
1170 | /* Extra constraints on the instruction that the verifier checks. */ | |
1171 | uint32_t constraints; | |
4bd13cde | 1172 | |
0c608d6b RS |
1173 | /* If nonzero, this operand and operand 0 are both registers and |
1174 | are required to have the same register number. */ | |
1175 | unsigned char tied_operand; | |
1176 | ||
4bd13cde | 1177 | /* If non-NULL, a function to verify that a given instruction is valid. */ |
755b748f | 1178 | enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn, |
9193bc42 | 1179 | bfd_vma, bool, aarch64_operand_error *, |
755b748f | 1180 | struct aarch64_instr_sequence *); |
a06ea964 NC |
1181 | }; |
1182 | ||
1183 | typedef struct aarch64_opcode aarch64_opcode; | |
1184 | ||
1185 | /* Table describing all the AArch64 opcodes. */ | |
6c2ede01 | 1186 | extern const aarch64_opcode aarch64_opcode_table[]; |
a06ea964 NC |
1187 | |
1188 | /* Opcode flags. */ | |
1189 | #define F_ALIAS (1 << 0) | |
1190 | #define F_HAS_ALIAS (1 << 1) | |
1191 | /* Disassembly preference priority 1-3 (the larger the higher). If nothing | |
1192 | is specified, it is the priority 0 by default, i.e. the lowest priority. */ | |
1193 | #define F_P1 (1 << 2) | |
1194 | #define F_P2 (2 << 2) | |
1195 | #define F_P3 (3 << 2) | |
1196 | /* Flag an instruction that is truly conditional executed, e.g. b.cond. */ | |
1197 | #define F_COND (1 << 4) | |
1198 | /* Instruction has the field of 'sf'. */ | |
1199 | #define F_SF (1 << 5) | |
1200 | /* Instruction has the field of 'size:Q'. */ | |
1201 | #define F_SIZEQ (1 << 6) | |
1202 | /* Floating-point instruction has the field of 'type'. */ | |
1203 | #define F_FPTYPE (1 << 7) | |
1204 | /* AdvSIMD scalar instruction has the field of 'size'. */ | |
1205 | #define F_SSIZE (1 << 8) | |
1206 | /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */ | |
1207 | #define F_T (1 << 9) | |
1208 | /* Size of GPR operand in AdvSIMD instructions encoded in Q. */ | |
1209 | #define F_GPRSIZE_IN_Q (1 << 10) | |
1210 | /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */ | |
1211 | #define F_LDS_SIZE (1 << 11) | |
1212 | /* Optional operand; assume maximum of 1 operand can be optional. */ | |
1213 | #define F_OPD0_OPT (1 << 12) | |
1214 | #define F_OPD1_OPT (2 << 12) | |
1215 | #define F_OPD2_OPT (3 << 12) | |
1216 | #define F_OPD3_OPT (4 << 12) | |
1217 | #define F_OPD4_OPT (5 << 12) | |
1218 | /* Default value for the optional operand when omitted from the assembly. */ | |
1219 | #define F_DEFAULT(X) (((X) & 0x1f) << 15) | |
1220 | /* Instruction that is an alias of another instruction needs to be | |
1221 | encoded/decoded by converting it to/from the real form, followed by | |
1222 | the encoding/decoding according to the rules of the real opcode. | |
1223 | This compares to the direct coding using the alias's information. | |
1224 | N.B. this flag requires F_ALIAS to be used together. */ | |
1225 | #define F_CONV (1 << 20) | |
1226 | /* Use together with F_ALIAS to indicate an alias opcode is a programmer | |
1227 | friendly pseudo instruction available only in the assembly code (thus will | |
1228 | not show up in the disassembly). */ | |
1229 | #define F_PSEUDO (1 << 21) | |
1230 | /* Instruction has miscellaneous encoding/decoding rules. */ | |
1231 | #define F_MISC (1 << 22) | |
1232 | /* Instruction has the field of 'N'; used in conjunction with F_SF. */ | |
1233 | #define F_N (1 << 23) | |
1234 | /* Opcode dependent field. */ | |
1235 | #define F_OD(X) (((X) & 0x7) << 24) | |
ee804238 JW |
1236 | /* Instruction has the field of 'sz'. */ |
1237 | #define F_LSE_SZ (1 << 27) | |
4989adac RS |
1238 | /* Require an exact qualifier match, even for NIL qualifiers. */ |
1239 | #define F_STRICT (1ULL << 28) | |
f9830ec1 TC |
1240 | /* This system instruction is used to read system registers. */ |
1241 | #define F_SYS_READ (1ULL << 29) | |
1242 | /* This system instruction is used to write system registers. */ | |
1243 | #define F_SYS_WRITE (1ULL << 30) | |
eae424ae TC |
1244 | /* This instruction has an extra constraint on it that imposes a requirement on |
1245 | subsequent instructions. */ | |
1246 | #define F_SCAN (1ULL << 31) | |
f89c290e VDN |
1247 | /* Instruction takes a pair of optional operands. If we specify the Nth operand |
1248 | to be optional, then we also implicitly specify (N+1)th operand to also be | |
1249 | optional. */ | |
1250 | #define F_OPD_PAIR_OPT (1ULL << 32) | |
5517af82 VDN |
1251 | /* This instruction does not allow the full range of values that the |
1252 | width of fields in the assembler instruction would theoretically | |
1253 | allow. This impacts the constraintts on assembly but yelds no | |
1254 | impact on disassembly. */ | |
1255 | #define F_OPD_NARROW (1ULL << 33) | |
1256 | /* Next bit is 34. */ | |
eae424ae TC |
1257 | |
1258 | /* Instruction constraints. */ | |
1259 | /* This instruction has a predication constraint on the instruction at PC+4. */ | |
1260 | #define C_SCAN_MOVPRFX (1U << 0) | |
1261 | /* This instruction's operation width is determined by the operand with the | |
1262 | largest element size. */ | |
1263 | #define C_MAX_ELEM (1U << 1) | |
63eff947 RS |
1264 | #define C_SCAN_MOPS_P (1U << 2) |
1265 | #define C_SCAN_MOPS_M (2U << 2) | |
1266 | #define C_SCAN_MOPS_E (3U << 2) | |
1267 | #define C_SCAN_MOPS_PME (3U << 2) | |
1268 | /* Next bit is 4. */ | |
a06ea964 | 1269 | |
9193bc42 | 1270 | static inline bool |
a06ea964 NC |
1271 | alias_opcode_p (const aarch64_opcode *opcode) |
1272 | { | |
63b4cc53 | 1273 | return (opcode->flags & F_ALIAS) != 0; |
a06ea964 NC |
1274 | } |
1275 | ||
9193bc42 | 1276 | static inline bool |
a06ea964 NC |
1277 | opcode_has_alias (const aarch64_opcode *opcode) |
1278 | { | |
63b4cc53 | 1279 | return (opcode->flags & F_HAS_ALIAS) != 0; |
a06ea964 NC |
1280 | } |
1281 | ||
1282 | /* Priority for disassembling preference. */ | |
1283 | static inline int | |
1284 | opcode_priority (const aarch64_opcode *opcode) | |
1285 | { | |
1286 | return (opcode->flags >> 2) & 0x3; | |
1287 | } | |
1288 | ||
9193bc42 | 1289 | static inline bool |
a06ea964 NC |
1290 | pseudo_opcode_p (const aarch64_opcode *opcode) |
1291 | { | |
63b4cc53 | 1292 | return (opcode->flags & F_PSEUDO) != 0lu; |
a06ea964 NC |
1293 | } |
1294 | ||
f89c290e VDN |
1295 | /* Deal with two possible scenarios: If F_OP_PAIR_OPT not set, as is the case |
1296 | by default, F_OPDn_OPT must equal IDX + 1, else F_OPDn_OPT must be in range | |
1297 | [IDX, IDX + 1]. */ | |
9193bc42 | 1298 | static inline bool |
a06ea964 NC |
1299 | optional_operand_p (const aarch64_opcode *opcode, unsigned int idx) |
1300 | { | |
f89c290e VDN |
1301 | if (opcode->flags & F_OPD_PAIR_OPT) |
1302 | return (((opcode->flags >> 12) & 0x7) == idx | |
1303 | || ((opcode->flags >> 12) & 0x7) == idx + 1); | |
63b4cc53 | 1304 | return ((opcode->flags >> 12) & 0x7) == idx + 1; |
a06ea964 NC |
1305 | } |
1306 | ||
1307 | static inline aarch64_insn | |
1308 | get_optional_operand_default_value (const aarch64_opcode *opcode) | |
1309 | { | |
1310 | return (opcode->flags >> 15) & 0x1f; | |
1311 | } | |
1312 | ||
1313 | static inline unsigned int | |
1314 | get_opcode_dependent_value (const aarch64_opcode *opcode) | |
1315 | { | |
1316 | return (opcode->flags >> 24) & 0x7; | |
1317 | } | |
1318 | ||
9193bc42 | 1319 | static inline bool |
a06ea964 NC |
1320 | opcode_has_special_coder (const aarch64_opcode *opcode) |
1321 | { | |
ee804238 | 1322 | return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T |
63b4cc53 | 1323 | | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) != 0; |
a06ea964 NC |
1324 | } |
1325 | \f | |
1326 | struct aarch64_name_value_pair | |
1327 | { | |
1328 | const char * name; | |
1329 | aarch64_insn value; | |
1330 | }; | |
1331 | ||
1332 | extern const struct aarch64_name_value_pair aarch64_operand_modifiers []; | |
a06ea964 | 1333 | extern const struct aarch64_name_value_pair aarch64_barrier_options [16]; |
fd195909 | 1334 | extern const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options [4]; |
a06ea964 | 1335 | extern const struct aarch64_name_value_pair aarch64_prfops [32]; |
9ed608f9 | 1336 | extern const struct aarch64_name_value_pair aarch64_hint_options []; |
a06ea964 | 1337 | |
fa63795f AC |
1338 | #define AARCH64_MAX_SYSREG_NAME_LEN 32 |
1339 | ||
49eec193 YZ |
1340 | typedef struct |
1341 | { | |
1342 | const char * name; | |
1343 | aarch64_insn value; | |
1344 | uint32_t flags; | |
14962256 AC |
1345 | |
1346 | /* A set of features, all of which are required for this system register to be | |
1347 | available. */ | |
1348 | aarch64_feature_set features; | |
49eec193 YZ |
1349 | } aarch64_sys_reg; |
1350 | ||
1351 | extern const aarch64_sys_reg aarch64_sys_regs []; | |
87b8eed7 | 1352 | extern const aarch64_sys_reg aarch64_pstatefields []; |
9193bc42 | 1353 | extern bool aarch64_sys_reg_deprecated_p (const uint32_t); |
9af8f671 | 1354 | extern bool aarch64_sys_reg_128bit_p (const uint32_t); |
1bf6696b | 1355 | extern bool aarch64_sys_reg_alias_p (const uint32_t); |
9193bc42 AM |
1356 | extern bool aarch64_pstatefield_supported_p (const aarch64_feature_set, |
1357 | const aarch64_sys_reg *); | |
49eec193 | 1358 | |
a06ea964 NC |
1359 | typedef struct |
1360 | { | |
875880c6 | 1361 | const char *name; |
a06ea964 | 1362 | uint32_t value; |
ea2deeec | 1363 | uint32_t flags ; |
a06ea964 NC |
1364 | } aarch64_sys_ins_reg; |
1365 | ||
9193bc42 AM |
1366 | extern bool aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *); |
1367 | extern bool | |
38cf07a6 AC |
1368 | aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, |
1369 | const char *reg_name, aarch64_insn, | |
4abb672a | 1370 | uint32_t, const aarch64_feature_set *); |
ea2deeec | 1371 | |
a06ea964 NC |
1372 | extern const aarch64_sys_ins_reg aarch64_sys_regs_ic []; |
1373 | extern const aarch64_sys_ins_reg aarch64_sys_regs_dc []; | |
1374 | extern const aarch64_sys_ins_reg aarch64_sys_regs_at []; | |
1375 | extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi []; | |
2ac435d4 | 1376 | extern const aarch64_sys_ins_reg aarch64_sys_regs_sr []; |
a06ea964 NC |
1377 | |
1378 | /* Shift/extending operator kinds. | |
1379 | N.B. order is important; keep aarch64_operand_modifiers synced. */ | |
1380 | enum aarch64_modifier_kind | |
1381 | { | |
1382 | AARCH64_MOD_NONE, | |
1383 | AARCH64_MOD_MSL, | |
1384 | AARCH64_MOD_ROR, | |
1385 | AARCH64_MOD_ASR, | |
1386 | AARCH64_MOD_LSR, | |
1387 | AARCH64_MOD_LSL, | |
1388 | AARCH64_MOD_UXTB, | |
1389 | AARCH64_MOD_UXTH, | |
1390 | AARCH64_MOD_UXTW, | |
1391 | AARCH64_MOD_UXTX, | |
1392 | AARCH64_MOD_SXTB, | |
1393 | AARCH64_MOD_SXTH, | |
1394 | AARCH64_MOD_SXTW, | |
1395 | AARCH64_MOD_SXTX, | |
2442d846 | 1396 | AARCH64_MOD_MUL, |
98907a70 | 1397 | AARCH64_MOD_MUL_VL, |
a06ea964 NC |
1398 | }; |
1399 | ||
9193bc42 | 1400 | bool |
a06ea964 NC |
1401 | aarch64_extend_operator_p (enum aarch64_modifier_kind); |
1402 | ||
1403 | enum aarch64_modifier_kind | |
1404 | aarch64_get_operand_modifier (const struct aarch64_name_value_pair *); | |
1405 | /* Condition. */ | |
1406 | ||
1407 | typedef struct | |
1408 | { | |
1409 | /* A list of names with the first one as the disassembly preference; | |
1410 | terminated by NULL if fewer than 3. */ | |
bb7eff52 | 1411 | const char *names[4]; |
a06ea964 NC |
1412 | aarch64_insn value; |
1413 | } aarch64_cond; | |
1414 | ||
1415 | extern const aarch64_cond aarch64_conds[16]; | |
1416 | ||
1417 | const aarch64_cond* get_cond_from_value (aarch64_insn value); | |
1418 | const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); | |
1419 | \f | |
575c497a RS |
1420 | /* Information about a reference to part of ZA. */ |
1421 | struct aarch64_indexed_za | |
1422 | { | |
586c6281 RS |
1423 | /* Which tile is being accessed. Unused (and 0) for an index into ZA. */ |
1424 | int regno; | |
1425 | ||
575c497a RS |
1426 | struct |
1427 | { | |
586c6281 RS |
1428 | /* The 32-bit index register. */ |
1429 | int regno; | |
1430 | ||
1431 | /* The first (or only) immediate offset. */ | |
1432 | int64_t imm; | |
1433 | ||
1434 | /* The last immediate offset minus the first immediate offset. | |
1435 | Unlike the range size, this is guaranteed not to overflow | |
1436 | when the end offset > the start offset. */ | |
1437 | uint64_t countm1; | |
575c497a | 1438 | } index; |
586c6281 RS |
1439 | |
1440 | /* The vector group size, or 0 if none. */ | |
e2dc4040 | 1441 | unsigned group_size : 8; |
586c6281 RS |
1442 | |
1443 | /* True if a tile access is vertical, false if it is horizontal. | |
1444 | Unused (and 0) for an index into ZA. */ | |
1445 | unsigned v : 1; | |
575c497a RS |
1446 | }; |
1447 | ||
f5b57fea RS |
1448 | /* Information about a list of registers. */ |
1449 | struct aarch64_reglist | |
1450 | { | |
1451 | unsigned first_regno : 8; | |
1452 | unsigned num_regs : 8; | |
1453 | /* The difference between the nth and the n+1th register. */ | |
1454 | unsigned stride : 8; | |
1455 | /* 1 if it is a list of reg element. */ | |
1456 | unsigned has_index : 1; | |
1457 | /* Lane index; valid only when has_index is 1. */ | |
1458 | int64_t index; | |
d0562653 | 1459 | }; |
f5b57fea | 1460 | |
a06ea964 NC |
1461 | /* Structure representing an operand. */ |
1462 | ||
1463 | struct aarch64_opnd_info | |
1464 | { | |
1465 | enum aarch64_opnd type; | |
1466 | aarch64_opnd_qualifier_t qualifier; | |
1467 | int idx; | |
1468 | ||
1469 | union | |
1470 | { | |
1471 | struct | |
1472 | { | |
1473 | unsigned regno; | |
1474 | } reg; | |
1475 | struct | |
1476 | { | |
dab26bf4 RS |
1477 | unsigned int regno; |
1478 | int64_t index; | |
a06ea964 NC |
1479 | } reglane; |
1480 | /* e.g. LVn. */ | |
f5b57fea | 1481 | struct aarch64_reglist reglist; |
a06ea964 NC |
1482 | /* e.g. immediate or pc relative address offset. */ |
1483 | struct | |
1484 | { | |
1485 | int64_t value; | |
1486 | unsigned is_fp : 1; | |
1487 | } imm; | |
1488 | /* e.g. address in STR (register offset). */ | |
1489 | struct | |
1490 | { | |
1491 | unsigned base_regno; | |
1492 | struct | |
1493 | { | |
1494 | union | |
1495 | { | |
1496 | int imm; | |
1497 | unsigned regno; | |
1498 | }; | |
1499 | unsigned is_reg; | |
1500 | } offset; | |
1501 | unsigned pcrel : 1; /* PC-relative. */ | |
1502 | unsigned writeback : 1; | |
1503 | unsigned preind : 1; /* Pre-indexed. */ | |
1504 | unsigned postind : 1; /* Post-indexed. */ | |
1505 | } addr; | |
561a72d4 TC |
1506 | |
1507 | struct | |
1508 | { | |
1509 | /* The encoding of the system register. */ | |
1510 | aarch64_insn value; | |
1511 | ||
1512 | /* The system register flags. */ | |
1513 | uint32_t flags; | |
1514 | } sysreg; | |
1515 | ||
7bb5f07c | 1516 | /* ZA tile vector, e.g. <ZAn><HV>.D[<Wv>{, <imm>}] */ |
575c497a | 1517 | struct aarch64_indexed_za indexed_za; |
7bb5f07c | 1518 | |
a06ea964 | 1519 | const aarch64_cond *cond; |
a06ea964 NC |
1520 | /* The encoding of the PSTATE field. */ |
1521 | aarch64_insn pstatefield; | |
1522 | const aarch64_sys_ins_reg *sysins_op; | |
1523 | const struct aarch64_name_value_pair *barrier; | |
9ed608f9 | 1524 | const struct aarch64_name_value_pair *hint_option; |
a06ea964 NC |
1525 | const struct aarch64_name_value_pair *prfop; |
1526 | }; | |
1527 | ||
1528 | /* Operand shifter; in use when the operand is a register offset address, | |
1529 | add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */ | |
1530 | struct | |
1531 | { | |
1532 | enum aarch64_modifier_kind kind; | |
a06ea964 NC |
1533 | unsigned operator_present: 1; /* Only valid during encoding. */ |
1534 | /* Value of the 'S' field in ld/st reg offset; used only in decoding. */ | |
1535 | unsigned amount_present: 1; | |
2442d846 | 1536 | int64_t amount; |
a06ea964 NC |
1537 | } shifter; |
1538 | ||
1539 | unsigned skip:1; /* Operand is not completed if there is a fixup needed | |
1540 | to be done on it. In some (but not all) of these | |
1541 | cases, we need to tell libopcodes to skip the | |
1542 | constraint checking and the encoding for this | |
1543 | operand, so that the libopcodes can pick up the | |
1544 | right opcode before the operand is fixed-up. This | |
1545 | flag should only be used during the | |
1546 | assembling/encoding. */ | |
1547 | unsigned present:1; /* Whether this operand is present in the assembly | |
1548 | line; not used during the disassembly. */ | |
1549 | }; | |
1550 | ||
1551 | typedef struct aarch64_opnd_info aarch64_opnd_info; | |
1552 | ||
1553 | /* Structure representing an instruction. | |
1554 | ||
1555 | It is used during both the assembling and disassembling. The assembler | |
1556 | fills an aarch64_inst after a successful parsing and then passes it to the | |
1557 | encoding routine to do the encoding. During the disassembling, the | |
1558 | disassembler calls the decoding routine to decode a binary instruction; on a | |
1559 | successful return, such a structure will be filled with information of the | |
1560 | instruction; then the disassembler uses the information to print out the | |
1561 | instruction. */ | |
1562 | ||
1563 | struct aarch64_inst | |
1564 | { | |
1565 | /* The value of the binary instruction. */ | |
1566 | aarch64_insn value; | |
1567 | ||
1568 | /* Corresponding opcode entry. */ | |
1569 | const aarch64_opcode *opcode; | |
1570 | ||
1571 | /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */ | |
1572 | const aarch64_cond *cond; | |
1573 | ||
1574 | /* Operands information. */ | |
1575 | aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; | |
1576 | }; | |
1577 | ||
ff605452 SD |
1578 | /* Defining the HINT #imm values for the aarch64_hint_options. */ |
1579 | #define HINT_OPD_CSYNC 0x11 | |
c58f84d8 | 1580 | #define HINT_OPD_DSYNC 0x13 |
ff605452 SD |
1581 | #define HINT_OPD_C 0x22 |
1582 | #define HINT_OPD_J 0x24 | |
1583 | #define HINT_OPD_JC 0x26 | |
1584 | #define HINT_OPD_NULL 0x00 | |
1585 | ||
a06ea964 NC |
1586 | \f |
1587 | /* Diagnosis related declaration and interface. */ | |
1588 | ||
1589 | /* Operand error kind enumerators. | |
1590 | ||
1591 | AARCH64_OPDE_RECOVERABLE | |
1592 | Less severe error found during the parsing, very possibly because that | |
1593 | GAS has picked up a wrong instruction template for the parsing. | |
1594 | ||
63eff947 RS |
1595 | AARCH64_OPDE_A_SHOULD_FOLLOW_B |
1596 | The instruction forms (or is expected to form) part of a sequence, | |
1597 | but the preceding instruction in the sequence wasn't the expected one. | |
1598 | The message refers to two strings: the name of the current instruction, | |
1599 | followed by the name of the expected preceding instruction. | |
1600 | ||
1601 | AARCH64_OPDE_EXPECTED_A_AFTER_B | |
1602 | Same as AARCH64_OPDE_A_SHOULD_FOLLOW_B, but shifting the focus | |
1603 | so that the current instruction is assumed to be the incorrect one: | |
1604 | "since the previous instruction was B, the current one should be A". | |
1605 | ||
a06ea964 NC |
1606 | AARCH64_OPDE_SYNTAX_ERROR |
1607 | General syntax error; it can be either a user error, or simply because | |
1608 | that GAS is trying a wrong instruction template. | |
1609 | ||
1610 | AARCH64_OPDE_FATAL_SYNTAX_ERROR | |
1611 | Definitely a user syntax error. | |
1612 | ||
1613 | AARCH64_OPDE_INVALID_VARIANT | |
1614 | No syntax error, but the operands are not a valid combination, e.g. | |
1615 | FMOV D0,S0 | |
1616 | ||
36043bcf RS |
1617 | The following errors are only reported against an asm string that is |
1618 | syntactically valid and that has valid operand qualifiers. | |
1619 | ||
e2dc4040 RS |
1620 | AARCH64_OPDE_INVALID_VG_SIZE |
1621 | Error about a "VGx<n>" modifier in a ZA index not having the | |
1622 | correct <n>. This error effectively forms a pair with | |
1623 | AARCH64_OPDE_REG_LIST_LENGTH, since both errors relate to the number | |
1624 | of vectors that an instruction operates on. However, the "VGx<n>" | |
1625 | modifier is optional, whereas a register list always has a known | |
1626 | and explicit length. It therefore seems better to place more | |
1627 | importance on the register list length when selecting an opcode table | |
1628 | entry. This in turn means that having an incorrect register length | |
1629 | should be more severe than having an incorrect "VGx<n>". | |
1630 | ||
f5b57fea RS |
1631 | AARCH64_OPDE_REG_LIST_LENGTH |
1632 | Error about a register list operand having an unexpected number of | |
36043bcf RS |
1633 | registers. This error is low severity because there might be another |
1634 | opcode entry that supports the given number of registers. | |
1635 | ||
f5b57fea RS |
1636 | AARCH64_OPDE_REG_LIST_STRIDE |
1637 | Error about a register list operand having the correct number | |
1638 | (and type) of registers, but an unexpected stride. This error is | |
1639 | more severe than AARCH64_OPDE_REG_LIST_LENGTH because it implies | |
1640 | that the length is known to be correct. However, it is lower than | |
1641 | many other errors, since some instructions have forms that share | |
1642 | the same number of registers but have different strides. | |
1643 | ||
01a4d082 PW |
1644 | AARCH64_OPDE_UNTIED_IMMS |
1645 | The asm failed to use the same immediate for a destination operand | |
1646 | and a tied source operand. | |
1647 | ||
0c608d6b RS |
1648 | AARCH64_OPDE_UNTIED_OPERAND |
1649 | The asm failed to use the same register for a destination operand | |
1650 | and a tied source operand. | |
1651 | ||
a06ea964 NC |
1652 | AARCH64_OPDE_OUT_OF_RANGE |
1653 | Error about some immediate value out of a valid range. | |
1654 | ||
1655 | AARCH64_OPDE_UNALIGNED | |
1656 | Error about some immediate value not properly aligned (i.e. not being a | |
1657 | multiple times of a certain value). | |
1658 | ||
a06ea964 NC |
1659 | AARCH64_OPDE_OTHER_ERROR |
1660 | Error of the highest severity and used for any severe issue that does not | |
1661 | fall into any of the above categories. | |
1662 | ||
859f51df RS |
1663 | AARCH64_OPDE_INVALID_REGNO |
1664 | A register was syntactically valid and had the right type, but it was | |
1665 | outside the range supported by the associated operand field. This is | |
1666 | a high severity error because there are currently no instructions that | |
1667 | would accept the operands that precede the erroneous one (if any) and | |
1668 | yet still accept a wider range of registers. | |
1669 | ||
63eff947 RS |
1670 | AARCH64_OPDE_RECOVERABLE, AARCH64_OPDE_SYNTAX_ERROR and |
1671 | AARCH64_OPDE_FATAL_SYNTAX_ERROR are only deteced by GAS while the | |
a06ea964 NC |
1672 | AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as |
1673 | only libopcodes has the information about the valid variants of each | |
1674 | instruction. | |
1675 | ||
1676 | The enumerators have an increasing severity. This is helpful when there are | |
1677 | multiple instruction templates available for a given mnemonic name (e.g. | |
1678 | FMOV); this mechanism will help choose the most suitable template from which | |
c1817dc2 RS |
1679 | the generated diagnostics can most closely describe the issues, if any. |
1680 | ||
1681 | This enum needs to be kept up-to-date with operand_mismatch_kind_names | |
1682 | in tc-aarch64.c. */ | |
a06ea964 NC |
1683 | |
1684 | enum aarch64_operand_error_kind | |
1685 | { | |
1686 | AARCH64_OPDE_NIL, | |
1687 | AARCH64_OPDE_RECOVERABLE, | |
63eff947 RS |
1688 | AARCH64_OPDE_A_SHOULD_FOLLOW_B, |
1689 | AARCH64_OPDE_EXPECTED_A_AFTER_B, | |
a06ea964 NC |
1690 | AARCH64_OPDE_SYNTAX_ERROR, |
1691 | AARCH64_OPDE_FATAL_SYNTAX_ERROR, | |
1692 | AARCH64_OPDE_INVALID_VARIANT, | |
e2dc4040 | 1693 | AARCH64_OPDE_INVALID_VG_SIZE, |
f5b57fea RS |
1694 | AARCH64_OPDE_REG_LIST_LENGTH, |
1695 | AARCH64_OPDE_REG_LIST_STRIDE, | |
01a4d082 | 1696 | AARCH64_OPDE_UNTIED_IMMS, |
0c608d6b | 1697 | AARCH64_OPDE_UNTIED_OPERAND, |
a06ea964 NC |
1698 | AARCH64_OPDE_OUT_OF_RANGE, |
1699 | AARCH64_OPDE_UNALIGNED, | |
859f51df RS |
1700 | AARCH64_OPDE_OTHER_ERROR, |
1701 | AARCH64_OPDE_INVALID_REGNO | |
a06ea964 NC |
1702 | }; |
1703 | ||
1704 | /* N.B. GAS assumes that this structure work well with shallow copy. */ | |
1705 | struct aarch64_operand_error | |
1706 | { | |
1707 | enum aarch64_operand_error_kind kind; | |
1708 | int index; | |
1709 | const char *error; | |
63eff947 RS |
1710 | /* Some data for extra information. */ |
1711 | union { | |
1712 | int i; | |
1713 | const char *s; | |
1714 | } data[3]; | |
9193bc42 | 1715 | bool non_fatal; |
a06ea964 NC |
1716 | }; |
1717 | ||
7e84b55d TC |
1718 | /* AArch64 sequence structure used to track instructions with F_SCAN |
1719 | dependencies for both assembler and disassembler. */ | |
1720 | struct aarch64_instr_sequence | |
1721 | { | |
b3e59f88 RS |
1722 | /* The instructions in the sequence, starting with the one that |
1723 | caused it to be opened. */ | |
7e84b55d | 1724 | aarch64_inst *instr; |
7e84b55d | 1725 | /* The number of instructions already in the sequence. */ |
b3e59f88 RS |
1726 | int num_added_insns; |
1727 | /* The number of instructions allocated to the sequence. */ | |
1728 | int num_allocated_insns; | |
7e84b55d | 1729 | }; |
a06ea964 NC |
1730 | |
1731 | /* Encoding entrypoint. */ | |
1732 | ||
9193bc42 | 1733 | extern bool |
a06ea964 NC |
1734 | aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *, |
1735 | aarch64_insn *, aarch64_opnd_qualifier_t *, | |
7e84b55d | 1736 | aarch64_operand_error *, aarch64_instr_sequence *); |
a06ea964 NC |
1737 | |
1738 | extern const aarch64_opcode * | |
1739 | aarch64_replace_opcode (struct aarch64_inst *, | |
1740 | const aarch64_opcode *); | |
1741 | ||
1742 | /* Given the opcode enumerator OP, return the pointer to the corresponding | |
1743 | opcode entry. */ | |
1744 | ||
1745 | extern const aarch64_opcode * | |
1746 | aarch64_get_opcode (enum aarch64_op); | |
1747 | ||
76a4c1e0 AB |
1748 | /* An instance of this structure is passed to aarch64_print_operand, and |
1749 | the callback within this structure is used to apply styling to the | |
1750 | disassembler output. This structure encapsulates the callback and a | |
1751 | state pointer. */ | |
1752 | ||
1753 | struct aarch64_styler | |
1754 | { | |
1755 | /* The callback used to apply styling. Returns a string created from FMT | |
1756 | and ARGS with STYLE applied to the string. STYLER is a pointer back | |
1757 | to this object so that the callback can access the state member. | |
1758 | ||
1759 | The string returned from this callback must remain valid until the | |
1760 | call to aarch64_print_operand has completed. */ | |
1761 | const char *(*apply_style) (struct aarch64_styler *styler, | |
1762 | enum disassembler_style style, | |
1763 | const char *fmt, | |
1764 | va_list args); | |
1765 | ||
1766 | /* A pointer to a state object which can be used by the apply_style | |
1767 | callback function. */ | |
1768 | void *state; | |
1769 | }; | |
1770 | ||
a06ea964 NC |
1771 | /* Generate the string representation of an operand. */ |
1772 | extern void | |
1773 | aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *, | |
7d02540a | 1774 | const aarch64_opnd_info *, int, int *, bfd_vma *, |
6837a663 | 1775 | char **, char *, size_t, |
76a4c1e0 AB |
1776 | aarch64_feature_set features, |
1777 | struct aarch64_styler *styler); | |
a06ea964 NC |
1778 | |
1779 | /* Miscellaneous interface. */ | |
1780 | ||
1781 | extern int | |
1782 | aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd); | |
1783 | ||
1784 | extern aarch64_opnd_qualifier_t | |
1785 | aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, | |
1786 | const aarch64_opnd_qualifier_t, int); | |
1787 | ||
9193bc42 | 1788 | extern bool |
a68f4cd2 TC |
1789 | aarch64_is_destructive_by_operands (const aarch64_opcode *); |
1790 | ||
a06ea964 NC |
1791 | extern int |
1792 | aarch64_num_of_operands (const aarch64_opcode *); | |
1793 | ||
1794 | extern int | |
1795 | aarch64_stack_pointer_p (const aarch64_opnd_info *); | |
1796 | ||
e141d84e YQ |
1797 | extern int |
1798 | aarch64_zero_register_p (const aarch64_opnd_info *); | |
a06ea964 | 1799 | |
1d482394 | 1800 | extern enum err_type |
9193bc42 | 1801 | aarch64_decode_insn (aarch64_insn, aarch64_inst *, bool, |
a68f4cd2 TC |
1802 | aarch64_operand_error *); |
1803 | ||
1804 | extern void | |
1805 | init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *); | |
36f4aab1 | 1806 | |
a06ea964 NC |
1807 | /* Given an operand qualifier, return the expected data element size |
1808 | of a qualified operand. */ | |
1809 | extern unsigned char | |
1810 | aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t); | |
1811 | ||
1812 | extern enum aarch64_operand_class | |
1813 | aarch64_get_operand_class (enum aarch64_opnd); | |
1814 | ||
1815 | extern const char * | |
1816 | aarch64_get_operand_name (enum aarch64_opnd); | |
1817 | ||
1818 | extern const char * | |
1819 | aarch64_get_operand_desc (enum aarch64_opnd); | |
1820 | ||
9193bc42 | 1821 | extern bool |
e950b345 RS |
1822 | aarch64_sve_dupm_mov_immediate_p (uint64_t, int); |
1823 | ||
199cfcc4 | 1824 | extern bool |
4abb672a | 1825 | aarch64_cpu_supports_inst_p (aarch64_feature_set, aarch64_inst *); |
199cfcc4 | 1826 | |
a06ea964 NC |
1827 | #ifdef DEBUG_AARCH64 |
1828 | extern int debug_dump; | |
1829 | ||
1830 | extern void | |
1831 | aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2))); | |
1832 | ||
1833 | #define DEBUG_TRACE(M, ...) \ | |
1834 | { \ | |
1835 | if (debug_dump) \ | |
1836 | aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ | |
1837 | } | |
1838 | ||
1839 | #define DEBUG_TRACE_IF(C, M, ...) \ | |
1840 | { \ | |
1841 | if (debug_dump && (C)) \ | |
1842 | aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \ | |
1843 | } | |
1844 | #else /* !DEBUG_AARCH64 */ | |
1845 | #define DEBUG_TRACE(M, ...) ; | |
1846 | #define DEBUG_TRACE_IF(C, M, ...) ; | |
1847 | #endif /* DEBUG_AARCH64 */ | |
1848 | ||
245d2e3f RS |
1849 | extern const char *const aarch64_sve_pattern_array[32]; |
1850 | extern const char *const aarch64_sve_prfop_array[16]; | |
8ff42920 | 1851 | extern const char *const aarch64_rprfmop_array[64]; |
99e01a66 | 1852 | extern const char *const aarch64_sme_vlxn_array[2]; |
245d2e3f | 1853 | |
d3e12b29 YQ |
1854 | #ifdef __cplusplus |
1855 | } | |
1856 | #endif | |
1857 | ||
a06ea964 | 1858 | #endif /* OPCODE_AARCH64_H */ |